summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/nouveau_object.c
AgeCommit message (Expand)Author
2011-11-30drm/nouveau: Keep RAMIN heap within the channel.Younes Manton
2011-09-20drm/nvd0: lets not attempt to dereference a nv50_display pointerBen Skeggs
2011-09-20drm/nouveau: fixup init/fini sequence to deal with no CRTCsBen Skeggs
2011-09-20drm/nvd0: add a card_type for 0xdX chipsetsBen Skeggs
2011-06-23drm/nouveau: fix off-by-oneBen Skeggs
2011-06-23drm/nouveau: fix null pointer deref on pre-nv50 chipsetsBen Skeggs
2011-06-23drm/nvc0: enable per-client address spacesBen Skeggs
2011-06-23drm/nvc0: explicitly map PDISP semaphore buffer into each channel's vmBen Skeggs
2011-06-23drm/nouveau: convert bo.mem.start usage to bo.offsetBen Skeggs
2011-06-23drm/nouveau: will need to specify channel for vm-ful gpuobj allocationsBen Skeggs
2011-06-23drm/nouveau: modify gpuobj/ntfy takedown orderingBen Skeggs
2011-06-23drm/nv50-nvc0/chan: inherit vm from fpriv, rather than chan_vm directlyBen Skeggs
2011-06-23drm/nouveau: store a per-client channel listBen Skeggs
2011-05-16drm/nouveau: remove remnants of nouveau_pgraph_engineBen Skeggs
2011-05-16drm/nv50/gr: move to exec engine interfacesBen Skeggs
2011-05-16drm/nouveau: working towards a common way to represent enginesBen Skeggs
2011-05-16drm/nouveau: move engine object creation into per-engine hooksBen Skeggs
2011-04-20drm/nouveau: split ramin_lock into two locks, one hardirq safeBen Skeggs
2011-02-25drm/nv50-nvc0: initialise display sync channelsBen Skeggs
2011-02-25drm/nouveau: introduce new gart type, and name _SGDMA more appropriatelyBen Skeggs
2011-02-23drm/nouveau: don't munge in drm_mm internalsDaniel Vetter
2011-01-07drm/nouveau: create grctx on the fly on all chipsetsBen Skeggs
2010-12-21drm/nvc0: implement channel structure initialisationBen Skeggs
2010-12-21drm/nvc0: gpuobj_new need only check validity and init the relevant engineBen Skeggs
2010-12-08drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.Francisco Jerez
2010-12-08drm/nv50: tidy up PCIEGART implementationBen Skeggs
2010-12-08drm/nv50: implement global channel address space on new VM codeBen Skeggs
2010-12-08drm/nv50: import new vm codeBen Skeggs
2010-12-08drm/nouveau: no need to zero dma objects, we fill them completely anywayBen Skeggs
2010-12-08drm/nouveau: implicitly insert non-DMA objects into RAMHTBen Skeggs
2010-12-08drm/nouveau: Synchronize with the user channel before GPU object destruction.Francisco Jerez
2010-12-08drm/nv04-nv40: Give "gpuobj->cinst" the same meaning as on nv50.Francisco Jerez
2010-12-03drm/nouveau: tidy up and extend dma object creation interfacesBen Skeggs
2010-12-03drm/nouveau: rework gpu-specific instmem interfacesBen Skeggs
2010-12-03drm/nouveau: simplify gpuobj suspend/resumeBen Skeggs
2010-12-03drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c filesBen Skeggs
2010-12-03drm/nv50: create graph and crypt contexts on demandBen Skeggs
2010-12-03drm/nv84: add support for the PCRYPT engineBen Skeggs
2010-12-03drm/nouveau: only expose the object classes that are supported by the chipsetBen Skeggs
2010-12-03drm/nouveau: use object class structs more extensivelyBen Skeggs
2010-12-03drm/nouveau: store engine type in gpuobj class structsBen Skeggs
2010-12-03drm/nouveau: pass gpuobj alignment request down into backing allocatorBen Skeggs
2010-12-03drm/nouveau: return error from nouveau_ramht_remove() if not foundBen Skeggs
2010-12-03drm/nouveau: add more fine-grained locking to channel list + structuresBen Skeggs
2010-11-18drm/nouveau: Return error from nouveau_gpuobj_new if we're out of RAMIN.Francisco Jerez
2010-09-24drm/nouveau: remove nouveau_gpuobj_late_takedownBen Skeggs
2010-09-24drm/nouveau: protect gpuobj list + global instmem heap with spinlockBen Skeggs
2010-09-24drm/nouveau: fix gpuobj refcount to use atomicsBen Skeggs
2010-09-24drm/nouveau: tidy ram{ht,fc,ro} a bitBen Skeggs
2010-09-24drm/nouveau: rework init ordering so nv50_instmem.c can be less badBen Skeggs
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-12-29 17:13:52 +0000