summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
AgeCommit message (Expand)Author
2011-02-25drm/nv50: drop explicit yields in favour of smaller PFIFO timesliceBen Skeggs
2010-12-08drm/nv50: import new vm codeBen Skeggs
2010-12-08drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs
2010-12-03drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs
2010-12-03drm/nouveau: Refactor context destruction to avoid a lock ordering issue.Francisco Jerez
2010-12-03drm/nouveau: add more fine-grained locking to channel list + structuresBen Skeggs
2010-11-18drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hangBen Skeggs
2010-09-24drm/nouveau: tidy ram{ht,fc,ro} a bitBen Skeggs
2010-09-24drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanityBen Skeggs
2010-09-24drm/nouveau: rebase per-channel pramin heap offsets to 0Ben Skeggs
2010-09-24drm/nouveau: modify object accessors, offset in bytes rather than dwordsBen Skeggs
2010-07-13drm/nv50: fix RAMHT sizeBen Skeggs
2010-07-13drm/nv50: cleanup nv50_fifo.cBen Skeggs
2010-07-13drm/nouveau: add instmem flush() hookBen Skeggs
2010-02-25drm/nv50: switch to indirect push buffer controlsBen Skeggs
2010-02-25drm/nouveau: protect channel create/destroy and irq handler with a spinlockMaarten Maathuis
2010-02-10drm/nv50: delete ramfc object after disabling fifo, not beforeMaarten Maathuis
2010-01-18drm/nv50: fix alignment of per-channel fifo cacheBen Skeggs
2010-01-11drm/nv50: restore correct cache1 get/put address on fifoctx loadBen Skeggs
2009-12-16drm/nv50: fix two potential suspend/resume oopsesBen Skeggs
2009-12-11drm/nouveau: Add DRM driver for NVIDIA GPUsBen Skeggs
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-11-01 02:37:58 +0000