Age | Commit message (Collapse) | Author |
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Right now it's called right after enable, but after
reworking the dpm init order, it will get called later
to accomodate loading the smc early, but enabling
thermal interrupts and block powergating later after
the ring tests are complete.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Make sure interrupts are enabled before we enable
thermal interrupts.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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I missed this when I fixed up this file.
Noticed-by: Mathias Fröhlich <Mathias.Froehlich@gmx.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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kfree() can accept NULL pointers so I have removed the checks. Also
I've used a pointer to shorten the lines.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs. Rather than indexing the arrays, use
pointer arithmetic.
See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Needed for DPM on CI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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convert from number of lanes to register setting.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Required for dpm on CI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Needed for DPM on CI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Uses a different table format if the board supports EVV.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Actually program the correct register to enable
engine clock scaling control.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Required for checking vblank time for mclk changes.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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This adds dpm support for SI asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2/gen3 switching
- power containment
- shader power scaling
Set radeon.dpm=1 to enable.
v2: enable hainan support, rebase
v3: guard acpi stuff
v4: fix 64 bit math
v5: fix 64 bit div harder
v6: fix thermal interrupt check noticed by Jerome
v7: attempt fix state enable
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Add a helper function to determine the preferred
pcie gen based on the card, system, and circumstance.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Forgot to free some structs when allocation fails for some
tables.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Used by SI dpm.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Required for dpm on SI.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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For r6xx-evergreen, they are no-ops as they don't support
any dynamic state adjustment.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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This data will be needed for dpm on newer asics.
v2: fix typo in rebase
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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This adds dpm support for rv6xx asics. This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching
Set radeon.dpm=1 to enable.
v2: remove duplicate line
v3: fix thermal interrupt check noticed by Jerome
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
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These are shared by rs780/rs880, rv6xx, and newer chips.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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