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2010-12-09drm/i915: Restore GTT mapping first upon resumeChris Wilson
As suggested by Daniel Vetter, this is a safeguard should any of the registers cause reference to PTE entries. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: driver.suspend and .resume are always setChris Wilson
So we can remove the repeated initialisation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Mark the user reloc error paths as unlikelyChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Eliminate drm_gem_object_lookup during relocationChris Wilson
As we provide a list of all objects that will be accessed from the batchbuffer, we can build a lut of the handles associated with those objects for this invocation and use that to avoid the overhead of looking up those objects again for every relocation. The cost of building and searching a small hash table is much less than that of acquiring a spinlock, searching a radix tree and manipulating an atomic refcnt per relocation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915: Re-arm the idle timers if the device is still busyChris Wilson
Don't post a downclocking task if the device is still active when the idle timer fires. A pathological process could queue up several seconds worth of processing and then go to sleep, during which time the idle timer would kick in and downclock the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/i915/ringbuffer: Handle wrapping of the autoreported HEADChris Wilson
If the tail advances beyond the autoreport HEAD value, then we need to fallback to an uncached read of the HEAD register in order to ascertain the correct amount of remaining space in the ringbuffer. Reported-by: Fang, Xun <xunx.fang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32259 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09drm/radeon/kms: don't apply 7xx HDP flush workaround on AGPAlex Deucher
It should be required for all 7xx asics, but seems to cause problems on some AGP 7xx chips. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=19002 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Reported-and-Tested-by: Duncan <1i5t5.duncan@cox.net> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-09drm: use after free in drm_queue_vblank_event()Dan Carpenter
The "e" pointer is either NULL or freed when we call drm_vblank_put(dev, e->pipe) on the error path. Just pass the "pipe" variable directly instead. I changed another caller to use "pipe" as well for consistency. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-09drm/kms: remove spaces from connector names (v2)Alex Deucher
Grub doesn't parse spaces in parameters correctly, so this makes it impossible to force video= parameters for kms on the grub kernel command line. v2: shorten the names to make them easier to type. Reported-by: Sergej Pupykin <ml@sergej.pp.ru> Cc: Sergej Pupykin <ml@sergej.pp.ru> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm/i915/dp: Fix I2C/EDID handling with active DisplayPort to DVI converterDavid Flynn
The DisplayPort standard (1.1a) states that: The I2C-over-AUX Reply field is valid only when Native AUX CH Reply field is AUX_ACK (00). When Native AUX CH Reply field is not 00, then, I2C-over-AUX Reply field must be 00 and be ignored. This fixes broken EDID reading when using an active DisplayPort to duallink DVI converter. If the AUX CH replier chooses to defer the transaction, a short read occurs and erroneous data is returned as the i2c reply due to a lack of length checking and failure to check for AUX ACK. As a result, broken EDIDs can look like: 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: bc bc bc ff bc bc bc ff bc bc bc ac bc bc bc 45 ???.???.???????E 10: bc bc bc 10 bc bc bc 34 bc bc bc ee bc bc bc 4c ???????4???????L 20: bc bc bc 50 bc bc bc 00 bc bc bc 40 bc bc bc 00 ???P???.???@???. 30: bc bc bc 01 bc bc bc 01 bc bc bc a0 bc bc bc 40 ???????????????@ 40: bc bc bc 00 bc bc bc 00 bc bc bc 00 bc bc bc 55 ???.???.???.???U 50: bc bc bc 35 bc bc bc 31 bc bc bc 20 bc bc bc fc ???5???1??? ???? 60: bc bc bc 4c bc bc bc 34 bc bc bc 46 bc bc bc 00 ???L???4???F???. 70: bc bc bc 38 bc bc bc 11 bc bc bc 20 bc bc bc 20 ???8??????? ??? 80: bc bc bc ff bc bc bc ff bc bc bc ff bc bc bc ff ???.???.???.???. ... which can lead to: [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder [drm:drm_edid_block_valid] *ERROR* Raw EDID: <3>30 30 30 30 30 30 30 32 38 32 30 32 63 63 31 61 000000028202cc1a <3>28 00 02 8c 00 00 00 00 18 00 00 00 00 00 00 00 (............... <3>20 4c 61 73 74 20 62 65 61 63 6f 6e 3a 20 33 32 Last beacon: 32 <3>32 30 6d 73 20 61 67 6f 46 00 05 8c 00 00 00 00 20ms agoF....... <3>36 00 00 00 00 00 00 00 00 0c 57 69 2d 46 69 20 6.........Wi-Fi <3>52 6f 75 74 65 72 01 08 82 84 8b 96 24 30 48 6c Router......$0Hl <3>03 01 01 06 02 00 00 2a 01 00 2f 01 00 32 04 0c .......*../..2.. <3>12 18 60 dd 09 00 10 18 02 00 00 01 00 00 18 00 ..`............. Signed-off-by: David Flynn <davidf@rd.bbc.co.uk> [ickle: fix up some surrounding checkpatch warnings] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-12-08drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/i915: i915 cannot provide switcher services.Dave Airlie
it has a DSM but the switcher is done via WMI. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm/nouveau: kick vram functions out into an "engine"Ben Skeggs
NVC0 will be able to share some of nv50's paths this way. This also makes it the card-specific vram code responsible for deciding if a given set of tile_flags is valid, rather than duplicating the allowed types in nv50_vram.c and nouveau_gem.c Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: allow gpuobj vinst to be a virtual address when necessaryBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: tidy up PCIEGART implementationBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: enable non-contig vram allocations where requestedBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: enable 4KiB pages for small vram allocationsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: implement global channel address space on new VM codeBen Skeggs
As of this commit, it's guaranteed that if an object is in VRAM that its GPU virtual address will be constant. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: implement BAR1/BAR3 management on top of new VM codeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: import new vm codeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv50: implement custom vram mmBen Skeggs
This is required on nv50 as we need to be able to have more precise control over physical VRAM allocations to avoid buffer corruption when using buffers of mixed memory types. This removes some nasty overallocation/alignment that we were previously using to "control" this problem. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: Avoid potential race between nouveau_fence_update() and context ↵Francisco Jerez
takedown. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: fix use of drm_mm_node in semaphore objectBen Skeggs
At some point in the future, this bo won't necessarily be backed by a drm_mm_node, so use the start/size fields of the ttm_mem_reg instead. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: wrap calls to ttm_bo_validate()Ben Skeggs
This will be used later to fixup bo.offset with a buffer's fixed GPU virtual address. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: no need to zero dma objects, we fill them completely anywayBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: introduce a util function to wait on reg != valBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: implicitly insert non-DMA objects into RAMHTBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs
The regs belong to PFIFO, they're different for pretty much the same generations we need different PFIFO control for, and NVC0 is going to be even more different than the rest. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU.Francisco Jerez
Sleeping doesn't pay off for very short delays in comparison with the minimum granularity of schedule_timeout(). Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: Use WC memory on the AGP GART.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nouveau: Synchronize with the user channel before GPU object destruction.Francisco Jerez
There have been reports of PFIFO cache errors during context take down (fdo bug 31637). They are caused by some GPU objects being taken out while the channel is still potentially processing commands. Make sure that all the previous rendering has landed before releasing a GPU object. Reported-by: Grzesiek Sójka <pld@pfu.pl> Reported-by: Patrice Mandin <patmandin@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Acked-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv04-nv10: Don't re-enable FIFO access multiple times after IRQ dispatch.Francisco Jerez
nvxx_graph_isr is already taking care of it. In some cases this could've made you miss PGRAPH interrupts (e.g. when you were supposed to get several IRQs of the same kind in a row). Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/nv04-nv40: Give "gpuobj->cinst" the same meaning as on nv50.Francisco Jerez
No functional changes, just simplify some code paths a bit. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-12-08drm/radeon/kms: fix vram base calculation on rs780/rs880Alex Deucher
Avoid overflowing a 32 bit value. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm/radeon/kms: fix formatting of vram and gtt infoAlex Deucher
print the full 64 bit values. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm/radeon/kms: forbid big bo allocation (fdo 31708) v3Jerome Glisse
Forbid allocating buffer bigger than visible VRAM or GTT, also properly set lpfn field. v2 - use max macro - silence warning v3 - don't explicitly set range limit - use min macro Cc: stable <stable@kernel.org> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm: Don't try and disable an encoder that was never enabledChris Wilson
Prevents code that assumes that the encoder is active when asked to be disabled from dying a horrible death. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-08drm: Add missing drm_vblank_put() along queue vblank error pathChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-12-07drm/i915: Disable renderctx powersaving support for IronlakeChris Wilson
... still causes a failure during suspend. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson
Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_dp.c
2010-12-07drm/i915/dp: Only apply the workaround if the select is still activeChris Wilson
As we may try to power down the link at various times, it is not necessarily still coupled with an encoder and so we must be careful not to depend upon an operation that is only valid when the link is still attached to a pipe. Fixes regression in 5bddd17. Reported-and-tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org [after applying 5bddd17]
2010-12-07drm/i915: Emit a request to clear a flushed and idle ring for unbusy boChris Wilson
In order for bos to retire eventually, a request must be sent down the ring. This is expected, for example, by occlusion queries for which mesa will wait upon (whilst running glean) before issuing more batches and so the normal activity upon the ring is suspended and we need to emit a request to clear the idle ring. Reported-by: Jinjin, Wang <jinjin.wang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30380 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Wait for the bo if a display flip is pipelined on the other ringChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06drm/i915: Only emit a flush if there is an outstanding gpu writeChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Completely disable fence pipelining.Chris Wilson
I'm still seeing tiling corruption of PutImage and CopyArea (I think) under mutter on pnv, so obviously the pipelining logic is deeply flawed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Uncouple render/power ctx before suspendingChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Ignore fenced commands for gpu access on gen4Chris Wilson
Userspace should not have been declaring that it needed fenced GPU access with gen4+ as those GPUs have no fenced commands, but to be on the safe side it is easier to ignore userspace in case they did. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: caps.has_rc6 is no longer used, remove it.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Power Context register is only available for gen4 mobilesChris Wilson
The ability to save the hardware context upon powering down the render clock through PWRCTXA is only available on a couple of gen4 chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05drm/i915: Avoid using PIPE_CONTROL on IronlakeChris Wilson
The workaround is hideous and we are using the STORE_DWORD on all other generations on all other rings, so use for the gen5 render ring as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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