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2014-11-16drm/msm/mdp5: drop attached planes tableRob Clark
Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp4: drop attached planes tableRob Clark
Simplify things a bit for atomic, gets rid of some bookkeeping, and makes the code cleaner. TODO move iterator macro somewhere common. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp4: don't care about fb in crtcRob Clark
Since we are configuring things via MDP4_PIPE regs in the plane, it seems like setting the dimensions of the primary plane on the OVLP/DMA regs in crtc is unnecessary. This will make life easier when we want to do a nofb modeset. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp5: drop private primary ptrRob Clark
Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/mdp4: drop private primary ptrRob Clark
Since primary-plane support in core, we can just use crtc->primary. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: Fix fbdev for 16- and 24-bit modes.Daniel Thompson
Currently forcing the video mode from the kernel command line (for example video=HDMI-A-1:1280x720-16@60) does not correctly set the number of bits per pixel. This is due to a rather aggressive override in msm_fbdev_create(). This is a particular problem for Android bring up because the software EGL fallbacks don't support 32bpp. Since the overrides are actually the default values anyway then this problem can be trivially fixed by removing the overrides completely. Change was tested by dd'ing a test image to /dev/fb0 with no video= (still 32bpp), video=1920x1080-32@60, video=1920x1080-24@60 and video=1920x1080-16@60 . Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Cc: David Airlie <airlied@linux.ie> Cc: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: Allow exported dma-bufs to be mappedDaniel Thompson
Currently msm does not implement gem_prime_mmap. Without this it is not possible to draw onto a dma-buf from userspace (making its very hard to implement the Android rendering model). Fixing this is just a matter of adding a little boilerplate. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/hdmi: refactor bind/initRob Clark
Split up hdmi_init() into hdmi_init() (done at hdmi sub-device bind/probe time) and hdmi_modeset_init() done from master driver's modeset_init(). Anything that can fail due to dependencies on other drivers which may be missing or not probed yet should go in hdmi_init(), so that devm error/cleanup paths work properly. Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: update generated headersRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm/adreno: slight init order cleanupRob Clark
Move anything that can fail after call to base class msm_gpu_init(). This way, if we fail, active_list has already been initialized so we don't trip 'WARN_ON(!list_empty(&gpu->active_list))' in msm_gpu_cleanup(). Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: select REGULATORRob Clark
Fixes a potential error, spotted by Felipe with randconfig: ----- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c: In function ‘mdp4_kms_init’: drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c:384:2: error: implicit declaration \ of function ‘devm_regulator_get_exclusive’ [-Werror=implicit-function-declaration] mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); ^ drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c:384:16: error: assignment makes \ pointer from integer without a cast [-Werror] mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); ^ ----- Also add a brief comment explaining the use of _get_exclusive() Reported-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-15drm/qxl: drop unused mode private pointerDave Airlie
This was pointless, forgot to remove the code. Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15Merge tag 'drm/gem-cma/for-3.19-rc1' of ↵Dave Airlie
git://people.freedesktop.org/~tagr/linux into drm-next drm: Sanitize DRM_IOCTL_MODE_CREATE_DUMB input Some drivers erroneously treat the .pitch and .size fields of struct drm_mode_create_dumb as inputs. While the include/uapi/drm/drm_mode.h header has a comment denoting them as outputs, that seemingly wasn't enough to make drivers use them properly. The result is that some userspace doesn't explicitly zero out those fields, assuming that the kernel won't use them. That causes problems since the data within the structure might be uninitialized, so bogus data may end up confusing drivers (ridiculously large values for the pitch, ...). This series attempts to improve the situation by fixing all drivers to not use the output fields. Furthermore to spare new drivers this bad surprise, the DRM core now zeros out these fields prior to handing the data structure to the driver. Lessons learned from this are that future IOCTLs should be properly documented (in the DRM DocBook for example) and should be rigorously defined. To prevent misuse like this, userspace should be required to zero out all output fields. The kernel should check for this and fail if that's not the case. * tag 'drm/gem-cma/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: drm/cma: Remove call to drm_gem_free_mmap_offset() drm: Sanitize DRM_IOCTL_MODE_CREATE_DUMB input drm/rcar: gem: dumb: pitch is an output drm/omap: gem: dumb: pitch is an output drm/cma: Introduce drm_gem_cma_dumb_create_internal() drm/doc: Add GEM/CMA helpers to kerneldoc drm/doc: mm: Fix indentation drm/gem: Fix a few kerneldoc typos
2014-11-15drm/qxl: use suggested x/y offset properties to pass guest prefsDave Airlie
This passes the guest preferences for a where to place the outputs through to userspace. Userspace would need to be updated to take note of this information, X server and GNOME. Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm: add properties for suggested x/y offset for connectors. (v2)Dave Airlie
Virtual GPUs would like to give the guest some indication where on the screen the outputs are layed out. So far we only provide modes, these properties could be exposed to userspace so the desktop environment could use them as hints to set the correct offsets. v2: rename properties to be more consistent. Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm: Simplify return value handling in drm_crtc.cDaniel Vetter
While looking through drm_crtc.c to double-check make locking changes I've noticed that there's a few other places that would now benefit from simplified return value handling. So let's flatten the control flow and replace and always 0 ret with 0 where possible. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15Merge tag 'drm/tegra/for-3.19-rc1' of ↵Dave Airlie
git://people.freedesktop.org/~tagr/linux into drm-next drm/tegra: Changes for v3.19-rc1 The highlights in this pull request are: * IOMMU support: The Tegra DRM driver can now deal with discontiguous buffers if an IOMMU exists in the system. That means it can allocate using drm_gem_get_pages() and will map them into IOVA space via the IOMMU API. Similarly, non-contiguous PRIME buffers can be imported from a different driver, which allows better integration with gk20a (nouveau) and less hacks. * Universal planes: This is precursory work for atomic modesetting and will allow hardware cursor support to be implemented on pre-Tegra114 where RGB cursors were not supported. * DSI ganged-mode support: The DSI controller can now gang up with a second DSI controller to drive high resolution DSI panels. Besides those bigger changes there is a slew of fixes, cleanups, plugged memory leaks and so on. * tag 'drm/tegra/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: (44 commits) drm/tegra: gem: Check before freeing CMA memory drm/tegra: fb: Add error codes to error messages drm/tegra: fb: Properly release GEM objects on failure drm/tegra: Detach panel when a connector is removed drm/tegra: Plug memory leak drm/tegra: gem: Use more consistent data types drm/tegra: fb: Do not destroy framebuffer drm/tegra: gem: dumb: pitch and size are outputs drm/tegra: Enable the hotplug interrupt only when necessary drm/tegra: dc: Universal plane support drm/tegra: dc: Registers are 32 bits wide drm/tegra: dc: Factor out DC, window and cursor commit drm/tegra: Add IOMMU support drm/tegra: Fix error handling cleanup drm/tegra: gem: Use dma_mmap_writecombine() drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset() drm/tegra: gem: Cleanup tegra_bo_create_with_handle() drm/tegra: gem: Extract tegra_bo_alloc_object() drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier drm/tegra: dsi: Replace 1000000 by USEC_PER_SEC ...
2014-11-15Merge tag 'drm/fixes/for-3.19-rc1' of ↵Dave Airlie
git://people.freedesktop.org/~tagr/linux into drm-next drm: Miscellaneous fixes for v3.19-rc1 This is a small collection of fixes that I've been carrying around for a while now. Many of these have been posted and reviewed or acked. The few that haven't I deemed too trivial to bother. * tag 'drm/fixes/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: video/hdmi: Relicense header under MIT license drm/gma500: mdfld: Reuse video/mipi_display.h drm: Make drm_mode_create_tv_properties() signature consistent drm: Implement drm_get_pci_dev() dummy for !PCI drm/prime: Use unsigned type for number of pages drm/gem: Fix typo in kerneldoc drm: Use const data when creating blob properties drm: Use size_t for blob property sizes
2014-11-15Merge tag 'drm/panel/for-3.19-rc1' of ↵Dave Airlie
git://people.freedesktop.org/~tagr/linux into drm-next drm/panel: Changes for v3.19-rc1 This contains support for a couple of new panels, updates for some GPIO API changes and a bunch of updates to the MIPI DSI support that should make it easier to write panel drivers in the future. * tag 'drm/panel/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: (31 commits) drm/panel: Add Sharp LQ101R1SX01 support drm/dsi: Do not require .owner field to be set drm/dsi: Resolve MIPI DSI device from phandle drm/dsi: Implement DCS set_{column,page}_address commands drm/dsi: Implement DCS {get,set}_pixel_format commands drm/dsi: Implement DCS get_power_mode command drm/dsi: Implement DCS soft_reset command drm/dsi: Implement DCS nop command drm/dsi: Add to DocBook documentation drm/dsi: Implement some standard DCS commands drm/dsi: Implement generic read and write commands drm/panel: s6e8aa0: Use standard MIPI DSI function drm/dsi: Add mipi_dsi_set_maximum_return_packet_size() helper drm/dsi: Constify mipi_dsi_msg drm/dsi: Make mipi_dsi_dcs_{read,write}() symmetrical drm/dsi: Add DSI transfer helper drm/dsi: Add message to packet translator drm/dsi: Introduce packet format helpers drm/panel: s6e8aa0: Fix build warnings on 64-bit drm/panel: ld9040: Fix build warnings on 64-bit ...
2014-11-15Merge tag 'drm-intel-next-2014-11-07-fixups' of ↵Dave Airlie
git://anongit.freedesktop.org/drm-intel into drm-next - skl watermarks code (Damien, Vandana, Pradeep) - reworked audio codec /eld handling code (Jani) - rework the mmio_flip code to use the vblank evade logic and wait for rendering using the standard wait_seqno interface (Ander) - skl forcewake support (Zhe Wang) - refactor the chv interrupt code to use functions shared with vlv (Ville) - prep work for different global gtt views (Tvrtko Ursulin) - precompute the display PLL config before touching hw state (Ander) - completely reworked panel power sequencer code for chv/vlv (Ville) - pre work to split the plane update code into a prepare and commit phase (Gustavo Padovan) - golden context for skl (Armin Reese) - as usual tons of fixes and improvements all over * tag 'drm-intel-next-2014-11-07-fixups' of git://anongit.freedesktop.org/drm-intel: (135 commits) drm/i915: Use correct pipe config to update pll dividers. V2 drm/i915: Plug memory leak in intel_shared_dpll_start_config() drm/i915: Update DRIVER_DATE to 20141107 drm/i915: Add gen to the gpu hang ecode drm/i915: Cache HPLL frequency on VLV/CHV Revert "drm/i915/vlv: Remove check for Old Ack during forcewake" drm/i915: Make mmio flip wait for seqno in the work function drm/i915: Make __wait_seqno non-static and rename to __i915_wait_seqno drm/i915: Move the .global_resources() hook call into modeset_update_crtc_power_domains() drm/i915/audio: add DOC comment describing HDA over HDMI/DP drm/i915: make pipe/port based audio valid accessors easier to use drm/i915/audio: add audio codec enable debug log for g4x drm/i915/audio: add audio codec disable on g4x drm/i915: enable audio codec after port drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence drm/i915/skl: Enable Gen9 RC6 drm/i915/skl: Gen9 Forcewake drm/i915/skl: Log the order in which we flush the pipes in the WM code drm/i915/skl: Flush the WM configuration ...
2014-11-15drm/dp/mst: Handle invalid link bandwidth from DPCD gracefullyChris Wilson
Don't BUG out if the link reports an invalid (or plain unknown) bandwidth value, but report the failure and fail gracefully. Fixes a trivial compiler warning in case the BUG is ever compiled away. Link: http://lkml.kernel.org/p/1415785566-12758-1-git-send-email-geert@linux-m68k.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm/atomic: rip out unnecessary locking checksRob Clark
For async commit, it is *intentional* that those locks are not held. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm: flip-work: change drm_flip_work_init prototypeBoris BREZILLON
Now that we're using lists instead of kfifo to store drm flip-work tasks we do not need the size parameter passed to drm_flip_work_init function anymore. Moreover this function cannot fail anymore, we can thus remove the return code. Modify drm_flip_work_init users to take account of these changes. [airlied: fixed two unused variable warnings] Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm: rework flip-work helpers to avoid calling func when the FIFO is fullBoris BREZILLON
Make use of lists instead of kfifo in order to dynamically allocate task entry when someone require some delayed work, and thus preventing drm_flip_work_queue from directly calling func instead of queuing this call. This allow drm_flip_work_queue to be safely called even within irq handlers. Add new helper functions to allocate a flip work task and queue it when needed. This prevents allocating data within irq context (which might impact the time spent in the irq handler). Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-14[media] gpu: ipu-v3: Make use of media_bus_format enumBoris BREZILLON
In order to have subsytem agnostic media bus format definitions we've moved media bus definition to include/uapi/linux/media-bus-format.h and prefixed enum values with MEDIA_BUS_FMT instead of V4L2_MBUS_FMT. Reference new definitions in the ipu-v3 driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
2014-11-14drm/i915: Fix comments about CHV snoop behaviourVille Syrjälä
Replace the misinformed notes about CHV snoop behaviour with something that's hopefully closer to reality. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915: Use vlv display irq setup code for chvVille Syrjälä
Throw away the hand rolled display irq setup code on chv, and instead just call vlv_display_irq_postinstall() and vlv_display_irq_uninstall(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915: Refactor vlv_display_irq_uninstall()Ville Syrjälä
Pull the vlv display irq uninstall code into a separate function, for eventual sharing with chv. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Don't allow disabling ppgtt and execlists on gen9+Damien Lespiau
Running the driver without execlists and hence PPGTT (either aliasing or full) isn't a supported configuration on gen9+. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Fix big integer constant sparse warningDamien Lespiau
intel_ddi.c:955:41: sparse: constant 8400000000 is so big it is long intel_ddi.c:955:53: sparse: constant 9000000000 is so big it is long intel_ddi.c:955:65: sparse: constant 9600000000 is so big it is long intel_ddi.c:1028:23: sparse: constant 9600000000 is so big it is long intel_ddi.c:1031:23: sparse: constant 9000000000 is so big it is long intel_ddi.c:1034:23: sparse: constant 8400000000 is so big it is long Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915: Let's hope future platforms will use the same WM code as SKLDamien Lespiau
Given the history, there's some chance we'll keep the same WM code for a bit (previously, we were able to reuse the same WM code from ILK to BDW, so that sounds like a fair assumption). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Use correct use counters for force wakesTvrtko Ursulin
Write and reads following the block changed use engine specific use counters and unless that is matched here force wake use counting goes bad. Same force wake is attempted to be taken twice which leads to at least time outs. NOTE: Depending on feedback from hardware designers it may not be necessary to grab force wakes on Gen9 here. But for Gen8 it is needed due to a race between RC6 and ELSP writes. v2: Added blitter force wake engine and made more future proof. Added commit note. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915: Clear PCODE_DATA1 on SNB+Damien Lespiau
Ville found out that the DATA1 register exists since SNB with some scarce apparitions in the specs throughout the times. In his own words: Also according to Bspec the mailbox data1 register already existed since snb. The hsw cdclk change sequence also mentions that it should be set to 0, but eg. the bdw IPS sequence doesn't mention it. I guess in theory some pcode command might cause it to be clobbered, so I'm thinking we should just explicitly set it to 0 for all platforms in the pcode read/write functions Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Add Gen9 LRC sizeMichael H. Nguyen
The LRC increased in size on gen9. Make sure we return the right size in get_lr_context_size() v2. Corrected the size, should be 22 pages. I unintentionally mailed out a test patch w/ size equaling 23 pages. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: AUX irqs have movedJesse Barnes
Use the new AUX port irq bits where needed. v2: Rebase on top of upstream changes v3: Rebase on top of Oscar change to write IIR as soon as possible (Damien) v4: Rebase on top of the for_each_pipe() change adding dev_priv as first argument (Damien) Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: fetch, enable/disable pfit as needed v2Jesse Barnes
This moved around on SKL, so we need to make sure we read/write the correct regs. v2: fixup WIN_POS offsets (Paulo) zero out WIN_POS reg at disable time (Paulo) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuougseek.org> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Implement queue_flipDamien Lespiau
A few bits have changed in MI_DISPLAY_FLIP to accomodate the new planes. DE_RRMR seems to have kept its plane flip bits backward compatible. v2: Rebase on top of nightly v3: Rebase on top of nightly (minor conflict in i915_reg.h) v4: Remove code that is now part of intel_crtc_page_flip() Don't use BUG() in default: Use intel_crtc->unpin_work->gtt_offset (Paulo) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Apply eDP WA only for gen < 9Vandana Kannan
The eDP WA to stop link train based on port type is for HSW/BDW, not required for SKL+. Suggested by Satheesh v2: Simplified the check befoe stop_link_train. Suggested by Satheesh. v3: stop_link_train need not be called from intel_enable_ddi for gen >= 9 Suggested-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Provide skl-specific pll hw state cross-checkingDamien Lespiau
v2: rebase on top of the hw state flattening. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Implementation of SKL DPLL programmingSatheeshakrishna M
This patch implements SKL DPLL programming that includes: - DPLL allocation - wide range PLL calculation and programming - DP link rate programming - DDI to DPLL mapping v2: Incorporated following changes - Added vfunc for function required outside - Fixed multiple comments in WRPLL calculation v3: - Fix the DCO computation - Move the initialization up to not clobber the computed values - Use the correct macro for DP link rate programming. - Use wait_for() to wait for the PLL locked bit v4: Rebase on top of nigthly (Damien) v5: A few code cleanups in the WRPLL computation (Damien) - Use uint32_t when possible - Use abs_diff() in the WRPLL computation - Make the 64bits divisions use div64_u64() - Fix typo in dco_central_feq_deviation (freq) - Replace the chain of breaks with a goto v6: Port of the patch to work on top of the shared DPLLs (Damien) v7: Don't try to handle eDP in ddi_pll_select() (Damien) v8: Modified as per review comments from Paulo (Satheesh) v9: Rebase on top of Ander's clock computation staging work for atomic (Damien) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v3) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Adjust the port PLL selection codeSatheeshakrishna M
Skylake deprecates the usage of PORT_CLK_SEL and we are advised to use the new DPLL_CRTL2 for the DDI->PLL mapping. v2: Modified as per review comments Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Define shared DPLLs for SkylakeSatheeshakrishna M
On skylake, DPLL 1, 2 and 3 can be used for DP and HDMI. The shared dpll framework allows us to share those DPLLs among DDIs when possible. The most tricky part is to provide a DPLL state that can be easily compared. DPLL_CRTL1 is shared by all the DPLLs, 6 bits each. The per-dpll crtl1 field of the hw state is then normalized to be the same value if 2 DPLLs do indeed have identical values for those 6 bits. v2: Port the code to the shared DPLL infrastructure (Damien) v3: Rebase on top of Ander's clock computation staging work for atomic (Damien) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v2) Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Query DPLL attached to port on SKLSatheeshakrishna M
Modify the implementation to query DPLL attached to a SKL port. v2: Rebase on top of the run-time PM on DPMS series (Damien) v3: Modified as per review comments from Paulo Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Determine enabled PLL and its linkrate/pixel clockSatheeshakrishna M
v2: Fixup compilation due to the removal of the intel_ddi_dpll_id enum. And add a fixme about the abuse of pipe_config here. v3: Rebase on top of the hsw_ddi_clock_get() rename (Damien) v4: Modified as per review comments from Paulo Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: CD clock back calculation for SKLSatheeshakrishna M
Determine programmed cd clock for SKL. v2: Fix the LCPLL1 enable warning logic v3: Rebase over the hsw pll rework. v4: Rebase on top of the per-platform split (Damien) v5: Modified as per review comments from Paulo Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Structure/enum definitions for SKL clocksSatheeshakrishna M
Adding structure/enum for SKL clocking implementation. v2: Addressed Damien's comment - Removed internal structure from this header file v3: Stove this into the generic intel_dpll_id enum and give them the established DPLL_ID_ prefixes. (Daniel) v4: - We'll only try to share DPLL1/2/3, leaving DPLL0 to eDP - Use SKL in the skylake shared DPLL names - Re-add the skl_dpll enum (Damien) v5: Remove SKL_DPLL_NONE (Daniel) v6: Modified as per review comments from Paulo Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v4,v5) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915/skl: Register definitions for SKL ClocksSatheeshakrishna M
This patch defines the necessary SKL registers for implementing the new clocking mechanism. v2: Addressed review comments by Damien - Added code comment - Introduced enum for WRPLL values v3: Rebase on top of nightly (minor conflict in i915_reg.h) v4: Use 0x, not 0X (Ville) v5: Modified as per review comments from Paulo Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3,v4) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915: preserve SSC if previously set v3Jesse Barnes
Some machines may have a broken VBT or no VBT at all, but we still want to use SSC there. So check for it and keep it enabled if we see it already on. Based on an earlier fix from Kristian. v2: honor modparam if set too (Daniel) read out at init time and store for panel_use_ssc() use (Jesse) v3: trust BIOS configuration over VBT like we do for DP (Jani) Reported-by: Kristian Høgsberg <hoegsberg@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-14drm/i915: Delete outdated comment in byt_pte_encodeDaniel Vetter
This has been invalidated in commit 24f3a8cf7766e52a087904b4346794c7b410f957 Author: Akash Goel <akash.goel@intel.com> Date: Tue Jun 17 10:59:42 2014 +0530 drm/i915: Added write-enable pte bit supportt But despite that it's in the diff context no one noticed :( Cc: Akash Goel <akash.goel@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2014-11-14drm/i915: unify remaining register save/restore code a bitJani Nikula
Use the same conditions, group by features, add comments. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>