| Age | Commit message (Collapse) | Author |
|---|
|
The current ndfc driver only compiles under arch/ppc. This arch was
removed from the kernel. I notice the event entry for the ndfc in
Kconfig has been removed in 2.6.28.
This patch converts the ndfc to a proper OF (OpenFirmware) driver. I
can give a working example of the DTS if needed.
The patch has been in production use on the PIKA Warp Appliance and is
in use by others. The Warp basically boots from NAND, so the ndfc driver
is very important to us.
Signed-off-by: Sean MacLennan <smaclennan@pikatech.com>
Acked-By: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
|
|
Since 43cc71eed1250755986da4c0f9898f9a635cb3bf, the platform modalias is
prefixed with "platform:". Add MODULE_ALIAS() to the hotpluggable MTD NAND
platform drivers, to re-enable auto loading.
NOTE: at91_nand for some reason disallows modular builds. I'm assuming that's
just an oversight that will be fixed.
[dbrownell@users.sourceforge.net: minor fix]
Signed-off-by: Kay Sievers <kay.sievers@vrfy.org>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
|
|
This patch adds 405 platform support to the 440 NDFC driver. The new
AMCC 405EZ PPC is equipped with the same NDFC core as the 440EP(x)
and other will follow soon.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
|
|
The writel() call accidentally clears all bits in the NDFC_CCR
register (endianess problem). Now __raw_writel() is used instead.
Tested on Bamboo with NAND on chip select 0 and chip select 1.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
|
|
Due to this typo, a wrong ECC layout table is chosen.
Signed-off-by: Frank Haverkamp <haver@vnet.ibm.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
|
|
The rework of the command handling in the nand driver
led to wrong address setting in the command control
function. Use the correct address again.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
Remove the remains of a broken merge.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
The nand_oobinfo structure is not fitting the newer error correction
demands anymore. Replace it by struct nand_ecclayout and fixup the users
all over the place. Keep the nand_oobinfo based ioctl for user space
compability reasons.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
The platform structure was lacking an oobinfo field.
The NDFC driver had some remains from another tree.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
The lock simplifying patch did not move the lock and waitqueue
initialization into the controller allocation patch.
This reinitializes waitqueue and spinlocks also for driver
supplied controller stuctures. Move it into the allocation path.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
The hwcontrol function enforced a step by step state machine
for any kind of hardware chip access. Let the hardware driver
know which control bits are set and inform it about a change
of the control lines. Let the hardware driver write out the
command and address bytes directly. This gives a peformance
advantage for address bus controlled chips and simplifies the
quirks in the hardware drivers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
First step of modularizing ECC support.
- Move ECC related functionality into a seperate embedded data structure
- Get rid of the hardware dependend constants to simplify new ECC models
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
NDFC NAND Flash controller is embedded in PPC EP44x SoCs.
Add platform driver based support.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
