summaryrefslogtreecommitdiffstats
path: root/include/asm-mips/cpu.h
AgeCommit message (Expand)Author
2008-01-29[MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss
2007-10-11[MIPS] Convert list of CPU types from #define to enum.Ralf Baechle
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno
2007-07-10[MIPS] PMC MSP71xx mips commonMarc St-Jean
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang
2007-07-10[MIPS] Enable support for the userlocal hardware registerRalf Baechle
2007-07-06[MIPS] Add macros to encode processor revisions.Ralf Baechle
2006-07-13[MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle
2006-06-01[MIPS] Treat R14000 like R10000.Kumba
2006-06-01[MIPS] Fix detection and handling of the 74K processor.Chris Dearman
2006-02-14[MIPS] Fix CPU type bitmasks for MIPS III, IV and V.Maciej W. Rozycki
2006-01-10MIPS: Reorganize ISA constants strictly as bitmasks.Ralf Baechle
2006-01-10MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle
2005-10-29Add support for SB1A CPU.Andrew Isaacson
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle
2005-10-29Move MIPS Technologies processor IDs to where they belong.Maciej W. Rozycki
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov
2005-10-29Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle
2005-10-29Detect the 34K.Ralf Baechle
2005-10-29Support the MIPS32 / MIPS64 DSP ASE.Ralf Baechle
2005-10-29Cleanup decoding of MIPSxx config registers.Ralf Baechle
2005-10-29Base Au1200 2.6 support.Pete Popov
2005-10-29Add a few more PrId vendor IDs.Ralf Baechle
2005-04-16Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2024-11-18 00:12:05 +0000