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The DAPM widgets are now insntantiated by the core when creating the card
so there is no need for the individual CODEC drivers to do so.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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snd_soc_init_card() is always called as the last part of the CODEC probe
function so we can factor it out into the core card setup rather than
have each CODEC replicate the code to do the initialiastation. This will
be required to support multiple CODECs per card.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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The PM core will grow pm_link infrastructure in 2.6.33 which can be
used to implement the intended functionality of the ASoC-specific
device suspend and resume callbacks so drop them.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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* topic/asoc: (226 commits)
ASoC: au1x: PSC-AC97 bugfixes
ASoC: Fix WM835x Out4 capture enumeration
ASoC: Remove unuused hw_read_t
ASoC: fix pxa2xx-ac97.c breakage
ASoC: Fully specify DC servo bits to update in wm_hubs
ASoC: Debugged improper setting of PLL fields in WM8580 driver
ASoC: new board driver to connect bfin-5xx with ad1836 codec
ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI
ASoC: davinci: i2c device creation moved into board files
ASoC: Don't reconfigure WM8350 FLL if not needed
ASoC: Fix s3c-i2s-v2 build
ASoC: Make platform data optional for TLV320AIC3x
ASoC: Add S3C24xx dependencies for Simtec machines
ASoC: SDP3430: Fix TWL GPIO6 pin mux request
ASoC: S3C platform: Fix s3c2410_dma_started() called at improper time
ARM: OMAP: McBSP: Merge two functions into omap_mcbsp_start/_stop
ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI
OMAP: McBSP: Use textual values in DMA operating mode sysfs files
ARM: OMAP: DMA: Add support for DMA channel self linking on OMAP1510
ASoC: Select core DMA when building for S3C64xx
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This converts all the Wolfson drivers using this format (the only devices
that do) except WM8753 to use it.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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While writes tend to be able to use a fairly bus independant format to
do the writes reads are all bus specific. To allow us to factor out
this code include the bus type as a parameter when setting up the
cache.
Initially just use this to factor out hw_write_t for I2C.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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This is the last in-kernel direct usage of driver_data, replace it with
the proper dev_get/set_drvdata() calls.
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Jaroslav Kysela <perex@perex.cz>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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A lot of CODECs share the same register data formats and therefore
replicate the code to manage access to and caching of the register
map. In order to reduce code duplication centralised versions of
this code will be introduced with drivers able to configure the use
of the common code by calling the new snd_soc_codec_set_cache_io()
API call during startup.
As an initial user the 7 bit address/9 bit data format used by many
Wolfson devices is supported for write only CODECs and the drivers
with straightforward register cache implementations are converted to
use it.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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The WM8988 is a low power, high quality stereo CODEC designed for
portable digital audio applications.
The device integrates complete interfaces to 2 stereo headphone or line
out ports. External component requirements are drastically reduced as no
separate headphone amplifiers are required. Advanced on-chip digital
signal processing performs graphic equaliser, 3-D sound enhancement and
automatic level control for the microphone or line input.
The WM8988 can operate as a master or a slave, with various master clock
frequencies including 12 or 24MHz for USB devices, or standard 256fs
rates like 12.288MHz and 24.576MHz. Different audio sample rates such as
96kHz, 48kHz, 44.1kHz are generated directly from the master clock
without the need for an external PLL.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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