From 73b39d4b443857c2155c7269bb593748f48d4852 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:14 +0200 Subject: arm: mach-dove: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/include/mach/bridge-regs.h | 16 ++-- arch/arm/mach-dove/include/mach/dove.h | 118 +++++++++++++------------- 2 files changed, 67 insertions(+), 67 deletions(-) diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h index f953bb54aa9..99f259e8cf3 100644 --- a/arch/arm/mach-dove/include/mach/bridge-regs.h +++ b/arch/arm/mach-dove/include/mach/bridge-regs.h @@ -13,22 +13,22 @@ #include -#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000) +#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define CPU_CTRL_PCIE0_LINK 0x00000001 #define CPU_RESET 0x00000002 #define CPU_CTRL_PCIE1_LINK 0x00000008 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_LOW_OFF 0x0000 #define IRQ_MASK_LOW_OFF 0x0004 #define FIQ_MASK_LOW_OFF 0x0008 @@ -47,9 +47,9 @@ #define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) -#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) +#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) #endif diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index d52b0ef313b..cccfd1d45f4 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -64,75 +64,75 @@ */ /* SPI, I2C, UART */ -#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000) -#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000) -#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000) -#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100) -#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100) -#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200) -#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200) -#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300) -#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300) -#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600) -#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600) +#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) +#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) +#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) +#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) +#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) +#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) +#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) +#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) +#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) +#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) +#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) /* North-South Bridge */ -#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) -#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x20000) +#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) +#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) /* Cryptographic Engine */ -#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) +#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) /* PCIe 0 */ -#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000) +#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) /* USB */ -#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000) -#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000) +#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) +#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) /* XOR 0 Engine */ -#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800) -#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800) -#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00) -#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00) +#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) +#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) +#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) +#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) /* XOR 1 Engine */ -#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900) -#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900) -#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00) -#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00) +#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) +#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) +#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) +#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) /* Gigabit Ethernet */ -#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000) +#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) /* PCIe 1 */ -#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000) +#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) /* CAFE */ -#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000) -#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000) -#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000) -#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000) +#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) +#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) +#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) +#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) /* SATA */ -#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000) +#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) /* I2S/SPDIF */ -#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000) -#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000) +#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) +#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) /* NAND Flash Controller */ -#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000) +#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) /* MPP, GPIO, Reset Sampling */ -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) +#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) -#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) -#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) -#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420) -#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) +#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) +#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) +#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) +#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) +#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) +#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) #define DOVE_NAND_GPIO_EN (1 << 0) #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) @@ -144,44 +144,44 @@ #define DOVE_SD0_GPIO_SEL (1 << 0) /* Power Management */ -#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) +#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) #define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) /* Real Time Clock */ -#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) +#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) /* AC97 */ -#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000) -#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000) +#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) +#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) /* Peripheral DMA */ -#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000) -#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000) +#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) +#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) #define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) +#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) #define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) #define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) #define DOVE_TWSI_OPTION3_GPIO (1 << 22) -#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) +#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) +#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) #define DOVE_SSP_ON_AU1 (1 << 0) #define DOVE_SSP_CLOCK_ENABLE (1 << 1) #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) /* Memory Controller */ -#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000) +#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) /* LCD Controller */ -#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) -#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000) -#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) -#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000) +#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) +#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) +#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) +#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) /* Graphic Engine */ -#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000) +#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) /* Video Engine */ -#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000) +#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) #endif -- cgit v1.2.3-70-g09d2 From 40306c8bc0dbef623fa02815929dace1c75046e2 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:15 +0200 Subject: arm: mach-kirkwood: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 20 ++-- arch/arm/mach-kirkwood/include/mach/kirkwood.h | 110 +++++++++++----------- 2 files changed, 65 insertions(+), 65 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index a115142f869..5c82b7dce4e 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -13,37 +13,37 @@ #include -#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100) +#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) #define CPU_CONFIG_ERROR_PROP 0x00000004 -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define CPU_RESET 0x00000002 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) #define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_LOW_OFF 0x0000 #define IRQ_MASK_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) -#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) +#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128) #define L2_WRITETHROUGH 0x00000010 -#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) +#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c) #define CGC_BIT_GE0 (0) #define CGC_BIT_PEX0 (2) #define CGC_BIT_USB0 (3) diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index c5b68510776..9695592d332 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -61,61 +61,61 @@ /* * Register Map */ -#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) - -#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) -#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140) -#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) -#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) - -#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) -#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000) - -#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) - -#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) -#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) -#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) -#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) -#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) -#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) - -#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) - -#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800) -#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800) -#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900) -#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900) -#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00) -#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00) -#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00) -#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00) - -#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) - -#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) -#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) -#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) -#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) -#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) -#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) - -#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) - -#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000) -#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000) +#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) +#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418) + +#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030) +#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140) +#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300) +#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) + +#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) +#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) + +#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) + +#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000) +#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70) +#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04) +#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000) +#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70) +#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04) + +#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000) + +#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800) +#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800) +#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900) +#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900) +#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00) +#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00) +#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00) +#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00) + +#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000) + +#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000) +#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000) +#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050) +#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330) +#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050) +#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330) + +#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000) + +#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000) +#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000) /* * Supported devices and revisions. -- cgit v1.2.3-70-g09d2 From 5ae9f5dbb3376c14201f8354d857485ff3ea14af Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:16 +0200 Subject: arm: mach-mv78xx0: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 12 ++-- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 82 ++++++++++++------------ 2 files changed, 47 insertions(+), 47 deletions(-) diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index eb187e0e059..5f03484584d 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h @@ -11,18 +11,18 @@ #include -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define L2_WRITETHROUGH 0x00020000 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_ERR_OFF 0x0000 #define IRQ_CAUSE_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0008 @@ -30,7 +30,7 @@ #define IRQ_MASK_LOW_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0..a86e79ecfea 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -65,47 +65,47 @@ /* * Register Map */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) /* * Supported devices and revisions. -- cgit v1.2.3-70-g09d2 From 2332656aec7ae88248cbd9aa6b35c857bb449c94 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:17 +0200 Subject: arm: mach-orion5x: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-orion5x/include/mach/bridge-regs.h | 20 ++++----- arch/arm/mach-orion5x/include/mach/orion5x.h | 52 ++++++++++++------------ arch/arm/mach-orion5x/pci.c | 2 +- 3 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 11a3c1e9801..461fd69a10a 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -13,27 +13,27 @@ #include -#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) +#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) -#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) +#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) +#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) #define WDT_RESET_OUT_EN 0x0002 -#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) +#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) -#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) +#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) -#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) +#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) #define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) +#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) -#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) +#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) -#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) +#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) #endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 683e085ce16..87bd378b820 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -68,42 +68,42 @@ * Orion Registers Map ******************************************************************************/ -#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) -#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) -#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) -#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) -#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) +#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500) +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) #define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) -#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) +#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) -#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) -#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x20000) +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) +#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) -#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) -#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) -#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) -#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) -#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) -#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) +#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) +#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) -#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) -#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) -#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) -#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) -#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) +#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) -#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) -#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) /******************************************************************************* * Device Bus Registers diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index cb19e1661bb..b36f928d017 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -198,7 +198,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /***************************************************************************** * PCI controller ****************************************************************************/ -#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x)) #define PCI_MODE ORION5X_PCI_REG(0xd00) #define PCI_CMD ORION5X_PCI_REG(0xc00) #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) -- cgit v1.2.3-70-g09d2 From c3c5a2815d0b7ebde157556685a0ef8ffa34b98c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:18 +0200 Subject: arm: mach-dove: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-dove code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/addr-map.c | 2 +- arch/arm/mach-dove/common.c | 25 +++++++++++++++---------- arch/arm/mach-dove/include/mach/dove.h | 12 ++++++------ arch/arm/mach-dove/irq.c | 10 +++++----- arch/arm/mach-dove/mpp.c | 3 ++- arch/arm/mach-dove/pcie.c | 6 +++--- 6 files changed, 32 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c index 2a06c016341..b92c9c7d1d6 100644 --- a/arch/arm/mach-dove/addr-map.c +++ b/arch/arm/mach-dove/addr-map.c @@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i) static struct __initdata orion_addr_map_cfg addr_map_cfg = { .num_wins = 8, .remappable_wins = 4, - .bridge_virt_base = BRIDGE_VIRT_BASE, + .bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 6321567d8ea..533fd8123c7 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -40,22 +40,22 @@ static int get_tclk(void); ****************************************************************************/ static struct map_desc dove_io_desc[] __initdata = { { - .virtual = DOVE_SB_REGS_VIRT_BASE, + .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), .length = DOVE_SB_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = DOVE_NB_REGS_VIRT_BASE, + .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .length = DOVE_NB_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = DOVE_PCIE0_IO_VIRT_BASE, + .virtual = (unsigned long) DOVE_PCIE0_IO_VIRT_BASE, .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), .length = DOVE_PCIE0_IO_SIZE, .type = MT_DEVICE, }, { - .virtual = DOVE_PCIE1_IO_VIRT_BASE, + .virtual = (unsigned long) DOVE_PCIE1_IO_VIRT_BASE, .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), .length = DOVE_PCIE1_IO_SIZE, .type = MT_DEVICE, @@ -128,7 +128,8 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init dove_uart0_init(void) { - orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, + orion_uart0_init((unsigned long) DOVE_UART0_VIRT_BASE, + DOVE_UART0_PHYS_BASE, IRQ_DOVE_UART_0, tclk); } @@ -137,7 +138,8 @@ void __init dove_uart0_init(void) ****************************************************************************/ void __init dove_uart1_init(void) { - orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, + orion_uart1_init((unsigned long) DOVE_UART1_VIRT_BASE, + DOVE_UART1_PHYS_BASE, IRQ_DOVE_UART_1, tclk); } @@ -146,7 +148,8 @@ void __init dove_uart1_init(void) ****************************************************************************/ void __init dove_uart2_init(void) { - orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, + orion_uart2_init((unsigned long) DOVE_UART2_VIRT_BASE, + DOVE_UART2_PHYS_BASE, IRQ_DOVE_UART_2, tclk); } @@ -155,7 +158,8 @@ void __init dove_uart2_init(void) ****************************************************************************/ void __init dove_uart3_init(void) { - orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, + orion_uart3_init((unsigned long) DOVE_UART3_VIRT_BASE, + DOVE_UART3_PHYS_BASE, IRQ_DOVE_UART_3, tclk); } @@ -185,7 +189,7 @@ void __init dove_i2c_init(void) ****************************************************************************/ void __init dove_init_early(void) { - orion_time_set_base(TIMER_VIRT_BASE); + orion_time_set_base((unsigned long) TIMER_VIRT_BASE); } static int get_tclk(void) @@ -196,7 +200,8 @@ static int get_tclk(void) static void __init dove_timer_init(void) { - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + orion_time_init((unsigned long) BRIDGE_VIRT_BASE, + BRIDGE_INT_TIMER1_CLR, IRQ_DOVE_BRIDGE, get_tclk()); } diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index cccfd1d45f4..735dd2ef393 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -25,7 +25,7 @@ */ #define DOVE_CESA_PHYS_BASE 0xc8000000 -#define DOVE_CESA_VIRT_BASE 0xfdb00000 +#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) #define DOVE_CESA_SIZE SZ_1M #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 @@ -38,24 +38,24 @@ #define DOVE_BOOTROM_SIZE SZ_128M #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 -#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000 +#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) #define DOVE_SCRATCHPAD_SIZE SZ_1M #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 -#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) #define DOVE_SB_REGS_SIZE SZ_8M #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 -#define DOVE_NB_REGS_VIRT_BASE 0xfe600000 +#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000) #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 -#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 +#define DOVE_PCIE0_IO_VIRT_BASE IOMEM(0xfee00000) #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 #define DOVE_PCIE0_IO_SIZE SZ_1M #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 +#define DOVE_PCIE1_IO_VIRT_BASE IOMEM(0xfef00000) #define DOVE_PCIE1_IO_BUS_BASE 0x00100000 #define DOVE_PCIE1_IO_SIZE SZ_1M diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 9bc97a5baaa..4ce306aff49 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -99,19 +99,19 @@ void __init dove_init_irq(void) { int i; - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); /* * Initialize gpiolib for GPIOs 0-71. */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0, + orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START, gpio0_irqs); - orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0, + orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32, gpio1_irqs); - orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0, + orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64, gpio2_irqs); /* diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 7f70afc26f9..fc04ebefbeb 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -151,7 +151,8 @@ void __init dove_mpp_conf(unsigned int *mpp_list, dove_mpp_dump_regs(); /* Use platform code for pins 0-23 */ - orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE); + orion_mpp_conf(mpp_list, 0, MPP_MAX, + (unsigned long) DOVE_MPP_VIRT_BASE); dove_mpp_conf_grp(mpp_grp_list); dove_mpp_cfg_au1(grp_au1_52_57); diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index 47921b0cdc6..b3724414fd1 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -197,18 +197,18 @@ static struct hw_pci dove_pci __initdata = { .map_irq = dove_pcie_map_irq, }; -static void __init add_pcie_port(int index, unsigned long base) +static void __init add_pcie_port(int index, void __iomem *base) { printk(KERN_INFO "Dove PCIe port %d: ", index); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { struct pcie_port *pp = &pcie_port[num_pcie_ports++]; printk(KERN_INFO "link up\n"); pp->index = index; pp->root_bus_nr = -1; - pp->base = (void __iomem *)base; + pp->base = base; spin_lock_init(&pp->conf_lock); memset(pp->res, 0, sizeof(pp->res)); } else { -- cgit v1.2.3-70-g09d2 From 060f3d191b1d80312d7c90de2f3c3356db413f40 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:19 +0200 Subject: arm: mach-kirkwood: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-kirkwood code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/addr-map.c | 2 +- arch/arm/mach-kirkwood/common.c | 23 ++++++++++++----------- arch/arm/mach-kirkwood/include/mach/kirkwood.h | 6 +++--- arch/arm/mach-kirkwood/irq.c | 9 +++++---- arch/arm/mach-kirkwood/mpp.c | 3 ++- arch/arm/mach-kirkwood/pcie.c | 12 ++++++------ arch/arm/mach-kirkwood/ts41x-setup.c | 3 ++- 7 files changed, 31 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index e9a7180863d..1b8c75c529d 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -41,7 +41,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = { .num_wins = 8, .remappable_wins = 4, - .bridge_virt_base = BRIDGE_VIRT_BASE, + .bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 1201191d7f1..75bc04da8d9 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -42,17 +42,17 @@ ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { - .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, + .virtual = (unsigned long) KIRKWOOD_PCIE_IO_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), .length = KIRKWOOD_PCIE_IO_SIZE, .type = MT_DEVICE, }, { - .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, + .virtual = (unsigned long) KIRKWOOD_PCIE1_IO_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), .length = KIRKWOOD_PCIE1_IO_SIZE, .type = MT_DEVICE, }, { - .virtual = KIRKWOOD_REGS_VIRT_BASE, + .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, .type = MT_DEVICE, @@ -215,8 +215,7 @@ static struct clk *tclk; static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) { - return clk_register_gate(NULL, name, "tclk", 0, - (void __iomem *)CLOCK_GATING_CTRL, + return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, bit_idx, 0, &gating_lock); } @@ -225,8 +224,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name, void (*fn_en)(void), void (*fn_dis)(void)) { - return clk_register_gate_fn(NULL, name, "tclk", 0, - (void __iomem *)CLOCK_GATING_CTRL, + return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL, bit_idx, 0, &gating_lock, fn_en, fn_dis); } @@ -458,7 +456,8 @@ void __init kirkwood_i2c_init(void) void __init kirkwood_uart0_init(void) { - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + orion_uart0_init((unsigned long) UART0_VIRT_BASE, + UART0_PHYS_BASE, IRQ_KIRKWOOD_UART_0, tclk); } @@ -468,7 +467,8 @@ void __init kirkwood_uart0_init(void) ****************************************************************************/ void __init kirkwood_uart1_init(void) { - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + orion_uart1_init((unsigned long) UART1_VIRT_BASE, + UART1_PHYS_BASE, IRQ_KIRKWOOD_UART_1, tclk); } @@ -516,7 +516,7 @@ void __init kirkwood_wdt_init(void) ****************************************************************************/ void __init kirkwood_init_early(void) { - orion_time_set_base(TIMER_VIRT_BASE); + orion_time_set_base((unsigned long) TIMER_VIRT_BASE); /* * Some Kirkwood devices allocate their coherent buffers from atomic @@ -545,7 +545,8 @@ static void __init kirkwood_timer_init(void) { kirkwood_tclk = kirkwood_find_tclk(); - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + orion_time_init((unsigned long) BRIDGE_VIRT_BASE, + BRIDGE_INT_TIMER1_CLR, IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); } diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 9695592d332..d3ea68269c9 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -37,17 +37,17 @@ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE1_IO_VIRT_BASE IOMEM(0xfef00000) #define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 #define KIRKWOOD_PCIE1_IO_SIZE SZ_1M #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE IOMEM(0xfee00000) #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 #define KIRKWOOD_PCIE_IO_SIZE SZ_1M #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 -#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 +#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000) #define KIRKWOOD_REGS_SIZE SZ_1M #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index 720063ffa19..f4ac804dc66 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -29,14 +30,14 @@ static int __initdata gpio1_irqs[4] = { void __init kirkwood_init_irq(void) { - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); /* * Initialize gpiolib for GPIOs 0-49. */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0, + orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START, gpio0_irqs); - orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0, + orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs); } diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 0c6ad63f10c..67742793f3c 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -38,5 +38,6 @@ static unsigned int __init kirkwood_variant(void) void __init kirkwood_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, kirkwood_variant(), - MPP_MAX, DEV_BUS_VIRT_BASE); + MPP_MAX, + (unsigned long) DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 6e8b2efa3c3..df6399dea74 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void) void kirkwood_pcie_id(u32 *dev, u32 *rev) { kirkwood_enable_pcie(); - *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); - *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE); + *dev = orion_pcie_dev_id(PCIE_VIRT_BASE); + *rev = orion_pcie_rev(PCIE_VIRT_BASE); } struct pcie_port { @@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = { static void __init pcie0_ioresources_init(struct pcie_port *pp) { - pp->base = (void __iomem *)PCIE_VIRT_BASE; + pp->base = PCIE_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE; /* @@ -155,7 +155,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp) static void __init pcie1_ioresources_init(struct pcie_port *pp) { - pp->base = (void __iomem *)PCIE1_VIRT_BASE; + pp->base = PCIE1_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE1; /* @@ -273,11 +273,11 @@ static struct hw_pci kirkwood_pci __initdata = { .map_irq = kirkwood_pcie_map_irq, }; -static void __init add_pcie_port(int index, unsigned long base) +static void __init add_pcie_port(int index, void __iomem *base) { printk(KERN_INFO "Kirkwood PCIe port %d: ", index); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { printk(KERN_INFO "link up\n"); pcie_port_map[num_pcie_ports++] = index; } else diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c index 5bbca268044..367a9400f53 100644 --- a/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/arch/arm/mach-kirkwood/ts41x-setup.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void) * (Marvell 88sx7042/sata_mv) is known to stop working * after a few minutes. */ - orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE); + orion_pcie_reset(PCIE_VIRT_BASE); kirkwood_pcie_id(&dev, &rev); if (dev == MV88F6282_DEV_ID) -- cgit v1.2.3-70-g09d2 From 383b99610e6084878930d4e4682dfc5e9141b038 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:20 +0200 Subject: arm: mach-mv78xx0: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-mv78xx0 code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/addr-map.c | 2 +- arch/arm/mach-mv78xx0/common.c | 23 ++++++++++++++--------- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 6 +++--- arch/arm/mach-mv78xx0/irq.c | 9 +++++---- arch/arm/mach-mv78xx0/mpp.c | 3 ++- arch/arm/mach-mv78xx0/pcie.c | 12 ++++++------ 6 files changed, 31 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index a9bc84180d2..3358f079bcd 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -47,7 +47,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i * so we don't need to take that into account here. */ - return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); + return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win); } /* diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 3057f7d4329..c4e3458e067 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -130,17 +130,17 @@ static int get_tclk(void) ****************************************************************************/ static struct map_desc mv78xx0_io_desc[] __initdata = { { - .virtual = MV78XX0_CORE_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE, .pfn = 0, .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), + .virtual = (unsigned long) MV78XX0_PCIE_IO_VIRT_BASE(0), .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), .length = MV78XX0_PCIE_IO_SIZE * 8, .type = MT_DEVICE, }, { - .virtual = MV78XX0_REGS_VIRT_BASE, + .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), .length = MV78XX0_REGS_SIZE, .type = MT_DEVICE, @@ -300,7 +300,8 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init mv78xx0_uart0_init(void) { - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + orion_uart0_init((unsigned long) UART0_VIRT_BASE, + UART0_PHYS_BASE, IRQ_MV78XX0_UART_0, tclk); } @@ -310,7 +311,8 @@ void __init mv78xx0_uart0_init(void) ****************************************************************************/ void __init mv78xx0_uart1_init(void) { - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + orion_uart1_init((unsigned long) UART1_VIRT_BASE, + UART1_PHYS_BASE, IRQ_MV78XX0_UART_1, tclk); } @@ -320,7 +322,8 @@ void __init mv78xx0_uart1_init(void) ****************************************************************************/ void __init mv78xx0_uart2_init(void) { - orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, + orion_uart2_init((unsigned long) UART2_VIRT_BASE, + UART2_PHYS_BASE, IRQ_MV78XX0_UART_2, tclk); } @@ -329,7 +332,8 @@ void __init mv78xx0_uart2_init(void) ****************************************************************************/ void __init mv78xx0_uart3_init(void) { - orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, + orion_uart3_init((unsigned long) UART3_VIRT_BASE, + UART3_PHYS_BASE, IRQ_MV78XX0_UART_3, tclk); } @@ -338,12 +342,13 @@ void __init mv78xx0_uart3_init(void) ****************************************************************************/ void __init mv78xx0_init_early(void) { - orion_time_set_base(TIMER_VIRT_BASE); + orion_time_set_base((unsigned long) TIMER_VIRT_BASE); } static void mv78xx0_timer_init(void) { - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + orion_time_init((unsigned long) BRIDGE_VIRT_BASE, + BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); } diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index a86e79ecfea..62405e8dda0 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -41,16 +41,16 @@ */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_VIRT_BASE(i) IOMEM(0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfef00000) #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index eff9a750bbe..b5c40c4f524 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include "common.h" @@ -23,16 +24,16 @@ static int __initdata gpio0_irqs[4] = { void __init mv78xx0_init_irq(void) { - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); - orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); + orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of * core #0.) */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index df50342179e..4da82f85d1c 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -33,5 +33,6 @@ static unsigned int __init mv78xx0_variant(void) void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, mv78xx0_variant(), - MPP_MAX, DEV_BUS_VIRT_BASE); + MPP_MAX, + (unsigned long) DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 2e56e86b6d6..e2940fbbcd6 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -36,8 +36,8 @@ static struct resource pcie_mem_space; void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { - *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); - *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); + *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE); + *rev = orion_pcie_rev(PCIE00_VIRT_BASE); } static void __init mv78xx0_pcie_preinit(void) @@ -267,11 +267,11 @@ static struct hw_pci mv78xx0_pci __initdata = { .map_irq = mv78xx0_pcie_map_irq, }; -static void __init add_pcie_port(int maj, int min, unsigned long base) +static void __init add_pcie_port(int maj, int min, void __iomem *base) { printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); - if (orion_pcie_link_up((void __iomem *)base)) { + if (orion_pcie_link_up(base)) { struct pcie_port *pp = &pcie_port[num_pcie_ports++]; printk("link up\n"); @@ -279,7 +279,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->maj = maj; pp->min = min; pp->root_bus_nr = -1; - pp->base = (void __iomem *)base; + pp->base = base; spin_lock_init(&pp->conf_lock); memset(pp->res, 0, sizeof(pp->res)); } else { @@ -293,7 +293,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1) if (init_port0) { add_pcie_port(0, 0, PCIE00_VIRT_BASE); - if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { + if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) { add_pcie_port(0, 1, PCIE01_VIRT_BASE); add_pcie_port(0, 2, PCIE02_VIRT_BASE); add_pcie_port(0, 3, PCIE03_VIRT_BASE); -- cgit v1.2.3-70-g09d2 From 3904a39321422d424f790d18a4746b99e1aed0e9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:21 +0200 Subject: arm: mach-orion5x: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-orion5x code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-orion5x/addr-map.c | 2 +- arch/arm/mach-orion5x/common.c | 19 +++++++++++-------- arch/arm/mach-orion5x/dns323-setup.c | 2 +- arch/arm/mach-orion5x/include/mach/orion5x.h | 8 ++++---- arch/arm/mach-orion5x/irq.c | 5 +++-- arch/arm/mach-orion5x/mpp.c | 3 ++- arch/arm/mach-orion5x/pci.c | 4 ++-- 7 files changed, 24 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index eaac83d1df6..d309f53b7a0 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, static struct orion_addr_map_cfg addr_map_cfg __initdata = { .num_wins = 8, .cpu_win_can_remap = cpu_win_can_remap, - .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, + .bridge_virt_base = (unsigned long) ORION5X_BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 410291c6766..a890cb0eb83 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -42,22 +42,22 @@ ****************************************************************************/ static struct map_desc orion5x_io_desc[] __initdata = { { - .virtual = ORION5X_REGS_VIRT_BASE, + .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), .length = ORION5X_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_IO_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCIE_IO_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), .length = ORION5X_PCIE_IO_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCI_IO_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCI_IO_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), .length = ORION5X_PCI_IO_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_WA_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .length = ORION5X_PCIE_WA_SIZE, .type = MT_DEVICE, @@ -156,7 +156,8 @@ void __init orion5x_spi_init() ****************************************************************************/ void __init orion5x_uart0_init(void) { - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + orion_uart0_init((unsigned long) UART0_VIRT_BASE, + UART0_PHYS_BASE, IRQ_ORION5X_UART0, tclk); } @@ -165,7 +166,8 @@ void __init orion5x_uart0_init(void) ****************************************************************************/ void __init orion5x_uart1_init(void) { - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + orion_uart1_init((unsigned long) UART1_VIRT_BASE, + UART1_PHYS_BASE, IRQ_ORION5X_UART1, tclk); } @@ -203,7 +205,7 @@ void __init orion5x_wdt_init(void) ****************************************************************************/ void __init orion5x_init_early(void) { - orion_time_set_base(TIMER_VIRT_BASE); + orion_time_set_base((unsigned long) TIMER_VIRT_BASE); } int orion5x_tclk; @@ -224,7 +226,8 @@ static void __init orion5x_timer_init(void) { orion5x_tclk = orion5x_find_tclk(); - orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + orion_time_init((unsigned long) ORION5X_BRIDGE_VIRT_BASE, + BRIDGE_INT_TIMER1_CLR, IRQ_ORION5X_BRIDGE, orion5x_tclk); } diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index d470864b4e4..3a5e6fc197f 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -700,7 +700,7 @@ static void __init dns323_init(void) * Note: AFAIK, rev B1 needs the same treatement but I'll let * somebody else test it. */ - writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c); + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); break; } } diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 87bd378b820..6fd38ab5e26 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -37,16 +37,16 @@ * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_VIRT_BASE IOMEM(0xfdd00000) #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION5X_PCIE_IO_VIRT_BASE IOMEM(0xfde00000) #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 #define ORION5X_PCIE_IO_SIZE SZ_1M #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_VIRT_BASE IOMEM(0xfdf00000) #define ORION5X_PCI_IO_BUS_BASE 0x00100000 #define ORION5X_PCI_IO_SIZE SZ_1M @@ -55,7 +55,7 @@ /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfe000000) #define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 17da7091d31..bf9ff4f0081 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -24,11 +25,11 @@ static int __initdata gpio0_irqs[4] = { void __init orion5x_init_irq(void) { - orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); + orion_irq_init(0, MAIN_IRQ_MASK); /* * Initialize gpiolib for GPIOs 0-31. */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0, + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 5b70026f478..30f5ef6e2ec 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -40,5 +40,6 @@ static unsigned int __init orion5x_variant(void) void __init orion5x_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, orion5x_variant(), - MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE); + MPP_MAX, + (unsigned long) ORION5X_DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index b36f928d017..b0822a864e0 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -38,7 +38,7 @@ /***************************************************************************** * PCIe controller ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) +#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE) void __init orion5x_pcie_id(u32 *dev, u32 *rev) { @@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, return PCIBIOS_DEVICE_NOT_FOUND; } - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, + ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val); return ret; -- cgit v1.2.3-70-g09d2 From 9758e70a448f92fb850712650a0394d8532c17ff Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:22 +0200 Subject: arm: mach-mvebu: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-mvebu code. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/armada-370-xp.c | 2 +- arch/arm/mach-mvebu/include/mach/armada-370-xp.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 4ef923b032e..dfe635b4813 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -25,7 +25,7 @@ static struct map_desc armada_370_xp_io_desc[] __initdata = { { - .virtual = ARMADA_370_XP_REGS_VIRT_BASE, + .virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE, .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE), .length = ARMADA_370_XP_REGS_SIZE, .type = MT_DEVICE, diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h index 25f0ca8d782..aac9bebc6b0 100644 --- a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h +++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h @@ -16,7 +16,7 @@ #define __MACH_ARMADA_370_XP_H #define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 -#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 +#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000) #define ARMADA_370_XP_REGS_SIZE SZ_1M #endif /* __MACH_ARMADA_370_XP_H */ -- cgit v1.2.3-70-g09d2 From d19beac1d9358bb4a2a303f4327bf2d40ba88464 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:23 +0200 Subject: arm: plat-orion: use void __iomem pointers for UART registration functions The registration functions for UARTs now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 12 ++++-------- arch/arm/mach-kirkwood/common.c | 6 ++---- arch/arm/mach-mv78xx0/common.c | 12 ++++-------- arch/arm/mach-orion5x/common.c | 6 ++---- arch/arm/plat-orion/common.c | 12 ++++++------ arch/arm/plat-orion/include/plat/common.h | 8 ++++---- 6 files changed, 22 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 533fd8123c7..ba55f631ccc 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -128,8 +128,7 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init dove_uart0_init(void) { - orion_uart0_init((unsigned long) DOVE_UART0_VIRT_BASE, - DOVE_UART0_PHYS_BASE, + orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, IRQ_DOVE_UART_0, tclk); } @@ -138,8 +137,7 @@ void __init dove_uart0_init(void) ****************************************************************************/ void __init dove_uart1_init(void) { - orion_uart1_init((unsigned long) DOVE_UART1_VIRT_BASE, - DOVE_UART1_PHYS_BASE, + orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, IRQ_DOVE_UART_1, tclk); } @@ -148,8 +146,7 @@ void __init dove_uart1_init(void) ****************************************************************************/ void __init dove_uart2_init(void) { - orion_uart2_init((unsigned long) DOVE_UART2_VIRT_BASE, - DOVE_UART2_PHYS_BASE, + orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, IRQ_DOVE_UART_2, tclk); } @@ -158,8 +155,7 @@ void __init dove_uart2_init(void) ****************************************************************************/ void __init dove_uart3_init(void) { - orion_uart3_init((unsigned long) DOVE_UART3_VIRT_BASE, - DOVE_UART3_PHYS_BASE, + orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, IRQ_DOVE_UART_3, tclk); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 75bc04da8d9..defceca5184 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -456,8 +456,7 @@ void __init kirkwood_i2c_init(void) void __init kirkwood_uart0_init(void) { - orion_uart0_init((unsigned long) UART0_VIRT_BASE, - UART0_PHYS_BASE, + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, IRQ_KIRKWOOD_UART_0, tclk); } @@ -467,8 +466,7 @@ void __init kirkwood_uart0_init(void) ****************************************************************************/ void __init kirkwood_uart1_init(void) { - orion_uart1_init((unsigned long) UART1_VIRT_BASE, - UART1_PHYS_BASE, + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, IRQ_KIRKWOOD_UART_1, tclk); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index c4e3458e067..fcda4a4f830 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -300,8 +300,7 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init mv78xx0_uart0_init(void) { - orion_uart0_init((unsigned long) UART0_VIRT_BASE, - UART0_PHYS_BASE, + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, IRQ_MV78XX0_UART_0, tclk); } @@ -311,8 +310,7 @@ void __init mv78xx0_uart0_init(void) ****************************************************************************/ void __init mv78xx0_uart1_init(void) { - orion_uart1_init((unsigned long) UART1_VIRT_BASE, - UART1_PHYS_BASE, + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, IRQ_MV78XX0_UART_1, tclk); } @@ -322,8 +320,7 @@ void __init mv78xx0_uart1_init(void) ****************************************************************************/ void __init mv78xx0_uart2_init(void) { - orion_uart2_init((unsigned long) UART2_VIRT_BASE, - UART2_PHYS_BASE, + orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, IRQ_MV78XX0_UART_2, tclk); } @@ -332,8 +329,7 @@ void __init mv78xx0_uart2_init(void) ****************************************************************************/ void __init mv78xx0_uart3_init(void) { - orion_uart3_init((unsigned long) UART3_VIRT_BASE, - UART3_PHYS_BASE, + orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, IRQ_MV78XX0_UART_3, tclk); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index a890cb0eb83..79f9ffb9a14 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -156,8 +156,7 @@ void __init orion5x_spi_init() ****************************************************************************/ void __init orion5x_uart0_init(void) { - orion_uart0_init((unsigned long) UART0_VIRT_BASE, - UART0_PHYS_BASE, + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, IRQ_ORION5X_UART0, tclk); } @@ -166,8 +165,7 @@ void __init orion5x_uart0_init(void) ****************************************************************************/ void __init orion5x_uart1_init(void) { - orion_uart1_init((unsigned long) UART1_VIRT_BASE, - UART1_PHYS_BASE, + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, IRQ_ORION5X_UART1, tclk); } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index b8b747a9d36..5bed7113994 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -86,13 +86,13 @@ static void __init uart_complete( struct platform_device *orion_uart, struct plat_serial8250_port *data, struct resource *resources, - unsigned int membase, + void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) { data->mapbase = mapbase; - data->membase = (void __iomem *)membase; + data->membase = membase; data->irq = irq; data->uartclk = uart_get_clk_rate(clk); orion_uart->dev.platform_data = data; @@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = { .id = PLAT8250_DEV_PLATFORM, }; -void __init orion_uart0_init(unsigned int membase, +void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = { .id = PLAT8250_DEV_PLATFORM1, }; -void __init orion_uart1_init(unsigned int membase, +void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = { .id = PLAT8250_DEV_PLATFORM2, }; -void __init orion_uart2_init(unsigned int membase, +void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = { .id = 3, }; -void __init orion_uart3_init(unsigned int membase, +void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index ae2377ef63e..6bbc3fe5f58 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -13,22 +13,22 @@ struct dsa_platform_data; -void __init orion_uart0_init(unsigned int membase, +void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart1_init(unsigned int membase, +void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart2_init(unsigned int membase, +void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart3_init(unsigned int membase, +void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -- cgit v1.2.3-70-g09d2 From 5a2f55019391218d8c08c6f9d32591d91200de77 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:24 +0200 Subject: arm: plat-orion: use void __iomem pointers for MPP functions The registration function for MPP now takes void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/mpp.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/mpp.c | 3 +-- arch/arm/mach-kirkwood/mpp.c | 3 +-- arch/arm/mach-mv78xx0/mpp.c | 3 +-- arch/arm/mach-orion5x/mpp.c | 3 +-- arch/arm/plat-orion/include/plat/mpp.h | 2 +- arch/arm/plat-orion/mpp.c | 6 +++--- 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index fc04ebefbeb..7f70afc26f9 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -151,8 +151,7 @@ void __init dove_mpp_conf(unsigned int *mpp_list, dove_mpp_dump_regs(); /* Use platform code for pins 0-23 */ - orion_mpp_conf(mpp_list, 0, MPP_MAX, - (unsigned long) DOVE_MPP_VIRT_BASE); + orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE); dove_mpp_conf_grp(mpp_grp_list); dove_mpp_cfg_au1(grp_au1_52_57); diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 67742793f3c..0c6ad63f10c 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -38,6 +38,5 @@ static unsigned int __init kirkwood_variant(void) void __init kirkwood_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, kirkwood_variant(), - MPP_MAX, - (unsigned long) DEV_BUS_VIRT_BASE); + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index 4da82f85d1c..df50342179e 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -33,6 +33,5 @@ static unsigned int __init mv78xx0_variant(void) void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, mv78xx0_variant(), - MPP_MAX, - (unsigned long) DEV_BUS_VIRT_BASE); + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 30f5ef6e2ec..5b70026f478 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -40,6 +40,5 @@ static unsigned int __init orion5x_variant(void) void __init orion5x_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, orion5x_variant(), - MPP_MAX, - (unsigned long) ORION5X_DEV_BUS_VIRT_BASE); + MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h index 723adce99f4..254552fee88 100644 --- a/arch/arm/plat-orion/include/plat/mpp.h +++ b/arch/arm/plat-orion/include/plat/mpp.h @@ -29,6 +29,6 @@ #define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1) void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, - unsigned int mpp_max, unsigned int dev_bus); + unsigned int mpp_max, void __iomem *dev_bus); #endif diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index 3b1e17bd3d1..20d4208436c 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -17,15 +17,15 @@ #include /* Address of the ith MPP control register */ -static __init unsigned long mpp_ctrl_addr(unsigned int i, - unsigned long dev_bus) +static __init void __iomem *mpp_ctrl_addr(unsigned int i, + void __iomem *dev_bus) { return dev_bus + (i) * 4; } void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, - unsigned int mpp_max, unsigned int dev_bus) + unsigned int mpp_max, void __iomem *dev_bus) { unsigned int mpp_nr_regs = (1 + mpp_max/8); u32 mpp_ctrl[mpp_nr_regs]; -- cgit v1.2.3-70-g09d2 From e96a0309f8545d539c1bf4acd5b58727a8f39818 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:25 +0200 Subject: arm: plat-orion: use void __iomem pointers for time functions The functions for time management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 5 ++--- arch/arm/mach-kirkwood/common.c | 5 ++--- arch/arm/mach-mv78xx0/common.c | 5 ++--- arch/arm/mach-orion5x/common.c | 5 ++--- arch/arm/plat-orion/include/plat/time.h | 4 ++-- arch/arm/plat-orion/time.c | 8 ++++---- 6 files changed, 14 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index ba55f631ccc..cb655998466 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -185,7 +185,7 @@ void __init dove_i2c_init(void) ****************************************************************************/ void __init dove_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); } static int get_tclk(void) @@ -196,8 +196,7 @@ static int get_tclk(void) static void __init dove_timer_init(void) { - orion_time_init((unsigned long) BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_DOVE_BRIDGE, get_tclk()); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index defceca5184..55bf9198cae 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -514,7 +514,7 @@ void __init kirkwood_wdt_init(void) ****************************************************************************/ void __init kirkwood_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); /* * Some Kirkwood devices allocate their coherent buffers from atomic @@ -543,8 +543,7 @@ static void __init kirkwood_timer_init(void) { kirkwood_tclk = kirkwood_find_tclk(); - orion_time_init((unsigned long) BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index fcda4a4f830..f123517a4bb 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -338,13 +338,12 @@ void __init mv78xx0_uart3_init(void) ****************************************************************************/ void __init mv78xx0_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); } static void mv78xx0_timer_init(void) { - orion_time_init((unsigned long) BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 79f9ffb9a14..58b754ff701 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -203,7 +203,7 @@ void __init orion5x_wdt_init(void) ****************************************************************************/ void __init orion5x_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); } int orion5x_tclk; @@ -224,8 +224,7 @@ static void __init orion5x_timer_init(void) { orion5x_tclk = orion5x_find_tclk(); - orion_time_init((unsigned long) ORION5X_BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_ORION5X_BRIDGE, orion5x_tclk); } diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h index 4d5f1f6e18d..07527e417c6 100644 --- a/arch/arm/plat-orion/include/plat/time.h +++ b/arch/arm/plat-orion/include/plat/time.h @@ -11,9 +11,9 @@ #ifndef __PLAT_TIME_H #define __PLAT_TIME_H -void orion_time_set_base(u32 timer_base); +void orion_time_set_base(void __iomem *timer_base); -void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask, +void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask, unsigned int irq, unsigned int tclk); diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 1ed8d1397fc..0f4fa863dd5 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = { }; void __init -orion_time_set_base(u32 _timer_base) +orion_time_set_base(void __iomem *_timer_base) { - timer_base = (void __iomem *)_timer_base; + timer_base = _timer_base; } void __init -orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, +orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, unsigned int irq, unsigned int tclk) { u32 u; @@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, /* * Set SoC-specific data. */ - bridge_base = (void __iomem *)_bridge_base; + bridge_base = _bridge_base; bridge_timer1_clr_mask = _bridge_timer1_clr_mask; ticks_per_jiffy = (tclk + HZ/2) / HZ; -- cgit v1.2.3-70-g09d2 From 9b7b7d8b024d3e44412abbbb0206ab8f60c459ad Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:26 +0200 Subject: arm: plat-orion: use void __iomem pointers for addr-map functions The functions for address mapping management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/addr-map.c | 2 +- arch/arm/mach-kirkwood/addr-map.c | 5 +++-- arch/arm/mach-mv78xx0/addr-map.c | 4 ++-- arch/arm/mach-orion5x/addr-map.c | 5 +++-- arch/arm/plat-orion/addr-map.c | 11 ++++------- arch/arm/plat-orion/include/plat/addr-map.h | 4 ++-- 6 files changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c index b92c9c7d1d6..2a06c016341 100644 --- a/arch/arm/mach-dove/addr-map.c +++ b/arch/arm/mach-dove/addr-map.c @@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i) static struct __initdata orion_addr_map_cfg addr_map_cfg = { .num_wins = 8, .remappable_wins = 4, - .bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE, + .bridge_virt_base = BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 1b8c75c529d..8f0d162a1e1 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -41,7 +41,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = { .num_wins = 8, .remappable_wins = 4, - .bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE, + .bridge_virt_base = BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { @@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void) /* * Setup MBUS dram target info. */ - orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); + orion_setup_cpu_mbus_target(&addr_map_cfg, + (void __iomem *) DDR_WINDOW_CPU_BASE); } diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 3358f079bcd..a51fc247e73 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void) */ if (mv78xx0_core_index() == 0) orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU0_BASE); + (void __iomem *) DDR_WINDOW_CPU0_BASE); else orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU1_BASE); + (void __iomem *) DDR_WINDOW_CPU1_BASE); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index d309f53b7a0..b5efc0fd31c 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, static struct orion_addr_map_cfg addr_map_cfg __initdata = { .num_wins = 8, .cpu_win_can_remap = cpu_win_can_remap, - .bridge_virt_base = (unsigned long) ORION5X_BRIDGE_VIRT_BASE, + .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { @@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void) /* * Setup MBUS dram target info. */ - orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); + orion_setup_cpu_mbus_target(&addr_map_cfg, + (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE); } void __init orion5x_setup_dev_boot_win(u32 base, u32 size) diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index 367ca89ac40..a7b8060c293 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info); static void __init __iomem * orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) { - return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); + return cfg->bridge_virt_base + (win << 4); } /* @@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg, * Setup MBUS dram target info. */ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, - const u32 ddr_window_cpu_base) + const void __iomem *ddr_window_cpu_base) { - void __iomem *addr; int i; int cs; orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - addr = (void __iomem *)ddr_window_cpu_base; - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i)); + u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); /* * Chip select enabled? diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h index fd556f77562..0a746fdfaf7 100644 --- a/arch/arm/plat-orion/include/plat/addr-map.h +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; struct orion_addr_map_cfg { const int num_wins; /* Total number of windows */ const int remappable_wins; - const u32 bridge_virt_base; + void __iomem * const bridge_virt_base; /* If NULL, the default cpu_win_can_remap will be used, using the value in remappable_wins */ @@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, const u8 attr, const int remap); void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, - const u32 ddr_window_cpu_base); + const void __iomem *ddr_window_cpu_base); #endif -- cgit v1.2.3-70-g09d2 From abcda1dc3e23366c8543b372e9bf4e9086d5cca1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:27 +0200 Subject: arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option Until now, the PLAT_ORION configuration option was common to all the Marvell EBU SoCs, and selecting this option had the effect of enabling the MPP code, GPIO code, address decoding and PCIe code from plat-orion, as well as providing access to driver-specific header files from plat-orion/include. However, the Armada 370 and XP SoCs will not use the MPP and GPIO code (instead some proper pinctrl and gpio drivers are in preparation), and generally, we want to move away from plat-orion and instead have everything in mach-mvebu. That said, in the mean time, we want to leverage the driver-specific headers as well as the address decoding code, so we introduce PLAT_ORION_LEGACY. The older Marvell SoCs need to select PLAT_ORION_LEGACY, while the newer Marvell SoCs need to select PLAT_ORION. Of course, when PLAT_ORION_LEGACY is selected, it automatically selects PLAT_ORION. Then, with just PLAT_ORION, you have the address decoding code plus the driver-specific headers. If you add PLAT_ORION_LEGACY to this, you gain the old MPP, GPIO and PCIe code. Again, this is only a temporary solution until we make all Marvell EBU platforms converge into the mach-mvebu directory. This solution avoids duplicating the existing address decoding code into mach-mvebu. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/Kconfig | 13 +++++++++---- arch/arm/plat-orion/Makefile | 9 ++++----- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2f88d8d9770..a4eab57bee2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -567,6 +567,7 @@ config ARCH_MVEBU select GENERIC_IRQ_CHIP select IRQ_DOMAIN select COMMON_CLK + select PLAT_ORION help Support for the Marvell SoC Family with device tree support @@ -577,7 +578,7 @@ config ARCH_DOVE select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select NEED_MACH_IO_H - select PLAT_ORION + select PLAT_ORION_LEGACY help Support for the Marvell Dove SoC 88AP510 @@ -588,7 +589,7 @@ config ARCH_KIRKWOOD select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select NEED_MACH_IO_H - select PLAT_ORION + select PLAT_ORION_LEGACY help Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281. @@ -615,7 +616,7 @@ config ARCH_MV78XX0 select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select NEED_MACH_IO_H - select PLAT_ORION + select PLAT_ORION_LEGACY help Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. @@ -628,7 +629,7 @@ config ARCH_ORION5X select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select NEED_MACH_IO_H - select PLAT_ORION + select PLAT_ORION_LEGACY help Support for the following Marvell Orion 5x series SoCs: Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), @@ -1148,6 +1149,10 @@ config PLAT_ORION select IRQ_DOMAIN select COMMON_CLK +config PLAT_ORION_LEGACY + bool + select PLAT_ORION + config PLAT_PXA bool diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index c20ce0f5ce3..1251e5bd41c 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,9 +2,8 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o -obj-m := -obj-n := -obj- := +obj-y += addr-map.o -obj-$(CONFIG_GENERIC_GPIO) += gpio.o +orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o +obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y) -- cgit v1.2.3-70-g09d2 From 87d136415c78c02680dc474cb4093ba7911b07a4 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:28 +0200 Subject: arm: plat-orion: make bridge_virt_base non-const to support DT use case For the Armada 370 and XP SoCs where the DT is used, we need to fill at runtime the bridge_virt_base field on the orion_addr_map_cfg. Therefore, remove the 'const' qualifier on this field. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/plat-orion/include/plat/addr-map.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h index 0a746fdfaf7..ec63e4a627d 100644 --- a/arch/arm/plat-orion/include/plat/addr-map.h +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; struct orion_addr_map_cfg { const int num_wins; /* Total number of windows */ const int remappable_wins; - void __iomem * const bridge_virt_base; + void __iomem *bridge_virt_base; /* If NULL, the default cpu_win_can_remap will be used, using the value in remappable_wins */ -- cgit v1.2.3-70-g09d2 From 74dd80a7b9fe5e8438458bd17cc9352dff8fd6b7 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:29 +0200 Subject: arm: mvebu: add basic address decoding support to Armada 370/XP This commit adds basic support for address decoding configuration for the Armada 370 and Armada XP SoCs, re-using the infrastructure provided in plat-orion. For now, only a BootROM window is configured on Armada XP, which is needed to get the non-boot CPUs started and is therefore a requirement for SMP support. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Makefile | 2 +- arch/arm/mach-mvebu/addr-map.c | 134 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-mvebu/addr-map.c diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index e61d2b8fdf5..21435581b92 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -1,2 +1,2 @@ obj-y += system-controller.o -obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o +obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c new file mode 100644 index 00000000000..fe454a4430b --- /dev/null +++ b/arch/arm/mach-mvebu/addr-map.c @@ -0,0 +1,134 @@ +/* + * Address map functions for Marvell 370 / XP SoCs + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Generic Address Decode Windows bit settings + */ +#define ARMADA_XP_TARGET_DEV_BUS 1 +#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D +#define ARMADA_XP_TARGET_ETH1 3 +#define ARMADA_XP_TARGET_PCIE_0_2 4 +#define ARMADA_XP_TARGET_ETH0 7 +#define ARMADA_XP_TARGET_PCIE_1_3 8 + +#define ARMADA_370_TARGET_DEV_BUS 1 +#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D +#define ARMADA_370_TARGET_PCIE_0 4 +#define ARMADA_370_TARGET_PCIE_1 8 + +#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90 +#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180 + +static const struct __initdata orion_addr_map_info +armada_xp_addr_map_info[] = { + /* + * Window for the BootROM, needed for SMP on Armada XP + */ + { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS, + ARMADA_XP_ATTR_DEV_BOOTROM, -1 }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 }, +}; + +static const struct __initdata orion_addr_map_info +armada_370_addr_map_info[] = { + /* End marker */ + { -1, 0, 0, 0, 0, 0 }, +}; + +static struct of_device_id of_addr_decoding_controller_table[] = { + { .compatible = "marvell,armada-addr-decoding-controller" }, + { /* end of list */ }, +}; + +static void __iomem * +armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win) +{ + unsigned int offset; + + /* The register layout is a bit annoying and the below code + * tries to cope with it. + * - At offset 0x0, there are the registers for the first 8 + * windows, with 4 registers of 32 bits per window (ctrl, + * base, remap low, remap high) + * - Then at offset 0x80, there is a hole of 0x10 bytes for + * the internal registers base address and internal units + * sync barrier register. + * - Then at offset 0x90, there the registers for 12 + * windows, with only 2 registers of 32 bits per window + * (ctrl, base). + */ + if (win < 8) + offset = (win << 4); + else + offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3); + + return cfg->bridge_virt_base + offset; +} + +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 20, + .remappable_wins = 8, + .win_cfg_base = armada_cfg_base, +}; + +static int __init armada_setup_cpu_mbus(void) +{ + struct device_node *np; + void __iomem *mbus_unit_addr_decoding_base; + void __iomem *sdram_addr_decoding_base; + + np = of_find_matching_node(NULL, of_addr_decoding_controller_table); + if (!np) + return -ENODEV; + + mbus_unit_addr_decoding_base = of_iomap(np, 0); + BUG_ON(!mbus_unit_addr_decoding_base); + + sdram_addr_decoding_base = + mbus_unit_addr_decoding_base + + ARMADA_SDRAM_ADDR_DECODING_OFFSET; + + addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base; + + /* + * Disable, clear and configure windows. + */ + if (of_machine_is_compatible("marvell,armadaxp")) + orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info); + else if (of_machine_is_compatible("marvell,armada370")) + orion_config_wins(&addr_map_cfg, armada_370_addr_map_info); + else { + pr_err("Unsupported SoC\n"); + return -EINVAL; + } + + /* + * Setup MBUS dram target info. + */ + orion_setup_cpu_mbus_target(&addr_map_cfg, + sdram_addr_decoding_base); + return 0; +} + +/* Using a early_initcall is needed so that this initialization gets + * done before the SMP initialization, which requires the BootROM to + * be remapped. */ +early_initcall(armada_setup_cpu_mbus); -- cgit v1.2.3-70-g09d2 From 5b40baee4a39d96d4d6a48a2b2383982912c429b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:30 +0200 Subject: arm: mvebu: add address decoding controller to the DT Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 6b6b932a5a7..16cc82cdaa8 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -63,6 +63,11 @@ reg = <0xd0020300 0x30>; interrupts = <37>, <38>, <39>, <40>; }; + + addr-decoding@d0020000 { + compatible = "marvell,armada-addr-decoding-controller"; + reg = <0xd0020000 0x258>; + }; }; }; -- cgit v1.2.3-70-g09d2