From 243f196d572822214bb86522f28b30e096d67414 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 16 Mar 2006 14:10:19 +0000 Subject: [ARM] 3366/1: Allow the 16bpp mode configuration in the CLCD control register Patch from Catalin Marinas Starting with PL111, the 5551 or 565 modes can be configured in the primecell's control register directly. This patch detects the required mode and sets the correct value. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/linux/amba/clcd.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/linux/amba/clcd.h b/include/linux/amba/clcd.h index 6b8d73dc1ab..9cf64b1b688 100644 --- a/include/linux/amba/clcd.h +++ b/include/linux/amba/clcd.h @@ -54,6 +54,7 @@ #define CNTL_LCDBPP4 (2 << 1) #define CNTL_LCDBPP8 (3 << 1) #define CNTL_LCDBPP16 (4 << 1) +#define CNTL_LCDBPP16_565 (6 << 1) #define CNTL_LCDBPP24 (5 << 1) #define CNTL_LCDBW (1 << 4) #define CNTL_LCDTFT (1 << 5) @@ -209,7 +210,16 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) val |= CNTL_LCDBPP8; break; case 16: - val |= CNTL_LCDBPP16; + /* + * PL110 cannot choose between 5551 and 565 modes in + * its control register + */ + if ((fb->dev->periphid & 0x000fffff) == 0x00041110) + val |= CNTL_LCDBPP16; + else if (fb->fb.var.green.length == 5) + val |= CNTL_LCDBPP16; + else + val |= CNTL_LCDBPP16_565; break; case 32: val |= CNTL_LCDBPP24; -- cgit v1.2.3-70-g09d2 From 9e7714d08061a77d3d2ec9a6ef6fd571a534fc7f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Thu, 16 Mar 2006 14:10:20 +0000 Subject: [ARM] 3367/1: CLCD mode no longer supported on the RealView boards Patch from Catalin Marinas Chosing of the CLCD RGB mode is no longer possible via the SYS_CLCD register on the RealView boards. Instead, this configuration is done in the CLCD primecell control register directly. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/core.c | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 4303d988c4b..d13270c5d7c 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -202,11 +202,6 @@ struct clk realview_clcd_clk = { /* * CLCD support. */ -#define SYS_CLCD_MODE_MASK (3 << 0) -#define SYS_CLCD_MODE_888 (0 << 0) -#define SYS_CLCD_MODE_5551 (1 << 0) -#define SYS_CLCD_MODE_565_RLSB (2 << 0) -#define SYS_CLCD_MODE_565_BLSB (3 << 0) #define SYS_CLCD_NLCDIOON (1 << 2) #define SYS_CLCD_VDDPOSSWITCH (1 << 3) #define SYS_CLCD_PWR3V5SWITCH (1 << 4) @@ -360,29 +355,10 @@ static void realview_clcd_enable(struct clcd_fb *fb) void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; u32 val; - val = readl(sys_clcd); - val &= ~SYS_CLCD_MODE_MASK; - - switch (fb->fb.var.green.length) { - case 5: - val |= SYS_CLCD_MODE_5551; - break; - case 6: - val |= SYS_CLCD_MODE_565_RLSB; - break; - case 8: - val |= SYS_CLCD_MODE_888; - break; - } - - /* - * Set the MUX - */ - writel(val, sys_clcd); - /* - * And now enable the PSUs + * Enable the PSUs */ + val = readl(sys_clcd); val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; writel(val, sys_clcd); } -- cgit v1.2.3-70-g09d2 From 7abe53155b77c31028a7158883bc9aac705790da Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 20 Mar 2006 10:12:31 +0000 Subject: [ARM] Fix cosmetic typo in asm/irq.h The IRQ resource flags are IORESOURCE_IRQ not IRQRESOURCE_IRQ. Signed-off-by: Russell King --- include/asm-arm/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h index 7772432d3fd..60b5105c9c9 100644 --- a/include/asm-arm/irq.h +++ b/include/asm-arm/irq.h @@ -27,7 +27,7 @@ extern void enable_irq(unsigned int); /* * These correspond with the SA_TRIGGER_* defines, and therefore the - * IRQRESOURCE_IRQ_* defines. + * IORESOURCE_IRQ_* defines. */ #define __IRQT_RISEDGE (1 << 0) #define __IRQT_FALEDGE (1 << 1) -- cgit v1.2.3-70-g09d2