From 7627dc802a98aebebc6a34e5b6558ea4717c968c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 5 Dec 2010 08:51:38 +0000 Subject: ARM: GIC: private a standard get_irqnr_preamble assembler macro Provide a standard get_irqnr_preamble assembler macro for platforms to use, which retrieves the base address of the GIC CPU interface from gic_cpu_base_addr. Allow platforms to override this by defining HAVE_GET_IRQNR_PREAMBLE. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/include/asm/hardware/entry-macro-gic.S | 7 +++++++ arch/arm/mach-cns3xxx/include/mach/entry-macro.S | 5 ----- arch/arm/mach-omap2/include/mach/entry-macro.S | 1 + arch/arm/mach-realview/include/mach/entry-macro.S | 5 ----- arch/arm/mach-tegra/include/mach/entry-macro.S | 2 +- arch/arm/mach-ux500/include/mach/entry-macro.S | 1 + arch/arm/mach-vexpress/include/mach/entry-macro.S | 5 ----- 7 files changed, 10 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S index 05587f125a1..c115b82fe80 100644 --- a/arch/arm/include/asm/hardware/entry-macro-gic.S +++ b/arch/arm/include/asm/hardware/entry-macro-gic.S @@ -10,6 +10,13 @@ #include +#ifndef HAVE_GET_IRQNR_PREAMBLE + .macro get_irqnr_preamble, base, tmp + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] + .endm +#endif + /* * The interrupt numbering scheme is defined in the * interrupt controller spec. To wit: diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S index e793c337672..6bd83ed90af 100644 --- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S +++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S @@ -14,10 +14,5 @@ .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - ldr \base, =gic_cpu_base_addr - ldr \base, [\base] - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 2e358df3fe1..d54c4f89a8b 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -170,6 +170,7 @@ omap_irq_base: .word 0 #ifdef CONFIG_ARCH_OMAP4 +#define HAVE_GET_IRQNR_PREAMBLE #include .macro get_irqnr_preamble, base, tmp diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S index 4417b103961..4071164aeba 100644 --- a/arch/arm/mach-realview/include/mach/entry-macro.S +++ b/arch/arm/mach-realview/include/mach/entry-macro.S @@ -13,11 +13,6 @@ .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - ldr \base, =gic_cpu_base_addr - ldr \base, [\base] - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S index dc092491518..dd165c53889 100644 --- a/arch/arm/mach-tegra/include/mach/entry-macro.S +++ b/arch/arm/mach-tegra/include/mach/entry-macro.S @@ -16,7 +16,7 @@ #include #if defined(CONFIG_ARM_GIC) - +#define HAVE_GET_IRQNR_PREAMBLE #include /* Uses the GIC interrupt controller built into the cpu */ diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S index 3cc3cdf5518..a37f585a3ec 100644 --- a/arch/arm/mach-ux500/include/mach/entry-macro.S +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S @@ -11,6 +11,7 @@ * warranty of any kind, whether express or implied. */ #include +#define HAVE_GET_IRQNR_PREAMBLE #include .macro disable_fiq diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S index 19d5ac8ba07..73c11297509 100644 --- a/arch/arm/mach-vexpress/include/mach/entry-macro.S +++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S @@ -3,10 +3,5 @@ .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - ldr \base, =gic_cpu_base_addr - ldr \base, [\base] - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm -- cgit v1.2.3-70-g09d2