From 38a1981ce31dc4c527cbc0137f638543261b471a Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Wed, 18 Sep 2013 16:50:11 +0530 Subject: ARM: OMAP2+: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency The real time counter also called master counter, is a free-running counter. It produces the count used by the CPU local timer peripherals in the MPU cluster. The timer counts at a rate of 6.144 MHz. The ratio registers are missing for a sys-clk of 20MHZ which is used by DRA7 socs. So because of this, the counter was getting wrongly programmed for a sys-clk of 38.4Mhz(default). So adding the ratio registers for 20MHZ sys-clk. Tested-by: Nishanth Menon Acked-by: Santosh Shilimkar Signed-off-by: Sricharan R Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index fa74a0625da..d0f80c02042 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -515,6 +515,10 @@ static void __init realtime_counter_init(void) num = 8; den = 25; break; + case 20000000: + num = 192; + den = 625; + break; case 2600000: num = 384; den = 1625; -- cgit v1.2.3-70-g09d2 From aa2f4b16f8305f0bddb5731a222b0ce39e6844aa Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 18 Sep 2013 09:05:42 -0500 Subject: ARM: OMAP5: id: Remove ES1.0 support OMAP5 ES1.0 was intended as a test chip and has major register level differences w.r.t ES2.0 revision of the chip. All register defines, dts support has been solely added for ES2.0 version of the chip. Further, all ES1.0 chips and platforms are supposed to have been removed from circulation. Hence, there is no need to further retain any resemblence of ES1.0 support in id detection code. Remove the omap_revision handling and BUG() instead to prevent folks who mistakenly try an older unsupported chip and report bogus errors. Signed-off-by: Nishanth Menon Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/id.c | 8 ++++---- arch/arm/mach-omap2/soc.h | 2 -- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 0289adcb6ef..4f8f1cb3f5f 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -576,8 +576,8 @@ void __init omap5xxx_check_revision(void) case 0xb942: switch (rev) { case 0: - omap_revision = OMAP5430_REV_ES1_0; - break; + /* No support for ES1.0 Test chip */ + BUG(); case 1: default: omap_revision = OMAP5430_REV_ES2_0; @@ -587,8 +587,8 @@ void __init omap5xxx_check_revision(void) case 0xb998: switch (rev) { case 0: - omap_revision = OMAP5432_REV_ES1_0; - break; + /* No support for ES1.0 Test chip */ + BUG(); case 1: default: omap_revision = OMAP5432_REV_ES2_0; diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 4588df1447e..076bd90a6ce 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -455,9 +455,7 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) #define OMAP54XX_CLASS 0x54000054 -#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) #define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) -#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) #define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) void omap2xxx_check_revision(void); -- cgit v1.2.3-70-g09d2 From 5523e4092ee4f2ef58d00c78365c8bddf730c900 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 10 Oct 2013 13:13:48 +0530 Subject: ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register The realtime counter called master counter, produces the count used by the private timer peripherals in the MPU_CLUSTER. The CNTFRQ per cpu register is used to denote the frequency of the counter. Currently the frequency value is passed from the DT file, but this is not scalable when we have other non-DT guest OS. This register must be set to the right value by the secure rom code. Setting this register helps in propagating the right frequency value across OSes. More discussions and the reason for adding this in a non-DT way can be seen from below. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html So configuring this secure register for all the cpus here. Cc: Nishanth Menon Cc: Rajendra Nayak Cc: Marc Zyngier Cc: Mark Rutland Tested-by: Nishanth Menon Acked-by: Santosh Shilimkar Signed-off-by: Sricharan R Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-secure.h | 4 ++++ arch/arm/mach-omap2/omap-smp.c | 7 +++++++ arch/arm/mach-omap2/timer.c | 10 ++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 0e729170c46..a5ee09d20ac 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -42,6 +42,8 @@ #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 +#define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 + /* Secure PPA(Primary Protected Application) APIs */ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 @@ -60,5 +62,7 @@ extern int omap_barrier_reserve_memblock(void); static inline void omap_barrier_reserve_memblock(void) { } #endif + +void set_cntfreq(void); #endif /* __ASSEMBLER__ */ #endif /* OMAP_ARCH_OMAP_SECURE_H */ diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 89121109329..75e95d4fb44 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -65,6 +65,13 @@ static void omap4_secondary_init(unsigned int cpu) omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, 4, 0, 0, 0, 0, 0); + /* + * Configure the CNTFRQ register for the secondary cpu's which + * indicates the frequency of the cpu local timers. + */ + if (soc_is_omap54xx() || soc_is_dra7xx()) + set_cntfreq(); + /* * Synchronise with the boot thread. */ diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index d0f80c02042..87259dc82aa 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -55,6 +55,7 @@ #include "soc.h" #include "common.h" #include "powerdomain.h" +#include "omap-secure.h" #define REALTIME_COUNTER_BASE 0x48243200 #define INCREMENTER_NUMERATOR_OFFSET 0x10 @@ -65,6 +66,12 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; +static unsigned long arch_timer_freq; + +void set_cntfreq(void) +{ + omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); +} static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { @@ -546,6 +553,9 @@ static void __init realtime_counter_init(void) reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + arch_timer_freq = (rate / den) * num; + set_cntfreq(); + iounmap(base); } #else -- cgit v1.2.3-70-g09d2 From d5da94b88efebc375bfcbab6bb0e59a6e8a6571e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 11 Oct 2013 17:28:04 -0700 Subject: ARM: OMAP2+: Fix build error for realtime counter init if not enabled Otherwise we can get an error with some configs: arch/arm/mach-omap2/timer.c:73: undefined reference to `omap_smc1' Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 87259dc82aa..d59b51f07cf 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -66,12 +66,15 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; + +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER static unsigned long arch_timer_freq; void set_cntfreq(void) { omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); } +#endif static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { -- cgit v1.2.3-70-g09d2