From 9cc2a0c95ff3f815deeba1ccd0d11b1d3bc46551 Mon Sep 17 00:00:00 2001 From: Padmavathi Venna Date: Tue, 13 Jan 2015 16:57:40 +0530 Subject: clk: samsung: exynos7: add gate clock for DMA block Add support for PDMA0 and PDMA1 gate clks. Signed-off-by: Padmavathi Venna Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos7.c | 4 ++++ include/dt-bindings/clock/exynos7-clk.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 945f41ce957..d01d766b3ea 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -722,6 +722,10 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 19, 0, 0), + GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", + ENABLE_ACLK_FSYS00, 3, 0, 0), + GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", + ENABLE_ACLK_FSYS00, 4, 0, 0), GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS01, 29, 0, 0), diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index e33d0ca4c12..05e2a47bcb9 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -91,7 +91,9 @@ #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 #define OSCCLK_PHY_CLKOUT_USB30_PHY 8 -#define FSYS0_NR_CLK 9 +#define ACLK_PDMA0 9 +#define ACLK_PDMA1 10 +#define FSYS0_NR_CLK 11 /* FSYS1 */ #define ACLK_MMC1 1 -- cgit v1.2.3-70-g09d2