From 9e6f39698ac66e08017114a51600bf633becd011 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Thu, 17 Jun 2010 20:36:13 +0900 Subject: MIPS: EMMA2RH: Remove EMMA2RH_CPU_CASCADE Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts, current EMMA2RH plat_irq_dispatch() supports IP2 only. We can make it configurable in the future, but for the time being, would like to make things explicitly allcated to IP2 in accordance with plat_irq_dispatch(). Signed-off-by: Shinya Kuribayashi To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1388/ Signed-off-by: Ralf Baechle --- arch/mips/emma/markeins/irq.c | 2 +- arch/mips/include/asm/emma/emma2rh.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 1d1c806056c..3a96799eb65 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -301,7 +301,7 @@ void __init arch_init_irq(void) /* setup cascade interrupts */ setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); - setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); + setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade); } asmlinkage void plat_irq_dispatch(void) diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h index fcc0064d6a8..95d0b7e683c 100644 --- a/arch/mips/include/asm/emma/emma2rh.h +++ b/arch/mips/include/asm/emma/emma2rh.h @@ -101,7 +101,6 @@ #define NUM_EMMA2RH_IRQ 96 -#define CPU_EMMA2RH_CASCADE 2 #define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) /* -- cgit v1.2.3-70-g09d2