From 2f65baff3ab546d011b0e3f944eccd1ec5816d5d Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 31 Jan 2008 21:30:24 +0000 Subject: [ARM] 21285 serial: fix build error drivers/serial/21285.c: In function 'serial21285_set_termios': drivers/serial/21285.c:280: error: 'tty' undeclared (first use in this function) drivers/serial/21285.c:280: error: (Each undeclared identifier is reported only once drivers/serial/21285.c:280: error: for each function it appears in.) Signed-off-by: Russell King --- drivers/serial/21285.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c index 6a48dfa1efe..0276471cb25 100644 --- a/drivers/serial/21285.c +++ b/drivers/serial/21285.c @@ -237,6 +237,12 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios, baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); quot = uart_get_divisor(port, baud); + if (port->info && port->info->tty) { + struct tty_struct *tty = port->info->tty; + unsigned int b = port->uartclk / (16 * quot); + tty_encode_baud_rate(tty, b, b); + } + switch (termios->c_cflag & CSIZE) { case CS5: h_lcr = 0x00; @@ -277,8 +283,6 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_iflag & INPCK) port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY; - tty_encode_baud_rate(tty, baud, baud); - /* * Which character status flags should we ignore? */ -- cgit v1.2.3-70-g09d2 From 66a2c077c36ee5c56e77ba3757702c4464011da6 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 1 Feb 2008 21:27:02 +0000 Subject: [ARM] xtime_seqlock: fix more ARM machines for xtime deadlocking move update_process_times() out from under xtime_lock. Signed-off-by: Peter Zijlstra Signed-off-by: Russell King --- arch/arm/common/time-acorn.c | 2 -- arch/arm/mach-at91/at91sam926x_time.c | 3 --- arch/arm/plat-iop/time.c | 4 ---- arch/arm/plat-s3c24xx/time.c | 2 -- 4 files changed, 11 deletions(-) diff --git a/arch/arm/common/time-acorn.c b/arch/arm/common/time-acorn.c index 34038eccbba..d544da41473 100644 --- a/arch/arm/common/time-acorn.c +++ b/arch/arm/common/time-acorn.c @@ -69,9 +69,7 @@ void __init ioctime_init(void) static irqreturn_t ioc_timer_interrupt(int irq, void *dev_id) { - write_seqlock(&xtime_lock); timer_tick(); - write_sequnlock(&xtime_lock); return IRQ_HANDLED; } diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 5c090c9442f..e38d2377099 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -49,8 +49,6 @@ static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id) volatile long nr_ticks; if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */ - write_seqlock(&xtime_lock); - /* Get number to ticks performed before interrupt and clear PIT interrupt */ nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); do { @@ -58,7 +56,6 @@ static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id) nr_ticks--; } while (nr_ticks); - write_sequnlock(&xtime_lock); return IRQ_HANDLED; } else return IRQ_NONE; /* not handled */ diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index ba3d21d8fba..6fe481ff4fd 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -57,8 +57,6 @@ unsigned long iop_gettimeoffset(void) static irqreturn_t iop_timer_interrupt(int irq, void *dev_id) { - write_seqlock(&xtime_lock); - write_tisr(1); while ((signed long)(next_jiffy_time - read_tcr1()) @@ -67,8 +65,6 @@ iop_timer_interrupt(int irq, void *dev_id) next_jiffy_time -= ticks_per_jiffy; } - write_sequnlock(&xtime_lock); - return IRQ_HANDLED; } diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c index 2ec1daaa0e5..766473b3f98 100644 --- a/arch/arm/plat-s3c24xx/time.c +++ b/arch/arm/plat-s3c24xx/time.c @@ -130,9 +130,7 @@ static unsigned long s3c2410_gettimeoffset (void) static irqreturn_t s3c2410_timer_interrupt(int irq, void *dev_id) { - write_seqlock(&xtime_lock); timer_tick(); - write_sequnlock(&xtime_lock); return IRQ_HANDLED; } -- cgit v1.2.3-70-g09d2 From 85e6c7a7dbdb18a93846073a7f01369e91665c53 Mon Sep 17 00:00:00 2001 From: Kristoffer Ericson Date: Sun, 3 Feb 2008 22:08:10 +0100 Subject: [ARM] 4810/1: - Fix 'section mismatch' building warnings Warning message : WARNING: vmlinux.o(.text+0x9afc): Section mismatch: reference to .init.text:sa1110_mb_enable (between 'sa1111_probe' and 'sa1111_remove') WARNING: vmlinux.o(.text+0x13b1ac): Section mismatch: reference to .init.text:pcmcia_jornada720_init (between 'pcmcia_probe' and 'pcmcia_remove') * fixes the 'section mismatch' building warnings for target sa1100. Solution is __init -> __devinit. Thanks to Randy Dunlap for pointing out the solution. Signed-off-by: Kristoffer Ericson Signed-off-by: Russell King --- arch/arm/mach-sa1100/generic.c | 2 +- drivers/pcmcia/sa1100_jornada720.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 9e13c8358ea..5c84c604ed8 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -470,7 +470,7 @@ void __init sa1110_mb_disable(void) * If the system is going to use the SA-1111 DMA engines, set up * the memory bus request/grant pins. */ -void __init sa1110_mb_enable(void) +void __devinit sa1110_mb_enable(void) { unsigned long flags; diff --git a/drivers/pcmcia/sa1100_jornada720.c b/drivers/pcmcia/sa1100_jornada720.c index af485ae3860..6284c35dabc 100644 --- a/drivers/pcmcia/sa1100_jornada720.c +++ b/drivers/pcmcia/sa1100_jornada720.c @@ -101,7 +101,7 @@ static struct pcmcia_low_level jornada720_pcmcia_ops = { .socket_suspend = sa1111_pcmcia_socket_suspend, }; -int __init pcmcia_jornada720_init(struct device *dev) +int __devinit pcmcia_jornada720_init(struct device *dev) { int ret = -ENODEV; -- cgit v1.2.3-70-g09d2 From 95053aec4d859edd6fbf7cd7d652e21704dda740 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:17:24 +0100 Subject: [ARM] 4766/2: ixp4xx: Update ixp4xx_defconfig, enabling all supported boards This updates the defconfig for the ixp4xx machine in arch/arm/config taking all the defaults, with the following additions: 1) Enable support for the nslu2, loft, gateway7001, wg302v2, dsmg600, and gtwx5715 boards. 2) Enable EABI, OABI, HOTPLUG and FW_LOADER. 3) Enable the RTC subsystem, with drivers for the RTC chips on the nslu2 (x1205) and nas100d/dsmg600 (pcf8563) boards. 4) Enable the LEDS subsystem to support the nslu2, nas100d and dsmg600 boards. Enable the ixp4xx beeper driver. 5) Enable the USB subsystem, USB host driver support and USB mass storage support (required for boot disk on nslu2 board). 6) Enable the ATA subsystem, with drivers for the nas100d/dsmg600 (pata_artop) and avila (ixp4xx_cf) boards. Signed-off-by: Rod Whitby Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/configs/ixp4xx_defconfig | 978 +++++++++++++++++++++++++------------- 1 file changed, 645 insertions(+), 333 deletions(-) diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index db850a5689e..2d5ae33f0ba 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -1,69 +1,96 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.15 -# Tue Jan 3 03:20:40 2006 +# Linux kernel version: 2.6.24-rc8 +# Wed Jan 23 17:26:16 2008 # CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y -CONFIG_UID16=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_SYSCTL=y +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y +CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# CONFIG_MODULES=y # CONFIG_MODULE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_KMOD=y - -# -# Block layer -# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set # # IO Schedulers @@ -81,28 +108,39 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # # System Type # +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set -CONFIG_ARCH_IXP4XX=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set # CONFIG_ARCH_IXP2000 is not set +CONFIG_ARCH_IXP4XX=y # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_AAEC2000 is not set CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y # @@ -112,8 +150,12 @@ CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y # # IXP4xx Platforms # -CONFIG_ARCH_AVILA=y +CONFIG_MACH_NSLU2=y +CONFIG_MACH_AVILA=y +CONFIG_MACH_LOFT=y CONFIG_ARCH_ADI_COYOTE=y +CONFIG_MACH_GATEWAY7001=y +CONFIG_MACH_WG302V2=y CONFIG_ARCH_IXDP425=y CONFIG_MACH_IXDPG425=y CONFIG_MACH_IXDP465=y @@ -121,16 +163,26 @@ CONFIG_MACH_KIXRP435=y CONFIG_ARCH_IXCDP1100=y CONFIG_ARCH_PRPMC1100=y CONFIG_MACH_NAS100D=y +CONFIG_MACH_DSMG600=y CONFIG_ARCH_IXDP4XX=y CONFIG_CPU_IXP46X=y CONFIG_CPU_IXP43X=y -# CONFIG_MACH_GTWX5715 is not set +CONFIG_MACH_GTWX5715=y # # IXP4xx Options # +CONFIG_DMABOUNCE=y # CONFIG_IXP4XX_INDIRECT_PCI is not set +# +# Boot options +# + +# +# Power management +# + # # Processor Type # @@ -140,33 +192,40 @@ CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y # # Processor Features # # CONFIG_ARM_THUMB is not set CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +# CONFIG_IWMMXT is not set CONFIG_XSCALE_PMU=y -CONFIG_DMABOUNCE=y # # Bus support # -CONFIG_ISA_DMA_API=y CONFIG_PCI=y -CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set # # Kernel Features # +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_PREEMPT is not set -# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -175,7 +234,12 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y CONFIG_ALIGNMENT_TRAP=y # @@ -185,6 +249,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp root=/dev/nfs" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set # # Floating point emulation @@ -203,13 +268,12 @@ CONFIG_FPE_NWFPE=y CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set # # Power management options # # CONFIG_PM is not set -# CONFIG_APM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y # # Networking @@ -219,11 +283,13 @@ CONFIG_NET=y # # Networking options # -CONFIG_PACKET=m +CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -232,9 +298,7 @@ CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_FWMARK=y CONFIG_IP_ROUTE_MULTIPATH=y -# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y @@ -251,15 +315,18 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y - -# -# IP: Virtual Server Configuration -# +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set CONFIG_IP_VS=m CONFIG_IP_VS_DEBUG=y CONFIG_IP_VS_TAB_BITS=12 @@ -290,6 +357,9 @@ CONFIG_IP_VS_SH=m # IPVS application helper # # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_BRIDGE_NETFILTER=y @@ -298,70 +368,57 @@ CONFIG_BRIDGE_NETFILTER=y # Core Netfilter Configuration # # CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NF_CONNTRACK_ENABLED is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set # # IP: Netfilter Configuration # -CONFIG_IP_NF_CONNTRACK=m -# CONFIG_IP_NF_CT_ACCT is not set -# CONFIG_IP_NF_CONNTRACK_MARK is not set -# CONFIG_IP_NF_CONNTRACK_EVENTS is not set -# CONFIG_IP_NF_CT_PROTO_SCTP is not set -CONFIG_IP_NF_FTP=m -CONFIG_IP_NF_IRC=m -# CONFIG_IP_NF_NETBIOS_NS is not set -# CONFIG_IP_NF_TFTP is not set -# CONFIG_IP_NF_AMANDA is not set -# CONFIG_IP_NF_PPTP is not set CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_LIMIT=m # CONFIG_IP_NF_MATCH_IPRANGE is not set -CONFIG_IP_NF_MATCH_MAC=m -# CONFIG_IP_NF_MATCH_PKTTYPE is not set -CONFIG_IP_NF_MATCH_MARK=m -CONFIG_IP_NF_MATCH_MULTIPORT=m CONFIG_IP_NF_MATCH_TOS=m # CONFIG_IP_NF_MATCH_RECENT is not set # CONFIG_IP_NF_MATCH_ECN is not set -# CONFIG_IP_NF_MATCH_DSCP is not set -CONFIG_IP_NF_MATCH_AH_ESP=m -CONFIG_IP_NF_MATCH_LENGTH=m +# CONFIG_IP_NF_MATCH_AH is not set CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_TCPMSS=m -# CONFIG_IP_NF_MATCH_HELPER is not set -CONFIG_IP_NF_MATCH_STATE=m -# CONFIG_IP_NF_MATCH_CONNTRACK is not set CONFIG_IP_NF_MATCH_OWNER=m -# CONFIG_IP_NF_MATCH_PHYSDEV is not set # CONFIG_IP_NF_MATCH_ADDRTYPE is not set -# CONFIG_IP_NF_MATCH_REALM is not set -# CONFIG_IP_NF_MATCH_SCTP is not set -# CONFIG_IP_NF_MATCH_DCCP is not set -# CONFIG_IP_NF_MATCH_COMMENT is not set -# CONFIG_IP_NF_MATCH_HASHLIMIT is not set -# CONFIG_IP_NF_MATCH_STRING is not set CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_TARGET_TCPMSS=m -# CONFIG_IP_NF_TARGET_NFQUEUE is not set -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_SAME is not set -CONFIG_IP_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_NAT_IRC=m -CONFIG_IP_NF_NAT_FTP=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_TOS=m # CONFIG_IP_NF_TARGET_ECN is not set -# CONFIG_IP_NF_TARGET_DSCP is not set -CONFIG_IP_NF_TARGET_MARK=m -# CONFIG_IP_NF_TARGET_CLASSIFY is not set # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set CONFIG_IP_NF_ARPTABLES=m @@ -372,16 +429,9 @@ CONFIG_IP_NF_ARPFILTER=m # Bridge: Netfilter Configuration # # CONFIG_BRIDGE_NF_EBTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set CONFIG_ATM=y CONFIG_ATM_CLIP=y # CONFIG_ATM_CLIP_NO_ICMP is not set @@ -397,25 +447,17 @@ CONFIG_LLC=m CONFIG_IPX=m # CONFIG_IPX_INTERN is not set CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=y +CONFIG_DEV_APPLETALK=m CONFIG_IPDDP=m CONFIG_IPDDP_ENCAP=y CONFIG_IPDDP_DECAP=y CONFIG_X25=m CONFIG_LAPB=m -# CONFIG_NET_DIVERT is not set CONFIG_ECONET=m CONFIG_ECONET_AUNUDP=y CONFIG_ECONET_NATIVE=y CONFIG_WAN_ROUTER=m - -# -# QoS and/or fair queueing -# CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CLK_JIFFIES=y -# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set -# CONFIG_NET_SCH_CLK_CPU is not set # # Queueing/Scheduling @@ -425,6 +467,7 @@ CONFIG_NET_SCH_HTB=m # CONFIG_NET_SCH_HFSC is not set # CONFIG_NET_SCH_ATM is not set CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_RR is not set CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -449,10 +492,17 @@ CONFIG_NET_CLS_U32=m CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m # CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set CONFIG_NET_CLS_POLICE=y # CONFIG_NET_CLS_IND is not set -CONFIG_NET_ESTIMATOR=y +CONFIG_NET_SCH_FIFO=y # # Network testing @@ -461,7 +511,18 @@ CONFIG_NET_PKTGEN=m # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -470,19 +531,14 @@ CONFIG_NET_PKTGEN=m # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set +CONFIG_FW_LOADER=y # CONFIG_DEBUG_DRIVER is not set - -# -# Connector - unified userspace <-> kernelspace linker -# +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set @@ -498,11 +554,14 @@ CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 # User Modules And Translation Layers # CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -528,7 +587,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_XIP is not set # # Mapping drivers for chip access @@ -538,6 +596,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_ARM_INTEGRATOR is not set CONFIG_MTD_IXP4XX=y # CONFIG_MTD_PCI is not set +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -547,7 +606,6 @@ CONFIG_MTD_IXP4XX=y # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set # CONFIG_MTD_BLOCK2MTD is not set # @@ -556,33 +614,24 @@ CONFIG_MTD_IXP4XX=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# CONFIG_MTD_NAND=m # CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set CONFIG_MTD_NAND_IDS=m # CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set # CONFIG_MTD_NAND_NANDSIM is not set - -# -# OneNAND Flash Device Drivers -# +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -592,17 +641,20 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# ATA/ATAPI/MFM/RLL support -# +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 CONFIG_BLK_DEV_IDE=y # @@ -614,24 +666,28 @@ CONFIG_BLK_DEV_IDEDISK=y # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set # CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set + +# +# PCI IDE chipsets support +# CONFIG_BLK_DEV_IDEPCI=y # CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_IDEPCI_PCIBUS_ORDER=y # CONFIG_BLK_DEV_OFFBOARD is not set # CONFIG_BLK_DEV_GENERIC is not set # CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_SL82C105 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_PCI_AUTO is not set # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set CONFIG_BLK_DEV_CMD64X=y # CONFIG_BLK_DEV_TRIFLEX is not set # CONFIG_BLK_DEV_CY82C693 is not set @@ -639,93 +695,162 @@ CONFIG_BLK_DEV_CMD64X=y # CONFIG_BLK_DEV_CS5530 is not set # CONFIG_BLK_DEV_HPT34X is not set CONFIG_BLK_DEV_HPT366=y +# CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8213 is not set # CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set CONFIG_BLK_DEV_PDC202XX_NEW=y -# CONFIG_PDC202XX_FORCE is not set # CONFIG_BLK_DEV_SVWKS is not set # CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SL82C105 is not set # CONFIG_BLK_DEV_SLC90E66 is not set # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set # CONFIG_IDE_ARM is not set CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -# CONFIG_IDEDMA_AUTO is not set +CONFIG_IDE_ARCH_OBSOLETE_INIT=y # CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +CONFIG_PATA_ARTOP=y +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +CONFIG_PATA_IXP4XX_CF=y # CONFIG_MD is not set - -# -# Fusion MPT device support -# # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # +# CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set - -# -# I2O device support -# # CONFIG_I2O is not set - -# -# Network device support -# CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_IFB is not set CONFIG_DUMMY=y # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# ARCnet devices -# +# CONFIG_VETH is not set # CONFIG_ARCNET is not set - -# -# PHY device support -# # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set - -# -# Tulip family network device support -# # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set CONFIG_EEPRO100=y # CONFIG_E100 is not set # CONFIG_FEALNX is not set @@ -738,93 +863,75 @@ CONFIG_EEPRO100=y # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set - -# -# Ethernet (1000 Mbit) -# +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set # CONFIG_SIS190 is not set # CONFIG_SKGE is not set +# CONFIG_SKY2 is not set # CONFIG_SK98LIN is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set - -# -# Ethernet (10000 Mbit) -# +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set - -# -# Token Ring devices -# +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set # CONFIG_TR is not set # -# Wireless LAN (non-hamradio) -# -CONFIG_NET_RADIO=y - -# -# Obsolete Wireless cards support (pre-802.11) -# -# CONFIG_STRIP is not set - -# -# Wireless 802.11b ISA/PCI cards support -# -# CONFIG_AIRO is not set -CONFIG_HERMES=y -# CONFIG_PLX_HERMES is not set -# CONFIG_TMD_HERMES is not set -# CONFIG_NORTEL_HERMES is not set -CONFIG_PCI_HERMES=y -# CONFIG_ATMEL is not set - -# -# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support +# Wireless LAN # -# CONFIG_PRISM54 is not set -# CONFIG_HOSTAP is not set -CONFIG_NET_WIRELESS=y +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set # -# Wan interfaces +# USB Network Adapters # +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set CONFIG_WAN=y -# CONFIG_DSCC4 is not set # CONFIG_LANMEDIA is not set -# CONFIG_SYNCLINK_SYNCPPP is not set CONFIG_HDLC=m -CONFIG_HDLC_RAW=y +CONFIG_HDLC_RAW=m # CONFIG_HDLC_RAW_ETH is not set -CONFIG_HDLC_CISCO=y -CONFIG_HDLC_FR=y -CONFIG_HDLC_PPP=y -CONFIG_HDLC_X25=y +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m # CONFIG_PCI200SYN is not set # CONFIG_WANXL is not set # CONFIG_PC300 is not set +# CONFIG_PC300TOO is not set # CONFIG_FARSYNC is not set +# CONFIG_DSCC4 is not set CONFIG_DLCI=m -CONFIG_DLCI_COUNT=24 CONFIG_DLCI_MAX=8 -CONFIG_WAN_ROUTER_DRIVERS=y +CONFIG_WAN_ROUTER_DRIVERS=m # CONFIG_CYCLADES_SYNC is not set # CONFIG_LAPBETHER is not set # CONFIG_X25_ASY is not set - -# -# ATM drivers -# +CONFIG_ATM_DRIVERS=y # CONFIG_ATM_DUMMY is not set CONFIG_ATM_TCP=m # CONFIG_ATM_LANAI is not set @@ -842,20 +949,19 @@ CONFIG_ATM_TCP=m # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_NET_FC is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -865,7 +971,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -875,8 +980,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_IXP4XX_BEEPER=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_UINPUT is not set # # Hardware I/O ports @@ -895,7 +1008,9 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set # @@ -907,51 +1022,17 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_IXP4XX_WATCHDOG=y - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set +CONFIG_HW_RANDOM=m +CONFIG_HW_RANDOM_IXP4XX=m # CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# +CONFIG_DEVPORT=y CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y # @@ -969,57 +1050,68 @@ CONFIG_I2C_ALGOBIT=y # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_GPIO is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_I810 is not set # CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_IOP3XX is not set CONFIG_I2C_IXP4XX=y # CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_PROSAVAGE is not set # CONFIG_I2C_SAVAGE4 is not set -# CONFIG_SCx200_ACB is not set +# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set -# CONFIG_I2C_PCA_ISA is not set # # Miscellaneous I2C Chip support # # CONFIG_SENSORS_DS1337 is not set # CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set CONFIG_SENSORS_EEPROM=y # CONFIG_SENSORS_PCF8574 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_RTC8564 is not set # CONFIG_SENSORS_MAX6875 is not set -# CONFIG_RTC_X1205_I2C is not set +# CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # -# Hardware Monitoring support +# SPI support # +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_FSCHER is not set -# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -1033,67 +1125,268 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set # -# Misc devices +# Watchdog Device Drivers # +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_IXP4XX_WATCHDOG=y # -# Multimedia Capabilities Port drivers +# PCI-based Watchdog Cards # +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set # -# Multimedia devices +# USB-based Watchdog Cards # -# CONFIG_VIDEO_DEV is not set +# CONFIG_USBPCWATCHDOG is not set # -# Digital Video Broadcasting Devices +# Sonics Silicon Backplane # -# CONFIG_DVB is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set # # Graphics support # +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Sound # # CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set # -# USB support +# USB Input Devices # +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# +# CONFIG_USB_ATM is not set + # # USB Gadget Support # # CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y # -# MMC/SD Card support +# LED drivers +# +CONFIG_LEDS_IXP4XX=y +# CONFIG_LEDS_GPIO is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +CONFIG_RTC_DRV_X1205=y +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers # -# CONFIG_MMC is not set # # File systems @@ -1107,16 +1400,19 @@ CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y # CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set @@ -1140,11 +1436,12 @@ CONFIG_DNOTIFY=y # Pseudo filesystems # CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -# CONFIG_RELAYFS_FS is not set +# CONFIG_CONFIGFS_FS is not set # # Miscellaneous filesystems @@ -1156,13 +1453,15 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_CRAMFS is not set @@ -1171,10 +1470,7 @@ CONFIG_JFFS2_RTIME=y # CONFIG_QNX4FS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set @@ -1186,6 +1482,7 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -1193,7 +1490,6 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types @@ -1213,37 +1509,53 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set - -# -# Native Language Support -# +# CONFIG_SYSV68_PARTITION is not set # CONFIG_NLS is not set - -# -# Profiling support -# +# CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y # CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y CONFIG_MAGIC_SYSRQ=y -CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_FS is not set # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set # CONFIG_DEBUG_USER is not set CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_LL=y @@ -1254,22 +1566,22 @@ CONFIG_DEBUG_LL=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set - -# -# Cryptographic options -# +# CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set -# -# Hardware crypto devices -# - # # Library routines # +CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- cgit v1.2.3-70-g09d2 From 8e93675e5b235291d9dec91af78e01dd4f73629a Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:22:57 +0100 Subject: [ARM] 4767/2: ixp4xx: Add bitops.h include to io.h Add include of to io.h to solve compilations errors in files such as drivers/w1/w1_io.c caused by the ixp4xx version of io.h using the BIT() macro without including first. Signed-off-by: Rod Whitby Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/io.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index 9c5d2357aff..de181ce958d 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H +#include + #include #define IO_SPACE_LIMIT 0xffff0000 -- cgit v1.2.3-70-g09d2 From 14645ebabd96d29f3050ea78a6417b6653bc48cf Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:29:38 +0100 Subject: [ARM] 4768/2: ixp4xx: Button and LED updates for the nas100d board * Convert GPIO and IRQ handling to use the api. * Perform the reset only after the power button has been held down for at least two seconds. Do the reset on the release of the power button, so that NAS devices which have been set to auto-power-on (by solder bridging the power button) do not continuously power cycle. * Remove all superflous constants from nas100d.h * Add LED constants to nas100d.h while we're there. * Update the board LED setup code to use those constants. Signed-off-by: Rod Whitby Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/nas100d-power.c | 75 +++++++++++++++++++++++++++++++---- arch/arm/mach-ixp4xx/nas100d-setup.c | 14 +++---- include/asm-arm/arch-ixp4xx/nas100d.h | 18 ++++----- 3 files changed, 83 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-ixp4xx/nas100d-power.c b/arch/arm/mach-ixp4xx/nas100d-power.c index 29aa98d3a7f..4c1c01bb3fe 100644 --- a/arch/arm/mach-ixp4xx/nas100d-power.c +++ b/arch/arm/mach-ixp4xx/nas100d-power.c @@ -21,15 +21,59 @@ #include #include #include +#include +#include +#include #include -static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) +/* This is used to make sure the power-button pusher is serious. The button + * must be held until the value of this counter reaches zero. + */ +static int power_button_countdown; + +/* Must hold the button down for at least this many counts to be processed */ +#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */ + +static void nas100d_power_handler(unsigned long data); +static DEFINE_TIMER(nas100d_power_timer, nas100d_power_handler, 0, 0); + +static void nas100d_power_handler(unsigned long data) { - /* Signal init to do the ctrlaltdel action, this will bypass init if - * it hasn't started and do a kernel_restart. + /* This routine is called twice per second to check the + * state of the power button. */ - ctrl_alt_del(); + + if (gpio_get_value(NAS100D_PB_GPIO)) { + + /* IO Pin is 1 (button pushed) */ + if (power_button_countdown > 0) + power_button_countdown--; + + } else { + + /* Done on button release, to allow for auto-power-on mods. */ + if (power_button_countdown == 0) { + /* Signal init to do the ctrlaltdel action, + * this will bypass init if it hasn't started + * and do a kernel_restart. + */ + ctrl_alt_del(); + + /* Change the state of the power LED to "blink" */ + gpio_line_set(NAS100D_LED_PWR_GPIO, IXP4XX_GPIO_LOW); + } else { + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + } + } + + mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); +} + +static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) +{ + /* This is the paper-clip reset, it shuts the machine down directly. */ + machine_power_off(); return IRQ_HANDLED; } @@ -39,17 +83,30 @@ static int __init nas100d_power_init(void) if (!(machine_is_nas100d())) return 0; - set_irq_type(NAS100D_RB_IRQ, IRQT_LOW); + set_irq_type(gpio_to_irq(NAS100D_RB_GPIO), IRQT_LOW); - if (request_irq(NAS100D_RB_IRQ, &nas100d_reset_handler, + if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler, IRQF_DISABLED, "NAS100D reset button", NULL) < 0) { printk(KERN_DEBUG "Reset Button IRQ %d not available\n", - NAS100D_RB_IRQ); + gpio_to_irq(NAS100D_RB_GPIO)); return -EIO; } + /* The power button on the Iomega NAS100d is on GPIO 14, but + * it cannot handle interrupts on that GPIO line. So we'll + * have to poll it with a kernel timer. + */ + + /* Make sure that the power button GPIO is set up as an input */ + gpio_line_config(NAS100D_PB_GPIO, IXP4XX_GPIO_IN); + + /* Set the initial value for the power button IRQ handler */ + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + + mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); + return 0; } @@ -58,7 +115,9 @@ static void __exit nas100d_power_exit(void) if (!(machine_is_nas100d())) return; - free_irq(NAS100D_RB_IRQ, NULL); + del_timer_sync(&nas100d_power_timer); + + free_irq(gpio_to_irq(NAS100D_RB_GPIO), NULL); } module_init(nas100d_power_init); diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 54d884fb251..213a4cea911 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -43,20 +43,20 @@ static struct platform_device nas100d_flash = { static struct resource nas100d_led_resources[] = { { .name = "wlan", /* green led */ - .start = 0, - .end = 0, + .start = NAS100D_LED_WLAN_GPIO, + .end = NAS100D_LED_WLAN_GPIO, .flags = IXP4XX_GPIO_LOW, }, { - .name = "ready", /* blue power led (off is flashing!) */ - .start = 15, - .end = 15, + .name = "power", /* blue power led (off=flashing) */ + .start = NAS100D_LED_PWR_GPIO, + .end = NAS100D_LED_PWR_GPIO, .flags = IXP4XX_GPIO_LOW, }, { .name = "disk", /* yellow led */ - .start = 3, - .end = 3, + .start = NAS100D_LED_DISK_GPIO, + .end = NAS100D_LED_DISK_GPIO, .flags = IXP4XX_GPIO_LOW, }, }; diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h index 131e0a1d0df..98d937897bc 100644 --- a/include/asm-arm/arch-ixp4xx/nas100d.h +++ b/include/asm-arm/arch-ixp4xx/nas100d.h @@ -38,15 +38,15 @@ /* Buttons */ -#define NAS100D_PB_GPIO 14 -#define NAS100D_RB_GPIO 4 +#define NAS100D_PB_GPIO 14 /* power button */ +#define NAS100D_RB_GPIO 4 /* reset button */ + +/* Power control */ + #define NAS100D_PO_GPIO 12 /* power off */ -#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14 -#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4 +/* LEDs */ -/* -#define NAS100D_PB_BM (1L << NAS100D_PB_GPIO) -#define NAS100D_PO_BM (1L << NAS100D_PO_GPIO) -#define NAS100D_RB_BM (1L << NAS100D_RB_GPIO) -*/ +#define NAS100D_LED_WLAN_GPIO 0 +#define NAS100D_LED_DISK_GPIO 3 +#define NAS100D_LED_PWR_GPIO 15 -- cgit v1.2.3-70-g09d2 From 2bea80187f6218ed8b5c1e1280220b1c53d8dd05 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:30:54 +0100 Subject: [ARM] 4769/2: ixp4xx: Button updates for the dsmg600 board * Remove the superfluous declaration of ctrl_alt_del(). * Convert GPIO and IRQ handling to use the api. * Perform the reset on the release of the power button, so that NAS devices which have been set to auto-power-on (by solder bridging the power button) do not continuously power cycle. * Remove all superflous constants from dsmg600.h Signed-off-by: Rod Whitby Acked-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/dsmg600-power.c | 30 +++++++++++++++++------------- include/asm-arm/arch-ixp4xx/dsmg600.h | 7 +------ 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-ixp4xx/dsmg600-power.c b/arch/arm/mach-ixp4xx/dsmg600-power.c index 34717872d07..db639877712 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-power.c +++ b/arch/arm/mach-ixp4xx/dsmg600-power.c @@ -26,14 +26,13 @@ #include #include +#include #include -extern void ctrl_alt_del(void); - /* This is used to make sure the power-button pusher is serious. The button * must be held until the value of this counter reaches zero. */ -static volatile int power_button_countdown; +static int power_button_countdown; /* Must hold the button down for at least this many counts to be processed */ #define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */ @@ -47,22 +46,27 @@ static void dsmg600_power_handler(unsigned long data) * state of the power button. */ - if (*IXP4XX_GPIO_GPINR & DSMG600_PB_BM) { + if (gpio_get_value(DSMG600_PB_GPIO)) { /* IO Pin is 1 (button pushed) */ + if (power_button_countdown > 0) + power_button_countdown--; + + } else { + + /* Done on button release, to allow for auto-power-on mods. */ if (power_button_countdown == 0) { - /* Signal init to do the ctrlaltdel action, this will bypass - * init if it hasn't started and do a kernel_restart. + /* Signal init to do the ctrlaltdel action, + * this will bypass init if it hasn't started + * and do a kernel_restart. */ ctrl_alt_del(); /* Change the state of the power LED to "blink" */ gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW); + } else { + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; } - power_button_countdown--; - - } else { - power_button_countdown = PBUTTON_HOLDDOWN_COUNT; } mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); @@ -81,12 +85,12 @@ static int __init dsmg600_power_init(void) if (!(machine_is_dsmg600())) return 0; - if (request_irq(DSMG600_RB_IRQ, &dsmg600_reset_handler, + if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler, IRQF_DISABLED | IRQF_TRIGGER_LOW, "DSM-G600 reset button", NULL) < 0) { printk(KERN_DEBUG "Reset Button IRQ %d not available\n", - DSMG600_RB_IRQ); + gpio_to_irq(DSMG600_RB_GPIO)); return -EIO; } @@ -114,7 +118,7 @@ static void __exit dsmg600_power_exit(void) del_timer_sync(&dsmg600_power_timer); - free_irq(DSMG600_RB_IRQ, NULL); + free_irq(gpio_to_irq(DSMG600_RB_GPIO), NULL); } module_init(dsmg600_power_init); diff --git a/include/asm-arm/arch-ixp4xx/dsmg600.h b/include/asm-arm/arch-ixp4xx/dsmg600.h index a19605ad240..b7673e171ab 100644 --- a/include/asm-arm/arch-ixp4xx/dsmg600.h +++ b/include/asm-arm/arch-ixp4xx/dsmg600.h @@ -40,18 +40,13 @@ /* Buttons */ #define DSMG600_PB_GPIO 15 /* power button */ -#define DSMG600_PB_BM (1L << DSMG600_PB_GPIO) - #define DSMG600_RB_GPIO 3 /* reset button */ -#define DSMG600_RB_IRQ IRQ_IXP4XX_GPIO3 +/* Power control */ #define DSMG600_PO_GPIO 2 /* power off */ /* LEDs */ #define DSMG600_LED_PWR_GPIO 0 -#define DSMG600_LED_PWR_BM (1L << DSMG600_LED_PWR_GPIO) - #define DSMG600_LED_WLAN_GPIO 14 -#define DSMG600_LED_WLAN_BM (1L << DSMG600_LED_WLAN_GPIO) -- cgit v1.2.3-70-g09d2 From e28067d533f1c6fc8c5e31495994f1c9bf7febe6 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:36:12 +0100 Subject: [ARM] 4772/2: ixp4xx: Register nslu2 rtc i2c_board_info Register the i2c board info related to the RTC chip on the nslu2 board to allow it to be found automatically on boot. Signed-off-by: Rod Whitby Signed-off-by: Alessandro Zummo Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/nslu2-setup.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index 77277d27fcc..16d091c98ea 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -47,6 +48,12 @@ static struct i2c_gpio_platform_data nslu2_i2c_gpio_data = { .scl_pin = NSLU2_SCL_PIN, }; +static struct i2c_board_info __initdata nslu2_i2c_board_info [] = { + { + I2C_BOARD_INFO("rtc-x1205", 0x6f), + }, +}; + #ifdef CONFIG_LEDS_IXP4XX static struct resource nslu2_led_resources[] = { { @@ -183,6 +190,9 @@ static void __init nslu2_init(void) pm_power_off = nslu2_power_off; + i2c_register_board_info(0, nslu2_i2c_board_info, + ARRAY_SIZE(nslu2_i2c_board_info)); + /* * This is only useful on a modified machine, but it is valuable * to have it first in order to see debug messages, and so that -- cgit v1.2.3-70-g09d2 From 400d8231484ce3485d04310beaef778efee1efb3 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:38:44 +0100 Subject: [ARM] 4773/2: ixp4xx: Register nas100d rtc i2c_board_info Register the i2c board info related to the RTC chip on the nas100d board to allow it to be found automatically on boot. Signed-off-by: Rod Whitby Signed-off-by: Alessandro Zummo Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/nas100d-setup.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 213a4cea911..dc782d06c2b 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,12 @@ static struct platform_device nas100d_flash = { .resource = &nas100d_flash_resource, }; +static struct i2c_board_info __initdata nas100d_i2c_board_info [] = { + { + I2C_BOARD_INFO("rtc-pcf8563", 0x51), + }, +}; + #ifdef CONFIG_LEDS_IXP4XX static struct resource nas100d_led_resources[] = { { @@ -157,6 +164,9 @@ static void __init nas100d_init(void) pm_power_off = nas100d_power_off; + i2c_register_board_info(0, nas100d_i2c_board_info, + ARRAY_SIZE(nas100d_i2c_board_info)); + /* * This is only useful on a modified machine, but it is valuable * to have it first in order to see debug messages, and so that -- cgit v1.2.3-70-g09d2 From a9a424ce9a209155f3d4b9f8ceba50cdebb7769b Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 29 Jan 2008 00:40:02 +0100 Subject: [ARM] 4774/2: ixp4xx: Register dsmg600 rtc i2c_board_info Register the i2c board info related to the RTC chip on the dsmg600 board to allow it to be found automatically on boot. Signed-off-by: Rod Whitby Signed-off-by: Alessandro Zummo Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/dsmg600-setup.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index c473d408aa7..a1c44efc45f 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -51,6 +52,12 @@ static struct platform_device dsmg600_i2c_gpio = { }, }; +static struct i2c_board_info __initdata dsmg600_i2c_board_info [] = { + { + I2C_BOARD_INFO("rtc-pcf8563", 0x51), + }, +}; + #ifdef CONFIG_LEDS_CLASS static struct resource dsmg600_led_resources[] = { { @@ -158,6 +165,9 @@ static void __init dsmg600_init(void) pm_power_off = dsmg600_power_off; + i2c_register_board_info(0, dsmg600_i2c_board_info, + ARRAY_SIZE(dsmg600_i2c_board_info)); + /* The UART is required on the DSM-G600 (Redboot cannot use the * NIC) -- do it here so that it does *not* get removed if * platform_add_devices fails! -- cgit v1.2.3-70-g09d2 From c18f65816ef80b67eb4511ed8359c2dfcd69680d Mon Sep 17 00:00:00 2001 From: Krzysztof Halasa Date: Tue, 18 Dec 2007 03:53:27 +0100 Subject: [ARM] 4712/2: Adds functions to read and write IXP4xx "feature" bits Adds functions to read and write IXP4xx "feature" (aka "fuse") bits, containing information about available/enabled CPU features. The uncompress.h included by boot/compressed/misc.c resides in a different space than rest of the kernel and thus can't use asm/hardware.h (including asm/arch/cpu.h - which, in turn, may use EXPORTed symbol "processor_id"). Posted to linux-arm-kernel on 2 Dec 2007 and revised. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 1 + include/asm-arm/arch-ixp4xx/cpu.h | 15 +++++++++++++ include/asm-arm/arch-ixp4xx/hardware.h | 6 +++--- include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 36 +++++++++++++++++++++++++++---- include/asm-arm/arch-ixp4xx/uncompress.h | 2 +- 5 files changed, 52 insertions(+), 8 deletions(-) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index bf56eb337df..dd37901f786 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -62,6 +62,7 @@ extern int root_mountflags; extern void _stext, _text, _etext, __data_start, _edata, _end; unsigned int processor_id; +EXPORT_SYMBOL(processor_id); unsigned int __machine_arch_type; EXPORT_SYMBOL(__machine_arch_type); diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h index d2523b326c6..2fa3d6b8dbb 100644 --- a/include/asm-arm/arch-ixp4xx/cpu.h +++ b/include/asm-arm/arch-ixp4xx/cpu.h @@ -28,4 +28,19 @@ extern unsigned int processor_id; #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ IXP465_PROCESSOR_ID_VALUE) +static inline u32 ixp4xx_read_feature_bits(void) +{ + unsigned int val = ~*IXP4XX_EXP_CFG2; + val &= ~IXP4XX_FEATURE_RESERVED; + if (!cpu_is_ixp46x()) + val &= ~IXP4XX_FEATURE_IXP46X_ONLY; + + return val; +} + +static inline void ixp4xx_write_feature_bits(u32 value) +{ + *IXP4XX_EXP_CFG2 = ~value; +} + #endif /* _ASM_ARCH_CPU_H */ diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index 297ceda08b6..73e8dc36f6a 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h @@ -27,13 +27,13 @@ #define pcibios_assign_all_busses() 1 +/* Register locations and bits */ +#include "ixp4xx-regs.h" + #ifndef __ASSEMBLER__ #include #endif -/* Register locations and bits */ -#include "ixp4xx-regs.h" - /* Platform helper functions and definitions */ #include "platform.h" diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h index 5d949d763a9..c704fe8cf42 100644 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h @@ -15,10 +15,6 @@ * */ -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - #ifndef _ASM_ARM_IXP4XX_H_ #define _ASM_ARM_IXP4XX_H_ @@ -607,4 +603,36 @@ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ +/* "fuse" bits of IXP_EXP_CFG2 */ +#define IXP4XX_FEATURE_RCOMP (1 << 0) +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1) +#define IXP4XX_FEATURE_HASH (1 << 2) +#define IXP4XX_FEATURE_AES (1 << 3) +#define IXP4XX_FEATURE_DES (1 << 4) +#define IXP4XX_FEATURE_HDLC (1 << 5) +#define IXP4XX_FEATURE_AAL (1 << 6) +#define IXP4XX_FEATURE_HSS (1 << 7) +#define IXP4XX_FEATURE_UTOPIA (1 << 8) +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10) +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11) +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12) +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13) +#define IXP4XX_FEATURE_PCI (1 << 14) +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) +#define IXP4XX_FEATURE_USB_HOST (1 << 18) +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19) +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) +#define IXP4XX_FEATURE_RSA (1 << 21) +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) +#define IXP4XX_FEATURE_RESERVED (0xFF << 24) + +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ + IXP4XX_FEATURE_USB_HOST | \ + IXP4XX_FEATURE_NPEA_ETH | \ + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ + IXP4XX_FEATURE_RSA | \ + IXP4XX_FEATURE_XSCALE_MAX_FREQ) + #endif diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index f7a35b78823..34ef48fe327 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -13,7 +13,7 @@ #ifndef _ARCH_UNCOMPRESS_H_ #define _ARCH_UNCOMPRESS_H_ -#include +#include "ixp4xx-regs.h" #include #include -- cgit v1.2.3-70-g09d2 From 82a96f5790ac93a406be72ed8f308dd29ad7e6af Mon Sep 17 00:00:00 2001 From: Krzysztof Halasa Date: Tue, 1 Jan 2008 21:55:23 +0100 Subject: [ARM] 4713/3: Adds drivers for IXP4xx QMgr and NPE features This patch adds drivers for IXP4xx hardware Queue Manager and for Network Processor Engines. Requires patch #4712 (reading/writing CPU feature (aka fuse) bits). Posted to linux-arm-kernel on 2 Dec 2007 and revised. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/Kconfig | 14 + arch/arm/mach-ixp4xx/Makefile | 2 + arch/arm/mach-ixp4xx/ixp4xx_npe.c | 741 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-ixp4xx/ixp4xx_qmgr.c | 274 ++++++++++++++ include/asm-arm/arch-ixp4xx/npe.h | 39 ++ include/asm-arm/arch-ixp4xx/qmgr.h | 126 +++++++ 6 files changed, 1196 insertions(+) create mode 100644 arch/arm/mach-ixp4xx/ixp4xx_npe.c create mode 100644 arch/arm/mach-ixp4xx/ixp4xx_qmgr.c create mode 100644 include/asm-arm/arch-ixp4xx/npe.h create mode 100644 include/asm-arm/arch-ixp4xx/qmgr.h diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 61b2dfcb89d..e774447c059 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -189,6 +189,20 @@ config IXP4XX_INDIRECT_PCI need to use the indirect method instead. If you don't know what you need, leave this option unselected. +config IXP4XX_QMGR + tristate "IXP4xx Queue Manager support" + help + This driver supports IXP4xx built-in hardware queue manager + and is automatically selected by Ethernet and HSS drivers. + +config IXP4XX_NPE + tristate "IXP4xx Network Processor Engine support" + select HOTPLUG + select FW_LOADER + help + This driver supports IXP4xx built-in network coprocessors + and is automatically selected by Ethernet and HSS drivers. + endmenu endif diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index 77e00ade558..4bb97e13f95 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -30,3 +30,5 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c new file mode 100644 index 00000000000..83c137ec582 --- /dev/null +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c @@ -0,0 +1,741 @@ +/* + * Intel IXP4xx Network Processor Engine driver for Linux + * + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * The code is based on publicly available information: + * - Intel IXP4xx Developer's Manual and other e-papers + * - Intel IXP400 Access Library Software (BSD license) + * - previous works by Christian Hohnstaedt + * Thanks, Christian. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEBUG_MSG 0 +#define DEBUG_FW 0 + +#define NPE_COUNT 3 +#define MAX_RETRIES 1000 /* microseconds */ +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */ +#define NPE_46X_DATA_SIZE 0x1000 +#define NPE_A_42X_INSTR_SIZE 0x1000 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800 +#define NPE_46X_INSTR_SIZE 0x1000 +#define REGS_SIZE 0x1000 + +#define NPE_PHYS_REG 32 + +#define FW_MAGIC 0xFEEDF00D +#define FW_BLOCK_TYPE_INSTR 0x0 +#define FW_BLOCK_TYPE_DATA 0x1 +#define FW_BLOCK_TYPE_EOF 0xF + +/* NPE exec status (read) and command (write) */ +#define CMD_NPE_STEP 0x01 +#define CMD_NPE_START 0x02 +#define CMD_NPE_STOP 0x03 +#define CMD_NPE_CLR_PIPE 0x04 +#define CMD_CLR_PROFILE_CNT 0x0C +#define CMD_RD_INS_MEM 0x10 /* instruction memory */ +#define CMD_WR_INS_MEM 0x11 +#define CMD_RD_DATA_MEM 0x12 /* data memory */ +#define CMD_WR_DATA_MEM 0x13 +#define CMD_RD_ECS_REG 0x14 /* exec access register */ +#define CMD_WR_ECS_REG 0x15 + +#define STAT_RUN 0x80000000 +#define STAT_STOP 0x40000000 +#define STAT_CLEAR 0x20000000 +#define STAT_ECS_K 0x00800000 /* pipeline clean */ + +#define NPE_STEVT 0x1B +#define NPE_STARTPC 0x1C +#define NPE_REGMAP 0x1E +#define NPE_CINDEX 0x1F + +#define INSTR_WR_REG_SHORT 0x0000C000 +#define INSTR_WR_REG_BYTE 0x00004000 +#define INSTR_RD_FIFO 0x0F888220 +#define INSTR_RESET_MBOX 0x0FAC8210 + +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */ +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */ +#define ECS_BG_CTXT_REG_2 0x02 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */ +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */ +#define ECS_PRI_1_CTXT_REG_2 0x06 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */ +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */ +#define ECS_PRI_2_CTXT_REG_2 0x0A +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */ +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */ +#define ECS_DBG_CTXT_REG_2 0x0E +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */ + +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */ +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */ +#define ECS_REG_0_LDUR_BITS 8 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */ +#define ECS_REG_1_CCTXT_BITS 16 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */ +#define ECS_REG_1_SELCTXT_BITS 0 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */ +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */ +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */ + +/* NPE watchpoint_fifo register bit */ +#define WFIFO_VALID 0x80000000 + +/* NPE messaging_status register bit definitions */ +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */ +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */ +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */ +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */ +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */ +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */ +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */ +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */ + +/* NPE messaging_control register bit definitions */ +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */ +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */ +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */ +#define MSGCTL_IN_FIFO_WRITE 0x02000000 + +/* NPE mailbox_status value for reset */ +#define RESET_MBOX_STAT 0x0000F0F0 + +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" }; + +#define print_npe(pri, npe, fmt, ...) \ + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__) + +#if DEBUG_MSG +#define debug_msg(npe, fmt, ...) \ + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__) +#else +#define debug_msg(npe, fmt, ...) +#endif + +static struct { + u32 reg, val; +} ecs_reset[] = { + { ECS_BG_CTXT_REG_0, 0xA0000000 }, + { ECS_BG_CTXT_REG_1, 0x01000000 }, + { ECS_BG_CTXT_REG_2, 0x00008000 }, + { ECS_PRI_1_CTXT_REG_0, 0x20000080 }, + { ECS_PRI_1_CTXT_REG_1, 0x01000000 }, + { ECS_PRI_1_CTXT_REG_2, 0x00008000 }, + { ECS_PRI_2_CTXT_REG_0, 0x20000080 }, + { ECS_PRI_2_CTXT_REG_1, 0x01000000 }, + { ECS_PRI_2_CTXT_REG_2, 0x00008000 }, + { ECS_DBG_CTXT_REG_0, 0x20000000 }, + { ECS_DBG_CTXT_REG_1, 0x00000000 }, + { ECS_DBG_CTXT_REG_2, 0x001E0000 }, + { ECS_INSTRUCT_REG, 0x1003C00F }, +}; + +static struct npe npe_tab[NPE_COUNT] = { + { + .id = 0, + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT, + .regs_phys = IXP4XX_NPEA_BASE_PHYS, + }, { + .id = 1, + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT, + .regs_phys = IXP4XX_NPEB_BASE_PHYS, + }, { + .id = 2, + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT, + .regs_phys = IXP4XX_NPEC_BASE_PHYS, + } +}; + +int npe_running(struct npe *npe) +{ + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0; +} + +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data) +{ + __raw_writel(data, &npe->regs->exec_data); + __raw_writel(addr, &npe->regs->exec_addr); + __raw_writel(cmd, &npe->regs->exec_status_cmd); +} + +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd) +{ + __raw_writel(addr, &npe->regs->exec_addr); + __raw_writel(cmd, &npe->regs->exec_status_cmd); + /* Iintroduce extra read cycles after issuing read command to NPE + so that we read the register after the NPE has updated it. + This is to overcome race condition between XScale and NPE */ + __raw_readl(&npe->regs->exec_data); + __raw_readl(&npe->regs->exec_data); + return __raw_readl(&npe->regs->exec_data); +} + +static void npe_clear_active(struct npe *npe, u32 reg) +{ + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); +} + +static void npe_start(struct npe *npe) +{ + /* ensure only Background Context Stack Level is active */ + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0); + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0); + npe_clear_active(npe, ECS_DBG_CTXT_REG_0); + + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); +} + +static void npe_stop(struct npe *npe) +{ + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ +} + +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx, + u32 ldur) +{ + u32 wc; + int i; + + /* set the Active bit, and the LDUR, in the debug level */ + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS)); + + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute + the instruction, and set SELCTXT at ECS DEBUG Level to specify + which context store to access. + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number + */ + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG, + (ctx << ECS_REG_1_CCTXT_BITS) | + (ctx << ECS_REG_1_SELCTXT_BITS)); + + /* clear the pipeline */ + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); + + /* load NPE instruction into the instruction register */ + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr); + + /* we need this value later to wait for completion of NPE execution + step */ + wc = __raw_readl(&npe->regs->watch_count); + + /* issue a Step One command via the Execution Control register */ + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd); + + /* Watch Count register increments when NPE completes an instruction */ + for (i = 0; i < MAX_RETRIES; i++) { + if (wc != __raw_readl(&npe->regs->watch_count)) + return 0; + udelay(1); + } + + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n"); + return -ETIMEDOUT; +} + +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr, + u8 val, u32 ctx) +{ + /* here we build the NPE assembler instruction: mov8 d0, #0 */ + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */ + addr << 9 | /* base Operand */ + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */ + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ +} + +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr, + u16 val, u32 ctx) +{ + /* here we build the NPE assembler instruction: mov16 d0, #0 */ + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */ + addr << 9 | /* base Operand */ + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */ + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */ + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */ +} + +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, + u32 val, u32 ctx) +{ + /* write in 16 bit steps first the high and then the low value */ + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx)) + return -ETIMEDOUT; + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx); +} + +static int npe_reset(struct npe *npe) +{ + u32 val, ctl, exec_count, ctx_reg2; + int i; + + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) & + 0x3F3FFFFF; + + /* disable parity interrupt */ + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control); + + /* pre exec - debug instruction */ + /* turn off the halt bit by clearing Execution Count register. */ + exec_count = __raw_readl(&npe->regs->exec_count); + __raw_writel(0, &npe->regs->exec_count); + /* ensure that IF and IE are on (temporarily), so that we don't end up + stepping forever */ + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG); + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 | + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE); + + /* clear the FIFOs */ + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID) + ; + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) + /* read from the outFIFO until empty */ + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n", + __raw_readl(&npe->regs->in_out_fifo)); + + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) + /* step execution of the NPE intruction to read inFIFO using + the Debug Executing Context stack */ + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0)) + return -ETIMEDOUT; + + /* reset the mailbox reg from the XScale side */ + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status); + /* from NPE side */ + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0)) + return -ETIMEDOUT; + + /* Reset the physical registers in the NPE register file */ + for (val = 0; val < NPE_PHYS_REG; val++) { + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0)) + return -ETIMEDOUT; + /* address is either 0 or 4 */ + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0)) + return -ETIMEDOUT; + } + + /* Reset the context store = each context's Context Store registers */ + + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC + for Background ECS, to set where NPE starts executing code */ + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG); + val &= ~ECS_REG_0_NEXTPC_MASK; + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK; + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val); + + for (i = 0; i < 16; i++) { + if (i) { /* Context 0 has no STEVT nor STARTPC */ + /* STEVT = off, 0x80 */ + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i)) + return -ETIMEDOUT; + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i)) + return -ETIMEDOUT; + } + /* REGMAP = d0->p0, d8->p2, d16->p4 */ + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i)) + return -ETIMEDOUT; + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i)) + return -ETIMEDOUT; + } + + /* post exec */ + /* clear active bit in debug level */ + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0); + /* clear the pipeline */ + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); + /* restore previous values */ + __raw_writel(exec_count, &npe->regs->exec_count); + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2); + + /* write reset values to Execution Context Stack registers */ + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++) + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, + ecs_reset[val].val); + + /* clear the profile counter */ + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd); + + __raw_writel(0, &npe->regs->exec_count); + __raw_writel(0, &npe->regs->action_points[0]); + __raw_writel(0, &npe->regs->action_points[1]); + __raw_writel(0, &npe->regs->action_points[2]); + __raw_writel(0, &npe->regs->action_points[3]); + __raw_writel(0, &npe->regs->watch_count); + + val = ixp4xx_read_feature_bits(); + /* reset the NPE */ + ixp4xx_write_feature_bits(val & + ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); + for (i = 0; i < MAX_RETRIES; i++) { + if (!(ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_RESET_NPEA << npe->id))) + break; /* reset completed */ + udelay(1); + } + if (i == MAX_RETRIES) + return -ETIMEDOUT; + + /* deassert reset */ + ixp4xx_write_feature_bits(val | + (IXP4XX_FEATURE_RESET_NPEA << npe->id)); + for (i = 0; i < MAX_RETRIES; i++) { + if (ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_RESET_NPEA << npe->id)) + break; /* NPE is back alive */ + udelay(1); + } + if (i == MAX_RETRIES) + return -ETIMEDOUT; + + npe_stop(npe); + + /* restore NPE configuration bus Control Register - parity settings */ + __raw_writel(ctl, &npe->regs->messaging_control); + return 0; +} + + +int npe_send_message(struct npe *npe, const void *msg, const char *what) +{ + const u32 *send = msg; + int cycles = 0; + + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n", + what, send[0], send[1]); + + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) { + debug_msg(npe, "NPE input FIFO not empty\n"); + return -EIO; + } + + __raw_writel(send[0], &npe->regs->in_out_fifo); + + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) { + debug_msg(npe, "NPE input FIFO full\n"); + return -EIO; + } + + __raw_writel(send[1], &npe->regs->in_out_fifo); + + while ((cycles < MAX_RETRIES) && + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) { + udelay(1); + cycles++; + } + + if (cycles == MAX_RETRIES) { + debug_msg(npe, "Timeout sending message\n"); + return -ETIMEDOUT; + } + + debug_msg(npe, "Sending a message took %i cycles\n", cycles); + return 0; +} + +int npe_recv_message(struct npe *npe, void *msg, const char *what) +{ + u32 *recv = msg; + int cycles = 0, cnt = 0; + + debug_msg(npe, "Trying to receive message %s\n", what); + + while (cycles < MAX_RETRIES) { + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) { + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo); + if (cnt == 2) + break; + } else { + udelay(1); + cycles++; + } + } + + switch(cnt) { + case 1: + debug_msg(npe, "Received [%08X]\n", recv[0]); + break; + case 2: + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]); + break; + } + + if (cycles == MAX_RETRIES) { + debug_msg(npe, "Timeout waiting for message\n"); + return -ETIMEDOUT; + } + + debug_msg(npe, "Receiving a message took %i cycles\n", cycles); + return 0; +} + +int npe_send_recv_message(struct npe *npe, void *msg, const char *what) +{ + int result; + u32 *send = msg, recv[2]; + + if ((result = npe_send_message(npe, msg, what)) != 0) + return result; + if ((result = npe_recv_message(npe, recv, what)) != 0) + return result; + + if ((recv[0] != send[0]) || (recv[1] != send[1])) { + debug_msg(npe, "Message %s: unexpected message received\n", + what); + return -EIO; + } + return 0; +} + + +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) +{ + const struct firmware *fw_entry; + + struct dl_block { + u32 type; + u32 offset; + } *blk; + + struct dl_image { + u32 magic; + u32 id; + u32 size; + union { + u32 data[0]; + struct dl_block blocks[0]; + }; + } *image; + + struct dl_codeblock { + u32 npe_addr; + u32 size; + u32 data[0]; + } *cb; + + int i, j, err, data_size, instr_size, blocks, table_end; + u32 cmd; + + if ((err = request_firmware(&fw_entry, name, dev)) != 0) + return err; + + err = -EINVAL; + if (fw_entry->size < sizeof(struct dl_image)) { + print_npe(KERN_ERR, npe, "incomplete firmware file\n"); + goto err; + } + image = (struct dl_image*)fw_entry->data; + +#if DEBUG_FW + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n", + image->magic, image->id, image->size, image->size * 4); +#endif + + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */ + image->id = swab32(image->id); + image->size = swab32(image->size); + } else if (image->magic != FW_MAGIC) { + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n", + image->magic); + goto err; + } + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) { + print_npe(KERN_ERR, npe, + "inconsistent size of firmware file\n"); + goto err; + } + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) { + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n"); + goto err; + } + if (image->magic == swab32(FW_MAGIC)) + for (i = 0; i < image->size; i++) + image->data[i] = swab32(image->data[i]); + + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) { + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on " + "IXP42x\n"); + goto err; + } + + if (npe_running(npe)) { + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is " + "already running\n"); + err = -EBUSY; + goto err; + } +#if 0 + npe_stop(npe); + npe_reset(npe); +#endif + + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, + (image->id >> 8) & 0xFF, image->id & 0xFF); + + if (!cpu_is_ixp46x()) { + if (!npe->id) + instr_size = NPE_A_42X_INSTR_SIZE; + else + instr_size = NPE_B_AND_C_42X_INSTR_SIZE; + data_size = NPE_42X_DATA_SIZE; + } else { + instr_size = NPE_46X_INSTR_SIZE; + data_size = NPE_46X_DATA_SIZE; + } + + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size; + blocks++) + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF) + break; + if (blocks * sizeof(struct dl_block) / 4 >= image->size) { + print_npe(KERN_INFO, npe, "firmware EOF block marker not " + "found\n"); + goto err; + } + +#if DEBUG_FW + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks); +#endif + + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */; + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) { + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4 + || blk->offset < table_end) { + print_npe(KERN_INFO, npe, "invalid offset 0x%X of " + "firmware block #%i\n", blk->offset, i); + goto err; + } + + cb = (struct dl_codeblock*)&image->data[blk->offset]; + if (blk->type == FW_BLOCK_TYPE_INSTR) { + if (cb->npe_addr + cb->size > instr_size) + goto too_big; + cmd = CMD_WR_INS_MEM; + } else if (blk->type == FW_BLOCK_TYPE_DATA) { + if (cb->npe_addr + cb->size > data_size) + goto too_big; + cmd = CMD_WR_DATA_MEM; + } else { + print_npe(KERN_INFO, npe, "invalid firmware block #%i " + "type 0x%X\n", i, blk->type); + goto err; + } + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) { + print_npe(KERN_INFO, npe, "firmware block #%i doesn't " + "fit in firmware image: type %c, start 0x%X," + " length 0x%X\n", i, + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', + cb->npe_addr, cb->size); + goto err; + } + + for (j = 0; j < cb->size; j++) + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]); + } + + npe_start(npe); + if (!npe_running(npe)) + print_npe(KERN_ERR, npe, "unable to start\n"); + release_firmware(fw_entry); + return 0; + +too_big: + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE " + "memory: type %c, start 0x%X, length 0x%X\n", i, + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D', + cb->npe_addr, cb->size); +err: + release_firmware(fw_entry); + return err; +} + + +struct npe *npe_request(int id) +{ + if (id < NPE_COUNT) + if (npe_tab[id].valid) + if (try_module_get(THIS_MODULE)) + return &npe_tab[id]; + return NULL; +} + +void npe_release(struct npe *npe) +{ + module_put(THIS_MODULE); +} + + +static int __init npe_init_module(void) +{ + + int i, found = 0; + + for (i = 0; i < NPE_COUNT; i++) { + struct npe *npe = &npe_tab[i]; + if (!(ixp4xx_read_feature_bits() & + (IXP4XX_FEATURE_RESET_NPEA << i))) + continue; /* NPE already disabled or not present */ + if (!(npe->mem_res = request_mem_region(npe->regs_phys, + REGS_SIZE, + npe_name(npe)))) { + print_npe(KERN_ERR, npe, + "failed to request memory region\n"); + continue; + } + + if (npe_reset(npe)) + continue; + npe->valid = 1; + found++; + } + + if (!found) + return -ENOSYS; + return 0; +} + +static void __exit npe_cleanup_module(void) +{ + int i; + + for (i = 0; i < NPE_COUNT; i++) + if (npe_tab[i].mem_res) { + npe_reset(&npe_tab[i]); + release_resource(npe_tab[i].mem_res); + } +} + +module_init(npe_init_module); +module_exit(npe_cleanup_module); + +MODULE_AUTHOR("Krzysztof Halasa"); +MODULE_LICENSE("GPL v2"); + +EXPORT_SYMBOL(npe_names); +EXPORT_SYMBOL(npe_running); +EXPORT_SYMBOL(npe_request); +EXPORT_SYMBOL(npe_release); +EXPORT_SYMBOL(npe_load_firmware); +EXPORT_SYMBOL(npe_send_message); +EXPORT_SYMBOL(npe_recv_message); +EXPORT_SYMBOL(npe_send_recv_message); diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c new file mode 100644 index 00000000000..e8330132530 --- /dev/null +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c @@ -0,0 +1,274 @@ +/* + * Intel IXP4xx Queue Manager driver for Linux + * + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#define DEBUG 0 + +struct qmgr_regs __iomem *qmgr_regs; +static struct resource *mem_res; +static spinlock_t qmgr_lock; +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ +static void (*irq_handlers[HALF_QUEUES])(void *pdev); +static void *irq_pdevs[HALF_QUEUES]; + +void qmgr_set_irq(unsigned int queue, int src, + void (*handler)(void *pdev), void *pdev) +{ + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */ + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ + unsigned long flags; + + src &= 7; + spin_lock_irqsave(&qmgr_lock, flags); + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg); + irq_handlers[queue] = handler; + irq_pdevs[queue] = pdev; + spin_unlock_irqrestore(&qmgr_lock, flags); +} + + +static irqreturn_t qmgr_irq1(int irq, void *pdev) +{ + int i; + u32 val = __raw_readl(&qmgr_regs->irqstat[0]); + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */ + + for (i = 0; i < HALF_QUEUES; i++) + if (val & (1 << i)) + irq_handlers[i](irq_pdevs[i]); + + return val ? IRQ_HANDLED : 0; +} + + +void qmgr_enable_irq(unsigned int queue) +{ + unsigned long flags; + + spin_lock_irqsave(&qmgr_lock, flags); + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue), + &qmgr_regs->irqen[0]); + spin_unlock_irqrestore(&qmgr_lock, flags); +} + +void qmgr_disable_irq(unsigned int queue) +{ + unsigned long flags; + + spin_lock_irqsave(&qmgr_lock, flags); + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), + &qmgr_regs->irqen[0]); + spin_unlock_irqrestore(&qmgr_lock, flags); +} + +static inline void shift_mask(u32 *mask) +{ + mask[3] = mask[3] << 1 | mask[2] >> 31; + mask[2] = mask[2] << 1 | mask[1] >> 31; + mask[1] = mask[1] << 1 | mask[0] >> 31; + mask[0] <<= 1; +} + +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, + unsigned int nearly_empty_watermark, + unsigned int nearly_full_watermark) +{ + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ + int err; + + if (queue >= HALF_QUEUES) + return -ERANGE; + + if ((nearly_empty_watermark | nearly_full_watermark) & ~7) + return -EINVAL; + + switch (len) { + case 16: + cfg = 0 << 24; + mask[0] = 0x1; + break; + case 32: + cfg = 1 << 24; + mask[0] = 0x3; + break; + case 64: + cfg = 2 << 24; + mask[0] = 0xF; + break; + case 128: + cfg = 3 << 24; + mask[0] = 0xFF; + break; + default: + return -EINVAL; + } + + cfg |= nearly_empty_watermark << 26; + cfg |= nearly_full_watermark << 29; + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */ + mask[1] = mask[2] = mask[3] = 0; + + if (!try_module_get(THIS_MODULE)) + return -ENODEV; + + spin_lock_irq(&qmgr_lock); + if (__raw_readl(&qmgr_regs->sram[queue])) { + err = -EBUSY; + goto err; + } + + while (1) { + if (!(used_sram_bitmap[0] & mask[0]) && + !(used_sram_bitmap[1] & mask[1]) && + !(used_sram_bitmap[2] & mask[2]) && + !(used_sram_bitmap[3] & mask[3])) + break; /* found free space */ + + addr++; + shift_mask(mask); + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) { + printk(KERN_ERR "qmgr: no free SRAM space for" + " queue %i\n", queue); + err = -ENOMEM; + goto err; + } + } + + used_sram_bitmap[0] |= mask[0]; + used_sram_bitmap[1] |= mask[1]; + used_sram_bitmap[2] |= mask[2]; + used_sram_bitmap[3] |= mask[3]; + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); + spin_unlock_irq(&qmgr_lock); + +#if DEBUG + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n", + queue, addr); +#endif + return 0; + +err: + spin_unlock_irq(&qmgr_lock); + module_put(THIS_MODULE); + return err; +} + +void qmgr_release_queue(unsigned int queue) +{ + u32 cfg, addr, mask[4]; + + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */ + + spin_lock_irq(&qmgr_lock); + cfg = __raw_readl(&qmgr_regs->sram[queue]); + addr = (cfg >> 14) & 0xFF; + + BUG_ON(!addr); /* not requested */ + + switch ((cfg >> 24) & 3) { + case 0: mask[0] = 0x1; break; + case 1: mask[0] = 0x3; break; + case 2: mask[0] = 0xF; break; + case 3: mask[0] = 0xFF; break; + } + + while (addr--) + shift_mask(mask); + + __raw_writel(0, &qmgr_regs->sram[queue]); + + used_sram_bitmap[0] &= ~mask[0]; + used_sram_bitmap[1] &= ~mask[1]; + used_sram_bitmap[2] &= ~mask[2]; + used_sram_bitmap[3] &= ~mask[3]; + irq_handlers[queue] = NULL; /* catch IRQ bugs */ + spin_unlock_irq(&qmgr_lock); + + module_put(THIS_MODULE); +#if DEBUG + printk(KERN_DEBUG "qmgr: released queue %i\n", queue); +#endif +} + +static int qmgr_init(void) +{ + int i, err; + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS, + IXP4XX_QMGR_REGION_SIZE, + "IXP4xx Queue Manager"); + if (mem_res == NULL) + return -EBUSY; + + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); + if (qmgr_regs == NULL) { + err = -ENOMEM; + goto error_map; + } + + /* reset qmgr registers */ + for (i = 0; i < 4; i++) { + __raw_writel(0x33333333, &qmgr_regs->stat1[i]); + __raw_writel(0, &qmgr_regs->irqsrc[i]); + } + for (i = 0; i < 2; i++) { + __raw_writel(0, &qmgr_regs->stat2[i]); + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */ + __raw_writel(0, &qmgr_regs->irqen[i]); + } + + for (i = 0; i < QUEUES; i++) + __raw_writel(0, &qmgr_regs->sram[i]); + + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0, + "IXP4xx Queue Manager", NULL); + if (err) { + printk(KERN_ERR "qmgr: failed to request IRQ%i\n", + IRQ_IXP4XX_QM1); + goto error_irq; + } + + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */ + spin_lock_init(&qmgr_lock); + + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n"); + return 0; + +error_irq: + iounmap(qmgr_regs); +error_map: + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); + return err; +} + +static void qmgr_remove(void) +{ + free_irq(IRQ_IXP4XX_QM1, NULL); + synchronize_irq(IRQ_IXP4XX_QM1); + iounmap(qmgr_regs); + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); +} + +module_init(qmgr_init); +module_exit(qmgr_remove); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Krzysztof Halasa"); + +EXPORT_SYMBOL(qmgr_regs); +EXPORT_SYMBOL(qmgr_set_irq); +EXPORT_SYMBOL(qmgr_enable_irq); +EXPORT_SYMBOL(qmgr_disable_irq); +EXPORT_SYMBOL(qmgr_request_queue); +EXPORT_SYMBOL(qmgr_release_queue); diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h new file mode 100644 index 00000000000..37d0511689d --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/npe.h @@ -0,0 +1,39 @@ +#ifndef __IXP4XX_NPE_H +#define __IXP4XX_NPE_H + +#include + +extern const char *npe_names[]; + +struct npe_regs { + u32 exec_addr, exec_data, exec_status_cmd, exec_count; + u32 action_points[4]; + u32 watchpoint_fifo, watch_count; + u32 profile_count; + u32 messaging_status, messaging_control; + u32 mailbox_status, /*messaging_*/ in_out_fifo; +}; + +struct npe { + struct resource *mem_res; + struct npe_regs __iomem *regs; + u32 regs_phys; + int id; + int valid; +}; + + +static inline const char *npe_name(struct npe *npe) +{ + return npe_names[npe->id]; +} + +int npe_running(struct npe *npe); +int npe_send_message(struct npe *npe, const void *msg, const char *what); +int npe_recv_message(struct npe *npe, void *msg, const char *what); +int npe_send_recv_message(struct npe *npe, void *msg, const char *what); +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); +struct npe *npe_request(int id); +void npe_release(struct npe *npe); + +#endif /* __IXP4XX_NPE_H */ diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h new file mode 100644 index 00000000000..1e52b95cede --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/qmgr.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2007 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + */ + +#ifndef IXP4XX_QMGR_H +#define IXP4XX_QMGR_H + +#include +#include + +#define HALF_QUEUES 32 +#define QUEUES 64 /* only 32 lower queues currently supported */ +#define MAX_QUEUE_LENGTH 4 /* in dwords */ + +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */ +#define QUEUE_STAT1_NEARLY_EMPTY 2 +#define QUEUE_STAT1_NEARLY_FULL 4 +#define QUEUE_STAT1_FULL 8 +#define QUEUE_STAT2_UNDERFLOW 1 +#define QUEUE_STAT2_OVERFLOW 2 + +#define QUEUE_WATERMARK_0_ENTRIES 0 +#define QUEUE_WATERMARK_1_ENTRY 1 +#define QUEUE_WATERMARK_2_ENTRIES 2 +#define QUEUE_WATERMARK_4_ENTRIES 3 +#define QUEUE_WATERMARK_8_ENTRIES 4 +#define QUEUE_WATERMARK_16_ENTRIES 5 +#define QUEUE_WATERMARK_32_ENTRIES 6 +#define QUEUE_WATERMARK_64_ENTRIES 7 + +/* queue interrupt request conditions */ +#define QUEUE_IRQ_SRC_EMPTY 0 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2 +#define QUEUE_IRQ_SRC_FULL 3 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6 +#define QUEUE_IRQ_SRC_NOT_FULL 7 + +struct qmgr_regs { + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */ + u32 stat1[4]; /* 0x400 - 0x40F */ + u32 stat2[2]; /* 0x410 - 0x417 */ + u32 statne_h; /* 0x418 - queue nearly empty */ + u32 statf_h; /* 0x41C - queue full */ + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */ + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */ + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */ + u32 reserved[1776]; + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */ +}; + +void qmgr_set_irq(unsigned int queue, int src, + void (*handler)(void *pdev), void *pdev); +void qmgr_enable_irq(unsigned int queue); +void qmgr_disable_irq(unsigned int queue); + +/* request_ and release_queue() must be called from non-IRQ context */ +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, + unsigned int nearly_empty_watermark, + unsigned int nearly_full_watermark); +void qmgr_release_queue(unsigned int queue); + + +static inline void qmgr_put_entry(unsigned int queue, u32 val) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + __raw_writel(val, &qmgr_regs->acc[queue][0]); +} + +static inline u32 qmgr_get_entry(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return __raw_readl(&qmgr_regs->acc[queue][0]); +} + +static inline int qmgr_get_stat1(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) + >> ((queue & 7) << 2)) & 0xF; +} + +static inline int qmgr_get_stat2(unsigned int queue) +{ + extern struct qmgr_regs __iomem *qmgr_regs; + return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) + >> ((queue & 0xF) << 1)) & 0x3; +} + +static inline int qmgr_stat_empty(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); +} + +static inline int qmgr_stat_nearly_empty(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); +} + +static inline int qmgr_stat_nearly_full(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); +} + +static inline int qmgr_stat_full(unsigned int queue) +{ + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); +} + +static inline int qmgr_stat_underflow(unsigned int queue) +{ + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); +} + +static inline int qmgr_stat_overflow(unsigned int queue) +{ + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); +} + +#endif -- cgit v1.2.3-70-g09d2 From 80bbdd27e4016ad39d33160ea7f39ac05bfe1d7c Mon Sep 17 00:00:00 2001 From: Krzysztof Halasa Date: Tue, 29 Jan 2008 01:03:00 +0100 Subject: [ARM] 4714/2: Headers for IXP4xx built-in Ethernet and WAN drivers Adds platform structs and #defines required by drivers for IXP4xx built-in Ethernet and WAN (sync serial) ports. The actual drivers will reside in drivers/net/arm and drivers/net/wan and will be submitted separately. Signed-off-by: Krzysztof Halasa Signed-off-by: Rod Whitby Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/platform.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h index 2ce28e3fd32..a1f2b5404db 100644 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ b/include/asm-arm/arch-ixp4xx/platform.h @@ -91,6 +91,27 @@ struct ixp4xx_pata_data { struct sys_timer; +#define IXP4XX_ETH_NPEA 0x00 +#define IXP4XX_ETH_NPEB 0x10 +#define IXP4XX_ETH_NPEC 0x20 + +/* Information about built-in Ethernet MAC interfaces */ +struct eth_plat_info { + u8 phy; /* MII PHY ID, 0 - 31 */ + u8 rxq; /* configurable, currently 0 - 31 only */ + u8 txreadyq; + u8 hwaddr[6]; +}; + +/* Information about built-in HSS (synchronous serial) interfaces */ +struct hss_plat_info { + int (*set_clock)(int port, unsigned int clock_type); + int (*open)(int port, void *pdev, + void (*set_carrier_cb)(void *pdev, int carrier)); + void (*close)(int port, void *pdev); + u8 txreadyq; +}; + /* * Frequency of clock used for primary clocksource */ -- cgit v1.2.3-70-g09d2 From 78225913709915d02a0a8025a1efcb767c6bdfe0 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Thu, 31 Jan 2008 12:44:03 +0100 Subject: [ARM] 4715/2: Ethernet support for IXDP425 boards Adds IXDP425 platform support for two built-in 10/100 Ethernet ports. This patch will do nothing until the actual Ethernet driver is also included. Signed-off-by: Krzysztof Halasa Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/ixdp425-setup.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c index e89070da28b..44584afb34a 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c @@ -177,6 +177,31 @@ static struct platform_device ixdp425_uart = { .resource = ixdp425_uart_resources }; +/* Built-in 10/100 Ethernet MAC interfaces */ +static struct eth_plat_info ixdp425_plat_eth[] = { + { + .phy = 0, + .rxq = 3, + .txreadyq = 20, + }, { + .phy = 1, + .rxq = 4, + .txreadyq = 21, + } +}; + +static struct platform_device ixdp425_eth[] = { + { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = ixdp425_plat_eth, + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = ixdp425_plat_eth + 1, + } +}; + static struct platform_device *ixdp425_devices[] __initdata = { &ixdp425_i2c_gpio, &ixdp425_flash, @@ -184,7 +209,9 @@ static struct platform_device *ixdp425_devices[] __initdata = { defined(CONFIG_MTD_NAND_PLATFORM_MODULE) &ixdp425_flash_nand, #endif - &ixdp425_uart + &ixdp425_uart, + &ixdp425_eth[0], + &ixdp425_eth[1], }; static void __init ixdp425_init(void) -- cgit v1.2.3-70-g09d2 From 1208ebf25b654a48f075c191de1d6410af7062b0 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Sat, 2 Feb 2008 00:03:56 +0100 Subject: [ARM] 4805/1: ixp4xx: Use leds-gpio driver instead of IXP4XX-GPIO-LED driver These are the only three boards to use the IXP4XX-GPIO-LED driver, and they can all use the new leds-gpio driver instead with no change in functionality. -- Signed-off-by: Rod Whitby Signed-off-by: Russell King --- arch/arm/configs/ixp4xx_defconfig | 4 ++-- arch/arm/mach-ixp4xx/dsmg600-setup.c | 36 ++++++++++++++++-------------------- arch/arm/mach-ixp4xx/nas100d-setup.c | 31 ++++++++++++++----------------- arch/arm/mach-ixp4xx/nslu2-setup.c | 34 ++++++++++++++-------------------- 4 files changed, 46 insertions(+), 59 deletions(-) diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index 2d5ae33f0ba..77fe3b00514 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -1330,8 +1330,8 @@ CONFIG_LEDS_CLASS=y # # LED drivers # -CONFIG_LEDS_IXP4XX=y -# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_IXP4XX is not set +CONFIG_LEDS_GPIO=y # # LED Triggers diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index a1c44efc45f..d0e129566fb 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -58,29 +59,28 @@ static struct i2c_board_info __initdata dsmg600_i2c_board_info [] = { }, }; -#ifdef CONFIG_LEDS_CLASS -static struct resource dsmg600_led_resources[] = { +static struct gpio_led dsmg600_led_pins[] = { { - .name = "power", - .start = DSMG600_LED_PWR_GPIO, - .end = DSMG600_LED_PWR_GPIO, - .flags = IXP4XX_GPIO_HIGH, + .name = "power", + .gpio = DSMG600_LED_PWR_GPIO, }, { - .name = "wlan", - .start = DSMG600_LED_WLAN_GPIO, - .end = DSMG600_LED_WLAN_GPIO, - .flags = IXP4XX_GPIO_LOW, + .name = "wlan", + .gpio = DSMG600_LED_WLAN_GPIO, + .active_low = true, }, }; +static struct gpio_led_platform_data dsmg600_led_data = { + .num_leds = ARRAY_SIZE(dsmg600_led_pins), + .leds = dsmg600_led_pins, +}; + static struct platform_device dsmg600_leds = { - .name = "IXP4XX-GPIO-LED", - .id = -1, - .num_resources = ARRAY_SIZE(dsmg600_led_resources), - .resource = dsmg600_led_resources, + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &dsmg600_led_data, }; -#endif static struct resource dsmg600_uart_resources[] = { { @@ -128,6 +128,7 @@ static struct platform_device dsmg600_uart = { static struct platform_device *dsmg600_devices[] __initdata = { &dsmg600_i2c_gpio, &dsmg600_flash, + &dsmg600_leds, }; static void dsmg600_power_off(void) @@ -175,11 +176,6 @@ static void __init dsmg600_init(void) (void)platform_device_register(&dsmg600_uart); platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices)); - -#ifdef CONFIG_LEDS_CLASS - /* We don't care whether or not this works. */ - (void)platform_device_register(&dsmg600_leds); -#endif } MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index dc782d06c2b..5801579ae95 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -46,35 +46,34 @@ static struct i2c_board_info __initdata nas100d_i2c_board_info [] = { }, }; -#ifdef CONFIG_LEDS_IXP4XX -static struct resource nas100d_led_resources[] = { +static struct gpio_led nas100d_led_pins[] = { { .name = "wlan", /* green led */ - .start = NAS100D_LED_WLAN_GPIO, - .end = NAS100D_LED_WLAN_GPIO, - .flags = IXP4XX_GPIO_LOW, + .gpio = NAS100D_LED_WLAN_GPIO, + .active_low = true, }, { .name = "power", /* blue power led (off=flashing) */ - .start = NAS100D_LED_PWR_GPIO, - .end = NAS100D_LED_PWR_GPIO, - .flags = IXP4XX_GPIO_LOW, + .gpio = NAS100D_LED_PWR_GPIO, + .active_low = true, }, { .name = "disk", /* yellow led */ - .start = NAS100D_LED_DISK_GPIO, - .end = NAS100D_LED_DISK_GPIO, - .flags = IXP4XX_GPIO_LOW, + .gpio = NAS100D_LED_DISK_GPIO, + .active_low = true, }, }; +static struct gpio_led_platform_data nas100d_led_data = { + .num_leds = ARRAY_SIZE(nas100d_led_pins), + .leds = nas100d_led_pins, +}; + static struct platform_device nas100d_leds = { - .name = "IXP4XX-GPIO-LED", + .name = "leds-gpio", .id = -1, - .num_resources = ARRAY_SIZE(nas100d_led_resources), - .resource = nas100d_led_resources, + .dev.platform_data = &nas100d_led_data, }; -#endif static struct i2c_gpio_platform_data nas100d_i2c_gpio_data = { .sda_pin = NAS100D_SDA_PIN, @@ -135,9 +134,7 @@ static struct platform_device nas100d_uart = { static struct platform_device *nas100d_devices[] __initdata = { &nas100d_i2c_gpio, &nas100d_flash, -#ifdef CONFIG_LEDS_IXP4XX &nas100d_leds, -#endif }; static void nas100d_power_off(void) diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index 16d091c98ea..41d55c84164 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -54,41 +54,37 @@ static struct i2c_board_info __initdata nslu2_i2c_board_info [] = { }, }; -#ifdef CONFIG_LEDS_IXP4XX -static struct resource nslu2_led_resources[] = { +static struct gpio_led nslu2_led_pins[] = { { .name = "ready", /* green led */ - .start = NSLU2_LED_GRN_GPIO, - .end = NSLU2_LED_GRN_GPIO, - .flags = IXP4XX_GPIO_HIGH, + .gpio = NSLU2_LED_GRN_GPIO, }, { .name = "status", /* red led */ - .start = NSLU2_LED_RED_GPIO, - .end = NSLU2_LED_RED_GPIO, - .flags = IXP4XX_GPIO_HIGH, + .gpio = NSLU2_LED_RED_GPIO, }, { .name = "disk-1", - .start = NSLU2_LED_DISK1_GPIO, - .end = NSLU2_LED_DISK1_GPIO, - .flags = IXP4XX_GPIO_LOW, + .gpio = NSLU2_LED_DISK1_GPIO, + .active_low = true, }, { .name = "disk-2", - .start = NSLU2_LED_DISK2_GPIO, - .end = NSLU2_LED_DISK2_GPIO, - .flags = IXP4XX_GPIO_LOW, + .gpio = NSLU2_LED_DISK2_GPIO, + .active_low = true, }, }; +static struct gpio_led_platform_data nslu2_led_data = { + .num_leds = ARRAY_SIZE(nslu2_led_pins), + .leds = nslu2_led_pins, +}; + static struct platform_device nslu2_leds = { - .name = "IXP4XX-GPIO-LED", + .name = "leds-gpio", .id = -1, - .num_resources = ARRAY_SIZE(nslu2_led_resources), - .resource = nslu2_led_resources, + .dev.platform_data = &nslu2_led_data, }; -#endif static struct platform_device nslu2_i2c_gpio = { .name = "i2c-gpio", @@ -151,9 +147,7 @@ static struct platform_device *nslu2_devices[] __initdata = { &nslu2_i2c_gpio, &nslu2_flash, &nslu2_beeper, -#ifdef CONFIG_LEDS_IXP4XX &nslu2_leds, -#endif }; static void nslu2_power_off(void) -- cgit v1.2.3-70-g09d2 From b7edc84a9619eb2c8bfb5265d4079da9c70ad270 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Sat, 2 Feb 2008 00:04:05 +0100 Subject: [ARM] 4806/1: ixp4xx: Ethernet support for the nslu2 and nas100d boards Enables the new ixp4xx qmgr and npe drivers in ixp4xx_defconfig. Sets up the corresponding platform data for the nslu2 and nas100d boards, and reads the ethernet MAC address from the internal flash. Tested on both little-endian and big-endian kernels. Tested-by: Tom King Signed-off-by: Rod Whitby Signed-off-by: Michael Westerhof Signed-off-by: Russell King --- arch/arm/configs/ixp4xx_defconfig | 8 +++++-- arch/arm/mach-ixp4xx/nas100d-setup.c | 43 +++++++++++++++++++++++++++++++++++ arch/arm/mach-ixp4xx/nslu2-setup.c | 44 ++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index 77fe3b00514..efa0485d2f7 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.24-rc8 -# Wed Jan 23 17:26:16 2008 +# Linux kernel version: 2.6.24 +# Sun Jan 27 07:33:38 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -174,6 +174,8 @@ CONFIG_MACH_GTWX5715=y # CONFIG_DMABOUNCE=y # CONFIG_IXP4XX_INDIRECT_PCI is not set +CONFIG_IXP4XX_QMGR=y +CONFIG_IXP4XX_NPE=y # # Boot options @@ -832,6 +834,7 @@ CONFIG_DUMMY=y # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y +CONFIG_IXP4XX_ETH=y # CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set @@ -925,6 +928,7 @@ CONFIG_HDLC_X25=m # CONFIG_PC300TOO is not set # CONFIG_FARSYNC is not set # CONFIG_DSCC4 is not set +# CONFIG_IXP4XX_HSS is not set CONFIG_DLCI=m CONFIG_DLCI_MAX=8 CONFIG_WAN_ROUTER_DRIVERS=m diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 5801579ae95..a432226b205 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -12,6 +12,7 @@ * */ +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include static struct flash_platform_data nas100d_flash_data = { .map_name = "cfi_probe", @@ -131,10 +133,28 @@ static struct platform_device nas100d_uart = { .resource = nas100d_uart_resources, }; +/* Built-in 10/100 Ethernet MAC interfaces */ +static struct eth_plat_info nas100d_plat_eth[] = { + { + .phy = 0, + .rxq = 3, + .txreadyq = 20, + } +}; + +static struct platform_device nas100d_eth[] = { + { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = nas100d_plat_eth, + } +}; + static struct platform_device *nas100d_devices[] __initdata = { &nas100d_i2c_gpio, &nas100d_flash, &nas100d_leds, + &nas100d_eth[0], }; static void nas100d_power_off(void) @@ -150,6 +170,10 @@ static void nas100d_power_off(void) static void __init nas100d_init(void) { + DECLARE_MAC_BUF(mac_buf); + uint8_t __iomem *f; + int i; + ixp4xx_sys_init(); /* gpio 14 and 15 are _not_ clocks */ @@ -172,6 +196,25 @@ static void __init nas100d_init(void) (void)platform_device_register(&nas100d_uart); platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices)); + + /* + * Map in a portion of the flash and read the MAC address. + * Since it is stored in BE in the flash itself, we need to + * byteswap it if we're in LE mode. + */ + f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000); + if (f) { + for (i = 0; i < 6; i++) +#ifdef __ARMEB__ + nas100d_plat_eth[0].hwaddr[i] = readb(f + 0xFC0FD8 + i); +#else + nas100d_plat_eth[0].hwaddr[i] = readb(f + 0xFC0FD8 + (i^3)); +#endif + iounmap(f); + } + printk(KERN_INFO "NAS100D: Using MAC address %s for port 0\n", + print_mac(mac_buf, nas100d_plat_eth[0].hwaddr)); + } MACHINE_START(NAS100D, "Iomega NAS 100d") diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index 41d55c84164..fd9ec17c8b8 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -14,6 +14,7 @@ * Changed to conform to new style __init ixdp425 kas11 10/22/04 */ +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include static struct flash_platform_data nslu2_flash_data = { .map_name = "cfi_probe", @@ -143,11 +145,29 @@ static struct platform_device nslu2_uart = { .resource = nslu2_uart_resources, }; +/* Built-in 10/100 Ethernet MAC interfaces */ +static struct eth_plat_info nslu2_plat_eth[] = { + { + .phy = 1, + .rxq = 3, + .txreadyq = 20, + } +}; + +static struct platform_device nslu2_eth[] = { + { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = nslu2_plat_eth, + } +}; + static struct platform_device *nslu2_devices[] __initdata = { &nslu2_i2c_gpio, &nslu2_flash, &nslu2_beeper, &nslu2_leds, + &nslu2_eth[0], }; static void nslu2_power_off(void) @@ -176,6 +196,10 @@ static struct sys_timer nslu2_timer = { static void __init nslu2_init(void) { + DECLARE_MAC_BUF(mac_buf); + uint8_t __iomem *f; + int i; + ixp4xx_sys_init(); nslu2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); @@ -195,6 +219,26 @@ static void __init nslu2_init(void) (void)platform_device_register(&nslu2_uart); platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices)); + + + /* + * Map in a portion of the flash and read the MAC address. + * Since it is stored in BE in the flash itself, we need to + * byteswap it if we're in LE mode. + */ + f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x40000); + if (f) { + for (i = 0; i < 6; i++) +#ifdef __ARMEB__ + nslu2_plat_eth[0].hwaddr[i] = readb(f + 0x3FFB0 + i); +#else + nslu2_plat_eth[0].hwaddr[i] = readb(f + 0x3FFB0 + (i^3)); +#endif + iounmap(f); + } + printk(KERN_INFO "NSLU2: Using MAC address %s for port 0\n", + print_mac(mac_buf, nslu2_plat_eth[0].hwaddr)); + } MACHINE_START(NSLU2, "Linksys NSLU2") -- cgit v1.2.3-70-g09d2 From 0929ac3ea4c0bece16b0c5c5365181fa45fbf582 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Sun, 3 Feb 2008 12:05:42 +0100 Subject: [ARM] 4807/2: ixp4xx: Merge nslu2-power.c into nslu2-setup.c There is no reason to have power control in a separate file from the board setup code. Merge it back into the board setup file, removing superfluous header includes and removing superfluous constants from the machine header file. -- Signed-off-by: Rod Whitby Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/Makefile | 2 +- arch/arm/mach-ixp4xx/nslu2-power.c | 91 ------------------------------------- arch/arm/mach-ixp4xx/nslu2-setup.c | 51 ++++++++++++++++++--- include/asm-arm/arch-ixp4xx/nslu2.h | 21 +-------- 4 files changed, 48 insertions(+), 117 deletions(-) delete mode 100644 arch/arm/mach-ixp4xx/nslu2-power.c diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index 4bb97e13f95..4fc7316191e 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MACH_AVILA) += avila-setup.o obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o -obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o nslu2-power.o +obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o nas100d-power.o obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o diff --git a/arch/arm/mach-ixp4xx/nslu2-power.c b/arch/arm/mach-ixp4xx/nslu2-power.c deleted file mode 100644 index 6f10dc20832..00000000000 --- a/arch/arm/mach-ixp4xx/nslu2-power.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/nslu2-power.c - * - * NSLU2 Power/Reset driver - * - * Copyright (C) 2005 Tower Technologies - * - * based on nslu2-io.c - * Copyright (C) 2004 Karen Spearel - * - * Author: Alessandro Zummo - * Maintainers: http://www.nslu2-linux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include - -#include - -static irqreturn_t nslu2_power_handler(int irq, void *dev_id) -{ - /* Signal init to do the ctrlaltdel action, this will bypass init if - * it hasn't started and do a kernel_restart. - */ - ctrl_alt_del(); - - return IRQ_HANDLED; -} - -static irqreturn_t nslu2_reset_handler(int irq, void *dev_id) -{ - /* This is the paper-clip reset, it shuts the machine down directly. - */ - machine_power_off(); - - return IRQ_HANDLED; -} - -static int __init nslu2_power_init(void) -{ - if (!(machine_is_nslu2())) - return 0; - - *IXP4XX_GPIO_GPISR = 0x20400000; /* read the 2 irqs to clr */ - - set_irq_type(NSLU2_RB_IRQ, IRQT_LOW); - set_irq_type(NSLU2_PB_IRQ, IRQT_HIGH); - - if (request_irq(NSLU2_RB_IRQ, &nslu2_reset_handler, - IRQF_DISABLED, "NSLU2 reset button", NULL) < 0) { - - printk(KERN_DEBUG "Reset Button IRQ %d not available\n", - NSLU2_RB_IRQ); - - return -EIO; - } - - if (request_irq(NSLU2_PB_IRQ, &nslu2_power_handler, - IRQF_DISABLED, "NSLU2 power button", NULL) < 0) { - - printk(KERN_DEBUG "Power Button IRQ %d not available\n", - NSLU2_PB_IRQ); - - return -EIO; - } - - return 0; -} - -static void __exit nslu2_power_exit(void) -{ - if (!(machine_is_nslu2())) - return; - - free_irq(NSLU2_RB_IRQ, NULL); - free_irq(NSLU2_PB_IRQ, NULL); -} - -module_init(nslu2_power_init); -module_exit(nslu2_power_exit); - -MODULE_AUTHOR("Alessandro Zummo "); -MODULE_DESCRIPTION("NSLU2 Power/Reset driver"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index fd9ec17c8b8..acaebcbce53 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -3,22 +3,26 @@ * * NSLU2 board-setup * - * based ixdp425-setup.c: + * Copyright (C) 2008 Rod Whitby + * + * based on ixdp425-setup.c: * Copyright (C) 2003-2004 MontaVista Software, Inc. + * based on nslu2-power.c: + * Copyright (C) 2005 Tower Technologies * * Author: Mark Rakes * Author: Rod Whitby + * Author: Alessandro Zummo * Maintainers: http://www.nslu2-linux.org/ * - * Fixed missing init_time in MACHINE_START kas11 10/22/04 - * Changed to conform to new style __init ixdp425 kas11 10/22/04 */ #include -#include +#include #include #include #include +#include #include #include @@ -27,6 +31,7 @@ #include #include #include +#include static struct flash_platform_data nslu2_flash_data = { .map_name = "cfi_probe", @@ -181,6 +186,25 @@ static void nslu2_power_off(void) gpio_line_set(NSLU2_PO_GPIO, IXP4XX_GPIO_HIGH); } +static irqreturn_t nslu2_power_handler(int irq, void *dev_id) +{ + /* Signal init to do the ctrlaltdel action, this will bypass init if + * it hasn't started and do a kernel_restart. + */ + ctrl_alt_del(); + + return IRQ_HANDLED; +} + +static irqreturn_t nslu2_reset_handler(int irq, void *dev_id) +{ + /* This is the paper-clip reset, it shuts the machine down directly. + */ + machine_power_off(); + + return IRQ_HANDLED; +} + static void __init nslu2_timer_init(void) { /* The xtal on this machine is non-standard. */ @@ -206,8 +230,6 @@ static void __init nslu2_init(void) nslu2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; - pm_power_off = nslu2_power_off; - i2c_register_board_info(0, nslu2_i2c_board_info, ARRAY_SIZE(nslu2_i2c_board_info)); @@ -220,6 +242,23 @@ static void __init nslu2_init(void) platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices)); + pm_power_off = nslu2_power_off; + + if (request_irq(gpio_to_irq(NSLU2_RB_GPIO), &nslu2_reset_handler, + IRQF_DISABLED | IRQF_TRIGGER_LOW, + "NSLU2 reset button", NULL) < 0) { + + printk(KERN_DEBUG "Reset Button IRQ %d not available\n", + gpio_to_irq(NSLU2_RB_GPIO)); + } + + if (request_irq(gpio_to_irq(NSLU2_PB_GPIO), &nslu2_power_handler, + IRQF_DISABLED | IRQF_TRIGGER_HIGH, + "NSLU2 power button", NULL) < 0) { + + printk(KERN_DEBUG "Power Button IRQ %d not available\n", + gpio_to_irq(NSLU2_PB_GPIO)); + } /* * Map in a portion of the flash and read the MAC address. diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h index 850fdc5b45d..714bbc65126 100644 --- a/include/asm-arm/arch-ixp4xx/nslu2.h +++ b/include/asm-arm/arch-ixp4xx/nslu2.h @@ -39,34 +39,17 @@ /* Buttons */ -#define NSLU2_PB_GPIO 5 +#define NSLU2_PB_GPIO 5 /* power button */ #define NSLU2_PO_GPIO 8 /* power off */ -#define NSLU2_RB_GPIO 12 - -#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5 -#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12 - -#define NSLU2_PB_BM (1L << NSLU2_PB_GPIO) -#define NSLU2_PO_BM (1L << NSLU2_PO_GPIO) -#define NSLU2_RB_BM (1L << NSLU2_RB_GPIO) +#define NSLU2_RB_GPIO 12 /* reset button */ /* Buzzer */ #define NSLU2_GPIO_BUZZ 4 -#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ) /* LEDs */ #define NSLU2_LED_RED_GPIO 0 #define NSLU2_LED_GRN_GPIO 1 - -#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED_GPIO) -#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN_GPIO) - #define NSLU2_LED_DISK1_GPIO 3 #define NSLU2_LED_DISK2_GPIO 2 - -#define NSLU2_LED_DISK1_BM (1L << NSLU2_LED_DISK1_GPIO) -#define NSLU2_LED_DISK2_BM (1L << NSLU2_LED_DISK2_GPIO) - - -- cgit v1.2.3-70-g09d2 From c7d1623e5820c46a39519e64fafb94f39419be82 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Sun, 3 Feb 2008 12:05:49 +0100 Subject: [ARM] 4808/2: ixp4xx: Merge nas100d-power.c into nas100d-setup.c There is no reason to have power control in a separate file from the board setup code. Merge it back into the board setup file and remove superfluous header includes. -- Signed-off-by: Rod Whitby Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/Makefile | 2 +- arch/arm/mach-ixp4xx/nas100d-power.c | 128 ----------------------------------- arch/arm/mach-ixp4xx/nas100d-setup.c | 90 ++++++++++++++++++++++-- 3 files changed, 87 insertions(+), 133 deletions(-) delete mode 100644 arch/arm/mach-ixp4xx/nas100d-power.c diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index 4fc7316191e..a7880aba3fa 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o -obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o nas100d-power.o +obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o diff --git a/arch/arm/mach-ixp4xx/nas100d-power.c b/arch/arm/mach-ixp4xx/nas100d-power.c deleted file mode 100644 index 4c1c01bb3fe..00000000000 --- a/arch/arm/mach-ixp4xx/nas100d-power.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/nas100d-power.c - * - * NAS 100d Power/Reset driver - * - * Copyright (C) 2005 Tower Technologies - * - * based on nas100d-io.c - * Copyright (C) 2004 Karen Spearel - * - * Author: Alessandro Zummo - * Maintainers: http://www.nslu2-linux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -/* This is used to make sure the power-button pusher is serious. The button - * must be held until the value of this counter reaches zero. - */ -static int power_button_countdown; - -/* Must hold the button down for at least this many counts to be processed */ -#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */ - -static void nas100d_power_handler(unsigned long data); -static DEFINE_TIMER(nas100d_power_timer, nas100d_power_handler, 0, 0); - -static void nas100d_power_handler(unsigned long data) -{ - /* This routine is called twice per second to check the - * state of the power button. - */ - - if (gpio_get_value(NAS100D_PB_GPIO)) { - - /* IO Pin is 1 (button pushed) */ - if (power_button_countdown > 0) - power_button_countdown--; - - } else { - - /* Done on button release, to allow for auto-power-on mods. */ - if (power_button_countdown == 0) { - /* Signal init to do the ctrlaltdel action, - * this will bypass init if it hasn't started - * and do a kernel_restart. - */ - ctrl_alt_del(); - - /* Change the state of the power LED to "blink" */ - gpio_line_set(NAS100D_LED_PWR_GPIO, IXP4XX_GPIO_LOW); - } else { - power_button_countdown = PBUTTON_HOLDDOWN_COUNT; - } - } - - mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); -} - -static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) -{ - /* This is the paper-clip reset, it shuts the machine down directly. */ - machine_power_off(); - - return IRQ_HANDLED; -} - -static int __init nas100d_power_init(void) -{ - if (!(machine_is_nas100d())) - return 0; - - set_irq_type(gpio_to_irq(NAS100D_RB_GPIO), IRQT_LOW); - - if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler, - IRQF_DISABLED, "NAS100D reset button", NULL) < 0) { - - printk(KERN_DEBUG "Reset Button IRQ %d not available\n", - gpio_to_irq(NAS100D_RB_GPIO)); - - return -EIO; - } - - /* The power button on the Iomega NAS100d is on GPIO 14, but - * it cannot handle interrupts on that GPIO line. So we'll - * have to poll it with a kernel timer. - */ - - /* Make sure that the power button GPIO is set up as an input */ - gpio_line_config(NAS100D_PB_GPIO, IXP4XX_GPIO_IN); - - /* Set the initial value for the power button IRQ handler */ - power_button_countdown = PBUTTON_HOLDDOWN_COUNT; - - mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); - - return 0; -} - -static void __exit nas100d_power_exit(void) -{ - if (!(machine_is_nas100d())) - return; - - del_timer_sync(&nas100d_power_timer); - - free_irq(gpio_to_irq(NAS100D_RB_GPIO), NULL); -} - -module_init(nas100d_power_init); -module_exit(nas100d_power_exit); - -MODULE_AUTHOR("Alessandro Zummo "); -MODULE_DESCRIPTION("NAS100D Power/Reset driver"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index a432226b205..4cecae84837 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -3,8 +3,14 @@ * * NAS 100d board-setup * - * based ixdp425-setup.c: + * Copyright (C) 2008 Rod Whitby + * + * based on ixdp425-setup.c: * Copyright (C) 2003-2004 MontaVista Software, Inc. + * based on nas100d-power.c: + * Copyright (C) 2005 Tower Technologies + * based on nas100d-io.c + * Copyright (C) 2004 Karen Spearel * * Author: Alessandro Zummo * Author: Rod Whitby @@ -13,10 +19,13 @@ */ #include -#include +#include +#include +#include #include #include #include +#include #include #include @@ -24,6 +33,7 @@ #include #include #include +#include static struct flash_platform_data nas100d_flash_data = { .map_name = "cfi_probe", @@ -168,6 +178,57 @@ static void nas100d_power_off(void) gpio_line_set(NAS100D_PO_GPIO, IXP4XX_GPIO_HIGH); } +/* This is used to make sure the power-button pusher is serious. The button + * must be held until the value of this counter reaches zero. + */ +static int power_button_countdown; + +/* Must hold the button down for at least this many counts to be processed */ +#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */ + +static void nas100d_power_handler(unsigned long data); +static DEFINE_TIMER(nas100d_power_timer, nas100d_power_handler, 0, 0); + +static void nas100d_power_handler(unsigned long data) +{ + /* This routine is called twice per second to check the + * state of the power button. + */ + + if (gpio_get_value(NAS100D_PB_GPIO)) { + + /* IO Pin is 1 (button pushed) */ + if (power_button_countdown > 0) + power_button_countdown--; + + } else { + + /* Done on button release, to allow for auto-power-on mods. */ + if (power_button_countdown == 0) { + /* Signal init to do the ctrlaltdel action, + * this will bypass init if it hasn't started + * and do a kernel_restart. + */ + ctrl_alt_del(); + + /* Change the state of the power LED to "blink" */ + gpio_line_set(NAS100D_LED_PWR_GPIO, IXP4XX_GPIO_LOW); + } else { + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + } + } + + mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); +} + +static irqreturn_t nas100d_reset_handler(int irq, void *dev_id) +{ + /* This is the paper-clip reset, it shuts the machine down directly. */ + machine_power_off(); + + return IRQ_HANDLED; +} + static void __init nas100d_init(void) { DECLARE_MAC_BUF(mac_buf); @@ -183,8 +244,6 @@ static void __init nas100d_init(void) nas100d_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; - pm_power_off = nas100d_power_off; - i2c_register_board_info(0, nas100d_i2c_board_info, ARRAY_SIZE(nas100d_i2c_board_info)); @@ -197,6 +256,29 @@ static void __init nas100d_init(void) platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices)); + pm_power_off = nas100d_power_off; + + if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler, + IRQF_DISABLED | IRQF_TRIGGER_LOW, + "NAS100D reset button", NULL) < 0) { + + printk(KERN_DEBUG "Reset Button IRQ %d not available\n", + gpio_to_irq(NAS100D_RB_GPIO)); + } + + /* The power button on the Iomega NAS100d is on GPIO 14, but + * it cannot handle interrupts on that GPIO line. So we'll + * have to poll it with a kernel timer. + */ + + /* Make sure that the power button GPIO is set up as an input */ + gpio_line_config(NAS100D_PB_GPIO, IXP4XX_GPIO_IN); + + /* Set the initial value for the power button IRQ handler */ + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + + mod_timer(&nas100d_power_timer, jiffies + msecs_to_jiffies(500)); + /* * Map in a portion of the flash and read the MAC address. * Since it is stored in BE in the flash itself, we need to -- cgit v1.2.3-70-g09d2 From 43816bcb72623c02a992e513feeaaf1178cea6dc Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Sun, 3 Feb 2008 12:05:55 +0100 Subject: [ARM] 4809/2: ixp4xx: Merge dsmg600-power.c into dsmg600-setup.c There is no reason to have power control in a separate file from the board setup code. Merge it back into the board setup file and remove superfluous header includes. -- Signed-off-by: Rod Whitby Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/Makefile | 2 +- arch/arm/mach-ixp4xx/dsmg600-power.c | 129 ----------------------------------- arch/arm/mach-ixp4xx/dsmg600-setup.c | 92 +++++++++++++++++++++++-- 3 files changed, 88 insertions(+), 135 deletions(-) delete mode 100644 arch/arm/mach-ixp4xx/dsmg600-power.c diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index a7880aba3fa..c1956882c48 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o -obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o dsmg600-power.o +obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o diff --git a/arch/arm/mach-ixp4xx/dsmg600-power.c b/arch/arm/mach-ixp4xx/dsmg600-power.c deleted file mode 100644 index db639877712..00000000000 --- a/arch/arm/mach-ixp4xx/dsmg600-power.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/dsmg600-power.c - * - * DSM-G600 Power/Reset driver - * Author: Michael Westerhof - * - * Based on nslu2-power.c - * Copyright (C) 2005 Tower Technologies - * Author: Alessandro Zummo - * - * which was based on nslu2-io.c - * Copyright (C) 2004 Karen Spearel - * - * Maintainers: http://www.nslu2-linux.org/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -/* This is used to make sure the power-button pusher is serious. The button - * must be held until the value of this counter reaches zero. - */ -static int power_button_countdown; - -/* Must hold the button down for at least this many counts to be processed */ -#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */ - -static void dsmg600_power_handler(unsigned long data); -static DEFINE_TIMER(dsmg600_power_timer, dsmg600_power_handler, 0, 0); - -static void dsmg600_power_handler(unsigned long data) -{ - /* This routine is called twice per second to check the - * state of the power button. - */ - - if (gpio_get_value(DSMG600_PB_GPIO)) { - - /* IO Pin is 1 (button pushed) */ - if (power_button_countdown > 0) - power_button_countdown--; - - } else { - - /* Done on button release, to allow for auto-power-on mods. */ - if (power_button_countdown == 0) { - /* Signal init to do the ctrlaltdel action, - * this will bypass init if it hasn't started - * and do a kernel_restart. - */ - ctrl_alt_del(); - - /* Change the state of the power LED to "blink" */ - gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW); - } else { - power_button_countdown = PBUTTON_HOLDDOWN_COUNT; - } - } - - mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); -} - -static irqreturn_t dsmg600_reset_handler(int irq, void *dev_id) -{ - /* This is the paper-clip reset, it shuts the machine down directly. */ - machine_power_off(); - - return IRQ_HANDLED; -} - -static int __init dsmg600_power_init(void) -{ - if (!(machine_is_dsmg600())) - return 0; - - if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler, - IRQF_DISABLED | IRQF_TRIGGER_LOW, "DSM-G600 reset button", - NULL) < 0) { - - printk(KERN_DEBUG "Reset Button IRQ %d not available\n", - gpio_to_irq(DSMG600_RB_GPIO)); - - return -EIO; - } - - /* The power button on the D-Link DSM-G600 is on GPIO 15, but - * it cannot handle interrupts on that GPIO line. So we'll - * have to poll it with a kernel timer. - */ - - /* Make sure that the power button GPIO is set up as an input */ - gpio_line_config(DSMG600_PB_GPIO, IXP4XX_GPIO_IN); - - /* Set the initial value for the power button IRQ handler */ - power_button_countdown = PBUTTON_HOLDDOWN_COUNT; - - mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); - - return 0; -} - -static void __exit dsmg600_power_exit(void) -{ - if (!(machine_is_dsmg600())) - return; - - del_timer_sync(&dsmg600_power_timer); - - free_irq(gpio_to_irq(DSMG600_RB_GPIO), NULL); -} - -module_init(dsmg600_power_init); -module_exit(dsmg600_power_exit); - -MODULE_AUTHOR("Michael Westerhof "); -MODULE_DESCRIPTION("DSM-G600 Power/Reset driver"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c index d0e129566fb..688659668bd 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-setup.c +++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c @@ -1,20 +1,29 @@ /* * DSM-G600 board-setup * + * Copyright (C) 2008 Rod Whitby * Copyright (C) 2006 Tower Technologies - * Author: Alessandro Zummo * - * based ixdp425-setup.c: + * based on ixdp425-setup.c: * Copyright (C) 2003-2004 MontaVista Software, Inc. + * based on nslu2-power.c: + * Copyright (C) 2005 Tower Technologies + * based on nslu2-io.c: + * Copyright (C) 2004 Karen Spearel * * Author: Alessandro Zummo + * Author: Michael Westerhof + * Author: Rod Whitby * Maintainers: http://www.nslu2-linux.org/ */ -#include +#include +#include +#include #include #include #include +#include #include #include @@ -22,6 +31,7 @@ #include #include #include +#include static struct flash_platform_data dsmg600_flash_data = { .map_name = "cfi_probe", @@ -140,6 +150,57 @@ static void dsmg600_power_off(void) gpio_line_set(DSMG600_PO_GPIO, IXP4XX_GPIO_HIGH); } +/* This is used to make sure the power-button pusher is serious. The button + * must be held until the value of this counter reaches zero. + */ +static int power_button_countdown; + +/* Must hold the button down for at least this many counts to be processed */ +#define PBUTTON_HOLDDOWN_COUNT 4 /* 2 secs */ + +static void dsmg600_power_handler(unsigned long data); +static DEFINE_TIMER(dsmg600_power_timer, dsmg600_power_handler, 0, 0); + +static void dsmg600_power_handler(unsigned long data) +{ + /* This routine is called twice per second to check the + * state of the power button. + */ + + if (gpio_get_value(DSMG600_PB_GPIO)) { + + /* IO Pin is 1 (button pushed) */ + if (power_button_countdown > 0) + power_button_countdown--; + + } else { + + /* Done on button release, to allow for auto-power-on mods. */ + if (power_button_countdown == 0) { + /* Signal init to do the ctrlaltdel action, + * this will bypass init if it hasn't started + * and do a kernel_restart. + */ + ctrl_alt_del(); + + /* Change the state of the power LED to "blink" */ + gpio_line_set(DSMG600_LED_PWR_GPIO, IXP4XX_GPIO_LOW); + } else { + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + } + } + + mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); +} + +static irqreturn_t dsmg600_reset_handler(int irq, void *dev_id) +{ + /* This is the paper-clip reset, it shuts the machine down directly. */ + machine_power_off(); + + return IRQ_HANDLED; +} + static void __init dsmg600_timer_init(void) { /* The xtal on this machine is non-standard. */ @@ -164,8 +225,6 @@ static void __init dsmg600_init(void) dsmg600_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; - pm_power_off = dsmg600_power_off; - i2c_register_board_info(0, dsmg600_i2c_board_info, ARRAY_SIZE(dsmg600_i2c_board_info)); @@ -176,6 +235,29 @@ static void __init dsmg600_init(void) (void)platform_device_register(&dsmg600_uart); platform_add_devices(dsmg600_devices, ARRAY_SIZE(dsmg600_devices)); + + pm_power_off = dsmg600_power_off; + + if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler, + IRQF_DISABLED | IRQF_TRIGGER_LOW, + "DSM-G600 reset button", NULL) < 0) { + + printk(KERN_DEBUG "Reset Button IRQ %d not available\n", + gpio_to_irq(DSMG600_RB_GPIO)); + } + + /* The power button on the D-Link DSM-G600 is on GPIO 15, but + * it cannot handle interrupts on that GPIO line. So we'll + * have to poll it with a kernel timer. + */ + + /* Make sure that the power button GPIO is set up as an input */ + gpio_line_config(DSMG600_PB_GPIO, IXP4XX_GPIO_IN); + + /* Set the initial value for the power button IRQ handler */ + power_button_countdown = PBUTTON_HOLDDOWN_COUNT; + + mod_timer(&dsmg600_power_timer, jiffies + msecs_to_jiffies(500)); } MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") -- cgit v1.2.3-70-g09d2 From e83aff58bf1b7e6b355a0cfa206e9d3aebe5623f Mon Sep 17 00:00:00 2001 From: David Brownell Date: Fri, 4 Jan 2008 18:30:24 +0100 Subject: [ARM] 4739/1: at91sam9263: make gpio bank C and D irqs work On the at91sam9263, IRQs for GPIO banks C and D don't currently work. This is because banks C, D, and E share one clock and toplevel IRQ, but the AT91 code setting up and handling GPIO IRQs expects no sharing. This patch: - Fixes GPIO IRQ setup and handling to cope with GPIO banks that are shared like on sam9263 chips, by setting up a list of those banks and making the IRQ dispatching logic scan that list. - Precomputes the address of each bank's registers, saving it with other per-bank data so that it no longer needs to be constantly recomputed during IRQs and other GPIO operations. That shrinks hot-path code, while helping the GPIO bank irq updates. - Fixes a minor bug where IRQ_TYPE_NONE was wrongly rejected (it just means "use the default", which is "both edges" here). Signed-off-by: David Brownell Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/generic.h | 3 ++ arch/arm/mach-at91/gpio.c | 89 +++++++++++++++++++++++++++++--------------- 2 files changed, 63 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index b5daf7f5e01..7b9ce7a336b 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -47,6 +47,9 @@ extern void at91_irq_resume(void); #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ struct at91_gpio_bank { + unsigned chipbase; /* bank's first GPIO number */ + void __iomem *regbase; /* base of register bank */ + struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */ unsigned short id; /* peripheral ID */ unsigned long offset; /* offset from system peripheral base */ struct clk *clock; /* associated clock */ diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index 6aeddd68d8a..f629c2b5f0c 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -33,12 +33,10 @@ static int gpio_banks; static inline void __iomem *pin_to_controller(unsigned pin) { - void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS; - pin -= PIN_BASE; pin /= 32; if (likely(pin < gpio_banks)) - return sys_base + gpio[pin].offset; + return gpio[pin].regbase; return NULL; } @@ -294,11 +292,11 @@ void at91_gpio_suspend(void) int i; for (i = 0; i < gpio_banks; i++) { - u32 pio = gpio[i].offset; + void __iomem *pio = gpio[i].regbase; - backups[i] = at91_sys_read(pio + PIO_IMR); - at91_sys_write(pio + PIO_IDR, backups[i]); - at91_sys_write(pio + PIO_IER, wakeups[i]); + backups[i] = __raw_readl(pio + PIO_IMR); + __raw_writel(backups[i], pio + PIO_IDR); + __raw_writel(wakeups[i], pio + PIO_IER); if (!wakeups[i]) clk_disable(gpio[i].clock); @@ -315,13 +313,13 @@ void at91_gpio_resume(void) int i; for (i = 0; i < gpio_banks; i++) { - u32 pio = gpio[i].offset; + void __iomem *pio = gpio[i].regbase; if (!wakeups[i]) clk_enable(gpio[i].clock); - at91_sys_write(pio + PIO_IDR, wakeups[i]); - at91_sys_write(pio + PIO_IER, backups[i]); + __raw_writel(wakeups[i], pio + PIO_IDR); + __raw_writel(backups[i], pio + PIO_IER); } } @@ -361,7 +359,13 @@ static void gpio_irq_unmask(unsigned pin) static int gpio_irq_type(unsigned pin, unsigned type) { - return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL; + switch (type) { + case IRQ_TYPE_NONE: + case IRQ_TYPE_EDGE_BOTH: + return 0; + default: + return -EINVAL; + } } static struct irq_chip gpio_irqchip = { @@ -376,20 +380,30 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { unsigned pin; struct irq_desc *gpio; + struct at91_gpio_bank *bank; void __iomem *pio; u32 isr; - pio = get_irq_chip_data(irq); + bank = get_irq_chip_data(irq); + pio = bank->regbase; /* temporarily mask (level sensitive) parent IRQ */ desc->chip->ack(irq); for (;;) { - /* reading ISR acks the pending (edge triggered) GPIO interrupt */ + /* Reading ISR acks pending (edge triggered) GPIO interrupts. + * When there none are pending, we're finished unless we need + * to process multiple banks (like ID_PIOCDE on sam9263). + */ isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); - if (!isr) - break; + if (!isr) { + if (!bank->next) + break; + bank = bank->next; + pio = bank->regbase; + continue; + } - pin = (unsigned) get_irq_data(irq); + pin = bank->chipbase; gpio = &irq_desc[pin]; while (isr) { @@ -481,24 +495,21 @@ postcore_initcall(at91_gpio_debugfs_init); */ void __init at91_gpio_irq_setup(void) { - unsigned pioc, pin; + unsigned pioc, pin; + struct at91_gpio_bank *this, *prev; - for (pioc = 0, pin = PIN_BASE; - pioc < gpio_banks; - pioc++) { - void __iomem *controller; - unsigned id = gpio[pioc].id; + for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL; + pioc++ < gpio_banks; + prev = this, this++) { + unsigned id = this->id; unsigned i; - clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ - - controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset; - __raw_writel(~0, controller + PIO_IDR); + /* enable PIO controller's clock */ + clk_enable(this->clock); - set_irq_data(id, (void *) pin); - set_irq_chip_data(id, controller); + __raw_writel(~0, this->regbase + PIO_IDR); - for (i = 0; i < 32; i++, pin++) { + for (i = 0, pin = this->chipbase; i < 32; i++, pin++) { /* * Can use the "simple" and not "edge" handler since it's * shorter, and the AIC handles interrupts sanely. @@ -508,6 +519,14 @@ void __init at91_gpio_irq_setup(void) set_irq_flags(pin, IRQF_VALID); } + /* The toplevel handler handles one bank of GPIOs, except + * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in + * the list, so we only set up that handler. + */ + if (prev && prev->next == this) + continue; + + set_irq_chip_data(id, this); set_irq_chained_handler(id, gpio_irq_handler); } pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); @@ -518,8 +537,20 @@ void __init at91_gpio_irq_setup(void) */ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) { + unsigned i; + struct at91_gpio_bank *last; + BUG_ON(nr_banks > MAX_GPIO_BANKS); gpio = data; gpio_banks = nr_banks; + + for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) { + data->chipbase = PIN_BASE + i * 32; + data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS; + + /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ + if (last && last->id == data->id) + last->next = data; + } } -- cgit v1.2.3-70-g09d2 From fa3218d8594869b38b1a170ea36d176ac455b897 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 29 Jan 2008 15:43:13 +0100 Subject: [ARM] 4660/3: at91: allow selecting UART for early kernel messages Currently early kernel messages, i.e., those from uncompression, go to the debugging UART. And if it is enabled in the platform configuration, but not initialized by the bootloader, the machine hangs, waiting for UART status change. Besides, having those messages on another UART - typically the console UART - may be preferrable. This patch allows selecting the UART in kernel configuration. Signed-off-by: Guennadi Liakhovetski Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/Kconfig | 30 ++++++++ drivers/serial/atmel_serial.c | 3 +- drivers/serial/atmel_serial.h | 127 -------------------------------- include/asm-arm/arch-at91/at91rm9200.h | 5 ++ include/asm-arm/arch-at91/at91sam9260.h | 7 ++ include/asm-arm/arch-at91/at91sam9261.h | 4 + include/asm-arm/arch-at91/at91sam9263.h | 4 + include/asm-arm/arch-at91/at91sam9rl.h | 5 ++ include/asm-arm/arch-at91/uncompress.h | 32 ++++++-- include/linux/atmel_serial.h | 127 ++++++++++++++++++++++++++++++++ 10 files changed, 207 insertions(+), 137 deletions(-) delete mode 100644 drivers/serial/atmel_serial.h create mode 100644 include/linux/atmel_serial.h diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 5b0422cdde7..074dcd5d9a7 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -253,6 +253,36 @@ config AT91_TIMER_HZ system clock (of at least several MHz), rounding is less of a problem so it can be safer to use a decimal values like 100. +choice + prompt "Select a UART for early kernel messages" + +config AT91_EARLY_DBGU + bool "DBGU" + +config AT91_EARLY_USART0 + bool "USART0" + +config AT91_EARLY_USART1 + bool "USART1" + +config AT91_EARLY_USART2 + bool "USART2" + depends on ! ARCH_AT91X40 + +config AT91_EARLY_USART3 + bool "USART3" + depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260) + +config AT91_EARLY_USART4 + bool "USART4" + depends on ARCH_AT91SAM9260 + +config AT91_EARLY_USART5 + bool "USART5" + depends on ARCH_AT91SAM9260 + +endchoice + endmenu endif diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c index 111da57f533..60f52904aad 100644 --- a/drivers/serial/atmel_serial.c +++ b/drivers/serial/atmel_serial.c @@ -34,6 +34,7 @@ #include #include #include +#include #include @@ -45,8 +46,6 @@ #include #endif -#include "atmel_serial.h" - #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) #define SUPPORT_SYSRQ #endif diff --git a/drivers/serial/atmel_serial.h b/drivers/serial/atmel_serial.h deleted file mode 100644 index e0141776517..00000000000 --- a/drivers/serial/atmel_serial.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * drivers/serial/atmel_serial.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * USART registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef ATMEL_SERIAL_H -#define ATMEL_SERIAL_H - -#define ATMEL_US_CR 0x00 /* Control Register */ -#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */ -#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */ -#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */ -#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */ -#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */ -#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */ -#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */ -#define ATMEL_US_STTBRK (1 << 9) /* Start Break */ -#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */ -#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */ -#define ATMEL_US_SENDA (1 << 12) /* Send Address */ -#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */ -#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ -#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */ -#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */ -#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */ -#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */ -#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */ - -#define ATMEL_US_MR 0x04 /* Mode Register */ -#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */ -#define ATMEL_US_USMODE_NORMAL 0 -#define ATMEL_US_USMODE_RS485 1 -#define ATMEL_US_USMODE_HWHS 2 -#define ATMEL_US_USMODE_MODEM 3 -#define ATMEL_US_USMODE_ISO7816_T0 4 -#define ATMEL_US_USMODE_ISO7816_T1 6 -#define ATMEL_US_USMODE_IRDA 8 -#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */ -#define ATMEL_US_USCLKS_MCK (0 << 4) -#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) -#define ATMEL_US_USCLKS_SCK (3 << 4) -#define ATMEL_US_CHRL (3 << 6) /* Character Length */ -#define ATMEL_US_CHRL_5 (0 << 6) -#define ATMEL_US_CHRL_6 (1 << 6) -#define ATMEL_US_CHRL_7 (2 << 6) -#define ATMEL_US_CHRL_8 (3 << 6) -#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */ -#define ATMEL_US_PAR (7 << 9) /* Parity Type */ -#define ATMEL_US_PAR_EVEN (0 << 9) -#define ATMEL_US_PAR_ODD (1 << 9) -#define ATMEL_US_PAR_SPACE (2 << 9) -#define ATMEL_US_PAR_MARK (3 << 9) -#define ATMEL_US_PAR_NONE (4 << 9) -#define ATMEL_US_PAR_MULTI_DROP (6 << 9) -#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */ -#define ATMEL_US_NBSTOP_1 (0 << 12) -#define ATMEL_US_NBSTOP_1_5 (1 << 12) -#define ATMEL_US_NBSTOP_2 (2 << 12) -#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */ -#define ATMEL_US_CHMODE_NORMAL (0 << 14) -#define ATMEL_US_CHMODE_ECHO (1 << 14) -#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14) -#define ATMEL_US_CHMODE_REM_LOOP (3 << 14) -#define ATMEL_US_MSBF (1 << 16) /* Bit Order */ -#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */ -#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */ -#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */ -#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */ -#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */ -#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */ -#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */ - -#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */ -#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */ -#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */ -#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */ -#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */ -#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */ -#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */ -#define ATMEL_US_FRAME (1 << 6) /* Framing Error */ -#define ATMEL_US_PARE (1 << 7) /* Parity Error */ -#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */ -#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */ -#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ -#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */ -#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */ -#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ -#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ -#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ -#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */ -#define ATMEL_US_RI (1 << 20) /* RI */ -#define ATMEL_US_DSR (1 << 21) /* DSR */ -#define ATMEL_US_DCD (1 << 22) /* DCD */ -#define ATMEL_US_CTS (1 << 23) /* CTS */ - -#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */ -#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */ -#define ATMEL_US_CSR 0x14 /* Channel Status Register */ -#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ -#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ -#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */ - -#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ -#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */ - -#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */ -#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */ - -#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */ -#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */ - -#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */ -#define ATMEL_US_NER 0x44 /* Number of Errors Register */ -#define ATMEL_US_IF 0x4c /* IrDA Filter Register */ - -#endif diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h index 802891a9cd8..e8fc0b1c33f 100644 --- a/include/asm-arm/arch-at91/at91rm9200.h +++ b/include/asm-arm/arch-at91/at91rm9200.h @@ -93,6 +93,11 @@ #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ +#define AT91_USART0 AT91RM9200_BASE_US0 +#define AT91_USART1 AT91RM9200_BASE_US1 +#define AT91_USART2 AT91RM9200_BASE_US2 +#define AT91_USART3 AT91RM9200_BASE_US3 + #define AT91_MATRIX 0 /* not supported */ /* diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 0427f8698c0..c8934fe34dc 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -99,6 +99,13 @@ #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9260_BASE_US0 +#define AT91_USART1 AT91SAM9260_BASE_US1 +#define AT91_USART2 AT91SAM9260_BASE_US2 +#define AT91_USART3 AT91SAM9260_BASE_US3 +#define AT91_USART4 AT91SAM9260_BASE_US4 +#define AT91_USART5 AT91SAM9260_BASE_US5 + /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index 9eb45957033..c7c4778dac4 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -84,6 +84,10 @@ #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9261_BASE_US0 +#define AT91_USART1 AT91SAM9261_BASE_US1 +#define AT91_USART2 AT91SAM9261_BASE_US2 + /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 115c47ac7eb..018a647311d 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -101,6 +101,10 @@ #define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9263_BASE_US0 +#define AT91_USART1 AT91SAM9263_BASE_US1 +#define AT91_USART2 AT91SAM9263_BASE_US2 + #define AT91_SMC AT91_SMC0 /* diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 8a9708a370c..16d2832f6c0 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -94,6 +94,11 @@ #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) +#define AT91_USART0 AT91SAM9RL_BASE_US0 +#define AT91_USART1 AT91SAM9RL_BASE_US1 +#define AT91_USART2 AT91SAM9RL_BASE_US2 +#define AT91_USART3 AT91SAM9RL_BASE_US3 + /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index 272a7e0dc6c..f5636a8f613 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -22,7 +22,23 @@ #define __ASM_ARCH_UNCOMPRESS_H #include -#include +#include + +#if defined(CONFIG_AT91_EARLY_DBGU) +#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS) +#elif defined(CONFIG_AT91_EARLY_USART0) +#define UART_OFFSET AT91_USART0 +#elif defined(CONFIG_AT91_EARLY_USART1) +#define UART_OFFSET AT91_USART1 +#elif defined(CONFIG_AT91_EARLY_USART2) +#define UART_OFFSET AT91_USART2 +#elif defined(CONFIG_AT91_EARLY_USART3) +#define UART_OFFSET AT91_USART3 +#elif defined(CONFIG_AT91_EARLY_USART4) +#define UART_OFFSET AT91_USART4 +#elif defined(CONFIG_AT91_EARLY_USART5) +#define UART_OFFSET AT91_USART5 +#endif /* * The following code assumes the serial port has already been @@ -33,22 +49,22 @@ */ static void putc(int c) { -#ifdef AT91_DBGU - void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ +#ifdef UART_OFFSET + void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) + while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY)) barrier(); - __raw_writel(c, sys + AT91_DBGU_THR); + __raw_writel(c, sys + ATMEL_US_THR); #endif } static inline void flush(void) { -#ifdef AT91_DBGU - void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ +#ifdef UART_OFFSET + void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ /* wait for transmission to complete */ - while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) + while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) barrier(); #endif } diff --git a/include/linux/atmel_serial.h b/include/linux/atmel_serial.h new file mode 100644 index 00000000000..fd6833764d7 --- /dev/null +++ b/include/linux/atmel_serial.h @@ -0,0 +1,127 @@ +/* + * include/linux/atmel_serial.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * USART registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef ATMEL_SERIAL_H +#define ATMEL_SERIAL_H + +#define ATMEL_US_CR 0x00 /* Control Register */ +#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */ +#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */ +#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */ +#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */ +#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */ +#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */ +#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */ +#define ATMEL_US_STTBRK (1 << 9) /* Start Break */ +#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */ +#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */ +#define ATMEL_US_SENDA (1 << 12) /* Send Address */ +#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */ +#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */ +#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */ +#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */ +#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */ +#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */ +#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */ + +#define ATMEL_US_MR 0x04 /* Mode Register */ +#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */ +#define ATMEL_US_USMODE_NORMAL 0 +#define ATMEL_US_USMODE_RS485 1 +#define ATMEL_US_USMODE_HWHS 2 +#define ATMEL_US_USMODE_MODEM 3 +#define ATMEL_US_USMODE_ISO7816_T0 4 +#define ATMEL_US_USMODE_ISO7816_T1 6 +#define ATMEL_US_USMODE_IRDA 8 +#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */ +#define ATMEL_US_USCLKS_MCK (0 << 4) +#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) +#define ATMEL_US_USCLKS_SCK (3 << 4) +#define ATMEL_US_CHRL (3 << 6) /* Character Length */ +#define ATMEL_US_CHRL_5 (0 << 6) +#define ATMEL_US_CHRL_6 (1 << 6) +#define ATMEL_US_CHRL_7 (2 << 6) +#define ATMEL_US_CHRL_8 (3 << 6) +#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */ +#define ATMEL_US_PAR (7 << 9) /* Parity Type */ +#define ATMEL_US_PAR_EVEN (0 << 9) +#define ATMEL_US_PAR_ODD (1 << 9) +#define ATMEL_US_PAR_SPACE (2 << 9) +#define ATMEL_US_PAR_MARK (3 << 9) +#define ATMEL_US_PAR_NONE (4 << 9) +#define ATMEL_US_PAR_MULTI_DROP (6 << 9) +#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */ +#define ATMEL_US_NBSTOP_1 (0 << 12) +#define ATMEL_US_NBSTOP_1_5 (1 << 12) +#define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */ +#define ATMEL_US_CHMODE_NORMAL (0 << 14) +#define ATMEL_US_CHMODE_ECHO (1 << 14) +#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14) +#define ATMEL_US_CHMODE_REM_LOOP (3 << 14) +#define ATMEL_US_MSBF (1 << 16) /* Bit Order */ +#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */ +#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */ +#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */ +#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */ +#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */ +#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */ +#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */ + +#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */ +#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */ +#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */ +#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */ +#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */ +#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */ +#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */ +#define ATMEL_US_FRAME (1 << 6) /* Framing Error */ +#define ATMEL_US_PARE (1 << 7) /* Parity Error */ +#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */ +#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */ +#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */ +#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */ +#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */ +#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */ +#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */ +#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */ +#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */ +#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */ +#define ATMEL_US_RI (1 << 20) /* RI */ +#define ATMEL_US_DSR (1 << 21) /* DSR */ +#define ATMEL_US_DCD (1 << 22) /* DCD */ +#define ATMEL_US_CTS (1 << 23) /* CTS */ + +#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */ +#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */ +#define ATMEL_US_CSR 0x14 /* Channel Status Register */ +#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ +#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ +#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */ + +#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ +#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */ + +#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */ +#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */ + +#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */ +#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */ + +#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */ +#define ATMEL_US_NER 0x44 /* Number of Errors Register */ +#define ATMEL_US_IF 0x4c /* IrDA Filter Register */ + +#endif -- cgit v1.2.3-70-g09d2 From a78de2f704a0954df011348c6022e0d49e773a44 Mon Sep 17 00:00:00 2001 From: Marc Pignat Date: Wed, 30 Jan 2008 13:41:32 +0100 Subject: [ARM] 4802/1: Fix typo and remove vague comment Fix typo and remove vague comment Signed-off-by: Marc Pignat Acked-by: Andrew Victor Acked-by: Nicolas Ferre Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91_mci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h index c2e11cc374b..1551fc24eb4 100644 --- a/include/asm-arm/arch-at91/at91_mci.h +++ b/include/asm-arm/arch-at91/at91_mci.h @@ -89,7 +89,7 @@ #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ #define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ -#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ +#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */ #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ -- cgit v1.2.3-70-g09d2 From 14271a705ae0fdfcb997ebed0b6e2ec6ffa58561 Mon Sep 17 00:00:00 2001 From: eric miao Date: Tue, 29 Jan 2008 08:57:45 +0800 Subject: [ARM] pxa: change set_kset_name() to direct name assignment for MFP sysclass Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/mfp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c index ec1b2d8f61c..6ce35041c7e 100644 --- a/arch/arm/mach-pxa/mfp.c +++ b/arch/arm/mach-pxa/mfp.c @@ -227,7 +227,7 @@ static int pxa3xx_mfp_resume(struct sys_device *d) } static struct sysdev_class mfp_sysclass = { - set_kset_name("mfp"), + .name = "mfp", .suspend = pxa3xx_mfp_suspend, .resume = pxa3xx_mfp_resume, }; -- cgit v1.2.3-70-g09d2 From cd5604d5618a802e4ed047eb8b1515edc5fc49b5 Mon Sep 17 00:00:00 2001 From: eric miao Date: Tue, 29 Jan 2008 09:00:19 +0800 Subject: [ARM] pxa: fix the warning of undeclared "struct pxaohci_platform_data" The header file was missing in the original file, include it to fix the warning. Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/devices.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 50ff453ad37..bfccb80ac8e 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "devices.h" -- cgit v1.2.3-70-g09d2 From c016550490687c6bdbcdf06c7b4d874b6c7c6e4e Mon Sep 17 00:00:00 2001 From: eric miao Date: Mon, 28 Jan 2008 23:00:02 +0000 Subject: [ARM] pxa: introduce sysdev for IRQ register saving/restoring Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/generic.h | 2 ++ arch/arm/mach-pxa/irq.c | 62 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-pxa/pxa25x.c | 24 +++++++++++++----- arch/arm/mach-pxa/pxa27x.c | 26 ++++++++++++++----- arch/arm/mach-pxa/pxa3xx.c | 24 +++++++++++++++--- 5 files changed, 122 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index b30f240a16c..367b67923e1 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -52,3 +52,5 @@ extern unsigned pxa3xx_get_memclk_frequency_10khz(void); #define pxa3xx_get_clk_frequency_khz(x) (0) #define pxa3xx_get_memclk_frequency_10khz() (0) #endif + +extern struct sysdev_class pxa_irq_sysclass; diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 07acb45b16e..5a1d5eef10a 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -321,3 +322,64 @@ void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) pxa_low_gpio_chip.set_wake = set_wake; pxa_muxed_gpio_chip.set_wake = set_wake; } + +#ifdef CONFIG_PM +static unsigned long saved_icmr[2]; + +static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) +{ + switch (dev->id) { + case 0: + saved_icmr[0] = ICMR; + ICMR = 0; + break; +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) + case 1: + saved_icmr[1] = ICMR2; + ICMR2 = 0; + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static int pxa_irq_resume(struct sys_device *dev) +{ + switch (dev->id) { + case 0: + ICMR = saved_icmr[0]; + ICLR = 0; + ICCR = 1; + break; +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) + case 1: + ICMR2 = saved_icmr[1]; + ICLR2 = 0; + break; +#endif + default: + return -EINVAL; + } + + return 0; +} +#else +#define pxa_irq_suspend NULL +#define pxa_irq_resume NULL +#endif + +struct sysdev_class pxa_irq_sysclass = { + .name = "irq", + .suspend = pxa_irq_suspend, + .resume = pxa_irq_resume, +}; + +static int __init pxa_irq_init(void) +{ + return sysdev_class_register(&pxa_irq_sysclass); +} + +core_initcall(pxa_irq_init); diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index ddd05bf78e0..797635eec6b 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -165,7 +166,6 @@ enum { SLEEP_SAVE_START = 0, SLEEP_SAVE_PSTR, - SLEEP_SAVE_ICMR, SLEEP_SAVE_CKEN, SLEEP_SAVE_SIZE @@ -184,7 +184,6 @@ static void pxa25x_cpu_pm_save(unsigned long *sleep_save) SAVE(GAFR1_L); SAVE(GAFR1_U); SAVE(GAFR2_L); SAVE(GAFR2_U); - SAVE(ICMR); ICMR = 0; SAVE(CKEN); SAVE(PSTR); @@ -210,10 +209,6 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) PSSR = PSSR_RDH | PSSR_PH; RESTORE(CKEN); - - ICLR = 0; - ICCR = 1; - RESTORE(ICMR); RESTORE(PSTR); } @@ -304,9 +299,15 @@ static struct platform_device *pxa25x_devices[] __initdata = { &pxa25x_device_assp, }; +static struct sys_device pxa25x_sysdev[] = { + { + .cls = &pxa_irq_sysclass, + }, +}; + static int __init pxa25x_init(void) { - int ret = 0; + int i, ret = 0; /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ if (cpu_is_pxa25x()) @@ -320,9 +321,18 @@ static int __init pxa25x_init(void) pxa25x_init_pm(); + for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { + ret = sysdev_register(&pxa25x_sysdev[i]); + if (ret) + pr_err("failed to register sysdev[%d]\n", i); + } + ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); + if (ret) + return ret; } + /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ if (cpu_is_pxa25x()) ret = platform_device_register(&pxa_device_hwuart); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 96cf274ec7c..343296a710b 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -196,7 +197,6 @@ enum { SLEEP_SAVE_START = 0, SLEEP_SAVE_PSTR, - SLEEP_SAVE_ICMR, SLEEP_SAVE_CKEN, SLEEP_SAVE_MDREFR, @@ -223,7 +223,6 @@ void pxa27x_cpu_pm_save(unsigned long *sleep_save) SAVE(PWER); SAVE(PCFR); SAVE(PRER); SAVE(PFER); SAVE(PKWR); - SAVE(ICMR); ICMR = 0; SAVE(CKEN); SAVE(PSTR); @@ -256,9 +255,6 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save) RESTORE(CKEN); - ICLR = 0; - ICCR = 1; - RESTORE(ICMR); RESTORE(PSTR); } @@ -409,9 +405,20 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_ssp3, }; +static struct sys_device pxa27x_sysdev[] = { + { + .id = 0, + .cls = &pxa_irq_sysclass, + }, { + .id = 1, + .cls = &pxa_irq_sysclass, + }, +}; + static int __init pxa27x_init(void) { - int ret = 0; + int i, ret = 0; + if (cpu_is_pxa27x()) { clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); @@ -420,8 +427,15 @@ static int __init pxa27x_init(void) pxa27x_init_pm(); + for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { + ret = sysdev_register(&pxa27x_sysdev[i]); + if (ret) + pr_err("failed to register sysdev[%d]\n", i); + } + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } + return ret; } diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 5cbf057a1b3..3a7e8ccd70b 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -452,9 +453,19 @@ static struct platform_device *devices[] __initdata = { &pxa3xx_device_ssp4, }; +static struct sys_device pxa3xx_sysdev[] = { + { + .id = 0, + .cls = &pxa_irq_sysclass, + }, { + .id = 1, + .cls = &pxa_irq_sysclass, + }, +}; + static int __init pxa3xx_init(void) { - int ret = 0; + int i, ret = 0; if (cpu_is_pxa3xx()) { clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); @@ -464,9 +475,16 @@ static int __init pxa3xx_init(void) pxa3xx_init_pm(); - return platform_add_devices(devices, ARRAY_SIZE(devices)); + for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { + ret = sysdev_register(&pxa3xx_sysdev[i]); + if (ret) + pr_err("failed to register sysdev[%d]\n", i); + } + + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } - return 0; + + return ret; } subsys_initcall(pxa3xx_init); -- cgit v1.2.3-70-g09d2 From 16dfdbf038706c12c56f327d14c6b901edc376a3 Mon Sep 17 00:00:00 2001 From: eric miao Date: Mon, 28 Jan 2008 23:00:02 +0000 Subject: [ARM] pxa: introduce sysdev for GPIO register saving/restoring Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/generic.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-pxa/generic.h | 1 + arch/arm/mach-pxa/pxa25x.c | 19 ++------------- arch/arm/mach-pxa/pxa27x.c | 23 ++---------------- arch/arm/mach-pxa/pxa3xx.c | 2 ++ 5 files changed, 64 insertions(+), 38 deletions(-) diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 698aeec5296..76970598f55 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -226,3 +227,59 @@ void __init pxa_map_io(void) iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); get_clk_frequency_khz(1); } + +#ifdef CONFIG_PM + +static unsigned long saved_gplr[4]; +static unsigned long saved_gpdr[4]; +static unsigned long saved_grer[4]; +static unsigned long saved_gfer[4]; + +static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) +{ + int i, gpio; + + for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { + saved_gplr[i] = GPLR(gpio); + saved_gpdr[i] = GPDR(gpio); + saved_grer[i] = GRER(gpio); + saved_gfer[i] = GFER(gpio); + + /* Clear GPIO transition detect bits */ + GEDR(gpio) = GEDR(gpio); + } + return 0; +} + +static int pxa_gpio_resume(struct sys_device *dev) +{ + int i, gpio; + + for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { + /* restore level with set/clear */ + GPSR(gpio) = saved_gplr[i]; + GPCR(gpio) = ~saved_gplr[i]; + + GRER(gpio) = saved_grer[i]; + GFER(gpio) = saved_gfer[i]; + GPDR(gpio) = saved_gpdr[i]; + } + return 0; +} +#else +#define pxa_gpio_suspend NULL +#define pxa_gpio_resume NULL +#endif + +struct sysdev_class pxa_gpio_sysclass = { + .name = "gpio", + .suspend = pxa_gpio_suspend, + .resume = pxa_gpio_resume, +}; + +static int __init pxa_gpio_init(void) +{ + return sysdev_class_register(&pxa_gpio_sysclass); +} + +core_initcall(pxa_gpio_init); diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 367b67923e1..1a16ad3ecee 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -54,3 +54,4 @@ extern unsigned pxa3xx_get_memclk_frequency_10khz(void); #endif extern struct sysdev_class pxa_irq_sysclass; +extern struct sysdev_class pxa_gpio_sysclass; diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 797635eec6b..599e53fcc2c 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -142,11 +142,6 @@ static struct clk pxa25x_clks[] = { #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] -#define RESTORE_GPLEVEL(n) do { \ - GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ - GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ -} while (0) - /* * List of global PXA peripheral registers to preserve. * More ones like CP and general purpose register values are preserved @@ -154,10 +149,6 @@ static struct clk pxa25x_clks[] = { */ enum { SLEEP_SAVE_START = 0, - SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, - SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, - SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, - SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, @@ -174,10 +165,6 @@ enum { SLEEP_SAVE_START = 0, static void pxa25x_cpu_pm_save(unsigned long *sleep_save) { - SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); - SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); - SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); - SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(GAFR0_L); SAVE(GAFR0_U); @@ -197,13 +184,9 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) PSPR = 0; /* restore registers */ - RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2); - RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GAFR0_L); RESTORE(GAFR0_U); RESTORE(GAFR1_L); RESTORE(GAFR1_U); RESTORE(GAFR2_L); RESTORE(GAFR2_U); - RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); - RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); PSSR = PSSR_RDH | PSSR_PH; @@ -302,6 +285,8 @@ static struct platform_device *pxa25x_devices[] __initdata = { static struct sys_device pxa25x_sysdev[] = { { .cls = &pxa_irq_sysclass, + }, { + .cls = &pxa_gpio_sysclass, }, }; diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 343296a710b..46a951c3e5a 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -172,11 +172,6 @@ static struct clk pxa27x_clks[] = { #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] -#define RESTORE_GPLEVEL(n) do { \ - GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \ - GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \ -} while (0) - /* * List of global PXA peripheral registers to preserve. * More ones like CP and general purpose register values are preserved @@ -184,10 +179,6 @@ static struct clk pxa27x_clks[] = { */ enum { SLEEP_SAVE_START = 0, - SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3, - SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3, - SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3, - SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3, SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, @@ -208,10 +199,6 @@ enum { SLEEP_SAVE_START = 0, void pxa27x_cpu_pm_save(unsigned long *sleep_save) { - SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3); - SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3); - SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3); - SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3); SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); SAVE(GAFR0_L); SAVE(GAFR0_U); @@ -225,9 +212,6 @@ void pxa27x_cpu_pm_save(unsigned long *sleep_save) SAVE(CKEN); SAVE(PSTR); - - /* Clear GPIO transition detect bits */ - GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3; } void pxa27x_cpu_pm_restore(unsigned long *sleep_save) @@ -236,15 +220,10 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save) PSPR = 0; /* restore registers */ - RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); - RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3); - RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3); RESTORE(GAFR0_L); RESTORE(GAFR0_U); RESTORE(GAFR1_L); RESTORE(GAFR1_U); RESTORE(GAFR2_L); RESTORE(GAFR2_U); RESTORE(GAFR3_L); RESTORE(GAFR3_U); - RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3); - RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3); RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); RESTORE(MDREFR); @@ -412,6 +391,8 @@ static struct sys_device pxa27x_sysdev[] = { }, { .id = 1, .cls = &pxa_irq_sysclass, + }, { + .cls = &pxa_gpio_sysclass, }, }; diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 3a7e8ccd70b..d0b2afd4368 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -460,6 +460,8 @@ static struct sys_device pxa3xx_sysdev[] = { }, { .id = 1, .cls = &pxa_irq_sysclass, + }, { + .cls = &pxa_gpio_sysclass, }, }; -- cgit v1.2.3-70-g09d2 From c4d1fb627ff307256d792280efcb09e1235affea Mon Sep 17 00:00:00 2001 From: eric miao Date: Mon, 28 Jan 2008 23:00:02 +0000 Subject: [ARM] pxa: add preliminary suspend/resume code for pxa3xx 1. clear RDH bit after resuming back from D3, otherwise, the multi function pins will retain the low power state 2. save/restore essential system registers Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/mfp.c | 9 +++ arch/arm/mach-pxa/pxa3xx.c | 73 ++++++++++++++++++----- arch/arm/mach-pxa/sleep.S | 102 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-pxa/pxa3xx-regs.h | 13 +++++ 4 files changed, 183 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c index 6ce35041c7e..f5809adce29 100644 --- a/arch/arm/mach-pxa/mfp.c +++ b/arch/arm/mach-pxa/mfp.c @@ -22,6 +22,7 @@ #include #include #include +#include /* mfp_spin_lock is used to ensure that MFP register configuration * (most likely a read-modify-write operation) is atomic, and that @@ -223,6 +224,14 @@ static int pxa3xx_mfp_resume(struct sys_device *d) struct pxa3xx_mfp_pin *p = &mfp_table[pin]; __mfp_config_run(p); } + + /* clear RDH bit when MFP settings are restored + * + * NOTE: the last 3 bits DxS are write-1-to-clear so carefully + * preserve them here in case they will be referenced later + */ + ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); + return 0; } diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index d0b2afd4368..e47e67c11af 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -40,6 +40,7 @@ #define RO_CLK 60000000 #define ACCR_D0CS (1 << 26) +#define ACCR_PCCE (1 << 11) /* crystal frequency to static memory controller multiplier (SMCFS) */ static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; @@ -204,7 +205,6 @@ static struct clk pxa3xx_clks[] = { }; #ifdef CONFIG_PM -#define SLEEP_SAVE_SIZE 4 #define ISRAM_START 0x5c000000 #define ISRAM_SIZE SZ_256K @@ -212,25 +212,29 @@ static struct clk pxa3xx_clks[] = { static void __iomem *sram; static unsigned long wakeup_src; -static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) -{ - pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB); +#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x +#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] - if (CKENA & (1 << CKEN_USBH)) { - printk(KERN_ERR "PM: USB host clock not stopped?\n"); - CKENA &= ~(1 << CKEN_USBH); - } -// CKENA |= 1 << (CKEN_ISC & 31); +enum { SLEEP_SAVE_START = 0, + SLEEP_SAVE_CKENA, + SLEEP_SAVE_CKENB, + SLEEP_SAVE_ACCR, - /* - * Low power modes require the HSIO2 clock to be enabled. - */ - CKENB |= 1 << (CKEN_HSIO2 & 31); + SLEEP_SAVE_SIZE, +}; + +static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) +{ + SAVE(CKENA); + SAVE(CKENB); + SAVE(ACCR); } static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) { - CKENB &= ~(1 << (CKEN_HSIO2 & 31)); + RESTORE(ACCR); + RESTORE(CKENA); + RESTORE(CKENB); } /* @@ -266,6 +270,46 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode) printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR); } +/* + * NOTE: currently, the OBM (OEM Boot Module) binary comes along with + * PXA3xx development kits assumes that the resuming process continues + * with the address stored within the first 4 bytes of SDRAM. The PSPR + * register is used privately by BootROM and OBM, and _must_ be set to + * 0x5c014000 for the moment. + */ +static void pxa3xx_cpu_pm_suspend(void) +{ + volatile unsigned long *p = (volatile void *)0xc0000000; + unsigned long saved_data = *p; + + extern void pxa3xx_cpu_suspend(void); + extern void pxa3xx_cpu_resume(void); + + /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ + CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); + CKENB |= 1 << (CKEN_HSIO2 & 0x1f); + + /* clear and setup wakeup source */ + AD3SR = ~0; + AD3ER = wakeup_src; + ASCR = ASCR; + ARSR = ARSR; + + PCFR |= (1u << 13); /* L1_DIS */ + PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ + + PSPR = 0x5c014000; + + /* overwrite with the resume address */ + *p = virt_to_phys(pxa3xx_cpu_resume); + + pxa3xx_cpu_suspend(); + + *p = saved_data; + + AD3ER = 0; +} + static void pxa3xx_cpu_pm_enter(suspend_state_t state) { /* @@ -280,6 +324,7 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state) break; case PM_SUSPEND_MEM: + pxa3xx_cpu_pm_suspend(); break; } } diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 14bb4a93ea5..784716eb7fc 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -50,6 +50,108 @@ pxa_cpu_save_sp: str r0, [r1] ldr pc, [sp], #4 +#ifdef CONFIG_PXA3xx +/* + * pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4) + * + * NOTE: unfortunately, pxa_cpu_save_cp can not be reused here since + * the auxiliary control register address is different between pxa3xx + * and pxa{25x,27x} + */ + +ENTRY(pxa3xx_cpu_suspend) + +#ifndef CONFIG_IWMMXT + mra r2, r3, acc0 +#endif + stmfd sp!, {r2 - r12, lr} @ save registers on stack + + mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode + mrc p15, 0, r4, c15, c1, 0 @ CP access reg + mrc p15, 0, r5, c13, c0, 0 @ PID + mrc p15, 0, r6, c3, c0, 0 @ domain ID + mrc p15, 0, r7, c2, c0, 0 @ translation table base addr + mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg + mrc p15, 0, r9, c1, c0, 0 @ control reg + + bic r3, r3, #2 @ clear frequency change bit + + @ store them plus current virtual stack ptr on stack + mov r10, sp + stmfd sp!, {r3 - r10} + + @ store physical address of stack pointer + mov r0, sp + bl sleep_phys_sp + ldr r1, =sleep_save_sp + str r0, [r1] + + @ clean data cache + bl xsc3_flush_kern_cache_all + + mov r0, #0x06 @ S2D3C4 mode + mcr p14, 0, r0, c7, c0, 0 @ enter sleep + +20: b 20b @ waiting for sleep + + .data + .align 5 +/* + * pxa3xx_cpu_resume + */ + +ENTRY(pxa3xx_cpu_resume) + + mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off + msr cpsr_c, r0 + + ldr r0, sleep_save_sp @ stack phys addr + ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr + + mov r1, #0 + mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB + mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer + mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer + mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs + + mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. + mcr p15, 0, r4, c15, c1, 0 @ CP access reg + mcr p15, 0, r5, c13, c0, 0 @ PID + mcr p15, 0, r6, c3, c0, 0 @ domain ID + mcr p15, 0, r7, c2, c0, 0 @ translation table base addr + mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg + + @ temporarily map resume_turn_on_mmu into the page table, + @ otherwise prefetch abort occurs after MMU is turned on + mov r1, r7 + bic r1, r1, #0x00ff + bic r1, r1, #0x3f00 + ldr r2, =0x542e + + adr r3, resume_turn_on_mmu + mov r3, r3, lsr #20 + orr r4, r2, r3, lsl #20 + ldr r5, [r1, r3, lsl #2] + str r4, [r1, r3, lsl #2] + + @ Mapping page table address in the page table + mov r6, r1, lsr #20 + orr r7, r2, r6, lsl #20 + ldr r8, [r1, r6, lsl #2] + str r7, [r1, r6, lsl #2] + + ldr r2, =pxa3xx_resume_after_mmu @ absolute virtual address + b resume_turn_on_mmu @ cache align execution + + .text +pxa3xx_resume_after_mmu: + /* restore the temporary mapping */ + str r5, [r1, r3, lsl #2] + str r8, [r1, r6, lsl #2] + b resume_after_mmu + +#endif /* CONFIG_PXA3xx */ + #ifdef CONFIG_PXA27x /* * pxa27x_cpu_suspend() diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h index 66d54119757..8e1b3ead827 100644 --- a/include/asm-arm/arch-pxa/pxa3xx-regs.h +++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h @@ -12,6 +12,19 @@ #ifndef __ASM_ARCH_PXA3XX_REGS_H #define __ASM_ARCH_PXA3XX_REGS_H +/* + * Service Power Management Unit (MPMU) + */ +#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ +#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ +#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ +#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ +#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ +#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ +#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ +#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ +#define PCMD(x) __REG(0x40F50110 + ((x) << 2)) /* * Slave Power Managment Unit -- cgit v1.2.3-70-g09d2 From b1d907f9ccb3ffe1d7f5f04d2e9163de22ab01e6 Mon Sep 17 00:00:00 2001 From: eric miao Date: Mon, 28 Jan 2008 23:00:02 +0000 Subject: [ARM] pxa: introduce sysdev for pxa3xx static memory controller Introduce a sysdev for pxa3xx static memory controller, mainly for register saving/restoring in PM Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/Makefile | 2 +- arch/arm/mach-pxa/smemc.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-pxa/smemc.c diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index b5c916c0747..8604938bd94 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -6,7 +6,7 @@ obj-y += clock.o devices.o generic.o irq.o dma.o time.o obj-$(CONFIG_PXA25x) += pxa25x.o obj-$(CONFIG_PXA27x) += pxa27x.o -obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o +obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o smemc.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c new file mode 100644 index 00000000000..ad346addc02 --- /dev/null +++ b/arch/arm/mach-pxa/smemc.c @@ -0,0 +1,88 @@ +/* + * Static Memory Controller + */ + +#include +#include +#include +#include +#include + +#define SMEMC_PHYS_BASE (0x4A000000) +#define SMEMC_PHYS_SIZE (0x90) + +#define MSC0 (0x08) /* Static Memory Controller Register 0 */ +#define MSC1 (0x0C) /* Static Memory Controller Register 1 */ +#define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */ +#define MEMCLKCFG (0x68) /* Clock Configuration */ +#define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */ +#define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */ +#define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */ +#define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */ + +#ifdef CONFIG_PM +static void __iomem *smemc_mmio_base; + +static unsigned long msc[2]; +static unsigned long sxcnfg, memclkcfg; +static unsigned long csadrcfg[4]; + +static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) +{ + msc[0] = __raw_readl(smemc_mmio_base + MSC0); + msc[1] = __raw_readl(smemc_mmio_base + MSC1); + sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG); + memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG); + csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0); + csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1); + csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2); + csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3); + + return 0; +} + +static int pxa3xx_smemc_resume(struct sys_device *dev) +{ + __raw_writel(msc[0], smemc_mmio_base + MSC0); + __raw_writel(msc[1], smemc_mmio_base + MSC1); + __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG); + __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG); + __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0); + __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1); + __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2); + __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3); + + return 0; +} + +static struct sysdev_class smemc_sysclass = { + .name = "smemc", + .suspend = pxa3xx_smemc_suspend, + .resume = pxa3xx_smemc_resume, +}; + +static struct sys_device smemc_sysdev = { + .id = 0, + .cls = &smemc_sysclass, +}; + +static int __init smemc_init(void) +{ + int ret = 0; + + if (cpu_is_pxa3xx()) { + smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE); + if (smemc_mmio_base == NULL) + return -ENODEV; + + ret = sysdev_class_register(&smemc_sysclass); + if (ret) + return ret; + + ret = sysdev_register(&smemc_sysdev); + } + + return ret; +} +subsys_initcall(smemc_init); +#endif -- cgit v1.2.3-70-g09d2 From bb548dd43202b9109f551ca3da396d163ca7ddf3 Mon Sep 17 00:00:00 2001 From: eric miao Date: Wed, 30 Jan 2008 09:39:48 +0100 Subject: [ARM] 4801/1: pxa: fix building issues of missing pxa2xx-regs.h Some machines are missing "pxa2xx-regs.h" due to the following patch: [ARM] pxa: move memory controller registers into pxa2xx-regs.h This patch fixes the issue by including the pxa2xx-regs.h where necessary. Signed-off-by: eric miao Signed-off-by: Russell King --- arch/arm/mach-pxa/cm-x270.c | 1 + arch/arm/mach-pxa/spitz.c | 1 + arch/arm/mach-pxa/tosa.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index 28cfd71c032..6012177a29a 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 5078edeadf9..9e7773fca01 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -36,6 +36,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 1a9c844ac7e..9b26fa5edad 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3-70-g09d2 From 6a0bd09dcd43ebca6ab73abcc2489bff824f7542 Mon Sep 17 00:00:00 2001 From: eric miao Date: Thu, 31 Jan 2008 02:41:16 +0100 Subject: [ARM] 4803/1: pxa: fix building issue of poodle.c caused by patch 4737/1 The is caused by the patch below: [ARM] 4737/1: Refactor corgi_lcd to improve readability + bugfix It renamed the confusing get_hsync_len() to get_hsync_invperiod(), which unfortunately leaves poodle.c un-modified. Signed-off-by: eric miao Acked-by: Richard Purdie Signed-off-by: Russell King --- arch/arm/mach-pxa/poodle.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index dd54496083c..209eabf0ed3 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -164,7 +164,7 @@ static struct resource poodlets_resources[] = { }, }; -static unsigned long poodle_get_hsync_len(void) +static unsigned long poodle_get_hsync_invperiod(void) { return 0; } @@ -174,9 +174,9 @@ static void poodle_null_hsync(void) } static struct corgits_machinfo poodle_ts_machinfo = { - .get_hsync_len = poodle_get_hsync_len, - .put_hsync = poodle_null_hsync, - .wait_hsync = poodle_null_hsync, + .get_hsync_invperiod = poodle_get_hsync_invperiod, + .put_hsync = poodle_null_hsync, + .wait_hsync = poodle_null_hsync, }; static struct platform_device poodle_ts_device = { -- cgit v1.2.3-70-g09d2 From c9a28fa7b9ac19b676deefa0a171ce7df8755c08 Mon Sep 17 00:00:00 2001 From: Juergen Beisert Date: Tue, 29 Jan 2008 23:43:49 +0100 Subject: [ARM] 4798/1: pcm027: fix missing header file This patch adds a PXA2xx specific header file to control chip setup. Without, the PCM027 BSP can't be built. Signed-off-by: Robert Schwebel Signed-off-by: Juergen Beisert Signed-off-by: Russell King --- arch/arm/mach-pxa/pcm027.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 540c3bba5f9..c14696b9979 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include "generic.h" -- cgit v1.2.3-70-g09d2 From 4cd9d6f774c7e0578bbc4409d4490d8f2097d40a Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Wed, 2 Jan 2008 00:56:46 +0100 Subject: [ARM] 4736/1: Export atags to userspace and allow kexec to use customised atags Currently, the atags used by kexec are fixed to the ones originally used to boot the kernel. This is less than ideal as changing the commandline, initrd and other options would be a useful feature. This patch exports the atags used for the current kernel to userspace through an "atags" file in procfs. The presence of the file is controlled by its own Kconfig option and cleans up several ifdef blocks into a separate file. The tags for the new kernel are assumed to be at a fixed location before the kernel image itself. The location of the tags used to boot the original kernel is unimportant and no longer saved. Based on a patch from Uli Luckas Signed-off-by: Richard Purdie Acked-by: Uli Luckas Signed-off-by: Russell King --- arch/arm/Kconfig | 7 ++++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/atags.c | 86 +++++++++++++++++++++++++++++++++++++++ arch/arm/kernel/atags.h | 5 +++ arch/arm/kernel/machine_kexec.c | 2 + arch/arm/kernel/relocate_kernel.S | 30 ++------------ arch/arm/kernel/setup.c | 32 +-------------- include/asm-arm/kexec.h | 3 ++ 8 files changed, 110 insertions(+), 56 deletions(-) create mode 100644 arch/arm/kernel/atags.c create mode 100644 arch/arm/kernel/atags.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4b1a8e3d292..4bd8952eef9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -894,6 +894,13 @@ config KEXEC initially work for you. It may help to enable device hotplugging support. +config ATAGS_PROC + bool "Export atags in procfs" + default n + help + Should the atags used to boot the kernel be exported in an "atags" + file in procfs. Useful with kexec. + endmenu if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index faa76192115..00d44c6fbfe 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PCI) += bios32.o isa.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o +obj-$(CONFIG_ATAGS_PROC) += atags.o obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags.c new file mode 100644 index 00000000000..e2e934c3808 --- /dev/null +++ b/arch/arm/kernel/atags.c @@ -0,0 +1,86 @@ +#include +#include +#include +#include +#include +#include + +struct buffer { + size_t size; + char *data; +}; +static struct buffer tags_buffer; + +static int +read_buffer(char* page, char** start, off_t off, int count, + int* eof, void* data) +{ + struct buffer *buffer = (struct buffer *)data; + + if (off >= buffer->size) { + *eof = 1; + return 0; + } + + count = min((int) (buffer->size - off), count); + + memcpy(page, &buffer->data[off], count); + + return count; +} + + +static int +create_proc_entries(void) +{ + struct proc_dir_entry* tags_entry; + + tags_entry = create_proc_read_entry("atags", 0400, &proc_root, read_buffer, &tags_buffer); + if (!tags_entry) + return -ENOMEM; + + return 0; +} + + +static char __initdata atags_copy_buf[KEXEC_BOOT_PARAMS_SIZE]; +static char __initdata *atags_copy; + +void __init save_atags(const struct tag *tags) +{ + atags_copy = atags_copy_buf; + memcpy(atags_copy, tags, KEXEC_BOOT_PARAMS_SIZE); +} + + +static int __init init_atags_procfs(void) +{ + struct tag *tag; + int error; + + if (!atags_copy) { + printk(KERN_WARNING "Exporting ATAGs: No saved tags found\n"); + return -EIO; + } + + for (tag = (struct tag *) atags_copy; tag->hdr.size; tag = tag_next(tag)) + ; + + tags_buffer.size = ((char *) tag - atags_copy) + sizeof(tag->hdr); + tags_buffer.data = kmalloc(tags_buffer.size, GFP_KERNEL); + if (tags_buffer.data == NULL) + return -ENOMEM; + memcpy(tags_buffer.data, atags_copy, tags_buffer.size); + + error = create_proc_entries(); + if (error) { + printk(KERN_ERR "Exporting ATAGs: not enough memory\n"); + kfree(tags_buffer.data); + tags_buffer.size = 0; + tags_buffer.data = NULL; + } + + return error; +} + +arch_initcall(init_atags_procfs); diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h new file mode 100644 index 00000000000..e5f028d214a --- /dev/null +++ b/arch/arm/kernel/atags.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_ATAGS_PROC +extern void save_atags(struct tag *tags); +#else +static inline void save_atags(struct tag *tags) { } +#endif diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index 863c66454f2..db8f54a3451 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -21,6 +21,7 @@ extern void setup_mm_for_reboot(char mode); extern unsigned long kexec_start_address; extern unsigned long kexec_indirection_page; extern unsigned long kexec_mach_type; +extern unsigned long kexec_boot_atags; /* * Provide a dummy crash_notes definition while crash dump arrives to arm. @@ -62,6 +63,7 @@ void machine_kexec(struct kimage *image) kexec_start_address = image->start; kexec_indirection_page = page_list; kexec_mach_type = machine_arch_type; + kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET; /* copy our kernel relocation code to the control code page */ memcpy(reboot_code_buffer, diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S index 062c111c572..61930eb0902 100644 --- a/arch/arm/kernel/relocate_kernel.S +++ b/arch/arm/kernel/relocate_kernel.S @@ -7,23 +7,6 @@ .globl relocate_new_kernel relocate_new_kernel: - /* Move boot params back to where the kernel expects them */ - - ldr r0,kexec_boot_params_address - teq r0,#0 - beq 8f - - ldr r1,kexec_boot_params_copy - mov r6,#KEXEC_BOOT_PARAMS_SIZE/4 -7: - ldr r5,[r1],#4 - str r5,[r0],#4 - subs r6,r6,#1 - bne 7b - -8: - /* Boot params moved, now go on with the kernel */ - ldr r0,kexec_indirection_page ldr r1,kexec_start_address @@ -67,7 +50,7 @@ relocate_new_kernel: mov lr,r1 mov r0,#0 ldr r1,kexec_mach_type - ldr r2,kexec_boot_params_address + ldr r2,kexec_boot_atags mov pc,lr .globl kexec_start_address @@ -82,14 +65,9 @@ kexec_indirection_page: kexec_mach_type: .long 0x0 - /* phy addr where new kernel will expect to find boot params */ - .globl kexec_boot_params_address -kexec_boot_params_address: - .long 0x0 - - /* phy addr where old kernel put a copy of orig boot params */ - .globl kexec_boot_params_copy -kexec_boot_params_copy: + /* phy addr of the atags for the new kernel */ + .globl kexec_boot_atags +kexec_boot_atags: .long 0x0 relocate_new_kernel_end: diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index bf56eb337df..ae3712d39ab 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include @@ -39,6 +38,7 @@ #include #include "compat.h" +#include "atags.h" #ifndef MEM_SIZE #define MEM_SIZE (16*1024*1024) @@ -784,23 +784,6 @@ static int __init customize_machine(void) } arch_initcall(customize_machine); -#ifdef CONFIG_KEXEC - -/* Physical addr of where the boot params should be for this machine */ -extern unsigned long kexec_boot_params_address; - -/* Physical addr of the buffer into which the boot params are copied */ -extern unsigned long kexec_boot_params_copy; - -/* Pointer to the boot params buffer, for manipulation and display */ -unsigned long kexec_boot_params; -EXPORT_SYMBOL(kexec_boot_params); - -/* The buffer itself - make sure it is sized correctly */ -static unsigned long kexec_boot_params_buf[(KEXEC_BOOT_PARAMS_SIZE + 3) / 4]; - -#endif - void __init setup_arch(char **cmdline_p) { struct tag *tags = (struct tag *)&init_tags; @@ -819,18 +802,6 @@ void __init setup_arch(char **cmdline_p) else if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); -#ifdef CONFIG_KEXEC - kexec_boot_params_copy = virt_to_phys(kexec_boot_params_buf); - kexec_boot_params = (unsigned long)kexec_boot_params_buf; - if (__atags_pointer) { - kexec_boot_params_address = __atags_pointer; - memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE); - } else if (mdesc->boot_params) { - kexec_boot_params_address = mdesc->boot_params; - memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE); - } -#endif - /* * If we have the old style parameters, convert them to * a tag list. @@ -846,6 +817,7 @@ void __init setup_arch(char **cmdline_p) if (tags->hdr.tag == ATAG_CORE) { if (meminfo.nr_banks != 0) squash_mem_tags(tags); + save_atags(tags); parse_tags(tags); } diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h index 46dcc4d0b9b..1ee17b6951d 100644 --- a/include/asm-arm/kexec.h +++ b/include/asm-arm/kexec.h @@ -16,6 +16,9 @@ #define KEXEC_BOOT_PARAMS_SIZE 1536 +#define KEXEC_ARM_ATAGS_OFFSET 0x1000 +#define KEXEC_ARM_ZIMAGE_OFFSET 0x8000 + #ifndef __ASSEMBLY__ struct kimage; -- cgit v1.2.3-70-g09d2 From 85802afeb010502471f64dccf9839f60995c8579 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:24:54 +0100 Subject: [ARM] 4811/1: RealView: clocksource support for the RealView platforms The patch updates the RealView platform code to use the generic clocksource infrastructure for basic time keeping. Based on the Versatile implementation by Kevin Hilman. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + arch/arm/mach-realview/core.c | 73 ++++++++++++++++++------------------------- 2 files changed, 32 insertions(+), 42 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4b1a8e3d292..a2b7e4a52f7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -168,6 +168,7 @@ config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA select ICST307 + select GENERIC_TIME help This enables support for ARM Ltd RealView boards. diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 61d70218f1e..f805840f6f4 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -484,47 +485,6 @@ void realview_leds_event(led_event_t ledevt) #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) #endif -/* - * Returns number of ms since last clock interrupt. Note that interrupts - * will have been disabled by do_gettimeoffset() - */ -static unsigned long realview_gettimeoffset(void) -{ - unsigned long ticks1, ticks2, status; - - /* - * Get the current number of ticks. Note that there is a race - * condition between us reading the timer and checking for - * an interrupt. We get around this by ensuring that the - * counter has not reloaded between our two reads. - */ - ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; - do { - ticks1 = ticks2; - status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET) - + ((IRQ_TIMERINT0_1 >> 5) << 2)); - ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; - } while (ticks2 > ticks1); - - /* - * Number of ticks since last interrupt. - */ - ticks1 = TIMER_RELOAD - ticks2; - - /* - * Interrupt pending? If so, we've reloaded once already. - * - * FIXME: Need to check this is effectively timer 0 that expires - */ - if (status & IRQMASK_TIMERINT0_1) - ticks1 += TIMER_RELOAD; - - /* - * Convert the ticks to usecs - */ - return TICKS2USECS(ticks1); -} - /* * IRQ handler for the timer */ @@ -549,6 +509,34 @@ static struct irqaction realview_timer_irq = { .handler = realview_timer_interrupt, }; +static cycle_t realview_get_cycles(void) +{ + return ~readl(TIMER3_VA_BASE + TIMER_VALUE); +} + +static struct clocksource clocksource_realview = { + .name = "timer3", + .rating = 200, + .read = realview_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init realview_clocksource_init(void) +{ + /* setup timer 0 as free-running clocksource */ + writel(0, TIMER3_VA_BASE + TIMER_CTRL); + writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); + writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); + writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, + TIMER3_VA_BASE + TIMER_CTRL); + + clocksource_realview.mult = + clocksource_khz2mult(1000, clocksource_realview.shift); + clocksource_register(&clocksource_realview); +} + /* * Set up timer interrupt, and return the current time in seconds. */ @@ -585,9 +573,10 @@ static void __init realview_timer_init(void) * Make irqs happen for the system timer */ setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq); + + realview_clocksource_init(); } struct sys_timer realview_timer = { .init = realview_timer_init, - .offset = realview_gettimeoffset, }; -- cgit v1.2.3-70-g09d2 From ae30ceac3c6bbacdb227816abe6f0c7ea867ac7c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:26:55 +0100 Subject: [ARM] 4812/1: RealView: clockevents support for the RealView platforms The patch updates the RealView code to the clockevents infrastructure. The SMP support is implemented in subsequent patches. Based on the Versatile implementation by Kevin Hilman. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + arch/arm/mach-realview/core.c | 78 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 67 insertions(+), 12 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a2b7e4a52f7..b82828e768a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -169,6 +169,7 @@ config ARCH_REALVIEW select ARM_AMBA select ICST307 select GENERIC_TIME + select GENERIC_CLOCKEVENTS help This enables support for ARM Ltd RealView boards. diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index f805840f6f4..6c68deed84d 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -485,20 +486,77 @@ void realview_leds_event(led_event_t ledevt) #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) #endif +static void timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + unsigned long ctrl; + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); + + ctrl = TIMER_CTRL_PERIODIC; + ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE; + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl = TIMER_CTRL_ONESHOT; + ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + } + + writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); +} + +static int timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); + + writel(evt, TIMER0_VA_BASE + TIMER_LOAD); + writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); + + return 0; +} + +static struct clock_event_device timer0_clockevent = { + .name = "timer0", + .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = timer_set_mode, + .set_next_event = timer_set_next_event, + .rating = 300, + .irq = IRQ_TIMERINT0_1, + .cpumask = CPU_MASK_ALL, +}; + +static void __init realview_clockevents_init(void) +{ + timer0_clockevent.mult = + div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); + timer0_clockevent.max_delta_ns = + clockevent_delta2ns(0xffffffff, &timer0_clockevent); + timer0_clockevent.min_delta_ns = + clockevent_delta2ns(0xf, &timer0_clockevent); + + clockevents_register_device(&timer0_clockevent); +} + /* * IRQ handler for the timer */ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) { - // ...clear the interrupt - writel(1, TIMER0_VA_BASE + TIMER_INTCLR); + struct clock_event_device *evt = &timer0_clockevent; - timer_tick(); + /* clear the interrupt */ + writel(1, TIMER0_VA_BASE + TIMER_INTCLR); -#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS) - smp_send_timer(); - update_process_times(user_mode(get_irq_regs())); -#endif + evt->event_handler(evt); return IRQ_HANDLED; } @@ -564,17 +622,13 @@ static void __init realview_timer_init(void) writel(0, TIMER2_VA_BASE + TIMER_CTRL); writel(0, TIMER3_VA_BASE + TIMER_CTRL); - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE); - writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC | - TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL); - /* * Make irqs happen for the system timer */ setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq); realview_clocksource_init(); + realview_clockevents_init(); } struct sys_timer realview_timer = { -- cgit v1.2.3-70-g09d2 From 3e459990961db7f3f2dcf21e2b38a7216dfd10dd Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:28:56 +0100 Subject: [ARM] 4813/1: Add SMP helper functions for clockevents support This patch adds the smp_call_function_single and smp_timer_broadcast functions and modifies ipi_timer to call the platform-specific function local_timer_interrupt. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/kernel/smp.c | 29 +++++++++++++++++++++++++++-- include/asm-arm/smp.h | 10 ++++++++++ 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index eafbb2b05eb..aef6f9ab900 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -454,6 +454,27 @@ int smp_call_function(void (*func)(void *info), void *info, int retry, } EXPORT_SYMBOL_GPL(smp_call_function); +int smp_call_function_single(int cpu, void (*func)(void *info), void *info, + int retry, int wait) +{ + /* prevent preemption and reschedule on another processor */ + int current_cpu = get_cpu(); + int ret = 0; + + if (cpu == current_cpu) { + local_irq_disable(); + func(info); + local_irq_enable(); + } else + ret = smp_call_function_on_cpu(func, info, retry, wait, + cpumask_of_cpu(cpu)); + + put_cpu(); + + return ret; +} +EXPORT_SYMBOL_GPL(smp_call_function_single); + void show_ipi_list(struct seq_file *p) { unsigned int cpu; @@ -481,8 +502,7 @@ void show_local_irqs(struct seq_file *p) static void ipi_timer(void) { irq_enter(); - profile_tick(CPU_PROFILING); - update_process_times(user_mode(get_irq_regs())); + local_timer_interrupt(); irq_exit(); } @@ -621,6 +641,11 @@ void smp_send_timer(void) send_ipi_message(mask, IPI_TIMER); } +void smp_timer_broadcast(cpumask_t mask) +{ + send_ipi_message(mask, IPI_TIMER); +} + void smp_send_stop(void) { cpumask_t mask = cpu_online_map; diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index f67acce387e..1f7c51a1886 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -60,6 +60,11 @@ extern void smp_cross_call(cpumask_t callmap); */ extern void smp_send_timer(void); +/* + * Broadcast a clock event to other CPUs. + */ +extern void smp_timer_broadcast(cpumask_t mask); + /* * Boot a secondary CPU, and assign it the specified idle task. * This also gives us the initial stack to use for this CPU. @@ -96,6 +101,11 @@ extern void platform_cpu_die(unsigned int cpu); extern int platform_cpu_kill(unsigned int cpu); extern void platform_cpu_enable(unsigned int cpu); +/* + * Local timer interrupt handling function (can be IPI'ed). + */ +extern void local_timer_interrupt(void); + #ifdef CONFIG_LOCAL_TIMERS /* * Setup a local timer interrupt for a CPU. -- cgit v1.2.3-70-g09d2 From a8655e83fc44ec2b92cbea9f3ff3cc0da05a991c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:30:57 +0100 Subject: [ARM] 4814/1: RealView: Add broadcasting clockevents support for ARM11MPCore This patch adds dummy local timers for each CPU so that the board clock device is used to broadcast events to the other CPUs. The patch also adds the declaration for the dummy_timer_setup function (the equivalent of local_timer_setup when CONFIG_LOCAL_TIMERS is not set). Due to the way clockevents work, the dummy timer on the first CPU has to be registered before the board timer. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 5 +++++ arch/arm/kernel/smp.c | 10 +++++----- arch/arm/mach-realview/Makefile | 3 +-- arch/arm/mach-realview/core.c | 10 +++++++++- arch/arm/mach-realview/localtimer.c | 39 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-realview/platsmp.c | 6 +++++- include/asm-arm/smp.h | 13 +++++-------- 7 files changed, 69 insertions(+), 17 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b82828e768a..a0aeecc33c7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -33,6 +33,11 @@ config GENERIC_CLOCKEVENTS bool default n +config GENERIC_CLOCKEVENTS_BROADCAST + bool + depends on GENERIC_CLOCKEVENTS + default y if SMP && !LOCAL_TIMERS + config MMU bool default y diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index aef6f9ab900..e9dfbab46cb 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -290,6 +290,11 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_irq_enable(); local_fiq_enable(); + /* + * Setup local timer for this CPU. + */ + local_timer_setup(cpu); + calibrate_delay(); smp_store_cpu_info(cpu); @@ -299,11 +304,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void) */ cpu_set(cpu, cpu_online_map); - /* - * Setup local timer for this CPU. - */ - local_timer_setup(cpu); - /* * OK, it's off to the idle thread for us */ diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index 36e76ba937f..ca1e390c3c2 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -4,6 +4,5 @@ obj-y := core.o clock.o obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 6c68deed84d..8cabfec31da 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -596,12 +596,20 @@ static void __init realview_clocksource_init(void) } /* - * Set up timer interrupt, and return the current time in seconds. + * Set up the clock source and clock events devices */ static void __init realview_timer_init(void) { u32 val; +#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST + /* + * The dummy clock device has to be registered before the main device + * so that the latter will broadcast the clock events + */ + local_timer_setup(smp_processor_id()); +#endif + /* * set clock frequency: * REALVIEW_REFCLK is 32KHz diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index c7bdf04ab09..529eb6979e6 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include @@ -25,6 +27,20 @@ #define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \ ((cpu) * REALVIEW_TWD_SIZE)) +static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); + +/* + * Used on SMP for either the local timer or IPI_TIMER + */ +void local_timer_interrupt(void) +{ + struct clock_event_device *clk = &__get_cpu_var(local_clockevent); + + clk->event_handler(clk); +} + +#ifdef CONFIG_LOCAL_TIMERS + static unsigned long mpcore_timer_rate; /* @@ -127,3 +143,26 @@ void __cpuexit local_timer_stop(unsigned int cpu) { __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL); } + +#else /* CONFIG_LOCAL_TIMERS */ + +static void dummy_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ +} + +void __cpuinit local_timer_setup(unsigned int cpu) +{ + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + + clk->name = "dummy_timer"; + clk->features = CLOCK_EVT_FEAT_DUMMY; + clk->rating = 200; + clk->set_mode = dummy_timer_set_mode; + clk->broadcast = smp_timer_broadcast; + clk->cpumask = cpumask_of_cpu(cpu); + + clockevents_register_device(clk); +} + +#endif /* !CONFIG_LOCAL_TIMERS */ diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index fce3596f995..bb5eaa48520 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -187,10 +187,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus) if (max_cpus > ncores) max_cpus = ncores; +#ifdef CONFIG_LOCAL_TIMERS /* - * Enable the local timer for primary CPU + * Enable the local timer for primary CPU. If the device is + * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in + * realview_timer_init */ local_timer_setup(cpu); +#endif /* * Initialise the present map, which describes the set of CPUs diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index 1f7c51a1886..af99636db40 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -107,10 +107,6 @@ extern void platform_cpu_enable(unsigned int cpu); extern void local_timer_interrupt(void); #ifdef CONFIG_LOCAL_TIMERS -/* - * Setup a local timer interrupt for a CPU. - */ -extern void local_timer_setup(unsigned int cpu); /* * Stop a local timer interrupt. @@ -124,16 +120,17 @@ extern int local_timer_ack(void); #else -static inline void local_timer_setup(unsigned int cpu) -{ -} - static inline void local_timer_stop(unsigned int cpu) { } #endif +/* + * Setup a local timer interrupt for a CPU. + */ +extern void local_timer_setup(unsigned int cpu); + /* * show local interrupt info */ -- cgit v1.2.3-70-g09d2 From 93c2904d5081468128e66792a85439df314de773 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:32:57 +0100 Subject: [ARM] 4815/1: RealView: Add clockevents suport for the local timers This patch registers the local timers on ARM11MPCore as clock event devices. The clock device can be set up as periodic or oneshot. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/localtimer.c | 94 +++++++++++++++++++++++++------------ include/asm-arm/hardware/arm_twd.h | 7 ++- 2 files changed, 71 insertions(+), 30 deletions(-) diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index 529eb6979e6..4f87b4d09c7 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -16,8 +16,8 @@ #include #include #include +#include -#include #include #include #include @@ -43,6 +43,43 @@ void local_timer_interrupt(void) static unsigned long mpcore_timer_rate; +static void local_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + void __iomem *base = TWD_BASE(smp_processor_id()); + unsigned long ctrl; + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* timer load already set up */ + ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE + | TWD_TIMER_CONTROL_PERIODIC; + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + } + + __raw_writel(ctrl, base + TWD_TIMER_CONTROL); +} + +static int local_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + void __iomem *base = TWD_BASE(smp_processor_id()); + unsigned long ctrl = __raw_readl(base + TWD_TIMER_CONTROL); + + __raw_writel(evt, base + TWD_TIMER_COUNTER); + __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, base + TWD_TIMER_CONTROL); + + return 0; +} + /* * local_timer_ack: checks for a local timer interrupt. * @@ -61,12 +98,11 @@ int local_timer_ack(void) return 0; } -void __cpuinit local_timer_setup(unsigned int cpu) +static void __cpuinit twd_calibrate_rate(unsigned int cpu) { void __iomem *base = TWD_BASE(cpu); - unsigned int load, offset; + unsigned long load, count; u64 waitjiffies; - unsigned int count; /* * If this is the first time round, we need to work out how fast @@ -104,36 +140,36 @@ void __cpuinit local_timer_setup(unsigned int cpu) load = mpcore_timer_rate / HZ; __raw_writel(load, base + TWD_TIMER_LOAD); - __raw_writel(0x7, base + TWD_TIMER_CONTROL); - - /* - * Now maneuver our local tick into the right part of the jiffy. - * Start by working out where within the tick our local timer - * interrupt should go. - */ - offset = ((mpcore_timer_rate / HZ) / (NR_CPUS + 1)) * (cpu + 1); +} - /* - * gettimeoffset() will return a number of us since the last tick. - * Convert this number of us to a local timer tick count. - * Be careful of integer overflow whilst keeping maximum precision. - * - * with HZ=100 and 1MHz (fpga) ~ 1GHz processor: - * load = 1 ~ 10,000 - * mpcore_timer_rate/10000 = 100 ~ 100,000 - * - * so the multiply value will be less than 10^9 always. - */ - load = (system_timer->offset() * (mpcore_timer_rate / 10000)) / 100; +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit local_timer_setup(unsigned int cpu) +{ + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + unsigned long flags; - /* Add on our offset to get the load value */ - load = (load + offset) % (mpcore_timer_rate / HZ); + twd_calibrate_rate(cpu); - __raw_writel(load, base + TWD_TIMER_COUNTER); + clk->name = "local_timer"; + clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clk->rating = 350; + clk->set_mode = local_timer_set_mode; + clk->set_next_event = local_timer_set_next_event; + clk->irq = IRQ_LOCALTIMER; + clk->cpumask = cpumask_of_cpu(cpu); + clk->shift = 20; + clk->mult = div_sc(mpcore_timer_rate, NSEC_PER_SEC, clk->shift); + clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); + clk->min_delta_ns = clockevent_delta2ns(0xf, clk); /* Make sure our local interrupt controller has this enabled */ - __raw_writel(1 << IRQ_LOCALTIMER, - __io_address(REALVIEW_GIC_DIST_BASE) + GIC_DIST_ENABLE_SET); + local_irq_save(flags); + get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER); + local_irq_restore(flags); + + clockevents_register_device(clk); } /* diff --git a/include/asm-arm/hardware/arm_twd.h b/include/asm-arm/hardware/arm_twd.h index 131d5b40e07..e521b70713c 100644 --- a/include/asm-arm/hardware/arm_twd.h +++ b/include/asm-arm/hardware/arm_twd.h @@ -1,7 +1,7 @@ #ifndef __ASM_HARDWARE_TWD_H #define __ASM_HARDWARE_TWD_H -#define TWD_TIMER_LOAD 0x00 +#define TWD_TIMER_LOAD 0x00 #define TWD_TIMER_COUNTER 0x04 #define TWD_TIMER_CONTROL 0x08 #define TWD_TIMER_INTSTAT 0x0C @@ -13,4 +13,9 @@ #define TWD_WDOG_RESETSTAT 0x30 #define TWD_WDOG_DISABLE 0x34 +#define TWD_TIMER_CONTROL_ENABLE (1 << 0) +#define TWD_TIMER_CONTROL_ONESHOT (0 << 1) +#define TWD_TIMER_CONTROL_PERIODIC (1 << 1) +#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) + #endif -- cgit v1.2.3-70-g09d2 From 356cb470b84bda67738ba320a75629acae70e5fa Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:34:58 +0100 Subject: [ARM] 4816/1: RealView: Move the platform-specific definitions into board-eb.h This patch moves the platform specific definitions from platform.h into the board-eb.h file. It drops the INT_* definitions as they are no longer used in irqs.h (moved to board-eb.h). It renames REALVIEW_* macros to REALVIEW_EB_* or REALVIEW_EB11MP_* to distinguish between standard EB and EB + the ARM11MPCore tile. The platform.h file contains common definitions to the RealView platforms and it is only directly included in board-*.h files. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/localtimer.c | 4 +- arch/arm/mach-realview/platsmp.c | 4 +- arch/arm/mach-realview/realview_eb.c | 1 + include/asm-arm/arch-realview/board-eb.h | 152 +++++++++++++++++++++++++ include/asm-arm/arch-realview/entry-macro.S | 5 + include/asm-arm/arch-realview/hardware.h | 1 - include/asm-arm/arch-realview/irqs.h | 105 ++--------------- include/asm-arm/arch-realview/platform.h | 170 ++-------------------------- include/asm-arm/arch-realview/scu.h | 4 +- include/asm-arm/arch-realview/uncompress.h | 2 + 10 files changed, 186 insertions(+), 262 deletions(-) create mode 100644 include/asm-arm/arch-realview/board-eb.h diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index 4f87b4d09c7..60500f0b878 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -24,8 +24,8 @@ #include #include -#define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \ - ((cpu) * REALVIEW_TWD_SIZE)) +#define TWD_BASE(cpu) (__io_address(REALVIEW_EB11MP_TWD_BASE) + \ + ((cpu) * REALVIEW_EB11MP_TWD_SIZE)) static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index bb5eaa48520..0186c80c904 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -31,7 +31,7 @@ static unsigned int __init get_core_count(void) { unsigned int ncores; - ncores = __raw_readl(__io_address(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG); + ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); return (ncores & 0x03) + 1; } @@ -52,7 +52,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); + gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); /* * let the primary processor know we're out of the diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index ecec2f85c4c..9c992568ee4 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -37,6 +37,7 @@ #include #include +#include #include #include "core.h" diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h new file mode 100644 index 00000000000..943efc5de4e --- /dev/null +++ b/include/asm-arm/arch-realview/board-eb.h @@ -0,0 +1,152 @@ +/* + * include/asm-arm/arch-realview/board-eb.h + * + * Copyright (C) 2007 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_BOARD_EB_H +#define __ASM_ARCH_BOARD_EB_H + +#include + +/* + * RealView EB + ARM11MPCore peripheral addresses + */ +#ifdef CONFIG_REALVIEW_MPCORE_REVB +#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ +#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_EB11MP_TWD_BASE 0x10100700 +#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ +#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ +#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ +#else +#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ +#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_EB11MP_TWD_BASE 0x1F000700 +#define REALVIEW_EB11MP_TWD_SIZE 0x00000100 +#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ +#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ +#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ +#endif + +#define IRQ_EB_GIC_START 32 + +/* + * RealView EB interrupt sources + */ +#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */ +#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */ +#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */ +#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */ +#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */ +#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */ +#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */ +#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */ +#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */ + /* 9 reserved */ +#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */ +#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */ +#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ +#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ +#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ +#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */ +#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */ +#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */ +#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */ +#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */ +#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */ +#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */ +#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */ +#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */ +#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */ +#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */ +#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */ +#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */ +#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */ +#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */ +#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */ +#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */ + +/* + * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile) + */ +#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0) +#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1) +#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2) +#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3) +#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4) +#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5) +#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6) +#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7) +#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8) +#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9) +#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */ +#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */ +#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */ +#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */ +#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14) +#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15) + +#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17) +#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18) +#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19) +#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20) +#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21) +#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22) +#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23) +#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24) +#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25) +#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26) +#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27) +#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28) + +#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29) +#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) +#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) + +#define IRQ_EB11MP_UART2 -1 +#define IRQ_EB11MP_UART3 -1 +#define IRQ_EB11MP_CLCD -1 +#define IRQ_EB11MP_DMA -1 +#define IRQ_EB11MP_WDOG -1 +#define IRQ_EB11MP_GPIO0 -1 +#define IRQ_EB11MP_GPIO1 -1 +#define IRQ_EB11MP_GPIO2 -1 +#define IRQ_EB11MP_SCI -1 +#define IRQ_EB11MP_SSP -1 + +#define NR_GIC_EB11MP 2 + +/* + * Only define NR_IRQS if less than NR_IRQS_EB + */ +#define NR_IRQS_EB (IRQ_EB_GIC_START + 96) + +#if defined(CONFIG_MACH_REALVIEW_EB) \ + && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB)) +#undef NR_IRQS +#define NR_IRQS NR_IRQS_EB +#endif + +#if defined(CONFIG_REALVIEW_MPCORE) \ + && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) +#undef MAX_GIC_NR +#define MAX_GIC_NR NR_GIC_EB11MP +#endif + +#endif /* __ASM_ARCH_BOARD_EB_H */ diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 3b4e2076603..629944deed5 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -9,12 +9,17 @@ */ #include #include +#include .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp +#ifdef CONFIG_REALVIEW_MPCORE + ldr \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE) +#else ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) +#endif .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h index aa78fe087ab..bad8d7ce9bf 100644 --- a/include/asm-arm/arch-realview/hardware.h +++ b/include/asm-arm/arch-realview/hardware.h @@ -23,7 +23,6 @@ #define __ASM_ARCH_HARDWARE_H #include -#include /* macro to get at IO space when running virtually */ #define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h index 5a5db56f86b..ad0c911002f 100644 --- a/include/asm-arm/arch-realview/irqs.h +++ b/include/asm-arm/arch-realview/irqs.h @@ -19,103 +19,18 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 +#include -/* - * IRQ interrupts definitions are the same the INT definitions - * held within platform.h - */ -#define IRQ_GIC_START 32 -#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT) -#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT) -#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx) -#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx) -#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1) -#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3) -#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0) -#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1) -#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2) -#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3) -#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT) -#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT) -#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0) -#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1) -#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2) -#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3) -#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT) -#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT) -#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT) -#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT) -#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT) -#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT) -#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B) -#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B) -#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0) -#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1) -#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3) -#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD) -#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH) -#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD) -#define IRQ_DoC (IRQ_GIC_START + INT_DoC) -#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A) -#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A) -#define IRQ_AACI (IRQ_GIC_START + INT_AACI) -#define IRQ_ETH (IRQ_GIC_START + INT_ETH) -#define IRQ_USB (IRQ_GIC_START + INT_USB) -#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0) -#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1) -#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2) -#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3) -#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0) -#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1) -#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2) -#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3) -#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4) -#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5) -#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6) -#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7) +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 -#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) -#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2) +#define IRQ_GIC_START 32 -#define IRQMASK_WDOGINT INTMASK_WDOGINT -#define IRQMASK_SOFTINT INTMASK_SOFTINT -#define IRQMASK_COMMRx INTMASK_COMMRx -#define IRQMASK_COMMTx INTMASK_COMMTx -#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 -#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 -#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 -#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 -#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 -#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 -#define IRQMASK_RTCINT INTMASK_RTCINT -#define IRQMASK_SSPINT INTMASK_SSPINT -#define IRQMASK_UARTINT0 INTMASK_UARTINT0 -#define IRQMASK_UARTINT1 INTMASK_UARTINT1 -#define IRQMASK_UARTINT2 INTMASK_UARTINT2 -#define IRQMASK_SCIINT INTMASK_SCIINT -#define IRQMASK_CLCDINT INTMASK_CLCDINT -#define IRQMASK_DMAINT INTMASK_DMAINT -#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT -#define IRQMASK_MBXINT INTMASK_MBXINT -#define IRQMASK_GNDINT INTMASK_GNDINT -#define IRQMASK_MMCI0B INTMASK_MMCI0B -#define IRQMASK_MMCI1B INTMASK_MMCI1B -#define IRQMASK_KMI0 INTMASK_KMI0 -#define IRQMASK_KMI1 INTMASK_KMI1 -#define IRQMASK_SCI3 INTMASK_SCI3 -#define IRQMASK_UART3 INTMASK_UART3 -#define IRQMASK_CLCD INTMASK_CLCD -#define IRQMASK_TOUCH INTMASK_TOUCH -#define IRQMASK_KEYPAD INTMASK_KEYPAD -#define IRQMASK_DoC INTMASK_DoC -#define IRQMASK_MMCI0A INTMASK_MMCI0A -#define IRQMASK_MMCI1A INTMASK_MMCI1A -#define IRQMASK_AACI INTMASK_AACI -#define IRQMASK_ETH INTMASK_ETH -#define IRQMASK_USB INTMASK_USB +#ifndef NR_IRQS +#error "NR_IRQS not defined by the board-specific files" +#endif -#define NR_IRQS (IRQ_GIC_START + 96) +#endif diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h index 6e0eab95a3a..4fd351b5e4a 100644 --- a/include/asm-arm/arch-realview/platform.h +++ b/include/asm-arm/arch-realview/platform.h @@ -18,8 +18,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __address_h -#define __address_h 1 +#ifndef __ASM_ARCH_PLATFORM_H +#define __ASM_ARCH_PLATFORM_H /* * Memory definitions @@ -81,11 +81,12 @@ #define REALVIEW_SYS_24MHz_OFFSET 0x5C #define REALVIEW_SYS_MISC_OFFSET 0x60 #define REALVIEW_SYS_IOSEL_OFFSET 0x70 -#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 -#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 -#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 -#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C -#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 +#define REALVIEW_SYS_PROCID_OFFSET 0x84 +#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 +#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 +#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 +#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC +#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 #define REALVIEW_SYS_BASE 0x10000000 #define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) @@ -114,6 +115,7 @@ #define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) #define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) #define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) +#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) #define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) #define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) #define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) @@ -203,30 +205,8 @@ /* Reserved 0x1001A000 - 0x1001FFFF */ #define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ -#ifndef CONFIG_REALVIEW_MPCORE #define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ #define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ -#else -#ifdef CONFIG_REALVIEW_MPCORE_REVB -#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */ -#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_TWD_BASE 0x10100700 -#define REALVIEW_TWD_SIZE 0x00000100 -#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ -#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */ -#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ -#else -#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */ -#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ -#define REALVIEW_TWD_BASE 0x1F000700 -#define REALVIEW_TWD_SIZE 0x00000100 -#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ -#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */ -#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ -#endif -#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ -#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ -#endif #define REALVIEW_SMC_BASE 0x10080000 /* SMC */ /* Reserved 0x10090000 - 0x100EFFFF */ @@ -283,134 +263,6 @@ #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ -/* ------------------------------------------------------------------------ - * Interrupts - bit assignment (primary) - * ------------------------------------------------------------------------ - */ -#ifndef CONFIG_REALVIEW_MPCORE -#define INT_WDOGINT 0 /* Watchdog timer */ -#define INT_SOFTINT 1 /* Software interrupt */ -#define INT_COMMRx 2 /* Debug Comm Rx interrupt */ -#define INT_COMMTx 3 /* Debug Comm Tx interrupt */ -#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ -#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ -#define INT_GPIOINT0 6 /* GPIO 0 */ -#define INT_GPIOINT1 7 /* GPIO 1 */ -#define INT_GPIOINT2 8 /* GPIO 2 */ -/* 9 reserved */ -#define INT_RTCINT 10 /* Real Time Clock */ -#define INT_SSPINT 11 /* Synchronous Serial Port */ -#define INT_UARTINT0 12 /* UART 0 on development chip */ -#define INT_UARTINT1 13 /* UART 1 on development chip */ -#define INT_UARTINT2 14 /* UART 2 on development chip */ -#define INT_UARTINT3 15 /* UART 3 on development chip */ -#define INT_SCIINT 16 /* Smart Card Interface */ -#define INT_MMCI0A 17 /* Multimedia Card 0A */ -#define INT_MMCI0B 18 /* Multimedia Card 0B */ -#define INT_AACI 19 /* Audio Codec */ -#define INT_KMI0 20 /* Keyboard/Mouse port 0 */ -#define INT_KMI1 21 /* Keyboard/Mouse port 1 */ -#define INT_CHARLCD 22 /* Character LCD */ -#define INT_CLCDINT 23 /* CLCD controller */ -#define INT_DMAINT 24 /* DMA controller */ -#define INT_PWRFAILINT 25 /* Power failure */ -#define INT_PISMO 26 -#define INT_DoC 27 /* Disk on Chip memory controller */ -#define INT_ETH 28 /* Ethernet controller */ -#define INT_USB 29 /* USB controller */ -#define INT_TSPENINT 30 /* Touchscreen pen */ -#define INT_TSKPADINT 31 /* Touchscreen keypad */ - -#else - -#define MAX_GIC_NR 2 - -#define INT_AACI 0 -#define INT_TIMERINT0_1 1 -#define INT_TIMERINT2_3 2 -#define INT_USB 3 -#define INT_UARTINT0 4 -#define INT_UARTINT1 5 -#define INT_RTCINT 6 -#define INT_KMI0 7 -#define INT_KMI1 8 -#define INT_ETH 9 -#define INT_EB_IRQ1 10 /* main GIC */ -#define INT_EB_IRQ2 11 /* tile GIC */ -#define INT_EB_FIQ1 12 /* main GIC */ -#define INT_EB_FIQ2 13 /* tile GIC */ -#define INT_MMCI0A 14 -#define INT_MMCI0B 15 - -#define INT_PMU_CPU0 17 -#define INT_PMU_CPU1 18 -#define INT_PMU_CPU2 19 -#define INT_PMU_CPU3 20 -#define INT_PMU_SCU0 21 -#define INT_PMU_SCU1 22 -#define INT_PMU_SCU2 23 -#define INT_PMU_SCU3 24 -#define INT_PMU_SCU4 25 -#define INT_PMU_SCU5 26 -#define INT_PMU_SCU6 27 -#define INT_PMU_SCU7 28 - -#define INT_L220_EVENT 29 -#define INT_L220_SLAVE 30 -#define INT_L220_DECODE 31 - -#define INT_UARTINT2 -1 -#define INT_UARTINT3 -1 -#define INT_CLCDINT -1 -#define INT_DMAINT -1 -#define INT_WDOGINT -1 -#define INT_GPIOINT0 -1 -#define INT_GPIOINT1 -1 -#define INT_GPIOINT2 -1 -#define INT_SCIINT -1 -#define INT_SSPINT -1 -#endif - -/* - * Interrupt bit positions - * - */ -#define INTMASK_WDOGINT (1 << INT_WDOGINT) -#define INTMASK_SOFTINT (1 << INT_SOFTINT) -#define INTMASK_COMMRx (1 << INT_COMMRx) -#define INTMASK_COMMTx (1 << INT_COMMTx) -#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) -#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) -#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) -#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) -#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) -#define INTMASK_RTCINT (1 << INT_RTCINT) -#define INTMASK_SSPINT (1 << INT_SSPINT) -#define INTMASK_UARTINT0 (1 << INT_UARTINT0) -#define INTMASK_UARTINT1 (1 << INT_UARTINT1) -#define INTMASK_UARTINT2 (1 << INT_UARTINT2) -#define INTMASK_UARTINT3 (1 << INT_UARTINT3) -#define INTMASK_SCIINT (1 << INT_SCIINT) -#define INTMASK_MMCI0A (1 << INT_MMCI0A) -#define INTMASK_MMCI0B (1 << INT_MMCI0B) -#define INTMASK_AACI (1 << INT_AACI) -#define INTMASK_KMI0 (1 << INT_KMI0) -#define INTMASK_KMI1 (1 << INT_KMI1) -#define INTMASK_CHARLCD (1 << INT_CHARLCD) -#define INTMASK_CLCDINT (1 << INT_CLCDINT) -#define INTMASK_DMAINT (1 << INT_DMAINT) -#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) -#define INTMASK_PISMO (1 << INT_PISMO) -#define INTMASK_DoC (1 << INT_DoC) -#define INTMASK_ETH (1 << INT_ETH) -#define INTMASK_USB (1 << INT_USB) -#define INTMASK_TSPENINT (1 << INT_TSPENINT) -#define INTMASK_TSKPADINT (1 << INT_TSKPADINT) - -#define MAXIRQNUM 31 -#define MAXFIQNUM 31 -#define MAXSWINUM 31 - /* * Application Flash * @@ -463,6 +315,4 @@ #define REALVIEW_CSR_BASE 0x10000000 #define REALVIEW_CSR_SIZE 0x10000000 -#endif - -/* END */ +#endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h index cc293640178..08b3db883c3 100644 --- a/include/asm-arm/arch-realview/scu.h +++ b/include/asm-arm/arch-realview/scu.h @@ -1,8 +1,8 @@ #ifndef __ASMARM_ARCH_SCU_H #define __ASMARM_ARCH_SCU_H -#include +#include -#define SCU_BASE REALVIEW_MPCORE_SCU_BASE +#define SCU_BASE REALVIEW_EB11MP_SCU_BASE #endif diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h index f05631d7674..3d5c2db07a2 100644 --- a/include/asm-arm/arch-realview/uncompress.h +++ b/include/asm-arm/arch-realview/uncompress.h @@ -19,6 +19,8 @@ */ #include +#include + #define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) #define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) #define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) -- cgit v1.2.3-70-g09d2 From 0fc2a1616f37175ff0cf54b99e9b76f7717a3f10 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:36:59 +0100 Subject: [ARM] 4817/1: RealView: Move the AMBA resource definitions to realview_eb.c This patch moves the IRQ and DMA definitions from core.h into realview_eb.c since they are platform-specific. It adds a realview_eb11mp_fixup function to adjust the IRQ numbers if the ARM11MPCore tile is fitted. The realview_smc91x_device is also moved from core.c into realview_eb.c. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/core.c | 20 ------ arch/arm/mach-realview/core.h | 63 +----------------- arch/arm/mach-realview/realview_eb.c | 123 ++++++++++++++++++++++++++++++++++- 3 files changed, 123 insertions(+), 83 deletions(-) diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 8cabfec31da..046d31ce27b 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -123,26 +123,6 @@ struct platform_device realview_flash_device = { .resource = &realview_flash_resource, }; -static struct resource realview_smc91x_resources[] = { - [0] = { - .start = REALVIEW_ETH_BASE, - .end = REALVIEW_ETH_BASE + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_ETH, - .end = IRQ_ETH, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device realview_smc91x_device = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(realview_smc91x_resources), - .resource = realview_smc91x_resources, -}; - static struct resource realview_i2c_resource = { .start = REALVIEW_I2C_BASE, .end = REALVIEW_I2C_BASE + SZ_4K - 1, diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 2b53420f9c1..9206db7b80b 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -38,7 +38,7 @@ static struct amba_device name##_device = { \ }, \ .res = { \ .start = REALVIEW_##base##_BASE, \ - .end = (REALVIEW_##base##_BASE) + SZ_4K - 1,\ + .end = (REALVIEW_##base##_BASE) + SZ_4K - 1, \ .flags = IORESOURCE_MEM, \ }, \ .dma_mask = ~0, \ @@ -46,68 +46,7 @@ static struct amba_device name##_device = { \ /* .dma = base##_DMA,*/ \ } -/* - * These devices are connected via the core APB bridge - */ -#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ } -#define GPIO2_DMA { 0, 0 } -#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ } -#define GPIO3_DMA { 0, 0 } - -#define AACI_IRQ { IRQ_AACI, NO_IRQ } -#define AACI_DMA { 0x80, 0x81 } -#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_MMCI0B } -#define MMCI0_DMA { 0x84, 0 } -#define KMI0_IRQ { IRQ_KMI0, NO_IRQ } -#define KMI0_DMA { 0, 0 } -#define KMI1_IRQ { IRQ_KMI1, NO_IRQ } -#define KMI1_DMA { 0, 0 } - -/* - * These devices are connected directly to the multi-layer AHB switch - */ -#define SMC_IRQ { NO_IRQ, NO_IRQ } -#define SMC_DMA { 0, 0 } -#define MPMC_IRQ { NO_IRQ, NO_IRQ } -#define MPMC_DMA { 0, 0 } -#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } -#define CLCD_DMA { 0, 0 } -#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } -#define DMAC_DMA { 0, 0 } - -/* - * These devices are connected via the core APB bridge - */ -#define SCTL_IRQ { NO_IRQ, NO_IRQ } -#define SCTL_DMA { 0, 0 } -#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } -#define WATCHDOG_DMA { 0, 0 } -#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } -#define GPIO0_DMA { 0, 0 } -#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } -#define GPIO1_DMA { 0, 0 } -#define RTC_IRQ { IRQ_RTCINT, NO_IRQ } -#define RTC_DMA { 0, 0 } - -/* - * These devices are connected via the DMA APB bridge - */ -#define SCI_IRQ { IRQ_SCIINT, NO_IRQ } -#define SCI_DMA { 7, 6 } -#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } -#define UART0_DMA { 15, 14 } -#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } -#define UART1_DMA { 13, 12 } -#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } -#define UART2_DMA { 11, 10 } -#define UART3_IRQ { IRQ_UART3, NO_IRQ } -#define UART3_DMA { 0x86, 0x87 } -#define SSP_IRQ { IRQ_SSPINT, NO_IRQ } -#define SSP_DMA { 9, 8 } - - extern struct platform_device realview_flash_device; -extern struct platform_device realview_smc91x_device; extern struct platform_device realview_i2c_device; extern struct mmc_platform_data realview_mmc0_plat_data; extern struct mmc_platform_data realview_mmc1_plat_data; diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 9c992568ee4..afcf27ceac5 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -109,6 +109,69 @@ static void __init realview_eb_map_io(void) iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); } +/* + * RealView EB AMBA devices + */ + +/* + * These devices are connected via the core APB bridge + */ +#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ } +#define GPIO2_DMA { 0, 0 } +#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ } +#define GPIO3_DMA { 0, 0 } + +#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ } +#define AACI_DMA { 0x80, 0x81 } +#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B } +#define MMCI0_DMA { 0x84, 0 } +#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ } +#define KMI0_DMA { 0, 0 } +#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ } +#define KMI1_DMA { 0, 0 } + +/* + * These devices are connected directly to the multi-layer AHB switch + */ +#define SMC_IRQ { NO_IRQ, NO_IRQ } +#define SMC_DMA { 0, 0 } +#define MPMC_IRQ { NO_IRQ, NO_IRQ } +#define MPMC_DMA { 0, 0 } +#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ } +#define CLCD_DMA { 0, 0 } +#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ } +#define DMAC_DMA { 0, 0 } + +/* + * These devices are connected via the core APB bridge + */ +#define SCTL_IRQ { NO_IRQ, NO_IRQ } +#define SCTL_DMA { 0, 0 } +#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ } +#define WATCHDOG_DMA { 0, 0 } +#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ } +#define GPIO0_DMA { 0, 0 } +#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ } +#define GPIO1_DMA { 0, 0 } +#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ } +#define RTC_DMA { 0, 0 } + +/* + * These devices are connected via the DMA APB bridge + */ +#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ } +#define SCI_DMA { 7, 6 } +#define UART0_IRQ { IRQ_EB_UART0, NO_IRQ } +#define UART0_DMA { 15, 14 } +#define UART1_IRQ { IRQ_EB_UART1, NO_IRQ } +#define UART1_DMA { 13, 12 } +#define UART2_IRQ { IRQ_EB_UART2, NO_IRQ } +#define UART2_DMA { 11, 10 } +#define UART3_IRQ { IRQ_EB_UART3, NO_IRQ } +#define UART3_DMA { 0x86, 0x87 } +#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ } +#define SSP_DMA { 9, 8 } + /* FPGA Primecells */ AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); @@ -154,6 +217,30 @@ static struct amba_device *amba_devs[] __initdata = { &kmi1_device, }; +/* + * RealView EB platform devices + */ + +static struct resource realview_eb_smc91x_resources[] = { + [0] = { + .start = REALVIEW_ETH_BASE, + .end = REALVIEW_ETH_BASE + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EB_ETH, + .end = IRQ_EB_ETH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device realview_eb_smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources), + .resource = realview_eb_smc91x_resources, +}; + static void __init gic_init_irq(void) { #ifdef CONFIG_REALVIEW_MPCORE @@ -173,11 +260,45 @@ static void __init gic_init_irq(void) #endif } +#ifdef CONFIG_REALVIEW_MPCORE +/* + * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile + */ +static void realview_eb11mp_fixup(void) +{ + /* AMBA devices */ + dmac_device.irq[0] = IRQ_EB11MP_DMA; + uart0_device.irq[0] = IRQ_EB11MP_UART0; + uart1_device.irq[0] = IRQ_EB11MP_UART1; + uart2_device.irq[0] = IRQ_EB11MP_UART2; + uart3_device.irq[0] = IRQ_EB11MP_UART3; + clcd_device.irq[0] = IRQ_EB11MP_CLCD; + wdog_device.irq[0] = IRQ_EB11MP_WDOG; + gpio0_device.irq[0] = IRQ_EB11MP_GPIO0; + gpio1_device.irq[0] = IRQ_EB11MP_GPIO1; + gpio2_device.irq[0] = IRQ_EB11MP_GPIO2; + rtc_device.irq[0] = IRQ_EB11MP_RTC; + sci0_device.irq[0] = IRQ_EB11MP_SCI; + ssp0_device.irq[0] = IRQ_EB11MP_SSP; + aaci_device.irq[0] = IRQ_EB11MP_AACI; + mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A; + mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B; + kmi0_device.irq[0] = IRQ_EB11MP_KMI0; + kmi1_device.irq[0] = IRQ_EB11MP_KMI1; + + /* platform devices */ + realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH; + realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; +} +#endif + static void __init realview_eb_init(void) { int i; #ifdef CONFIG_REALVIEW_MPCORE + realview_eb11mp_fixup(); + /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled * Bits: .... ...0 0111 1001 0000 .... .... .... */ l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff); @@ -185,7 +306,7 @@ static void __init realview_eb_init(void) clk_register(&realview_clcd_clk); platform_device_register(&realview_flash_device); - platform_device_register(&realview_smc91x_device); + platform_device_register(&realview_eb_smc91x_device); platform_device_register(&realview_i2c_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { -- cgit v1.2.3-70-g09d2 From 7dd19e755dbe481ae42590dbd921dfd47e94779c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:39:00 +0100 Subject: [ARM] 4818/1: RealView: Add core-tile detection This patch adds the core-tile detection and only enables devices if the corresponding tile is present. It currently detects the ARM11MPCore via the core_tile_eb11mp() macro. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/platsmp.c | 12 +++-- arch/arm/mach-realview/realview_eb.c | 93 ++++++++++++++++++-------------- include/asm-arm/arch-realview/board-eb.h | 19 +++++++ 3 files changed, 80 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 0186c80c904..de2b7159557 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -18,6 +18,7 @@ #include #include #include +#include extern void realview_secondary_startup(void); @@ -31,9 +32,13 @@ static unsigned int __init get_core_count(void) { unsigned int ncores; - ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); + if (machine_is_realview_eb() && core_tile_eb11mp()) { + ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG); + ncores = (ncores & 0x03) + 1; + } else + ncores = 1; - return (ncores & 0x03) + 1; + return ncores; } static DEFINE_SPINLOCK(boot_lock); @@ -193,7 +198,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in * realview_timer_init */ - local_timer_setup(cpu); + if (machine_is_realview_eb() && core_tile_eb11mp()) + local_timer_setup(cpu); #endif /* diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index afcf27ceac5..e42ac56e4db 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -59,26 +59,7 @@ static struct map_desc realview_eb_io_desc[] __initdata = { .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), .length = SZ_4K, .type = MT_DEVICE, - }, -#ifdef CONFIG_REALVIEW_MPCORE - { - .virtual = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE), - .pfn = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE), - .length = SZ_4K, - .type = MT_DEVICE, }, { - .virtual = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE), - .pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = IO_ADDRESS(REALVIEW_MPCORE_L220_BASE), - .pfn = __phys_to_pfn(REALVIEW_MPCORE_L220_BASE), - .length = SZ_8K, - .type = MT_DEVICE, - }, -#endif - { .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), .length = SZ_4K, @@ -104,9 +85,30 @@ static struct map_desc realview_eb_io_desc[] __initdata = { #endif }; +static struct map_desc realview_eb11mp_io_desc[] __initdata = { + { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE), + .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE), + .length = SZ_8K, + .type = MT_DEVICE, + } +}; + static void __init realview_eb_map_io(void) { iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); + if (core_tile_eb11mp()) + iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); } /* @@ -243,24 +245,33 @@ static struct platform_device realview_eb_smc91x_device = { static void __init gic_init_irq(void) { -#ifdef CONFIG_REALVIEW_MPCORE - unsigned int pldctrl; - writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); - pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); - pldctrl |= 0x00800000; /* New irq mode */ - writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); - writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); -#endif - gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); - gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); -#if defined(CONFIG_REALVIEW_MPCORE) && !defined(CONFIG_REALVIEW_MPCORE_REVB) - gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64); - gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE)); - gic_cascade_irq(1, IRQ_EB_IRQ1); + if (core_tile_eb11mp()) { + unsigned int pldctrl; + + /* new irq mode */ + writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); + pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); + pldctrl |= 0x00800000; + writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1); + writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); + + /* core tile GIC, primary */ + gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); + gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); + +#ifndef CONFIG_REALVIEW_MPCORE_REVB + /* board GIC, secondary */ + gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64); + gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE)); + gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); #endif + } else { + /* board GIC, primary */ + gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); + gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); + } } -#ifdef CONFIG_REALVIEW_MPCORE /* * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile */ @@ -290,19 +301,19 @@ static void realview_eb11mp_fixup(void) realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH; realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; } -#endif static void __init realview_eb_init(void) { int i; -#ifdef CONFIG_REALVIEW_MPCORE - realview_eb11mp_fixup(); + if (core_tile_eb11mp()) { + realview_eb11mp_fixup(); + + /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled + * Bits: .... ...0 0111 1001 0000 .... .... .... */ + l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); + } - /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled - * Bits: .... ...0 0111 1001 0000 .... .... .... */ - l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff); -#endif clk_register(&realview_clcd_clk); platform_device_register(&realview_flash_device); diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h index 943efc5de4e..9e76b236b52 100644 --- a/include/asm-arm/arch-realview/board-eb.h +++ b/include/asm-arm/arch-realview/board-eb.h @@ -149,4 +149,23 @@ #define MAX_GIC_NR NR_GIC_EB11MP #endif +/* + * Core tile identification (REALVIEW_SYS_PROCID) + */ +#define REALVIEW_EB_PROC_MASK 0xFF000000 +#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000 +#define REALVIEW_EB_PROC_ARM9 0x02000000 +#define REALVIEW_EB_PROC_ARM11 0x04000000 +#define REALVIEW_EB_PROC_ARM11MP 0x06000000 + +#define check_eb_proc(proc_type) \ + ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \ + == proc_type) + +#ifdef CONFIG_REALVIEW_MPCORE +#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP) +#else +#define core_tile_eb11mp() 0 +#endif + #endif /* __ASM_ARCH_BOARD_EB_H */ -- cgit v1.2.3-70-g09d2 From c4057f5260650f165054bc56e16acc4aa0510d4f Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:41:01 +0100 Subject: [ARM] 4819/1: RealView: Fix entry-macro.S to work with multiple platforms This patch modifies the get_irqnr_preamble macro to work with multiple platforms at run-time by reading the address of the GIC controller from the gic_cpu_base_addr variable. This variable is defined in core.c and intialised in realview_eb.c (gic_init_irq). Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/core.c | 3 +++ arch/arm/mach-realview/core.h | 1 + arch/arm/mach-realview/realview_eb.c | 6 ++++-- include/asm-arm/arch-realview/entry-macro.S | 8 ++------ 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 046d31ce27b..29514ac94f3 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -50,6 +50,9 @@ #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) +/* used by entry-macro.S */ +void __iomem *gic_cpu_base_addr; + /* * This is the RealView sched_clock implementation. This has * a resolution of 41.7ns, and a maximum value of about 179s. diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 9206db7b80b..1c091372be6 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -52,6 +52,7 @@ extern struct mmc_platform_data realview_mmc0_plat_data; extern struct mmc_platform_data realview_mmc1_plat_data; extern struct clk realview_clcd_clk; extern struct clcd_board clcd_plat_data; +extern void __iomem *gic_cpu_base_addr; extern void realview_leds_event(led_event_t ledevt); diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index e42ac56e4db..f36af133502 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -256,8 +256,9 @@ static void __init gic_init_irq(void) writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); /* core tile GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE); gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); - gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); + gic_cpu_init(0, gic_cpu_base_addr); #ifndef CONFIG_REALVIEW_MPCORE_REVB /* board GIC, secondary */ @@ -267,8 +268,9 @@ static void __init gic_init_irq(void) #endif } else { /* board GIC, primary */ + gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE); gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); - gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); + gic_cpu_init(0, gic_cpu_base_addr); } } diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 629944deed5..cd26306d8e5 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -9,17 +9,13 @@ */ #include #include -#include .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp -#ifdef CONFIG_REALVIEW_MPCORE - ldr \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE) -#else - ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) -#endif + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] .endm .macro arch_ret_to_user, tmp1, tmp2 -- cgit v1.2.3-70-g09d2 From 8cc4c5488a28fe6a1f834e99317bb762798600f7 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:43:02 +0100 Subject: [ARM] 4820/1: RealView: Select the timer IRQ at run-time This patch sets the timer IRQ at run-time by moving the sys_timer structure and the timer_init function to the realview_eb.c file. This allows multiple RealView platforms to be compiled in the same kernel image. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/core.c | 15 +++++---------- arch/arm/mach-realview/core.h | 3 +-- arch/arm/mach-realview/realview_eb.c | 19 ++++++++++++++++++- 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 29514ac94f3..98aefc9f4df 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include @@ -513,12 +512,12 @@ static struct clock_event_device timer0_clockevent = { .set_mode = timer_set_mode, .set_next_event = timer_set_next_event, .rating = 300, - .irq = IRQ_TIMERINT0_1, .cpumask = CPU_MASK_ALL, }; -static void __init realview_clockevents_init(void) +static void __init realview_clockevents_init(unsigned int timer_irq) { + timer0_clockevent.irq = timer_irq; timer0_clockevent.mult = div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); timer0_clockevent.max_delta_ns = @@ -581,7 +580,7 @@ static void __init realview_clocksource_init(void) /* * Set up the clock source and clock events devices */ -static void __init realview_timer_init(void) +void __init realview_timer_init(unsigned int timer_irq) { u32 val; @@ -616,12 +615,8 @@ static void __init realview_timer_init(void) /* * Make irqs happen for the system timer */ - setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq); + setup_irq(timer_irq, &realview_timer_irq); realview_clocksource_init(); - realview_clockevents_init(); + realview_clockevents_init(timer_irq); } - -struct sys_timer realview_timer = { - .init = realview_timer_init, -}; diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 1c091372be6..16c9d45ce2c 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -27,8 +27,6 @@ #include #include -extern struct sys_timer realview_timer; - #define AMBA_DEVICE(name,busid,base,plat) \ static struct amba_device name##_device = { \ .dev = { \ @@ -55,5 +53,6 @@ extern struct clcd_board clcd_plat_data; extern void __iomem *gic_cpu_base_addr; extern void realview_leds_event(led_event_t ledevt); +extern void realview_timer_init(unsigned int timer_irq); #endif diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index f36af133502..20b05f2ed61 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -304,6 +305,22 @@ static void realview_eb11mp_fixup(void) realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH; } +static void __init realview_eb_timer_init(void) +{ + unsigned int timer_irq; + + if (core_tile_eb11mp()) + timer_irq = IRQ_EB11MP_TIMER0_1; + else + timer_irq = IRQ_EB_TIMER0_1; + + realview_timer_init(timer_irq); +} + +static struct sys_timer realview_eb_timer = { + .init = realview_eb_timer_init, +}; + static void __init realview_eb_init(void) { int i; @@ -339,6 +356,6 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB") .boot_params = 0x00000100, .map_io = realview_eb_map_io, .init_irq = gic_init_irq, - .timer = &realview_timer, + .timer = &realview_eb_timer, .init_machine = realview_eb_init, MACHINE_END -- cgit v1.2.3-70-g09d2 From 39e823e35b791b905e0d8eba62e8b3a0b3351936 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:45:03 +0100 Subject: [ARM] 4821/1: RealView: Remove the platform dependencies from localtimer.c This patch removes the TWD_BASE macro used to set up and configure the local timers on ARM11MPCore. The twd_base_addr and twd_size variables are defined in localtimer.c and set from the realview_eb_init function. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-realview/core.h | 4 ++++ arch/arm/mach-realview/localtimer.c | 9 ++++++--- arch/arm/mach-realview/realview_eb.c | 8 ++++++-- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 16c9d45ce2c..492a14c0d60 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -51,6 +51,10 @@ extern struct mmc_platform_data realview_mmc1_plat_data; extern struct clk realview_clcd_clk; extern struct clcd_board clcd_plat_data; extern void __iomem *gic_cpu_base_addr; +#ifdef CONFIG_LOCAL_TIMERS +extern void __iomem *twd_base_addr; +extern unsigned int twd_size; +#endif extern void realview_leds_event(led_event_t ledevt); extern void realview_timer_init(unsigned int timer_irq); diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index 60500f0b878..50604360479 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c @@ -24,9 +24,6 @@ #include #include -#define TWD_BASE(cpu) (__io_address(REALVIEW_EB11MP_TWD_BASE) + \ - ((cpu) * REALVIEW_EB11MP_TWD_SIZE)) - static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); /* @@ -41,6 +38,12 @@ void local_timer_interrupt(void) #ifdef CONFIG_LOCAL_TIMERS +#define TWD_BASE(cpu) (twd_base_addr + (cpu) * twd_size) + +/* set up by the platform code */ +void __iomem *twd_base_addr; +unsigned int twd_size; + static unsigned long mpcore_timer_rate; static void local_timer_set_mode(enum clock_event_mode mode, diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 20b05f2ed61..8ded2cc79cc 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -309,9 +309,13 @@ static void __init realview_eb_timer_init(void) { unsigned int timer_irq; - if (core_tile_eb11mp()) + if (core_tile_eb11mp()) { +#ifdef CONFIG_LOCAL_TIMERS + twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE); + twd_size = REALVIEW_EB11MP_TWD_SIZE; +#endif timer_irq = IRQ_EB11MP_TIMER0_1; - else + } else timer_irq = IRQ_EB_TIMER0_1; realview_timer_init(timer_irq); -- cgit v1.2.3-70-g09d2 From 41579f49da23e2d26b6e5efa5c3311998e911e5c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 4 Feb 2008 17:47:04 +0100 Subject: [ARM] 4822/1: RealView: Change the REALVIEW_MPCORE configuration option This patch changes the REALVIEW_MPCORE configuration option to REALVIEW_EB_ARM11MP since this is only specific to RealView/EB. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 4 ++-- arch/arm/mach-realview/Kconfig | 21 +++++++++------------ arch/arm/mach-realview/realview_eb.c | 2 +- include/asm-arm/arch-realview/board-eb.h | 6 +++--- 4 files changed, 15 insertions(+), 18 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0aeecc33c7..a421a7f2409 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -611,7 +611,7 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL && REALVIEW_MPCORE + depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -645,7 +645,7 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" - depends on SMP && REALVIEW_MPCORE + depends on SMP && REALVIEW_EB_ARM11MP default y help Enable support for local timers on SMP platforms, rather then the diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 35156ca39df..39b3bb7f102 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -7,24 +7,21 @@ config MACH_REALVIEW_EB help Include support for the ARM(R) RealView Emulation Baseboard platform. -config REALVIEW_MPCORE - bool "Support MPcore tile" +config REALVIEW_EB_ARM11MP + bool "Support ARM11MPCore tile" depends on MACH_REALVIEW_EB select CACHE_L2X0 help - Enable support for the MPCore tile on the Realview platform. - Since there are device address and interrupt differences, a - kernel built with this option enabled is not compatible with - other tiles. + Enable support for the ARM11MPCore tile on the Realview platform. -config REALVIEW_MPCORE_REVB - bool "Support MPcore RevB tile" - depends on REALVIEW_MPCORE +config REALVIEW_EB_ARM11MP_REVB + bool "Support ARM11MPCore RevB tile" + depends on REALVIEW_EB_ARM11MP default n help - Enable support for the MPCore RevB tile on the Realview platform. - Since there are device address differences, a + Enable support for the ARM11MPCore RevB tile on the Realview + platform. Since there are device address differences, a kernel built with this option enabled is not compatible with - other tiles. + other revisions of the ARM11MPCore tile. endmenu diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 8ded2cc79cc..60d9eb81024 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -261,7 +261,7 @@ static void __init gic_init_irq(void) gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); gic_cpu_init(0, gic_cpu_base_addr); -#ifndef CONFIG_REALVIEW_MPCORE_REVB +#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB /* board GIC, secondary */ gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64); gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE)); diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h index 9e76b236b52..3e437b7f425 100644 --- a/include/asm-arm/arch-realview/board-eb.h +++ b/include/asm-arm/arch-realview/board-eb.h @@ -26,7 +26,7 @@ /* * RealView EB + ARM11MPCore peripheral addresses */ -#ifdef CONFIG_REALVIEW_MPCORE_REVB +#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ #define REALVIEW_EB11MP_TWD_BASE 0x10100700 @@ -143,7 +143,7 @@ #define NR_IRQS NR_IRQS_EB #endif -#if defined(CONFIG_REALVIEW_MPCORE) \ +#if defined(CONFIG_REALVIEW_EB_ARM11MP) \ && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) #undef MAX_GIC_NR #define MAX_GIC_NR NR_GIC_EB11MP @@ -162,7 +162,7 @@ ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \ == proc_type) -#ifdef CONFIG_REALVIEW_MPCORE +#ifdef CONFIG_REALVIEW_EB_ARM11MP #define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP) #else #define core_tile_eb11mp() 0 -- cgit v1.2.3-70-g09d2