From d30982b93a79aafa688e7df1f6948ad28bb94e89 Mon Sep 17 00:00:00 2001
From: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Date: Fri, 23 May 2014 16:32:39 -0400
Subject: Documentation: dt: add bindings for keystone pll control controller
The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization.
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[santosh.shilimkar@ti.com: Fixed the subject line]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
---
.../bindings/clock/ti-keystone-pllctrl.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
(limited to 'Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt')
diff --git a/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt b/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
new file mode 100644
index 00000000000..3e6a81e9980
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti-keystone-pllctrl.txt
@@ -0,0 +1,20 @@
+* Device tree bindings for Texas Instruments keystone pll controller
+
+The main pll controller used to drive theC66x CorePacs, the switch fabric,
+and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
+the NETCP modules) requires a PLL Controller to manage the various clock
+divisions, gating, and synchronization.
+
+Required properties:
+
+- compatible: "ti,keystone-pllctrl", "syscon"
+
+- reg: contains offset/length value for pll controller
+ registers space.
+
+Example:
+
+pllctrl: pll-controller@0x02310000 {
+ compatible = "ti,keystone-pllctrl", "syscon";
+ reg = <0x02310000 0x200>;
+};
--
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