From 85f8879ca4f3d26a7f473522101fb74a79bda3f2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 1 Oct 2012 08:41:23 +0200 Subject: pwm: dt: Fix description of second PWM cell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The second cell in the PWM specifier denotes the period in nanoseconds, not the duty cycle. The latter can be freely configured at runtime and a PWM with a fixed duty cycle would be rather pointless. Signed-off-by: Thierry Reding Cc: Shawn Guo Cc: Sascha Hauer Cc: Philipp Zabel Cc: "Benoît Thébaudeau" Cc: Stephen Warren Acked-by: Sascha Hauer Acked-by: Shawn Guo --- Documentation/devicetree/bindings/pwm/imx-pwm.txt | 2 +- Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 2 +- Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index 9b9b18514b6..8522bfbccfd 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -4,7 +4,7 @@ Required properties: - compatible: should be "fsl,-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. The first cell specifies the per-chip index - of the PWM to use and the second cell is the duty cycle in nanoseconds. + of the PWM to use and the second cell is the period in nanoseconds. - interrupts: The interrupt for the pwm controller Example: diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt index b16f4a57d11..d7946be6cd2 100644 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt @@ -4,7 +4,7 @@ Required properties: - compatible: should be "fsl,imx23-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. The first cell specifies the per-chip index - of the PWM to use and the second cell is the duty cycle in nanoseconds. + of the PWM to use and the second cell is the period in nanoseconds. - fsl,pwm-number: the number of PWM devices Example: diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index bbbeedb4ec0..01438ecd662 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -7,7 +7,7 @@ Required properties: - reg: physical base address and length of the controller's registers - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The first cell specifies the per-chip index of the PWM to use and the second - cell is the duty cycle in nanoseconds. + cell is the period in nanoseconds. Example: -- cgit v1.2.3-70-g09d2