From 4566b4beafe4582488907b84cb04e6c0efba384a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 2 Jan 2014 22:05:04 +0100 Subject: ARM: sun7i: Add missing serial aliases Some UART aliases have been defined, but not all of them. Add the remaining ones to be consistent and to ease the parsing of the DT by the bootloaders. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 119f066f0d9..b47685587eb 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -18,6 +18,14 @@ aliases { ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; }; cpus { -- cgit v1.2.3-70-g09d2 From 4261ec43b199a214f6b0ae5fefefff2e524f8977 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 14 Jan 2014 22:49:50 +0800 Subject: ARM: dts: sun7i: add pin muxing options for UART2 UART2 is used on CubieTruck to connect to the Bluetooth module. Add the pin set used in this case. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index b47685587eb..bfb2cf283db 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -381,6 +381,13 @@ allwinner,pull = <0>; }; + uart2_pins_a: uart2@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "uart2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart6_pins_a: uart6@0 { allwinner,pins = "PI12", "PI13"; allwinner,function = "uart6"; -- cgit v1.2.3-70-g09d2 From 06067a2f62a20130fe20b2837ebf097f0d670dd3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Feb 2014 09:51:44 +0800 Subject: ARM: dts: sun7i: rename clock node names to clk@N Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index bfb2cf283db..4fbe530ec4c 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -54,11 +54,12 @@ #size-cells = <1>; ranges; - osc24M: osc24M@01c20050 { + osc24M: clk@01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; osc32k: clk@0 { @@ -68,21 +69,23 @@ clock-output-names = "osc32k"; }; - pll1: pll1@01c20000 { + pll1: clk@01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4@01c20018 { + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5@01c20020 { + pll5: clk@01c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll5-clk"; reg = <0x01c20020 0x4>; @@ -90,7 +93,7 @@ clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6@01c20028 { + pll6: clk@01c20028 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll6-clk"; reg = <0x01c20028 0x4>; @@ -103,6 +106,7 @@ compatible = "allwinner,sun4i-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; + clock-output-names = "cpu"; }; axi: axi@01c20054 { @@ -110,6 +114,7 @@ compatible = "allwinner,sun4i-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; + clock-output-names = "axi"; }; ahb: ahb@01c20054 { @@ -117,9 +122,10 @@ compatible = "allwinner,sun4i-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; + clock-output-names = "ahb"; }; - ahb_gates: ahb_gates@01c20060 { + ahb_gates: clk@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-ahb-gates-clk"; reg = <0x01c20060 0x8>; @@ -144,9 +150,10 @@ compatible = "allwinner,sun4i-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; + clock-output-names = "apb0"; }; - apb0_gates: apb0_gates@01c20068 { + apb0_gates: clk@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb0-gates-clk"; reg = <0x01c20068 0x4>; @@ -162,6 +169,7 @@ compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; + clock-output-names = "apb1_mux"; }; apb1: apb1@01c20058 { @@ -169,9 +177,10 @@ compatible = "allwinner,sun4i-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; + clock-output-names = "apb1"; }; - apb1_gates: apb1_gates@01c2006c { + apb1_gates: clk@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb1-gates-clk"; reg = <0x01c2006c 0x4>; -- cgit v1.2.3-70-g09d2 From daed5a8163dcc9ff63e4fde8f7e8ce885ba4c34b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 10 Feb 2014 18:35:48 +0800 Subject: ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI The GMAC uses 1 of 2 sources for its transmit clock, depending on the PHY interface mode. Add both sources as dummy clocks, and as parents to the GMAC clock node. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 4fbe530ec4c..dd567eac3de 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -321,6 +321,34 @@ clock-output-names = "mbus"; }; + /* + * The following two are dummy clocks, placeholders used in the gmac_tx + * clock. The gmac driver will choose one parent depending on the PHY + * interface mode, using clk_set_rate auto-reparenting. + * The actual TX clock rate is not controlled by the gmac_tx clock. + */ + mii_phy_tx_clk: clk@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: clk@3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@01c20164 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c20164 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; + /* * Dummy clock used by output clocks */ -- cgit v1.2.3-70-g09d2 From c40b8d5858f6396b11d7f859a76bef9b82a65743 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 10 Feb 2014 18:35:49 +0800 Subject: ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index dd567eac3de..8eb4d54a905 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -645,6 +645,21 @@ status = "disabled"; }; + gmac: ethernet@01c50000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x01c50000 0x10000>; + interrupts = <0 85 4>; + interrupt-names = "macirq"; + clocks = <&ahb_gates 49>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + hstimer@01c60000 { compatible = "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; -- cgit v1.2.3-70-g09d2 From 129ccbcd6fc704f3a0df892240f3aeb463d461f5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 10 Feb 2014 18:35:50 +0800 Subject: ARM: dts: sun7i: Add pin muxing options for the GMAC The A20 has EMAC and GMAC muxed on the same pins. Add pin sets with gmac function for MII and RGMII mode to the DTSI. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 8eb4d54a905..68c889c9fd3 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -484,6 +484,32 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "gmac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA10", + "PA11", "PA12", "PA13", + "PA15", "PA16"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = <3>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.2.3-70-g09d2 From 18428f7782920171fbcf0ccedcf6a146e7cc2e6f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 10 Feb 2014 18:35:54 +0800 Subject: ARM: dts: sun7i: Add ethernet alias for GMAC All Allwinner A20 boards we support can only use either EMAC or GMAC, as they share the same pins. As we have switched all supported to GMAC, we should alias GMAC (the active controller) as ethernet0, so u-boot will insert the MAC address for the correct controller. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 68c889c9fd3..1b5fb880435 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -17,7 +17,7 @@ interrupt-parent = <&gic>; aliases { - ethernet0 = &emac; + ethernet0 = &gmac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; -- cgit v1.2.3-70-g09d2 From 434e41b34a894de3b4c7af9d0ab9a2040eeeee6b Mon Sep 17 00:00:00 2001 From: Roman Byshko Date: Fri, 7 Feb 2014 16:21:53 +0100 Subject: ARM: sun7i: dt: Add bindings for USB clocks Signed-off-by: Roman Byshko Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 1b5fb880435..2cdf57da190 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -305,6 +305,15 @@ clock-output-names = "ir1"; }; + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&pll6 1>; + clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; + }; + spi3_clk: clk@01c200d4 { #clock-cells = <0>; compatible = "allwinner,sun4i-mod0-clk"; -- cgit v1.2.3-70-g09d2 From 7902763e4a4d04a96406447f935a8f676e73e0ce Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 18 Feb 2014 14:04:44 +0000 Subject: ARM: sun7i: add arch timer node The Allwinner A20 SoC is built around a pair of Cortex-A7 cores, which have the usual generic timers. Report this in the DT. Signed-off-by: Marc Zyngier Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 2cdf57da190..25ba9fa99c5 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -49,6 +49,14 @@ reg = <0x40000000 0x80000000>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3-70-g09d2 From bf6534a180d6d596521b0bfa6de29da5e18314a6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 6 Feb 2014 09:55:58 +0100 Subject: ARM: sunxi: dt: Convert to the new clock compatibles Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 60 +++++++++++++++++++-------------------- arch/arm/boot/dts/sun5i-a10s.dtsi | 48 +++++++++++++++---------------- arch/arm/boot/dts/sun5i-a13.dtsi | 48 +++++++++++++++---------------- arch/arm/boot/dts/sun6i-a31.dtsi | 10 +++---- arch/arm/boot/dts/sun7i-a20.dtsi | 54 +++++++++++++++++------------------ 5 files changed, 110 insertions(+), 110 deletions(-) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index b268f68cf8f..5b18f7d9485 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -60,7 +60,7 @@ osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; @@ -75,7 +75,7 @@ pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; clock-output-names = "pll1"; @@ -83,7 +83,7 @@ pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; clock-output-names = "pll4"; @@ -91,7 +91,7 @@ pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; @@ -99,7 +99,7 @@ pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -108,7 +108,7 @@ /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; clock-output-names = "cpu"; @@ -116,7 +116,7 @@ axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; clock-output-names = "axi"; @@ -124,7 +124,7 @@ axi_gates: clk@01c2005c { #clock-cells = <1>; - compatible = "allwinner,sun4i-axi-gates-clk"; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; clock-output-names = "axi_dram"; @@ -132,7 +132,7 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; clock-output-names = "ahb"; @@ -140,7 +140,7 @@ ahb_gates: clk@01c20060 { #clock-cells = <1>; - compatible = "allwinner,sun4i-ahb-gates-clk"; + compatible = "allwinner,sun4i-a10-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; clock-output-names = "ahb_usb0", "ahb_ehci0", @@ -158,7 +158,7 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; clock-output-names = "apb0"; @@ -166,7 +166,7 @@ apb0_gates: clk@01c20068 { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb0-gates-clk"; + compatible = "allwinner,sun4i-a10-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; clock-output-names = "apb0_codec", "apb0_spdif", @@ -176,7 +176,7 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1_mux"; @@ -184,7 +184,7 @@ apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; clock-output-names = "apb1"; @@ -192,7 +192,7 @@ apb1_gates: clk@01c2006c { #clock-cells = <1>; - compatible = "allwinner,sun4i-apb1-gates-clk"; + compatible = "allwinner,sun4i-a10-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; clock-output-names = "apb1_i2c0", "apb1_i2c1", @@ -205,7 +205,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -213,7 +213,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -221,7 +221,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -229,7 +229,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -237,7 +237,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -245,7 +245,7 @@ mmc3_clk: clk@01c20094 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20094 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc3"; @@ -253,7 +253,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -261,7 +261,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -269,7 +269,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -277,7 +277,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -285,7 +285,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -293,7 +293,7 @@ pata_clk: clk@01c200ac { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "pata"; @@ -301,7 +301,7 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; @@ -309,7 +309,7 @@ ir1_clk: clk@01c200b4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir1"; @@ -326,7 +326,7 @@ spi3_clk: clk@01c200d4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200d4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi3"; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 0e0da137279..9cbd88421db 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -53,7 +53,7 @@ osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; @@ -68,7 +68,7 @@ pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; clock-output-names = "pll1"; @@ -76,7 +76,7 @@ pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; clock-output-names = "pll4"; @@ -84,7 +84,7 @@ pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; @@ -92,7 +92,7 @@ pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -101,7 +101,7 @@ /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; clock-output-names = "cpu"; @@ -109,7 +109,7 @@ axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; clock-output-names = "axi"; @@ -117,7 +117,7 @@ axi_gates: clk@01c2005c { #clock-cells = <1>; - compatible = "allwinner,sun4i-axi-gates-clk"; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; clock-output-names = "axi_dram"; @@ -125,7 +125,7 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; clock-output-names = "ahb"; @@ -147,7 +147,7 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; clock-output-names = "apb0"; @@ -164,7 +164,7 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1_mux"; @@ -172,7 +172,7 @@ apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; clock-output-names = "apb1"; @@ -190,7 +190,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -198,7 +198,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -206,7 +206,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -214,7 +214,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -222,7 +222,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -230,7 +230,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -238,7 +238,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -246,7 +246,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -254,7 +254,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -262,7 +262,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -270,7 +270,7 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; @@ -287,7 +287,7 @@ mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mbus"; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index b1468b3c7c5..6caf65dbf18 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -54,7 +54,7 @@ osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; @@ -69,7 +69,7 @@ pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; clock-output-names = "pll1"; @@ -77,7 +77,7 @@ pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; clock-output-names = "pll4"; @@ -85,7 +85,7 @@ pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; @@ -93,7 +93,7 @@ pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -102,7 +102,7 @@ /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; clock-output-names = "cpu"; @@ -110,7 +110,7 @@ axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; clock-output-names = "axi"; @@ -118,7 +118,7 @@ axi_gates: clk@01c2005c { #clock-cells = <1>; - compatible = "allwinner,sun4i-axi-gates-clk"; + compatible = "allwinner,sun4i-a10-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; clock-output-names = "axi_dram"; @@ -126,7 +126,7 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; clock-output-names = "ahb"; @@ -147,7 +147,7 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; clock-output-names = "apb0"; @@ -163,7 +163,7 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1_mux"; @@ -171,7 +171,7 @@ apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; clock-output-names = "apb1"; @@ -188,7 +188,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -196,7 +196,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -204,7 +204,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -212,7 +212,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -220,7 +220,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -228,7 +228,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -236,7 +236,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -244,7 +244,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -252,7 +252,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -260,7 +260,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -268,7 +268,7 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; @@ -285,7 +285,7 @@ mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mbus"; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d3f19951d50..af6f87c4e1c 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -95,7 +95,7 @@ cpu: cpu@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20050 0x4>; /* @@ -110,7 +110,7 @@ axi: axi@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20050 0x4>; clocks = <&cpu>; clock-output-names = "axi"; @@ -126,7 +126,7 @@ ahb1: ahb1@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb1_mux>; clock-output-names = "ahb1"; @@ -155,7 +155,7 @@ apb1: apb1@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb1>; clock-output-names = "apb1"; @@ -173,7 +173,7 @@ apb2_mux: apb2_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; clock-output-names = "apb2_mux"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 25ba9fa99c5..bc528de39f8 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -64,7 +64,7 @@ osc24M: clk@01c20050 { #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; + compatible = "allwinner,sun4i-a10-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; clock-output-names = "osc24M"; @@ -79,7 +79,7 @@ pll1: clk@01c20000 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; clock-output-names = "pll1"; @@ -87,7 +87,7 @@ pll4: clk@01c20018 { #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; + compatible = "allwinner,sun4i-a10-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; clock-output-names = "pll4"; @@ -95,7 +95,7 @@ pll5: clk@01c20020 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; + compatible = "allwinner,sun4i-a10-pll5-clk"; reg = <0x01c20020 0x4>; clocks = <&osc24M>; clock-output-names = "pll5_ddr", "pll5_other"; @@ -103,7 +103,7 @@ pll6: clk@01c20028 { #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; + compatible = "allwinner,sun4i-a10-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; clock-output-names = "pll6_sata", "pll6_other", "pll6"; @@ -111,7 +111,7 @@ cpu: cpu@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; + compatible = "allwinner,sun4i-a10-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; clock-output-names = "cpu"; @@ -119,7 +119,7 @@ axi: axi@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-axi-clk"; + compatible = "allwinner,sun4i-a10-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; clock-output-names = "axi"; @@ -127,7 +127,7 @@ ahb: ahb@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-ahb-clk"; + compatible = "allwinner,sun4i-a10-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; clock-output-names = "ahb"; @@ -155,7 +155,7 @@ apb0: apb0@01c20054 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb0-clk"; + compatible = "allwinner,sun4i-a10-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; clock-output-names = "apb0"; @@ -174,7 +174,7 @@ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1_mux"; @@ -182,7 +182,7 @@ apb1: apb1@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-apb1-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; clock-output-names = "apb1"; @@ -203,7 +203,7 @@ nand_clk: clk@01c20080 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20080 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "nand"; @@ -211,7 +211,7 @@ ms_clk: clk@01c20084 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20084 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ms"; @@ -219,7 +219,7 @@ mmc0_clk: clk@01c20088 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc0"; @@ -227,7 +227,7 @@ mmc1_clk: clk@01c2008c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc1"; @@ -235,7 +235,7 @@ mmc2_clk: clk@01c20090 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc2"; @@ -243,7 +243,7 @@ mmc3_clk: clk@01c20094 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20094 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mmc3"; @@ -251,7 +251,7 @@ ts_clk: clk@01c20098 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20098 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ts"; @@ -259,7 +259,7 @@ ss_clk: clk@01c2009c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2009c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ss"; @@ -267,7 +267,7 @@ spi0_clk: clk@01c200a0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi0"; @@ -275,7 +275,7 @@ spi1_clk: clk@01c200a4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi1"; @@ -283,7 +283,7 @@ spi2_clk: clk@01c200a8 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi2"; @@ -291,7 +291,7 @@ pata_clk: clk@01c200ac { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "pata"; @@ -299,7 +299,7 @@ ir0_clk: clk@01c200b0 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b0 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; @@ -307,7 +307,7 @@ ir1_clk: clk@01c200b4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200b4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir1"; @@ -324,7 +324,7 @@ spi3_clk: clk@01c200d4 { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200d4 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi3"; @@ -332,7 +332,7 @@ mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-mod0-clk"; + compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; clock-output-names = "mbus"; -- cgit v1.2.3-70-g09d2 From 36ab3e73b7acd50f77070de696cb349abfd8ae6f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 22 Feb 2014 22:35:54 +0100 Subject: ARM: dt: sun7i: Add A20 SPI controller nodes The A20 has 4 SPI controllers compatible with the one found in the A10. Add them in the DT. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index bc528de39f8..7c0f61001e9 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -401,6 +401,28 @@ #size-cells = <1>; ranges; + spi0: spi@01c05000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <0 10 4>; + clocks = <&ahb_gates 20>, <&spi0_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c06000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <0 11 4>; + clocks = <&ahb_gates 21>, <&spi1_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@01c0b000 { compatible = "allwinner,sun4i-emac"; reg = <0x01c0b000 0x1000>; @@ -417,6 +439,28 @@ #size-cells = <0>; }; + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <0 12 4>; + clocks = <&ahb_gates 22>, <&spi2_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi3: spi@01c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb_gates 23>, <&spi3_clk>; + clock-names = "ahb", "mod"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; -- cgit v1.2.3-70-g09d2 From 412f2c6fa43ae00a8be2c08a49b1dd57e2223715 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 22 Feb 2014 22:35:58 +0100 Subject: ARM: dt: sun7i: Add SPI muxing options Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 7c0f61001e9..fa0e5f8c448 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -571,6 +571,20 @@ allwinner,drive = <3>; allwinner,pull = <0>; }; + + spi1_pins_a: spi1@0 { + allwinner,pins = "PI16", "PI17", "PI18", "PI19"; + allwinner,function = "spi1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + spi2_pins_a: spi2@0 { + allwinner,pins = "PC19", "PC20", "PC21", "PC22"; + allwinner,function = "spi2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.2.3-70-g09d2 From 902febf9ea856dc9a9376bcdc70dfaa9b3ad5a74 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 1 Mar 2014 20:26:22 +0100 Subject: ARM: sun7i: dt: Add ahci / sata support This patch adds sunxi sata support to A20 boards that have such a connector. Some boards also feature a regulator via a GPIO and support for this is also added. Signed-off-by: Olliver Schinagl Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 10 ++++++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 19 +++++++++++++++++++ arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 10 ++++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 4 files changed, 47 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 7bf4935a58a..4bed1159cee 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -13,12 +13,18 @@ /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Cubietech Cubieboard2"; compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; soc@01c00000 { + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + pinctrl@01c20800 { led_pins_cubieboard2: led_pins@0 { allwinner,pins = "PH20", "PH21"; @@ -74,4 +80,8 @@ gpios = <&pio 7 20 0>; }; }; + + reg_ahci_5v: ahci-5v { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 025ce523469..ef5fed898a1 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -13,13 +13,26 @@ /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Cubietech Cubietruck"; compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; soc@01c00000 { + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + pinctrl@01c20800 { + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + led_pins_cubietruck: led_pins@0 { allwinner,pins = "PH7", "PH11", "PH20", "PH21"; allwinner,function = "gpio_out"; @@ -90,4 +103,10 @@ gpios = <&pio 7 7 0>; }; }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_cubietruck>; + gpio = <&pio 7 12 0>; + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 9d98316c992..c9b0f370b03 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -13,6 +13,7 @@ /dts-v1/; /include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Olimex A20-Olinuxino Micro"; @@ -36,6 +37,11 @@ status = "okay"; }; + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + pinctrl@01c20800 { led_pins_olinuxino: led_pins@0 { allwinner,pins = "PH2"; @@ -105,4 +111,8 @@ default-state = "on"; }; }; + + reg_ahci_5v: ahci-5v { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index fa0e5f8c448..38916fbffaa 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -450,6 +450,14 @@ #size-cells = <0>; }; + ahci: sata@01c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <0 56 4>; + clocks = <&pll6 0>, <&ahb_gates 25>; + status = "disabled"; + }; + spi3: spi@01c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; -- cgit v1.2.3-70-g09d2 From 9debd0a2af9335900e4cc6fb1ed75ea467bb5c30 Mon Sep 17 00:00:00 2001 From: Roman Byshko Date: Sat, 1 Mar 2014 20:26:25 +0100 Subject: ARM: sun7i: dt: Add USB host bindings Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: Roman Byshko Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 38916fbffaa..f1d903f678c 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -439,6 +439,38 @@ #size-cells = <0>; }; + usbphy: phy@01c13400 { + #phy-cells = <1>; + compatible = "allwinner,sun7i-a20-usb-phy"; + reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; + reg-names = "phy_ctrl", "pmu1", "pmu2"; + clocks = <&usb_clk 8>; + clock-names = "usb_phy"; + resets = <&usb_clk 1>, <&usb_clk 2>; + reset-names = "usb1_reset", "usb2_reset"; + status = "disabled"; + }; + + ehci0: usb@01c14000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c14000 0x100>; + interrupts = <0 39 4>; + clocks = <&ahb_gates 1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c14400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c14400 0x100>; + interrupts = <0 64 4>; + clocks = <&usb_clk 6>, <&ahb_gates 2>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; @@ -458,6 +490,26 @@ status = "disabled"; }; + ehci1: usb@01c1c000 { + compatible = "allwinner,sun7i-a20-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <0 40 4>; + clocks = <&ahb_gates 3>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1c400 { + compatible = "allwinner,sun7i-a20-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <0 65 4>; + clocks = <&usb_clk 7>, <&ahb_gates 4>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + spi3: spi@01c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; -- cgit v1.2.3-70-g09d2 From ca5d04d90825a3f3f2fc1aaba09953a55564e0e8 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Feb 2014 22:29:26 +0100 Subject: ARM: sunxi: dt: Update the watchdog compatibles The watchdog compatibles were following a different pattern than the one found in the other devices. Now that the driver supports the right pattern, switch to it in the DT. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 56eaf11c446..385ce919326 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -539,7 +539,7 @@ }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index fc1ee20a34d..efe870508d8 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -461,7 +461,7 @@ }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 8931c0895c7..7c6bb1bde9d 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -425,7 +425,7 @@ }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 7fff9a20f07..922864c2e1a 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -310,7 +310,7 @@ }; wdt1: watchdog@01c20ca0 { - compatible = "allwinner,sun6i-wdt"; + compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index f1d903f678c..ed43a5cee35 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -660,7 +660,7 @@ }; wdt: watchdog@01c20c90 { - compatible = "allwinner,sun4i-wdt"; + compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; }; -- cgit v1.2.3-70-g09d2