From 34c2e5feeb0164baef76555141ad5b8dc84394bb Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 6 Feb 2013 21:15:09 -0600 Subject: ARM: dts: vexpress: disable CA9 core tile sp804 timer The motherboard sp804 timer is used, but core tile sp804 timer is not. According to Russell King, the clock configuration is undocumented and defaults to 32kHz which is not desireable. So mark core tile sp804 timer as disabled. Signed-off-by: Rob Herring --- arch/arm/boot/dts/vexpress-v2p-ca9.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/vexpress-v2p-ca9.dts') diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 1420bb14d95..62d9b225dcc 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -98,6 +98,7 @@ <0 49 4>; clocks = <&oscclk2>, <&oscclk2>; clock-names = "timclk", "apb_pclk"; + status = "disabled"; }; watchdog@100e5000 { -- cgit v1.2.3-70-g09d2