From 8777539479abd7b3efeb691685415dc2b057d0e0 Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Thu, 12 Dec 2013 08:32:02 +0530 Subject: ARM: dts: exynos5250: Fix MDMA0 clock number Due to incorrect clock specified in MDMA0 node, using MDMA0 controller could cause system failures, due to wrong clock being controlled. This patch fixes this by specifying correct clock. Signed-off-by: Abhilash Kesavan Acked-by: Mike Turquette [t.figa: Corrected commit message and description.] Signed-off-by: Tomasz Figa --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9db5047812f..177becde7a2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -559,7 +559,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = <0 33 0>; - clocks = <&clock 271>; + clocks = <&clock 346>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; -- cgit v1.2.3-70-g09d2 From c08ceea3a9d3276ec464e8b74573b1c58e93db7f Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Wed, 25 Sep 2013 14:12:50 -0700 Subject: ARM: dts: exynos5250: add input clocks to audss clock controller Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS clock controller. Signed-off-by: Andrew Bresticker Acked-by: Mike Turquette Acked-by: Kukjin Kim Signed-off-by: Tomasz Figa --- arch/arm/boot/dts/exynos5250.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 177becde7a2..c70843fe1e2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -88,6 +88,8 @@ compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; timer { -- cgit v1.2.3-70-g09d2 From 59d711e9ddd2f68822a2a99fc939e11a9288b73e Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Wed, 25 Sep 2013 14:12:52 -0700 Subject: ARM: dts: exynos5420: add input clocks to audss clock controller Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in) for the AudioSS clock controller. Signed-off-by: Andrew Bresticker Acked-by: Mike Turquette Acked-by: Kukjin Kim Signed-off-by: Tomasz Figa --- arch/arm/boot/dts/exynos5420.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 09aa06cb3d3..25a1120d88a 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -76,8 +76,8 @@ compatible = "samsung,exynos5420-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock 148>; - clock-names = "sclk_audio"; + clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; codec@11000000 { -- cgit v1.2.3-70-g09d2 From ada12c4798bcd01128e8e30f45e889083bb68730 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 12 Dec 2013 17:07:21 +0100 Subject: ARM: dts: Add clock provider specific properties to max77686 node This patch adds a label and #clock-cells property to device node of max77686 PMIC to allow using it as a clock provider. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Signed-off-by: Mike Turquette --- arch/arm/boot/dts/cros5250-common.dtsi | 1 + arch/arm/boot/dts/exynos4412-odroidx.dts | 1 + arch/arm/boot/dts/exynos4412-trats2.dts | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index dc259e8b8a7..c33a01eda52 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -36,6 +36,7 @@ max77686@09 { compatible = "maxim,max77686"; reg = <0x09>; + #clock-cells = <1>; voltage-regulators { ldo1_reg: LDO1 { diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 46c678ee119..8d337cc8f4e 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -119,6 +119,7 @@ max77686: pmic@09 { compatible = "maxim,max77686"; reg = <0x09>; + #clock-cells = <1>; voltage-regulators { ldo1_reg: LDO1 { diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index fb7b9ae5f39..c21a8b916bf 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -139,6 +139,7 @@ interrupt-parent = <&gpx0>; interrupts = <7 0>; reg = <0x09>; + #clock-cells = <1>; voltage-regulators { ldo1_reg: ldo1 { -- cgit v1.2.3-70-g09d2