From f00ec48fadf5e37e7889f14cff900aa70d18b644 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Sep 2010 10:47:48 +0100 Subject: ARM: Allow SMP kernels to boot on UP systems UP systems do not implement all the instructions that SMP systems have, so in order to boot a SMP kernel on a UP system, we need to rewrite parts of the kernel. Do this using an 'alternatives' scheme, where the kernel code and data is modified prior to initialization to replace the SMP instructions, thereby rendering the problematical code ineffectual. We use the linker to generate a list of 32-bit word locations and their replacement values, and run through these replacements when we detect a UP system. Signed-off-by: Russell King --- arch/arm/kernel/head.S | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch/arm/kernel/head.S') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index eb62bf94721..b44d21e1e34 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -86,6 +86,9 @@ ENTRY(stext) movs r8, r5 @ invalid machine (r5=0)? beq __error_a @ yes, error 'a' bl __vet_atags +#ifdef CONFIG_SMP_ON_UP + bl __fixup_smp +#endif bl __create_page_tables /* @@ -333,4 +336,51 @@ __create_page_tables: ENDPROC(__create_page_tables) .ltorg +#ifdef CONFIG_SMP_ON_UP +__fixup_smp: + mov r7, #0x00070000 + orr r6, r7, #0xff000000 @ mask 0xff070000 + orr r7, r7, #0x41000000 @ val 0x41070000 + and r0, r9, r6 + teq r0, r7 @ ARM CPU and ARMv6/v7? + bne __fixup_smp_on_up @ no, assume UP + + orr r6, r6, #0x0000ff00 + orr r6, r6, #0x000000f0 @ mask 0xff07fff0 + orr r7, r7, #0x0000b000 + orr r7, r7, #0x00000020 @ val 0x4107b020 + and r0, r9, r6 + teq r0, r7 @ ARM 11MPCore? + moveq pc, lr @ yes, assume SMP + + mrc p15, 0, r0, c0, c0, 5 @ read MPIDR + tst r0, #1 << 31 + movne pc, lr @ bit 31 => SMP + +__fixup_smp_on_up: + adr r0, 1f + ldmia r0, {r3, r6, r7} + sub r3, r0, r3 + add r6, r6, r3 + add r7, r7, r3 +2: cmp r6, r7 + ldmia r6!, {r0, r4} + strlo r4, [r0, r3] + blo 2b + mov pc, lr +ENDPROC(__fixup_smp) + +1: .word . + .word __smpalt_begin + .word __smpalt_end + + .pushsection .data + .globl smp_on_up +smp_on_up: + ALT_SMP(.long 1) + ALT_UP(.long 0) + .popsection + +#endif + #include "head-common.S" -- cgit v1.2.3-70-g09d2 From a4ae41341fd39af6e25ec9861a6a4dc0c5c58b16 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 4 Oct 2010 16:22:34 +0100 Subject: ARM: cleanup boot cpu calling __mmap_switched This allows us to relocate __mmap_switched and associated data away from the head section. Signed-off-by: Russell King --- arch/arm/kernel/head-common.S | 3 +-- arch/arm/kernel/head.S | 3 ++- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/kernel/head.S') diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 6ad24d2cb14..9f473ef2a64 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -18,7 +18,6 @@ .align 2 .type __switch_data, %object __switch_data: - .long __mmap_switched .long __data_loc @ r4 .long _data @ r5 .long __bss_start @ r6 @@ -39,7 +38,7 @@ __switch_data: * r9 = processor ID */ __mmap_switched: - adr r3, __switch_data + 4 + adr r3, __switch_data ldmia r3!, {r4, r5, r6, r7} cmp r4, r5 @ Copy data segment if needed diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index eb62bf94721..aa6ab9d8646 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -95,13 +95,14 @@ ENTRY(stext) * above. On return, the CPU will be ready for the MMU to be * turned on, and r0 will hold the CPU control register value. */ - ldr r13, __switch_data @ address to jump to after + ldr r13, =__mmap_switched @ address to jump to after @ mmu has been enabled adr lr, BSYM(__enable_mmu) @ return (PIC) address ARM( add pc, r10, #PROCINFO_INITFUNC ) THUMB( add r12, r10, #PROCINFO_INITFUNC ) THUMB( mov pc, r12 ) ENDPROC(stext) + .ltorg #if defined(CONFIG_SMP) ENTRY(secondary_startup) -- cgit v1.2.3-70-g09d2 From 786f1b73f7d5cad5c88dc75a96d53a74160aa7d7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 4 Oct 2010 17:51:54 +0100 Subject: ARM: hotplug cpu: ensure that __enable_mmu is identity mapped __enable_mmu is required to be executed in an identity mapped region to ensure that variances in CPUs do not cause a crash. We currently achieve this by assuming that it will be co-located with __create_page_tables. With hotplug CPU support, this assumption becomes invalid. Implement a better solution which ensures that it will be appropriately mapped no matter where it is placed. Signed-off-by: Russell King --- arch/arm/kernel/head.S | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) (limited to 'arch/arm/kernel/head.S') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index aa6ab9d8646..17414e29948 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -201,6 +201,7 @@ __turn_mmu_on: mov r3, r3 mov r3, r13 mov pc, r3 +__enable_mmu_end: ENDPROC(__turn_mmu_on) @@ -214,7 +215,7 @@ ENDPROC(__turn_mmu_on) * r10 = procinfo * * Returns: - * r0, r3, r6, r7 corrupted + * r0, r3, r5-r7 corrupted * r4 = physical page table address */ __create_page_tables: @@ -236,20 +237,30 @@ __create_page_tables: ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags /* - * Create identity mapping for first MB of kernel to - * cater for the MMU enable. This identity mapping - * will be removed by paging_init(). We use our current program - * counter to determine corresponding section base address. + * Create identity mapping to cater for __enable_mmu. + * This identity mapping will be removed by paging_init(). */ - mov r6, pc - mov r6, r6, lsr #20 @ start of kernel section - orr r3, r7, r6, lsl #20 @ flags + kernel base - str r3, [r4, r6, lsl #2] @ identity mapping + adr r0, __enable_mmu_loc + ldmia r0, {r3, r5, r6} + sub r0, r0, r3 @ virt->phys offset + add r5, r5, r0 @ phys __enable_mmu + add r6, r6, r0 @ phys __enable_mmu_end + mov r5, r5, lsr #20 + mov r6, r6, lsr #20 + +1: orr r3, r7, r5, lsl #20 @ flags + kernel base + str r3, [r4, r5, lsl #2] @ identity mapping + teq r5, r6 + addne r5, r5, #1 @ next section + bne 1b /* * Now setup the pagetables for our kernel direct * mapped region. */ + mov r3, pc + mov r3, r3, lsr #20 + orr r3, r7, r3, lsl #20 add r0, r4, #(KERNEL_START & 0xff000000) >> 18 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! ldr r6, =(KERNEL_END - 1) @@ -333,5 +344,9 @@ __create_page_tables: mov pc, lr ENDPROC(__create_page_tables) .ltorg +__enable_mmu_loc: + .long . + .long __enable_mmu + .long __enable_mmu_end #include "head-common.S" -- cgit v1.2.3-70-g09d2 From 00945010c063b95e813b966f44bf58ffa1955a38 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 4 Oct 2010 17:56:13 +0100 Subject: ARM: hotplug cpu: move secondary_startup, __enable_mmu to cpuinit Move these two functions, both of which are required for secondary CPU booting, into the cpuinit section. Ensure bad processors call __error_p for better diagnostics, rather than just __error. Signed-off-by: Russell King --- arch/arm/kernel/head.S | 206 +++++++++++++++++++++++++------------------------ 1 file changed, 104 insertions(+), 102 deletions(-) (limited to 'arch/arm/kernel/head.S') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 17414e29948..ed9ebe59178 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -97,114 +97,14 @@ ENTRY(stext) */ ldr r13, =__mmap_switched @ address to jump to after @ mmu has been enabled - adr lr, BSYM(__enable_mmu) @ return (PIC) address + adr lr, BSYM(1f) @ return (PIC) address ARM( add pc, r10, #PROCINFO_INITFUNC ) THUMB( add r12, r10, #PROCINFO_INITFUNC ) THUMB( mov pc, r12 ) +1: b __enable_mmu ENDPROC(stext) .ltorg -#if defined(CONFIG_SMP) -ENTRY(secondary_startup) - /* - * Common entry point for secondary CPUs. - * - * Ensure that we're in SVC mode, and IRQs are disabled. Lookup - * the processor type - there is no need to check the machine type - * as it has already been validated by the primary processor. - */ - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 - mrc p15, 0, r9, c0, c0 @ get processor id - bl __lookup_processor_type - movs r10, r5 @ invalid processor? - moveq r0, #'p' @ yes, error 'p' - beq __error - - /* - * Use the page tables supplied from __cpu_up. - */ - adr r4, __secondary_data - ldmia r4, {r5, r7, r12} @ address to jump to after - sub r4, r4, r5 @ mmu has been enabled - ldr r4, [r7, r4] @ get secondary_data.pgdir - adr lr, BSYM(__enable_mmu) @ return address - mov r13, r12 @ __secondary_switched address - ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor - @ (return control reg) - THUMB( add r12, r10, #PROCINFO_INITFUNC ) - THUMB( mov pc, r12 ) -ENDPROC(secondary_startup) - - /* - * r6 = &secondary_data - */ -ENTRY(__secondary_switched) - ldr sp, [r7, #4] @ get secondary_data.stack - mov fp, #0 - b secondary_start_kernel -ENDPROC(__secondary_switched) - - .type __secondary_data, %object -__secondary_data: - .long . - .long secondary_data - .long __secondary_switched -#endif /* defined(CONFIG_SMP) */ - - - -/* - * Setup common bits before finally enabling the MMU. Essentially - * this is just loading the page table pointer and domain access - * registers. - */ -__enable_mmu: -#ifdef CONFIG_ALIGNMENT_TRAP - orr r0, r0, #CR_A -#else - bic r0, r0, #CR_A -#endif -#ifdef CONFIG_CPU_DCACHE_DISABLE - bic r0, r0, #CR_C -#endif -#ifdef CONFIG_CPU_BPREDICT_DISABLE - bic r0, r0, #CR_Z -#endif -#ifdef CONFIG_CPU_ICACHE_DISABLE - bic r0, r0, #CR_I -#endif - mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_IO, DOMAIN_CLIENT)) - mcr p15, 0, r5, c3, c0, 0 @ load domain access register - mcr p15, 0, r4, c2, c0, 0 @ load page table pointer - b __turn_mmu_on -ENDPROC(__enable_mmu) - -/* - * Enable the MMU. This completely changes the structure of the visible - * memory space. You will not be able to trace execution through this. - * If you have an enquiry about this, *please* check the linux-arm-kernel - * mailing list archives BEFORE sending another post to the list. - * - * r0 = cp#15 control register - * r13 = *virtual* address to jump to upon completion - * - * other registers depend on the function called upon completion - */ - .align 5 -__turn_mmu_on: - mov r0, r0 - mcr p15, 0, r0, c1, c0, 0 @ write control reg - mrc p15, 0, r3, c0, c0, 0 @ read id reg - mov r3, r3 - mov r3, r13 - mov pc, r3 -__enable_mmu_end: -ENDPROC(__turn_mmu_on) - - /* * Setup the initial page tables. We only setup the barest * amount which are required to get the kernel running, which @@ -349,4 +249,106 @@ __enable_mmu_loc: .long __enable_mmu .long __enable_mmu_end +#if defined(CONFIG_SMP) + __CPUINIT +ENTRY(secondary_startup) + /* + * Common entry point for secondary CPUs. + * + * Ensure that we're in SVC mode, and IRQs are disabled. Lookup + * the processor type - there is no need to check the machine type + * as it has already been validated by the primary processor. + */ + setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 + mrc p15, 0, r9, c0, c0 @ get processor id + bl __lookup_processor_type + movs r10, r5 @ invalid processor? + moveq r0, #'p' @ yes, error 'p' + beq __error_p + + /* + * Use the page tables supplied from __cpu_up. + */ + adr r4, __secondary_data + ldmia r4, {r5, r7, r12} @ address to jump to after + sub r4, r4, r5 @ mmu has been enabled + ldr r4, [r7, r4] @ get secondary_data.pgdir + adr lr, BSYM(__enable_mmu) @ return address + mov r13, r12 @ __secondary_switched address + ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor + @ (return control reg) + THUMB( add r12, r10, #PROCINFO_INITFUNC ) + THUMB( mov pc, r12 ) +ENDPROC(secondary_startup) + + /* + * r6 = &secondary_data + */ +ENTRY(__secondary_switched) + ldr sp, [r7, #4] @ get secondary_data.stack + mov fp, #0 + b secondary_start_kernel +ENDPROC(__secondary_switched) + + .type __secondary_data, %object +__secondary_data: + .long . + .long secondary_data + .long __secondary_switched +#endif /* defined(CONFIG_SMP) */ + + + +/* + * Setup common bits before finally enabling the MMU. Essentially + * this is just loading the page table pointer and domain access + * registers. + */ +__enable_mmu: +#ifdef CONFIG_ALIGNMENT_TRAP + orr r0, r0, #CR_A +#else + bic r0, r0, #CR_A +#endif +#ifdef CONFIG_CPU_DCACHE_DISABLE + bic r0, r0, #CR_C +#endif +#ifdef CONFIG_CPU_BPREDICT_DISABLE + bic r0, r0, #CR_Z +#endif +#ifdef CONFIG_CPU_ICACHE_DISABLE + bic r0, r0, #CR_I +#endif + mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ + domain_val(DOMAIN_IO, DOMAIN_CLIENT)) + mcr p15, 0, r5, c3, c0, 0 @ load domain access register + mcr p15, 0, r4, c2, c0, 0 @ load page table pointer + b __turn_mmu_on +ENDPROC(__enable_mmu) + +/* + * Enable the MMU. This completely changes the structure of the visible + * memory space. You will not be able to trace execution through this. + * If you have an enquiry about this, *please* check the linux-arm-kernel + * mailing list archives BEFORE sending another post to the list. + * + * r0 = cp#15 control register + * r13 = *virtual* address to jump to upon completion + * + * other registers depend on the function called upon completion + */ + .align 5 +__turn_mmu_on: + mov r0, r0 + mcr p15, 0, r0, c1, c0, 0 @ write control reg + mrc p15, 0, r3, c0, c0, 0 @ read id reg + mov r3, r3 + mov r3, r13 + mov pc, r3 +__enable_mmu_end: +ENDPROC(__turn_mmu_on) + + #include "head-common.S" -- cgit v1.2.3-70-g09d2 From 865a4fae7793b80e2b8bca76e279d6dfecbeac17 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 4 Oct 2010 18:02:59 +0100 Subject: ARM: add register documentation for __enable_mmu Add some additional documentation on register usage in __enable_mmu to help complete the overall picture. Signed-off-by: Russell King --- arch/arm/kernel/head.S | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/kernel/head.S') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index ed9ebe59178..c11dd14afc1 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -303,6 +303,13 @@ __secondary_data: * Setup common bits before finally enabling the MMU. Essentially * this is just loading the page table pointer and domain access * registers. + * + * r0 = cp#15 control register + * r1 = machine ID + * r2 = atags pointer + * r4 = page table pointer + * r9 = processor ID + * r13 = *virtual* address to jump to upon completion */ __enable_mmu: #ifdef CONFIG_ALIGNMENT_TRAP @@ -335,6 +342,9 @@ ENDPROC(__enable_mmu) * mailing list archives BEFORE sending another post to the list. * * r0 = cp#15 control register + * r1 = machine ID + * r2 = atags pointer + * r9 = processor ID * r13 = *virtual* address to jump to upon completion * * other registers depend on the function called upon completion -- cgit v1.2.3-70-g09d2 From c293393faa8e11a5a80a9e358718432b8697f451 Mon Sep 17 00:00:00 2001 From: Jeremy Kerr Date: Wed, 7 Jul 2010 11:19:48 +0800 Subject: arm: use addruart macro to establish debug mappings Since we can get both physical and virtual addresses from the addruart macro, we can use this to establish the debug mappings. In the case of CONFIG_DEBUG_ICEDCC, we don't need any mappings, but may still need to setup r7 correctly. Incorporating ASM changes from Nicolas Pitre . Signed-off-by: Jeremy Kerr Tested-by: Kevin Hilman --- arch/arm/kernel/head.S | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) (limited to 'arch/arm/kernel/head.S') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 767390449e0..dd6b369ac69 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -22,6 +22,10 @@ #include #include +#ifdef CONFIG_DEBUG_LL +#include +#endif + #if (PHYS_OFFSET & 0x001fffff) #error "PHYS_OFFSET must be at an even 2MiB boundary!" #endif @@ -204,24 +208,35 @@ __create_page_tables: str r6, [r0] #ifdef CONFIG_DEBUG_LL - ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags +#ifndef CONFIG_DEBUG_ICEDCC /* * Map in IO space for serial debugging. * This allows debug messages to be output * via a serial console before paging_init. */ - ldr r3, [r8, #MACHINFO_PGOFFIO] + addruart r7, r3 + + mov r3, r3, lsr #20 + mov r3, r3, lsl #2 + add r0, r4, r3 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) cmp r3, #0x0800 @ limit to 512MB movhi r3, #0x0800 add r6, r0, r3 - ldr r3, [r8, #MACHINFO_PHYSIO] - orr r3, r3, r7 + mov r3, r7, lsr #20 + ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags + orr r3, r7, r3, lsl #20 1: str r3, [r0], #4 add r3, r3, #1 << 20 teq r0, r6 bne 1b + +#else /* CONFIG_DEBUG_ICEDCC */ + /* we don't need any serial debugging mappings for ICEDCC */ + ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags +#endif /* !CONFIG_DEBUG_ICEDCC */ + #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) /* * If we're using the NetWinder or CATS, we also need to map -- cgit v1.2.3-70-g09d2