From e7eccc7e16acfcc3e613e7c0df7e62528d24581c Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Thu, 13 Jun 2013 19:50:56 +0800 Subject: ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresd WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx6q.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-imx/clk-imx6q.c') diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 930a1a589c6..4282e99f5ca 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -550,6 +550,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); clk_register_clkdev(clk[arm], NULL, "cpu0"); + clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); + clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); -- cgit v1.2.3-70-g09d2