From 5cfe82c674c77c21274769643c0b92dd7bb4cb05 Mon Sep 17 00:00:00 2001 From: Benoît Thébaudeau Date: Thu, 28 Jun 2012 16:59:23 +0200 Subject: ARM: imx: make ehci power/oc polarities configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make ehci power and overcurrent polarities configurable. If not set, these new configurartions keep the default register values so that existing board files do not have to be changed. Cc: Sascha Hauer Cc: Signed-off-by: Benoît Thébaudeau Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/ehci-imx5.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx/ehci-imx5.c') diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c index c17fa131728..49e3b342758 100644 --- a/arch/arm/mach-imx/ehci-imx5.c +++ b/arch/arm/mach-imx/ehci-imx5.c @@ -28,11 +28,14 @@ #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ +#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ /* USB_PHY_CTRL_FUNC */ +#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ +#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ +#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ /* USBH2CTRL */ #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) @@ -80,6 +83,10 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_OTG_PHYCTRL_OC_POL_BIT; + else + v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) { /* OC/USBPWR is not used */ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; @@ -87,6 +94,10 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) /* OC/USBPWR is used */ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; } + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; + else + v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); @@ -119,6 +130,10 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_H1_OC_POL_BIT; + else + v &= ~MXC_H1_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ else -- cgit v1.2.3-70-g09d2 From 0b87c1d4be230d109effe8aef78728160800e67f Mon Sep 17 00:00:00 2001 From: Benoît Thébaudeau Date: Thu, 28 Jun 2012 16:59:46 +0200 Subject: ARM: imx: fix mx51 ehci setup errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch completes commit 08406f5 by fixing the following issues, according to the reference manual: * MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like H1PM and H2PM, not the opposite. * MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like H1_OC_DIS, not the opposite. * Typos in comments. Cc: Sascha Hauer Cc: Arnaud Patard (Rtp) Cc: Signed-off-by: Benoît Thébaudeau Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/ehci-imx5.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-imx/ehci-imx5.c') diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c index 49e3b342758..a6a4afb0ad6 100644 --- a/arch/arm/mach-imx/ehci-imx5.c +++ b/arch/arm/mach-imx/ehci-imx5.c @@ -88,11 +88,11 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) else v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) { - /* OC/USBPWR is not used */ - v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; - } else { /* OC/USBPWR is used */ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; + } else { + /* OC/USBPWR is not used */ + v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; } if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; @@ -106,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) else v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v |= MXC_OTG_UCTRL_OPM_BIT; - else v &= ~MXC_OTG_UCTRL_OPM_BIT; + else + v |= MXC_OTG_UCTRL_OPM_BIT; __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; @@ -124,7 +124,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) } if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/ else v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); @@ -157,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) } if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/ else v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); -- cgit v1.2.3-70-g09d2