From e0557c0d1a3a9c38af6777d308f98da12c94e137 Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawn.guo@linaro.org>
Date: Thu, 13 Sep 2012 15:51:15 +0800
Subject: ARM: imx: move platform device code into mach-imx
It moves platform device code from plat-mxc into mach-imx. Along with
that, header devices-common.h gets moved from plat-mxc/include/mach/
into mach-imx/devices/.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-imx/pm-imx3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm/mach-imx/pm-imx3.c')
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
index 822103bdb70..884dc9453d3 100644
--- a/arch/arm/mach-imx/pm-imx3.c
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -11,8 +11,8 @@
#include <linux/io.h>
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/devices-common.h>
#include "crmregs-imx3.h"
+#include "devices/devices-common.h"
/*
* Set cpu low power mode before WFI instruction. This function is called
--
cgit v1.2.3-70-g09d2
From e3372474cfa0dc016f10ec47baddbd1ed0abecf3 Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawn.guo@linaro.org>
Date: Thu, 13 Sep 2012 21:01:00 +0800
Subject: ARM: imx: include common.h rather than mach/common.h
Rename mach-imx/include/mach/common.h to mach-imx/common.h and update
all users to include common.h rather than mach/common.h.
It also removes an unneeded inclusion to common.h in
mach-imx/devices/devices.c.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-imx/avic.c | 2 +-
arch/arm/mach-imx/clk-imx1.c | 3 +-
arch/arm/mach-imx/clk-imx21.c | 3 +-
arch/arm/mach-imx/clk-imx25.c | 3 +-
arch/arm/mach-imx/clk-imx27.c | 3 +-
arch/arm/mach-imx/clk-imx31.c | 2 +-
arch/arm/mach-imx/clk-imx35.c | 2 +-
arch/arm/mach-imx/clk-imx51-imx53.c | 2 +-
arch/arm/mach-imx/clk-imx6q.c | 3 +-
arch/arm/mach-imx/clk-pllv1.c | 2 +-
arch/arm/mach-imx/common.h | 162 +++++++++++++++++++++++++
arch/arm/mach-imx/cpu-imx31.c | 3 +-
arch/arm/mach-imx/devices/devices.c | 1 -
arch/arm/mach-imx/epit.c | 3 +-
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 2 +-
arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c | 2 +-
arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 2 +-
arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c | 2 +-
arch/arm/mach-imx/hotplug.c | 3 +-
arch/arm/mach-imx/imx27-dt.c | 3 +-
arch/arm/mach-imx/imx31-dt.c | 3 +-
arch/arm/mach-imx/imx51-dt.c | 3 +-
arch/arm/mach-imx/include/mach/common.h | 162 -------------------------
arch/arm/mach-imx/mach-apf9328.c | 2 +-
arch/arm/mach-imx/mach-armadillo5x0.c | 2 +-
arch/arm/mach-imx/mach-bug.c | 2 +-
arch/arm/mach-imx/mach-cpuimx27.c | 2 +-
arch/arm/mach-imx/mach-cpuimx35.c | 2 +-
arch/arm/mach-imx/mach-cpuimx51sd.c | 2 +-
arch/arm/mach-imx/mach-eukrea_cpuimx25.c | 2 +-
arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 2 +-
arch/arm/mach-imx/mach-imx27ipcam.c | 2 +-
arch/arm/mach-imx/mach-imx27lite.c | 2 +-
arch/arm/mach-imx/mach-imx53.c | 3 +-
arch/arm/mach-imx/mach-imx6q.c | 2 +-
arch/arm/mach-imx/mach-kzm_arm11_01.c | 2 +-
arch/arm/mach-imx/mach-mx1ads.c | 2 +-
arch/arm/mach-imx/mach-mx21ads.c | 2 +-
arch/arm/mach-imx/mach-mx25_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx27_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx27ads.c | 2 +-
arch/arm/mach-imx/mach-mx31_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx31ads.c | 2 +-
arch/arm/mach-imx/mach-mx31lilly.c | 2 +-
arch/arm/mach-imx/mach-mx31lite.c | 2 +-
arch/arm/mach-imx/mach-mx31moboard.c | 2 +-
arch/arm/mach-imx/mach-mx35_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx50_rdp.c | 2 +-
arch/arm/mach-imx/mach-mx51_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx51_babbage.c | 2 +-
arch/arm/mach-imx/mach-mxt_td60.c | 2 +-
arch/arm/mach-imx/mach-pca100.c | 2 +-
arch/arm/mach-imx/mach-pcm037.c | 2 +-
arch/arm/mach-imx/mach-pcm037_eet.c | 3 +-
arch/arm/mach-imx/mach-pcm038.c | 2 +-
arch/arm/mach-imx/mach-pcm043.c | 2 +-
arch/arm/mach-imx/mach-qong.c | 2 +-
arch/arm/mach-imx/mach-scb9328.c | 2 +-
arch/arm/mach-imx/mach-vpr200.c | 2 +-
arch/arm/mach-imx/mm-imx1.c | 2 +-
arch/arm/mach-imx/mm-imx21.c | 2 +-
arch/arm/mach-imx/mm-imx25.c | 2 +-
arch/arm/mach-imx/mm-imx27.c | 2 +-
arch/arm/mach-imx/mm-imx3.c | 2 +-
arch/arm/mach-imx/mm-imx5.c | 2 +-
arch/arm/mach-imx/mx31lilly-db.c | 2 +-
arch/arm/mach-imx/mx31lite-db.c | 2 +-
arch/arm/mach-imx/mx31moboard-devboard.c | 2 +-
arch/arm/mach-imx/mx31moboard-marxbot.c | 2 +-
arch/arm/mach-imx/mx31moboard-smartbot.c | 2 +-
arch/arm/mach-imx/pcm970-baseboard.c | 2 +-
arch/arm/mach-imx/platsmp.c | 3 +-
arch/arm/mach-imx/pm-imx3.c | 3 +-
arch/arm/mach-imx/pm-imx5.c | 3 +-
arch/arm/mach-imx/pm-imx6q.c | 3 +-
arch/arm/mach-imx/system.c | 3 +-
arch/arm/mach-imx/time.c | 3 +-
arch/arm/mach-imx/tzic.c | 2 +-
78 files changed, 255 insertions(+), 239 deletions(-)
create mode 100644 arch/arm/mach-imx/common.h
delete mode 100644 arch/arm/mach-imx/include/mach/common.h
(limited to 'arch/arm/mach-imx/pm-imx3.c')
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index cbd55c36def..204fd94c57d 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -22,12 +22,12 @@
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
-#include <mach/common.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
+#include "common.h"
#include "irq-common.h"
#define AVIC_INTCNTL 0x00 /* int control reg */
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 516ddee1948..b5f90cc9e37 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -23,8 +23,9 @@
#include <linux/err.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+
#include "clk.h"
+#include "common.h"
/* CCM register addresses */
#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index cf65148bc51..fbee6a4b1de 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -26,8 +26,9 @@
#include <linux/err.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+
#include "clk.h"
+#include "common.h"
#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index d20d4795f4e..08a143a19e6 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -25,9 +25,10 @@
#include <linux/err.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <mach/mx25.h>
+
#include "clk.h"
+#include "common.h"
#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 3b6b640eed2..31010cb93c6 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -6,9 +6,10 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+
#include "clk.h"
+#include "common.h"
#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 1253af2d997..a4c298acd04 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -24,9 +24,9 @@
#include <mach/hardware.h>
#include <mach/mx31.h>
-#include <mach/common.h>
#include "clk.h"
+#include "common.h"
#include "crmregs-imx3.h"
static const char *mcu_main_sel[] = { "spll", "mpll", };
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 177259b523c..ba26bf3ee93 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -15,10 +15,10 @@
#include <linux/err.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include "crmregs-imx3.h"
#include "clk.h"
+#include "common.h"
struct arm_ahb_div {
unsigned char arm, ahb, sel;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a0bf84803ea..024587cee62 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -15,10 +15,10 @@
#include <linux/err.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include "crm-regs-imx5.h"
#include "clk.h"
+#include "common.h"
/* Low-power Audio Playback Mode clock */
static const char *lp_apm_sel[] = { "osc", };
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 3ec242f3341..e5a82bb95b5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -19,8 +19,9 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <mach/common.h>
+
#include "clk.h"
+#include "common.h"
#define CCGR0 0x68
#define CCGR1 0x6c
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 02be7317891..02f9013d499 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -4,10 +4,10 @@
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/err.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include "clk.h"
+#include "common.h"
/**
* pll v1
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
new file mode 100644
index 00000000000..ead901814c0
--- /dev/null
+++ b/arch/arm/mach-imx/common.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_COMMON_H__
+#define __ASM_ARCH_MXC_COMMON_H__
+
+struct platform_device;
+struct clk;
+enum mxc_cpu_pwr_mode;
+
+extern void mx1_map_io(void);
+extern void mx21_map_io(void);
+extern void mx25_map_io(void);
+extern void mx27_map_io(void);
+extern void mx31_map_io(void);
+extern void mx35_map_io(void);
+extern void mx50_map_io(void);
+extern void mx51_map_io(void);
+extern void mx53_map_io(void);
+extern void imx1_init_early(void);
+extern void imx21_init_early(void);
+extern void imx25_init_early(void);
+extern void imx27_init_early(void);
+extern void imx31_init_early(void);
+extern void imx35_init_early(void);
+extern void imx50_init_early(void);
+extern void imx51_init_early(void);
+extern void imx53_init_early(void);
+extern void mxc_init_irq(void __iomem *);
+extern void tzic_init_irq(void __iomem *);
+extern void mx1_init_irq(void);
+extern void mx21_init_irq(void);
+extern void mx25_init_irq(void);
+extern void mx27_init_irq(void);
+extern void mx31_init_irq(void);
+extern void mx35_init_irq(void);
+extern void mx50_init_irq(void);
+extern void mx51_init_irq(void);
+extern void mx53_init_irq(void);
+extern void imx1_soc_init(void);
+extern void imx21_soc_init(void);
+extern void imx25_soc_init(void);
+extern void imx27_soc_init(void);
+extern void imx31_soc_init(void);
+extern void imx35_soc_init(void);
+extern void imx50_soc_init(void);
+extern void imx51_soc_init(void);
+extern void imx51_init_late(void);
+extern void imx53_init_late(void);
+extern void epit_timer_init(void __iomem *base, int irq);
+extern void mxc_timer_init(void __iomem *, int);
+extern int mx1_clocks_init(unsigned long fref);
+extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
+extern int mx25_clocks_init(void);
+extern int mx27_clocks_init(unsigned long fref);
+extern int mx31_clocks_init(unsigned long fref);
+extern int mx35_clocks_init(void);
+extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
+ unsigned long ckih1, unsigned long ckih2);
+extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
+ unsigned long ckih1, unsigned long ckih2);
+extern int mx27_clocks_init_dt(void);
+extern int mx31_clocks_init_dt(void);
+extern int mx51_clocks_init_dt(void);
+extern int mx53_clocks_init_dt(void);
+extern int mx6q_clocks_init(void);
+extern struct platform_device *mxc_register_gpio(char *name, int id,
+ resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
+extern void mxc_set_cpu_type(unsigned int type);
+extern void mxc_restart(char, const char *);
+extern void mxc_arch_reset_init(void __iomem *);
+extern int mx53_revision(void);
+extern int mx53_display_revision(void);
+extern void imx_set_aips(void __iomem *);
+
+enum mxc_cpu_pwr_mode {
+ WAIT_CLOCKED, /* wfi only */
+ WAIT_UNCLOCKED, /* WAIT */
+ WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
+ STOP_POWER_ON, /* just STOP */
+ STOP_POWER_OFF, /* STOP + SRPG */
+};
+
+enum mx3_cpu_pwr_mode {
+ MX3_RUN,
+ MX3_WAIT,
+ MX3_DOZE,
+ MX3_SLEEP,
+};
+
+extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
+extern void imx_print_silicon_rev(const char *cpu, int srev);
+
+void avic_handle_irq(struct pt_regs *);
+void tzic_handle_irq(struct pt_regs *);
+
+#define imx1_handle_irq avic_handle_irq
+#define imx21_handle_irq avic_handle_irq
+#define imx25_handle_irq avic_handle_irq
+#define imx27_handle_irq avic_handle_irq
+#define imx31_handle_irq avic_handle_irq
+#define imx35_handle_irq avic_handle_irq
+#define imx50_handle_irq tzic_handle_irq
+#define imx51_handle_irq tzic_handle_irq
+#define imx53_handle_irq tzic_handle_irq
+#define imx6q_handle_irq gic_handle_irq
+
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+#ifdef CONFIG_DEBUG_LL
+extern void imx_lluart_map_io(void);
+#else
+static inline void imx_lluart_map_io(void) {}
+#endif
+extern void v7_cpu_resume(void);
+extern u32 *pl310_get_save_ptr(void);
+#ifdef CONFIG_SMP
+extern void v7_secondary_startup(void);
+extern void imx_scu_map_io(void);
+extern void imx_smp_prepare(void);
+#else
+static inline void imx_scu_map_io(void) {}
+static inline void imx_smp_prepare(void) {}
+#endif
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+extern void imx_src_init(void);
+extern void imx_src_prepare_restart(void);
+extern void imx_gpc_init(void);
+extern void imx_gpc_pre_suspend(void);
+extern void imx_gpc_post_resume(void);
+extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+extern void imx6q_clock_map_io(void);
+
+extern void imx_cpu_die(unsigned int cpu);
+
+#ifdef CONFIG_PM
+extern void imx6q_pm_init(void);
+extern void imx51_pm_init(void);
+extern void imx53_pm_init(void);
+#else
+static inline void imx6q_pm_init(void) {}
+static inline void imx51_pm_init(void) {}
+static inline void imx53_pm_init(void) {}
+#endif
+
+#ifdef CONFIG_NEON
+extern int mx51_neon_fixup(void);
+#else
+static inline int mx51_neon_fixup(void) { return 0; }
+#endif
+
+extern struct smp_operations imx_smp_ops;
+
+#endif
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index 3f2345f0cda..9d3a91c96a5 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -13,7 +13,8 @@
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/iim.h>
-#include <mach/common.h>
+
+#include "common.h"
static int mx31_cpu_rev = -1;
diff --git a/arch/arm/mach-imx/devices/devices.c b/arch/arm/mach-imx/devices/devices.c
index 4d55a7a26e9..9301e07b612 100644
--- a/arch/arm/mach-imx/devices/devices.c
+++ b/arch/arm/mach-imx/devices/devices.c
@@ -21,7 +21,6 @@
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
-#include <mach/common.h>
struct device mxc_aips_bus = {
.init_name = "mxc_aips",
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
index 88726f4dbbf..76720f528b1 100644
--- a/arch/arm/mach-imx/epit.c
+++ b/arch/arm/mach-imx/epit.c
@@ -54,7 +54,8 @@
#include <mach/hardware.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
+
+#include "common.h"
static struct clock_event_device clockevent_epit;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index ad4ee83e898..27b55702bda 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -29,9 +29,9 @@
#include <asm/mach/arch.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 19d7fa63c8e..34e46dcfb6d 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -27,11 +27,11 @@
#include <video/platform_lcd.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/mx25.h>
+#include "common.h"
#include "devices-imx25.h"
#include "iomux-mx25.h"
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index b5733217c2e..63a42f6f9c2 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -37,8 +37,8 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+#include "common.h"
#include "devices-imx35.h"
#include "iomux-mx35.h"
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
index 4c7e33d44a1..f1cf5219300 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
@@ -37,8 +37,8 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+#include "common.h"
#include "devices-imx51.h"
#include "iomux-mx51.h"
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index b07b778dc9a..3dec962b077 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -13,7 +13,8 @@
#include <linux/errno.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
-#include <mach/common.h>
+
+#include "common.h"
static inline void cpu_enter_lowpower(void)
{
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index e80d5235dac..83c56fb46aa 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -14,9 +14,10 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/mx27.h>
+#include "common.h"
+
static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index a68ba207b2b..408afcc91f0 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -14,9 +14,10 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/mx31.h>
+#include "common.h"
+
static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
"imx21-uart.0", NULL),
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index f233b4bb234..e105f12f1e6 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -15,9 +15,10 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/mx51.h>
+#include "common.h"
+
/*
* Lookup table for attaching a specific name and platform_data pointer to
* devices as they get created by of_platform_populate(). Ideally this table
diff --git a/arch/arm/mach-imx/include/mach/common.h b/arch/arm/mach-imx/include/mach/common.h
deleted file mode 100644
index ead901814c0..00000000000
--- a/arch/arm/mach-imx/include/mach/common.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_COMMON_H__
-#define __ASM_ARCH_MXC_COMMON_H__
-
-struct platform_device;
-struct clk;
-enum mxc_cpu_pwr_mode;
-
-extern void mx1_map_io(void);
-extern void mx21_map_io(void);
-extern void mx25_map_io(void);
-extern void mx27_map_io(void);
-extern void mx31_map_io(void);
-extern void mx35_map_io(void);
-extern void mx50_map_io(void);
-extern void mx51_map_io(void);
-extern void mx53_map_io(void);
-extern void imx1_init_early(void);
-extern void imx21_init_early(void);
-extern void imx25_init_early(void);
-extern void imx27_init_early(void);
-extern void imx31_init_early(void);
-extern void imx35_init_early(void);
-extern void imx50_init_early(void);
-extern void imx51_init_early(void);
-extern void imx53_init_early(void);
-extern void mxc_init_irq(void __iomem *);
-extern void tzic_init_irq(void __iomem *);
-extern void mx1_init_irq(void);
-extern void mx21_init_irq(void);
-extern void mx25_init_irq(void);
-extern void mx27_init_irq(void);
-extern void mx31_init_irq(void);
-extern void mx35_init_irq(void);
-extern void mx50_init_irq(void);
-extern void mx51_init_irq(void);
-extern void mx53_init_irq(void);
-extern void imx1_soc_init(void);
-extern void imx21_soc_init(void);
-extern void imx25_soc_init(void);
-extern void imx27_soc_init(void);
-extern void imx31_soc_init(void);
-extern void imx35_soc_init(void);
-extern void imx50_soc_init(void);
-extern void imx51_soc_init(void);
-extern void imx51_init_late(void);
-extern void imx53_init_late(void);
-extern void epit_timer_init(void __iomem *base, int irq);
-extern void mxc_timer_init(void __iomem *, int);
-extern int mx1_clocks_init(unsigned long fref);
-extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
-extern int mx25_clocks_init(void);
-extern int mx27_clocks_init(unsigned long fref);
-extern int mx31_clocks_init(unsigned long fref);
-extern int mx35_clocks_init(void);
-extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
- unsigned long ckih1, unsigned long ckih2);
-extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
- unsigned long ckih1, unsigned long ckih2);
-extern int mx27_clocks_init_dt(void);
-extern int mx31_clocks_init_dt(void);
-extern int mx51_clocks_init_dt(void);
-extern int mx53_clocks_init_dt(void);
-extern int mx6q_clocks_init(void);
-extern struct platform_device *mxc_register_gpio(char *name, int id,
- resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
-extern void mxc_set_cpu_type(unsigned int type);
-extern void mxc_restart(char, const char *);
-extern void mxc_arch_reset_init(void __iomem *);
-extern int mx53_revision(void);
-extern int mx53_display_revision(void);
-extern void imx_set_aips(void __iomem *);
-
-enum mxc_cpu_pwr_mode {
- WAIT_CLOCKED, /* wfi only */
- WAIT_UNCLOCKED, /* WAIT */
- WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
- STOP_POWER_ON, /* just STOP */
- STOP_POWER_OFF, /* STOP + SRPG */
-};
-
-enum mx3_cpu_pwr_mode {
- MX3_RUN,
- MX3_WAIT,
- MX3_DOZE,
- MX3_SLEEP,
-};
-
-extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
-extern void imx_print_silicon_rev(const char *cpu, int srev);
-
-void avic_handle_irq(struct pt_regs *);
-void tzic_handle_irq(struct pt_regs *);
-
-#define imx1_handle_irq avic_handle_irq
-#define imx21_handle_irq avic_handle_irq
-#define imx25_handle_irq avic_handle_irq
-#define imx27_handle_irq avic_handle_irq
-#define imx31_handle_irq avic_handle_irq
-#define imx35_handle_irq avic_handle_irq
-#define imx50_handle_irq tzic_handle_irq
-#define imx51_handle_irq tzic_handle_irq
-#define imx53_handle_irq tzic_handle_irq
-#define imx6q_handle_irq gic_handle_irq
-
-extern void imx_enable_cpu(int cpu, bool enable);
-extern void imx_set_cpu_jump(int cpu, void *jump_addr);
-#ifdef CONFIG_DEBUG_LL
-extern void imx_lluart_map_io(void);
-#else
-static inline void imx_lluart_map_io(void) {}
-#endif
-extern void v7_cpu_resume(void);
-extern u32 *pl310_get_save_ptr(void);
-#ifdef CONFIG_SMP
-extern void v7_secondary_startup(void);
-extern void imx_scu_map_io(void);
-extern void imx_smp_prepare(void);
-#else
-static inline void imx_scu_map_io(void) {}
-static inline void imx_smp_prepare(void) {}
-#endif
-extern void imx_enable_cpu(int cpu, bool enable);
-extern void imx_set_cpu_jump(int cpu, void *jump_addr);
-extern void imx_src_init(void);
-extern void imx_src_prepare_restart(void);
-extern void imx_gpc_init(void);
-extern void imx_gpc_pre_suspend(void);
-extern void imx_gpc_post_resume(void);
-extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-extern void imx6q_clock_map_io(void);
-
-extern void imx_cpu_die(unsigned int cpu);
-
-#ifdef CONFIG_PM
-extern void imx6q_pm_init(void);
-extern void imx51_pm_init(void);
-extern void imx53_pm_init(void);
-#else
-static inline void imx6q_pm_init(void) {}
-static inline void imx51_pm_init(void) {}
-static inline void imx53_pm_init(void) {}
-#endif
-
-#ifdef CONFIG_NEON
-extern int mx51_neon_fixup(void);
-#else
-static inline int mx51_neon_fixup(void) { return 0; }
-#endif
-
-extern struct smp_operations imx_smp_ops;
-
-#endif
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index b24f4b63c45..a0b4c3fd289 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -25,9 +25,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "devices-imx1.h"
#include "iomux-mx1.h"
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index d288b9afe1a..d05b63fbeef 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -48,9 +48,9 @@
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/ulpi.h>
+#include "common.h"
#include "devices-imx31.h"
#include "crmregs-imx3.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 55b71d12cae..b98e982918f 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -20,12 +20,12 @@
#include <linux/platform_device.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <asm/mach/time.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 0a05eabbf74..271528b1d9a 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -34,10 +34,10 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/ulpi.h>
+#include "common.h"
#include "devices-imx27.h"
#include "eukrea-baseboards.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 132243b2b70..86d4ac90ea6 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -38,8 +38,8 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+#include "common.h"
#include "devices-imx35.h"
#include "eukrea-baseboards.h"
#include "iomux-mx35.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 3c2ceeddcd8..58ad093d059 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -26,7 +26,6 @@
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/setup.h>
@@ -34,6 +33,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
+#include "common.h"
#include "devices-imx51.h"
#include "cpu_op-mx51.h"
#include "eukrea-baseboards.h"
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 7dece3463a2..e754b0cbfd8 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -33,9 +33,9 @@
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/mx25.h>
+#include "common.h"
#include "devices-imx25.h"
#include "eukrea-baseboards.h"
#include "iomux-mx25.h"
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 64b2d5ad9ba..ec33607ebb6 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -40,9 +40,9 @@
#include <asm/mach/time.h>
#include <asm/system_info.h>
#include <asm/memblock.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 4e2dcd3c162..725a87fdf13 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -18,8 +18,8 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 49be646d613..ec460301103 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -21,8 +21,8 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 29711e95579..aaa90a781b3 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -19,9 +19,10 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/mx53.h>
+#include "common.h"
+
/*
* Lookup table for attaching a specific name and platform_data pointer to
* devices as they get created by of_platform_populate(). Ideally this table
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 47c91f7185d..85657610b4b 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -33,10 +33,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
-#include <mach/common.h>
#include <mach/cpuidle.h>
#include <mach/hardware.h>
+#include "common.h"
void imx6q_restart(char mode, const char *cmd)
{
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 050791677de..7b973dcba93 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,9 +36,9 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index e9e2401a62b..8be62f3559b 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -23,9 +23,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "devices-imx1.h"
#include "iomux-mx1.h"
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 0df370a4a0c..99adc9f893d 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -18,13 +18,13 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
+#include "common.h"
#include "devices-imx21.h"
#include "iomux-mx21.h"
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 4e741c57d3c..5a17dd66c05 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -37,9 +37,9 @@
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/mx25.h>
+#include "common.h"
#include "devices-imx25.h"
#include "iomux-mx25.h"
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 8a89555e763..5f78bb2dc84 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -37,10 +37,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <mach/ulpi.h>
#include "3ds_debugboard.h"
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 50b5d049255..beb281c250f 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -21,13 +21,13 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index d38b696efdf..ee6a3f300a1 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -37,10 +37,10 @@
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
-#include <mach/common.h>
#include <mach/ulpi.h>
#include "3ds_debugboard.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 837839bb159..deb89d2cc1b 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -28,7 +28,6 @@
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -37,6 +36,7 @@
#include <linux/mfd/wm8350/pmic.h>
#endif
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index ae2dc78edf1..15d26a0390d 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -43,10 +43,10 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <mach/ulpi.h>
#include "board-mx31lilly.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 7d80aa25901..ef8d28f6b29 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -40,10 +40,10 @@
#include <asm/setup.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <mach/ulpi.h>
#include "board-mx31lite.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 6c2e058b9a7..955275bbbc8 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -42,12 +42,12 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/ulpi.h>
#include <linux/platform_data/asoc-imx-ssi.h>
#include "board-mx31moboard.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 63d7a76165a..ee7d0375c70 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -44,12 +44,12 @@
#include <asm/memblock.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <video/platform_lcd.h>
#include <media/soc_camera.h>
#include "3ds_debugboard.h"
+#include "common.h"
#include "devices-imx35.h"
#include "iomux-mx35.h"
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
index 4762a3f8093..4a3e98e3779 100644
--- a/arch/arm/mach-imx/mach-mx50_rdp.c
+++ b/arch/arm/mach-imx/mach-mx50_rdp.c
@@ -24,7 +24,6 @@
#include <linux/delay.h>
#include <linux/io.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/irq.h>
@@ -33,6 +32,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
+#include "common.h"
#include "devices-imx50.h"
#include "iomux-mx50.h"
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 4eb4299836f..476c759216b 100644
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
@@ -20,9 +20,9 @@
#include <asm/mach/time.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include "3ds_debugboard.h"
+#include "common.h"
#include "devices-imx51.h"
#include "iomux-mx51.h"
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 20e6b9ef8c2..383948a1717 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -20,7 +20,6 @@
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/setup.h>
@@ -28,6 +27,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
+#include "common.h"
#include "devices-imx51.h"
#include "cpu_op-mx51.h"
#include "iomux-mx51.h"
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index b5c036ac64a..f1cbe03a446 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -21,7 +21,6 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -30,6 +29,7 @@
#include <linux/gpio.h>
#include <linux/i2c/pca953x.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 42f407b21d5..826d326bdcd 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -32,11 +32,11 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach/time.h>
#include <mach/ulpi.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 0bdec552f7d..59d227470d5 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -42,10 +42,10 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/ulpi.h>
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
#include "pcm037.h"
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index 727dd639120..8fd8255068e 100644
--- a/arch/arm/mach-imx/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -11,11 +11,10 @@
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
-#include <mach/common.h>
-
#include <asm/mach-types.h>
#include "pcm037.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 288838c166a..9ebc248791e 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -33,11 +33,11 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/ulpi.h>
#include "board-pcm038.h"
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 051e8830e75..285ac8bbb60 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -34,9 +34,9 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <mach/ulpi.h>
+#include "common.h"
#include "devices-imx35.h"
#include "iomux-mx35.h"
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index c85425fb987..962988a8cfa 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -26,10 +26,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <asm/page.h>
#include <asm/setup.h>
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 7528bb2d382..c4917565871 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -20,9 +20,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "devices-imx1.h"
#include "iomux-mx1.h"
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 37fff6188a2..288a920ad64 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -29,12 +29,12 @@
#include <asm/mach/time.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/mfd/mc13xxx.h>
+#include "common.h"
#include "devices-imx35.h"
#include "iomux-mx35.h"
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index af612429b44..118aa928cd8 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -22,9 +22,9 @@
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "iomux-v1.h"
static struct map_desc imx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 79d94aaa064..0c24556f299 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -22,10 +22,10 @@
#include <linux/init.h>
#include <linux/pinctrl/machine.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
+#include "common.h"
#include "devices/devices-common.h"
#include "iomux-v1.h"
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index c8ea3aaf432..a08a960de23 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -24,10 +24,10 @@
#include <asm/pgtable.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/mx25.h>
+#include "common.h"
#include "devices/devices-common.h"
#include "iomux-v3.h"
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 6d91808a044..3241314b4f2 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -22,10 +22,10 @@
#include <linux/init.h>
#include <linux/pinctrl/machine.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
+#include "common.h"
#include "devices/devices-common.h"
#include "iomux-v1.h"
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 6a5d4e496f8..3e2ed2ab1ea 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -26,9 +26,9 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "crmregs-imx3.h"
#include "devices/devices-common.h"
#include "iomux-v3.h"
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index cc1423c0cce..d9ef24b2260 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -19,8 +19,8 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
+#include "common.h"
#include "devices/devices-common.h"
#include "iomux-v3.h"
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index d364d52dfff..8cdcf0f2522 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -31,9 +31,9 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include "board-mx31lilly.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index 944f7a83b34..c9eb91c344b 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -32,9 +32,9 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include "board-mx31lite.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 3dfb344db10..527f1739b0a 100644
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -22,10 +22,10 @@
#include <linux/usb/otg.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/ulpi.h>
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index 21cb93e347b..4679309c2ab 100644
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -24,12 +24,12 @@
#include <linux/usb/otg.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index 318be44ee34..afb4d054fb0 100644
--- a/arch/arm/mach-imx/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -23,13 +23,13 @@
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
-#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
#include "board-mx31moboard.h"
+#include "common.h"
#include "devices-imx31.h"
#include "iomux-mx3.h"
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index 8e458073301..c491f59e729 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -23,9 +23,9 @@
#include <asm/mach/arch.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 2ac43e1a2df..6147be27af4 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -16,9 +16,10 @@
#include <asm/smp_scu.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
+
static void __iomem *scu_base;
static struct map_desc scu_io_desc __initdata = {
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
index 884dc9453d3..e509be04c92 100644
--- a/arch/arm/mach-imx/pm-imx3.c
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -9,8 +9,9 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/io.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+
+#include "common.h"
#include "crmregs-imx3.h"
#include "devices/devices-common.h"
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 19621ed1ffa..9fead8c4ea9 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -16,9 +16,10 @@
#include <asm/cacheflush.h>
#include <asm/system_misc.h>
#include <asm/tlbflush.h>
-#include <mach/common.h>
#include <mach/cpuidle.h>
#include <mach/hardware.h>
+
+#include "common.h"
#include "crm-regs-imx5.h"
/*
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index f7b0c2b1b90..05618afb559 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -18,9 +18,10 @@
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>
-#include <mach/common.h>
#include <mach/hardware.h>
+#include "common.h"
+
extern unsigned long phys_l2x0_saved_regs;
static int imx6q_suspend_finish(unsigned long val)
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 3da78cfc5a9..bbd80f25cdc 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -23,11 +23,12 @@
#include <linux/delay.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <asm/system_misc.h>
#include <asm/proc-fns.h>
#include <asm/mach-types.h>
+#include "common.h"
+
static void __iomem *wdog_base;
/*
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index a17abcf9832..8ee6f3608a8 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -30,7 +30,8 @@
#include <mach/hardware.h>
#include <asm/sched_clock.h>
#include <asm/mach/time.h>
-#include <mach/common.h>
+
+#include "common.h"
/*
* There are 2 versions of the timer hardware on Freescale MXC hardware.
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 3ed1adbc09f..6134e962da1 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -22,9 +22,9 @@
#include <asm/exception.h>
#include <mach/hardware.h>
-#include <mach/common.h>
#include <mach/irqs.h>
+#include "common.h"
#include "irq-common.h"
/*
--
cgit v1.2.3-70-g09d2
From 50f2de61269bbe2f40bead1969a9594fa8599b93 Mon Sep 17 00:00:00 2001
From: Shawn Guo <shawn.guo@linaro.org>
Date: Fri, 14 Sep 2012 14:14:45 +0800
Subject: ARM: imx: include hardware.h rather than mach/hardware.h
It moves a bunch of header files included in hardware.h and itself
from mach-imx/include/mach to mach-imx, and updates users to include
hardware.h rather than mach/hardware.h. The files in mach-imx/devices
will need to include "../hardware.h".
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-imx/3ds_debugboard.c | 2 +-
arch/arm/mach-imx/avic.c | 2 +-
arch/arm/mach-imx/clk-imx1.c | 3 +-
arch/arm/mach-imx/clk-imx21.c | 3 +-
arch/arm/mach-imx/clk-imx25.c | 5 +-
arch/arm/mach-imx/clk-imx27.c | 3 +-
arch/arm/mach-imx/clk-imx31.c | 5 +-
arch/arm/mach-imx/clk-imx35.c | 3 +-
arch/arm/mach-imx/clk-imx51-imx53.c | 3 +-
arch/arm/mach-imx/clk-pllv1.c | 2 +-
arch/arm/mach-imx/cpu-imx25.c | 2 +-
arch/arm/mach-imx/cpu-imx27.c | 2 +-
arch/arm/mach-imx/cpu-imx31.c | 2 +-
arch/arm/mach-imx/cpu-imx35.c | 2 +-
arch/arm/mach-imx/cpu-imx5.c | 3 +-
arch/arm/mach-imx/cpu.c | 3 +-
arch/arm/mach-imx/cpu_op-mx51.c | 3 +-
arch/arm/mach-imx/cpufreq.c | 3 +-
arch/arm/mach-imx/devices/platform-ahci-imx.c | 3 +-
arch/arm/mach-imx/devices/platform-fec.c | 3 +-
arch/arm/mach-imx/devices/platform-flexcan.c | 2 +-
arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c | 3 +-
arch/arm/mach-imx/devices/platform-gpio_keys.c | 3 +-
arch/arm/mach-imx/devices/platform-imx-fb.c | 3 +-
arch/arm/mach-imx/devices/platform-imx-i2c.c | 2 +-
arch/arm/mach-imx/devices/platform-imx-keypad.c | 2 +-
arch/arm/mach-imx/devices/platform-imx-ssi.c | 2 +-
arch/arm/mach-imx/devices/platform-imx-uart.c | 2 +-
arch/arm/mach-imx/devices/platform-imx2-wdt.c | 3 +-
arch/arm/mach-imx/devices/platform-imx21-hcd.c | 2 +-
arch/arm/mach-imx/devices/platform-imx27-coda.c | 2 +-
arch/arm/mach-imx/devices/platform-imx_udc.c | 2 +-
arch/arm/mach-imx/devices/platform-imxdi_rtc.c | 3 +-
arch/arm/mach-imx/devices/platform-ipu-core.c | 3 +-
arch/arm/mach-imx/devices/platform-mx1-camera.c | 2 +-
arch/arm/mach-imx/devices/platform-mx2-camera.c | 2 +-
arch/arm/mach-imx/devices/platform-mxc-ehci.c | 3 +-
arch/arm/mach-imx/devices/platform-mxc-mmc.c | 3 +-
arch/arm/mach-imx/devices/platform-mxc_nand.c | 3 +-
arch/arm/mach-imx/devices/platform-mxc_pwm.c | 2 +-
arch/arm/mach-imx/devices/platform-mxc_rnga.c | 2 +-
arch/arm/mach-imx/devices/platform-mxc_rtc.c | 2 +-
arch/arm/mach-imx/devices/platform-mxc_w1.c | 2 +-
arch/arm/mach-imx/devices/platform-pata_imx.c | 2 +-
.../mach-imx/devices/platform-sdhci-esdhc-imx.c | 3 +-
arch/arm/mach-imx/devices/platform-spi_imx.c | 2 +-
arch/arm/mach-imx/ehci-imx25.c | 4 +-
arch/arm/mach-imx/ehci-imx27.c | 4 +-
arch/arm/mach-imx/ehci-imx31.c | 4 +-
arch/arm/mach-imx/ehci-imx35.c | 4 +-
arch/arm/mach-imx/ehci-imx5.c | 4 +-
arch/arm/mach-imx/epit.c | 3 +-
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 3 +-
arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c | 4 +-
arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c | 3 +-
arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c | 3 +-
arch/arm/mach-imx/hardware.h | 134 ++++++++
arch/arm/mach-imx/imx27-dt.c | 2 +-
arch/arm/mach-imx/imx31-dt.c | 2 +-
arch/arm/mach-imx/imx51-dt.c | 2 +-
arch/arm/mach-imx/include/mach/hardware.h | 134 --------
arch/arm/mach-imx/include/mach/mx1.h | 172 ----------
arch/arm/mach-imx/include/mach/mx21.h | 189 -----------
arch/arm/mach-imx/include/mach/mx25.h | 117 -------
arch/arm/mach-imx/include/mach/mx27.h | 238 --------------
arch/arm/mach-imx/include/mach/mx2x.h | 145 ---------
arch/arm/mach-imx/include/mach/mx31.h | 196 ------------
arch/arm/mach-imx/include/mach/mx35.h | 190 -----------
arch/arm/mach-imx/include/mach/mx3x.h | 195 ------------
arch/arm/mach-imx/include/mach/mx50.h | 290 -----------------
arch/arm/mach-imx/include/mach/mx51.h | 346 ---------------------
arch/arm/mach-imx/include/mach/mx53.h | 342 --------------------
arch/arm/mach-imx/include/mach/mx6q.h | 35 ---
arch/arm/mach-imx/include/mach/mxc.h | 179 -----------
arch/arm/mach-imx/iomux-imx31.c | 2 +-
arch/arm/mach-imx/iomux-v1.c | 2 +-
arch/arm/mach-imx/iomux-v3.c | 2 +-
arch/arm/mach-imx/lluart.c | 3 +-
arch/arm/mach-imx/mach-apf9328.c | 3 +-
arch/arm/mach-imx/mach-armadillo5x0.c | 2 +-
arch/arm/mach-imx/mach-bug.c | 3 +-
arch/arm/mach-imx/mach-cpuimx27.c | 3 +-
arch/arm/mach-imx/mach-cpuimx35.c | 3 +-
arch/arm/mach-imx/mach-cpuimx51sd.c | 3 +-
arch/arm/mach-imx/mach-eukrea_cpuimx25.c | 4 +-
arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 2 +-
arch/arm/mach-imx/mach-imx27ipcam.c | 2 +-
arch/arm/mach-imx/mach-imx27lite.c | 2 +-
arch/arm/mach-imx/mach-imx53.c | 2 +-
arch/arm/mach-imx/mach-imx6q.c | 2 +-
arch/arm/mach-imx/mach-kzm_arm11_01.c | 3 +-
arch/arm/mach-imx/mach-mx1ads.c | 3 +-
arch/arm/mach-imx/mach-mx21ads.c | 2 +-
arch/arm/mach-imx/mach-mx25_3ds.c | 4 +-
arch/arm/mach-imx/mach-mx27_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx27ads.c | 2 +-
arch/arm/mach-imx/mach-mx31_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx31ads.c | 2 +-
arch/arm/mach-imx/mach-mx31lilly.c | 3 +-
arch/arm/mach-imx/mach-mx31lite.c | 3 +-
arch/arm/mach-imx/mach-mx31moboard.c | 2 +-
arch/arm/mach-imx/mach-mx35_3ds.c | 2 +-
arch/arm/mach-imx/mach-mx50_rdp.c | 3 +-
arch/arm/mach-imx/mach-mx51_3ds.c | 3 +-
arch/arm/mach-imx/mach-mx51_babbage.c | 3 +-
arch/arm/mach-imx/mach-mxt_td60.c | 2 +-
arch/arm/mach-imx/mach-pca100.c | 2 +-
arch/arm/mach-imx/mach-pcm037.c | 2 +-
arch/arm/mach-imx/mach-pcm038.c | 3 +-
arch/arm/mach-imx/mach-pcm043.c | 3 +-
arch/arm/mach-imx/mach-qong.c | 2 +-
arch/arm/mach-imx/mach-scb9328.c | 3 +-
arch/arm/mach-imx/mach-vpr200.c | 3 +-
arch/arm/mach-imx/mm-imx1.c | 3 +-
arch/arm/mach-imx/mm-imx21.c | 2 +-
arch/arm/mach-imx/mm-imx25.c | 5 +-
arch/arm/mach-imx/mm-imx27.c | 2 +-
arch/arm/mach-imx/mm-imx3.c | 3 +-
arch/arm/mach-imx/mm-imx5.c | 3 +-
arch/arm/mach-imx/mx1.h | 172 ++++++++++
arch/arm/mach-imx/mx21.h | 189 +++++++++++
arch/arm/mach-imx/mx25.h | 117 +++++++
arch/arm/mach-imx/mx27.h | 238 ++++++++++++++
arch/arm/mach-imx/mx2x.h | 145 +++++++++
arch/arm/mach-imx/mx31.h | 196 ++++++++++++
arch/arm/mach-imx/mx31lilly-db.c | 3 +-
arch/arm/mach-imx/mx31lite-db.c | 3 +-
arch/arm/mach-imx/mx31moboard-devboard.c | 3 +-
arch/arm/mach-imx/mx31moboard-marxbot.c | 3 +-
arch/arm/mach-imx/mx31moboard-smartbot.c | 3 +-
arch/arm/mach-imx/mx35.h | 190 +++++++++++
arch/arm/mach-imx/mx3x.h | 195 ++++++++++++
arch/arm/mach-imx/mx50.h | 290 +++++++++++++++++
arch/arm/mach-imx/mx51.h | 346 +++++++++++++++++++++
arch/arm/mach-imx/mx53.h | 342 ++++++++++++++++++++
arch/arm/mach-imx/mx6q.h | 35 +++
arch/arm/mach-imx/mxc.h | 179 +++++++++++
arch/arm/mach-imx/pcm970-baseboard.c | 3 +-
arch/arm/mach-imx/platsmp.c | 2 +-
arch/arm/mach-imx/pm-imx27.c | 3 +-
arch/arm/mach-imx/pm-imx3.c | 2 +-
arch/arm/mach-imx/pm-imx5.c | 2 +-
arch/arm/mach-imx/pm-imx6q.c | 2 +-
arch/arm/mach-imx/system.c | 2 +-
arch/arm/mach-imx/time.c | 2 +-
arch/arm/mach-imx/tzic.c | 2 +-
146 files changed, 2915 insertions(+), 2934 deletions(-)
create mode 100644 arch/arm/mach-imx/hardware.h
delete mode 100644 arch/arm/mach-imx/include/mach/hardware.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx1.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx21.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx25.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx27.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx2x.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx31.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx35.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx3x.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx50.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx51.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx53.h
delete mode 100644 arch/arm/mach-imx/include/mach/mx6q.h
delete mode 100644 arch/arm/mach-imx/include/mach/mxc.h
create mode 100644 arch/arm/mach-imx/mx1.h
create mode 100644 arch/arm/mach-imx/mx21.h
create mode 100644 arch/arm/mach-imx/mx25.h
create mode 100644 arch/arm/mach-imx/mx27.h
create mode 100644 arch/arm/mach-imx/mx2x.h
create mode 100644 arch/arm/mach-imx/mx31.h
create mode 100644 arch/arm/mach-imx/mx35.h
create mode 100644 arch/arm/mach-imx/mx3x.h
create mode 100644 arch/arm/mach-imx/mx50.h
create mode 100644 arch/arm/mach-imx/mx51.h
create mode 100644 arch/arm/mach-imx/mx53.h
create mode 100644 arch/arm/mach-imx/mx6q.h
create mode 100644 arch/arm/mach-imx/mxc.h
(limited to 'arch/arm/mach-imx/pm-imx3.c')
diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c
index 5c10ad05df7..13437735296 100644
--- a/arch/arm/mach-imx/3ds_debugboard.c
+++ b/arch/arm/mach-imx/3ds_debugboard.c
@@ -21,7 +21,7 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
-#include <mach/hardware.h>
+#include "hardware.h"
/* LAN9217 ethernet base address */
#define LAN9217_BASE_ADDR(n) (n + 0x0)
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 204fd94c57d..adc64bc5b34 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -24,10 +24,10 @@
#include <linux/of.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
-#include <mach/hardware.h>
#include <mach/irqs.h>
#include "common.h"
+#include "hardware.h"
#include "irq-common.h"
#define AVIC_INTCNTL 0x00 /* int control reg */
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 796d8b86e8b..15f9d223cf0 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -22,10 +22,9 @@
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/hardware.h>
-
#include "clk.h"
#include "common.h"
+#include "hardware.h"
/* CCM register addresses */
#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index fcdaa9b9cec..d7ed66091a2 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -25,10 +25,9 @@
#include <linux/module.h>
#include <linux/err.h>
-#include <mach/hardware.h>
-
#include "clk.h"
#include "common.h"
+#include "hardware.h"
#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 08d98030e02..fd8b27f965d 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -24,11 +24,10 @@
#include <linux/clkdev.h>
#include <linux/err.h>
-#include <mach/hardware.h>
-#include <mach/mx25.h>
-
#include "clk.h"
#include "common.h"
+#include "hardware.h"
+#include "mx25.h"
#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 4204092ab64..c3bddd3e255 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -6,10 +6,9 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <mach/hardware.h>
-
#include "clk.h"
#include "common.h"
+#include "hardware.h"
#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 1277f732d1f..8be64e0a4ac 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -22,12 +22,11 @@
#include <linux/err.h>
#include <linux/of.h>
-#include <mach/hardware.h>
-#include <mach/mx31.h>
-
#include "clk.h"
#include "common.h"
#include "crmregs-imx3.h"
+#include "hardware.h"
+#include "mx31.h"
static const char *mcu_main_sel[] = { "spll", "mpll", };
static const char *per_sel[] = { "per_div", "ipg", };
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index fec48e656ef..66f3d65ea27 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -14,11 +14,10 @@
#include <linux/of.h>
#include <linux/err.h>
-#include <mach/hardware.h>
-
#include "crmregs-imx3.h"
#include "clk.h"
#include "common.h"
+#include "hardware.h"
struct arm_ahb_div {
unsigned char arm, ahb, sel;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4836b4d39a0..abb71f6b4d6 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -14,11 +14,10 @@
#include <linux/of.h>
#include <linux/err.h>
-#include <mach/hardware.h>
-
#include "crm-regs-imx5.h"
#include "clk.h"
#include "common.h"
+#include "hardware.h"
/* Low-power Audio Playback Mode clock */
static const char *lp_apm_sel[] = { "osc", };
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 02f9013d499..abff350ba24 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -4,10 +4,10 @@
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/err.h>
-#include <mach/hardware.h>
#include "clk.h"
#include "common.h"
+#include "hardware.h"
/**
* pll v1
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c
index 79d4d1c5689..96ec64b5ff7 100644
--- a/arch/arm/mach-imx/cpu-imx25.c
+++ b/arch/arm/mach-imx/cpu-imx25.c
@@ -11,9 +11,9 @@
*/
#include <linux/module.h>
#include <linux/io.h>
-#include <mach/hardware.h>
#include "iim.h"
+#include "hardware.h"
static int mx25_cpu_rev = -1;
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index ff38e1505f6..fe8d36f7e30 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -24,7 +24,7 @@
#include <linux/io.h>
#include <linux/module.h>
-#include <mach/hardware.h>
+#include "hardware.h"
static int mx27_cpu_rev = -1;
static int mx27_cpu_partnumber;
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index 51c938fefe6..fde1860a252 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -11,9 +11,9 @@
#include <linux/module.h>
#include <linux/io.h>
-#include <mach/hardware.h>
#include "common.h"
+#include "hardware.h"
#include "iim.h"
static int mx31_cpu_rev = -1;
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
index 8b36d3ac79e..ec3aaa098c1 100644
--- a/arch/arm/mach-imx/cpu-imx35.c
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -10,8 +10,8 @@
*/
#include <linux/module.h>
#include <linux/io.h>
-#include <mach/hardware.h>
+#include "hardware.h"
#include "iim.h"
static int mx35_cpu_rev = -1;
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 8eb15a2fcaf..d88760014ff 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -15,9 +15,10 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
-#include <mach/hardware.h>
#include <linux/io.h>
+#include "hardware.h"
+
static int mx5_cpu_rev = -1;
#define IIM_SREV 0x24
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 220dd6f9312..03fcbd08259 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -1,7 +1,8 @@
#include <linux/module.h>
#include <linux/io.h>
-#include <mach/hardware.h>
+
+#include "hardware.h"
unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
index 7b92cd6da6d..b9ef692b61a 100644
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ b/arch/arm/mach-imx/cpu_op-mx51.c
@@ -13,9 +13,10 @@
#include <linux/bug.h>
#include <linux/types.h>
-#include <mach/hardware.h>
#include <linux/kernel.h>
+#include "hardware.h"
+
static struct cpu_op mx51_cpu_op[] = {
{
.cpu_rate = 160000000,},
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index b5b6f808313..36e8b399447 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -22,7 +22,8 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/slab.h>
-#include <mach/hardware.h>
+
+#include "hardware.h"
#define CLK32_FREQ 32768
#define NANOSECOND (1000 * 1000 * 1000)
diff --git a/arch/arm/mach-imx/devices/platform-ahci-imx.c b/arch/arm/mach-imx/devices/platform-ahci-imx.c
index bf7f46d930e..3d87dd9c284 100644
--- a/arch/arm/mach-imx/devices/platform-ahci-imx.c
+++ b/arch/arm/mach-imx/devices/platform-ahci-imx.c
@@ -24,7 +24,8 @@
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <asm/sizes.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_ahci_imx_data_entry_single(soc, _devid) \
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
index e62114f1f4f..2cb188ad9a0 100644
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ b/arch/arm/mach-imx/devices/platform-fec.c
@@ -8,7 +8,8 @@
*/
#include <linux/dma-mapping.h>
#include <asm/sizes.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_fec_data_entry_single(soc, _devid) \
diff --git a/arch/arm/mach-imx/devices/platform-flexcan.c b/arch/arm/mach-imx/devices/platform-flexcan.c
index e776d8efea9..1078bf0a94e 100644
--- a/arch/arm/mach-imx/devices/platform-flexcan.c
+++ b/arch/arm/mach-imx/devices/platform-flexcan.c
@@ -5,7 +5,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
index 6ecccf97774..37e44398197 100644
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_fsl_usb2_udc_data_entry_single(soc) \
diff --git a/arch/arm/mach-imx/devices/platform-gpio_keys.c b/arch/arm/mach-imx/devices/platform-gpio_keys.c
index 3f8727952ed..486282539c7 100644
--- a/arch/arm/mach-imx/devices/platform-gpio_keys.c
+++ b/arch/arm/mach-imx/devices/platform-gpio_keys.c
@@ -16,7 +16,8 @@
* Boston, MA 02110-1301, USA.
*/
#include <asm/sizes.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
struct platform_device *__init imx_add_gpio_keys(
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
index abea28bea28..10b0ed39f07 100644
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ b/arch/arm/mach-imx/devices/platform-imx-fb.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx_fb_data_entry_single(soc, _devid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
index 424ce246fe4..8e30e5703cd 100644
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ b/arch/arm/mach-imx/devices/platform-imx-i2c.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
index 371b1e6ec95..8f22a4c98a4 100644
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ b/arch/arm/mach-imx/devices/platform-imx-keypad.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx_keypad_data_entry_single(soc, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
index bf0c5e4e2d1..bfcb8f3dfa8 100644
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ b/arch/arm/mach-imx/devices/platform-imx-ssi.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
index e6132f2b98e..67bf866a2cb 100644
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ b/arch/arm/mach-imx/devices/platform-imx-uart.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
index 729c1914e22..ec75d641368 100644
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <asm/sizes.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-imx21-hcd.c b/arch/arm/mach-imx/devices/platform-imx21-hcd.c
index 18b9963f607..30c81616a9a 100644
--- a/arch/arm/mach-imx/devices/platform-imx21-hcd.c
+++ b/arch/arm/mach-imx/devices/platform-imx21-hcd.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx21_hcd_data_entry_single(soc) \
diff --git a/arch/arm/mach-imx/devices/platform-imx27-coda.c b/arch/arm/mach-imx/devices/platform-imx27-coda.c
index 54996038e75..25bebc29e54 100644
--- a/arch/arm/mach-imx/devices/platform-imx27-coda.c
+++ b/arch/arm/mach-imx/devices/platform-imx27-coda.c
@@ -7,7 +7,7 @@
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#ifdef CONFIG_SOC_IMX27
diff --git a/arch/arm/mach-imx/devices/platform-imx_udc.c b/arch/arm/mach-imx/devices/platform-imx_udc.c
index 75aee0bf034..5ced7e4e2c7 100644
--- a/arch/arm/mach-imx/devices/platform-imx_udc.c
+++ b/arch/arm/mach-imx/devices/platform-imx_udc.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imx_udc_data_entry_single(soc, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
index e4b22eb5950..5bb490d556e 100644
--- a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
+++ b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <asm/sizes.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_imxdi_rtc_data_entry_single(soc) \
diff --git a/arch/arm/mach-imx/devices/platform-ipu-core.c b/arch/arm/mach-imx/devices/platform-ipu-core.c
index dc0e8370cae..fc4dd7cedc1 100644
--- a/arch/arm/mach-imx/devices/platform-ipu-core.c
+++ b/arch/arm/mach-imx/devices/platform-ipu-core.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_ipu_core_entry_single(soc) \
diff --git a/arch/arm/mach-imx/devices/platform-mx1-camera.c b/arch/arm/mach-imx/devices/platform-mx1-camera.c
index 756b0e659b2..2c678813108 100644
--- a/arch/arm/mach-imx/devices/platform-mx1-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx1-camera.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mx1_camera_data_entry_single(soc, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
index b88877d54d7..f4910160346 100644
--- a/arch/arm/mach-imx/devices/platform-mx2-camera.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-camera.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mx2_camera_data_entry_single(soc, _devid) \
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
index 27c81713a64..5d4bbbfde64 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \
diff --git a/arch/arm/mach-imx/devices/platform-mxc-mmc.c b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
index 487f61cfbc8..7da19afa1bb 100644
--- a/arch/arm/mach-imx/devices/platform-mxc-mmc.c
+++ b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index 24aaad1a58c..7af1c53e42b 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -7,7 +7,8 @@
* Free Software Foundation.
*/
#include <asm/sizes.h>
-#include <mach/hardware.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mxc_nand_data_entry_single(soc, _devid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
index a0551bfff55..dcd28977768 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
index 37bb23caa9d..c58404badb5 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_rnga.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_rnga.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
struct imx_mxc_rnga_data {
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rtc.c b/arch/arm/mach-imx/devices/platform-mxc_rtc.c
index f35f848b0d5..c7fffaadf84 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_rtc.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_rtc.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mxc_rtc_data_entry_single(soc, _devid) \
diff --git a/arch/arm/mach-imx/devices/platform-mxc_w1.c b/arch/arm/mach-imx/devices/platform-mxc_w1.c
index 5f972c66956..88c18b720d6 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_w1.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_w1.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_mxc_w1_data_entry_single(soc) \
diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c
index 3627ec8d8a9..e4ec11c8ce5 100644
--- a/arch/arm/mach-imx/devices/platform-pata_imx.c
+++ b/arch/arm/mach-imx/devices/platform-pata_imx.c
@@ -3,7 +3,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_pata_imx_data_entry_single(soc, _size) \
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
index 772ba2dc3f5..e66a4e31631 100644
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
@@ -6,8 +6,9 @@
* Free Software Foundation.
*/
-#include <mach/hardware.h>
#include <linux/platform_data/mmc-esdhc-imx.h>
+
+#include "../hardware.h"
#include "devices-common.h"
#define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
index 63a116bae10..8880bcb11e0 100644
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ b/arch/arm/mach-imx/devices/platform-spi_imx.c
@@ -6,7 +6,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <mach/hardware.h>
+#include "../hardware.h"
#include "devices-common.h"
#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 412c583a24b..27e40d17de9 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -15,10 +15,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
-
-#include <mach/hardware.h>
#include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
+
#define USBCTRL_OTGBASE_OFFSET 0x600
#define MX25_OTG_SIC_SHIFT 29
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
index cd6e1f81508..448d9115539 100644
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -15,10 +15,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
-
-#include <mach/hardware.h>
#include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
+
#define USBCTRL_OTGBASE_OFFSET 0x600
#define MX27_OTG_SIC_SHIFT 29
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index 9a880c78af3..05de4e1e39d 100644
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -15,10 +15,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
-
-#include <mach/hardware.h>
#include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
+
#define USBCTRL_OTGBASE_OFFSET 0x600
#define MX31_OTG_SIC_SHIFT 29
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 779e16eb65c..a596f709a93 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -15,10 +15,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
-
-#include <mach/hardware.h>
#include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
+
#define USBCTRL_OTGBASE_OFFSET 0x600
#define MX35_OTG_SIC_SHIFT 29
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
index cf8d00e5cce..e49710b10c6 100644
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ b/arch/arm/mach-imx/ehci-imx5.c
@@ -15,10 +15,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
-
-#include <mach/hardware.h>
#include <linux/platform_data/usb-ehci-mxc.h>
+#include "hardware.h"
+
#define MXC_OTG_OFFSET 0
#define MXC_H1_OFFSET 0x200
#define MXC_H2_OFFSET 0x400
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
index 76720f528b1..04a5961beea 100644
--- a/arch/arm/mach-imx/epit.c
+++ b/arch/arm/mach-imx/epit.c
@@ -51,11 +51,10 @@
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/err.h>
-
-#include <mach/hardware.h>
#include <asm/mach/time.h>
#include "common.h"
+#include "hardware.h"
static struct clock_event_device clockevent_epit;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 27b55702bda..b4c70028d35 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -29,10 +29,9 @@
#include <asm/mach/arch.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
static const int eukrea_mbimx27_pins[] __initconst = {
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 34e46dcfb6d..e2b70f4c1a2 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -26,14 +26,14 @@
#include <linux/spi/spi.h>
#include <video/platform_lcd.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <mach/mx25.h>
#include "common.h"
#include "devices-imx25.h"
+#include "hardware.h"
#include "iomux-mx25.h"
+#include "mx25.h"
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LCD */
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 63a42f6f9c2..5a2d5ef12dd 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -36,10 +36,9 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx35.h"
+#include "hardware.h"
#include "iomux-mx35.h"
static const struct fb_videomode fb_modedb[] = {
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
index f1cf5219300..9be6c1e69d6 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
@@ -36,10 +36,9 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx51.h"
+#include "hardware.h"
#include "iomux-mx51.h"
static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
new file mode 100644
index 00000000000..3ce7fa3bd43
--- /dev/null
+++ b/arch/arm/mach-imx/hardware.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#define __ASM_ARCH_MXC_HARDWARE_H__
+
+#include <asm/sizes.h>
+
+#define addr_in_module(addr, mod) \
+ ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
+
+#define IMX_IO_P2V_MODULE(addr, module) \
+ (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
+ (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
+
+/*
+ * This is rather complicated for humans and ugly to verify, but for a machine
+ * it's OK. Still more as it is usually only applied to constants. The upsides
+ * on using this approach are:
+ *
+ * - same mapping on all i.MX machines
+ * - works for assembler, too
+ * - no need to nurture #defines for virtual addresses
+ *
+ * The downside it, it's hard to verify (but I have a script for that).
+ *
+ * Obviously this needs to be injective for each SoC. In general it maps the
+ * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
+ * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
+ *
+ * It applies the following mappings for the different SoCs:
+ *
+ * mx1:
+ * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
+ * mx21:
+ * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
+ * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
+ * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
+ * mx25:
+ * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
+ * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
+ * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
+ * mx27:
+ * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
+ * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
+ * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
+ * mx31:
+ * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
+ * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
+ * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
+ * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
+ * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
+ * mx35:
+ * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
+ * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
+ * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
+ * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
+ * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
+ * mx50:
+ * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
+ * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
+ * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
+ * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
+ * mx51:
+ * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
+ * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
+ * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
+ * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
+ * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
+ * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000
+ * mx53:
+ * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
+ * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000
+ * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
+ * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
+ * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
+ * mx6q:
+ * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
+ * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
+ * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
+ * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
+ */
+#define IMX_IO_P2V(x) ( \
+ (((x) & 0x80000000) >> 7) | \
+ (0xf4000000 + \
+ (((x) & 0x50000000) >> 6) + \
+ (((x) & 0x0b000000) >> 4) + \
+ (((x) & 0x000fffff))))
+
+#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
+
+#include "mxc.h"
+
+#include "mx6q.h"
+#include "mx50.h"
+#include "mx51.h"
+#include "mx53.h"
+#include "mx3x.h"
+#include "mx31.h"
+#include "mx35.h"
+#include "mx2x.h"
+#include "mx21.h"
+#include "mx27.h"
+#include "mx1.h"
+#include "mx25.h"
+
+#define imx_map_entry(soc, name, _type) { \
+ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
+ .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
+ .length = soc ## _ ## name ## _SIZE, \
+ .type = _type, \
+}
+
+/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* range e.g. GPIO_1_5 is gpio 5 under linux */
+#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
+
+#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index a6c288e180c..ebfae96543c 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -14,9 +14,9 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/mx27.h>
#include "common.h"
+#include "mx27.h"
static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 408afcc91f0..af476de2570 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -14,9 +14,9 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/mx31.h>
#include "common.h"
+#include "mx31.h"
static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index a0391a14ad2..50742990a13 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -15,9 +15,9 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/mx51.h>
#include "common.h"
+#include "mx51.h"
/*
* Lookup table for attaching a specific name and platform_data pointer to
diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h
deleted file mode 100644
index ebf10654bb4..00000000000
--- a/arch/arm/mach-imx/include/mach/hardware.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#define __ASM_ARCH_MXC_HARDWARE_H__
-
-#include <asm/sizes.h>
-
-#define addr_in_module(addr, mod) \
- ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
-
-#define IMX_IO_P2V_MODULE(addr, module) \
- (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
- (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
-
-/*
- * This is rather complicated for humans and ugly to verify, but for a machine
- * it's OK. Still more as it is usually only applied to constants. The upsides
- * on using this approach are:
- *
- * - same mapping on all i.MX machines
- * - works for assembler, too
- * - no need to nurture #defines for virtual addresses
- *
- * The downside it, it's hard to verify (but I have a script for that).
- *
- * Obviously this needs to be injective for each SoC. In general it maps the
- * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
- * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
- *
- * It applies the following mappings for the different SoCs:
- *
- * mx1:
- * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
- * mx21:
- * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
- * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
- * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
- * mx25:
- * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
- * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
- * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
- * mx27:
- * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
- * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
- * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
- * mx31:
- * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
- * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
- * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
- * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
- * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
- * mx35:
- * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
- * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
- * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
- * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
- * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
- * mx50:
- * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
- * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
- * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
- * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
- * mx51:
- * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
- * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
- * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
- * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
- * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
- * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000
- * mx53:
- * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
- * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000
- * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
- * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
- * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
- * mx6q:
- * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
- * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
- * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
- * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
- */
-#define IMX_IO_P2V(x) ( \
- (((x) & 0x80000000) >> 7) | \
- (0xf4000000 + \
- (((x) & 0x50000000) >> 6) + \
- (((x) & 0x0b000000) >> 4) + \
- (((x) & 0x000fffff))))
-
-#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
-
-#include <mach/mxc.h>
-
-#include <mach/mx6q.h>
-#include <mach/mx50.h>
-#include <mach/mx51.h>
-#include <mach/mx53.h>
-#include <mach/mx3x.h>
-#include <mach/mx31.h>
-#include <mach/mx35.h>
-#include <mach/mx2x.h>
-#include <mach/mx21.h>
-#include <mach/mx27.h>
-#include <mach/mx1.h>
-#include <mach/mx25.h>
-
-#define imx_map_entry(soc, name, _type) { \
- .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
- .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
- .length = soc ## _ ## name ## _SIZE, \
- .type = _type, \
-}
-
-/* There's a off-by-one betweem the gpio bank number and the gpiochip */
-/* range e.g. GPIO_1_5 is gpio 5 under linux */
-#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
-
-#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx1.h b/arch/arm/mach-imx/include/mach/mx1.h
deleted file mode 100644
index 45bd31cc34d..00000000000
--- a/arch/arm/mach-imx/include/mach/mx1.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright (C) 1997,1998 Russell King
- * Copyright (C) 1999 ARM Limited
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MX1_H__
-#define __MACH_MX1_H__
-
-/*
- * Memory map
- */
-#define MX1_IO_BASE_ADDR 0x00200000
-#define MX1_IO_SIZE SZ_1M
-
-#define MX1_CS0_PHYS 0x10000000
-#define MX1_CS0_SIZE 0x02000000
-
-#define MX1_CS1_PHYS 0x12000000
-#define MX1_CS1_SIZE 0x01000000
-
-#define MX1_CS2_PHYS 0x13000000
-#define MX1_CS2_SIZE 0x01000000
-
-#define MX1_CS3_PHYS 0x14000000
-#define MX1_CS3_SIZE 0x01000000
-
-#define MX1_CS4_PHYS 0x15000000
-#define MX1_CS4_SIZE 0x01000000
-
-#define MX1_CS5_PHYS 0x16000000
-#define MX1_CS5_SIZE 0x01000000
-
-/*
- * Register BASEs, based on OFFSETs
- */
-#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
-#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
-#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
-#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
-#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
-#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
-#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
-#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
-#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
-#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
-#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
-#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
-#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
-#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
-#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
-#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
-#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
-#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
-#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
-#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
-#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
-#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
-#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
-#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
-#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
-#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
-#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
-
-/* macro to get at IO space when running virtually */
-#define MX1_IO_P2V(x) IMX_IO_P2V(x)
-#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
-
-/* fixed interrput numbers */
-#include <asm/irq.h>
-#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
-#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
-#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
-#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
-#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
-#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
-#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
-#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
-#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
-#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
-#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
-#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
-#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
-#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
-#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
-#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
-#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
-#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
-#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
-#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
-#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
-#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
-#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
-#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
-#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
-#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
-#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
-#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
-#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
-#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
-#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
-#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
-#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
-#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
-#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
-#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
-#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
-#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
-#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
-#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
-#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
-#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
-#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
-#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
-#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
-#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
-#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
-#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
-#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
-#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
-#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
-#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
-#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
-#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
-#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
-
-/* DMA */
-#define MX1_DMA_REQ_UART3_T 2
-#define MX1_DMA_REQ_UART3_R 3
-#define MX1_DMA_REQ_SSI2_T 4
-#define MX1_DMA_REQ_SSI2_R 5
-#define MX1_DMA_REQ_CSI_STAT 6
-#define MX1_DMA_REQ_CSI_R 7
-#define MX1_DMA_REQ_MSHC 8
-#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
-#define MX1_DMA_REQ_DSPA_DCT_DIN 10
-#define MX1_DMA_REQ_DSPA_MAC 11
-#define MX1_DMA_REQ_EXT 12
-#define MX1_DMA_REQ_SDHC 13
-#define MX1_DMA_REQ_SPI1_R 14
-#define MX1_DMA_REQ_SPI1_T 15
-#define MX1_DMA_REQ_SSI_T 16
-#define MX1_DMA_REQ_SSI_R 17
-#define MX1_DMA_REQ_ASP_DAC 18
-#define MX1_DMA_REQ_ASP_ADC 19
-#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
-#define MX1_DMA_REQ_SPI2_R 26
-#define MX1_DMA_REQ_SPI2_T 27
-#define MX1_DMA_REQ_UART2_T 28
-#define MX1_DMA_REQ_UART2_R 29
-#define MX1_DMA_REQ_UART1_T 30
-#define MX1_DMA_REQ_UART1_R 31
-
-/*
- * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
- * to not break drivers/usb/gadget/imx_udc. Should go
- * away after this driver uses the new name.
- */
-#define USBD_INT0 MX1_INT_USBD0
-
-#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx21.h b/arch/arm/mach-imx/include/mach/mx21.h
deleted file mode 100644
index 468738aa997..00000000000
--- a/arch/arm/mach-imx/include/mach/mx21.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
- *
- * This contains i.MX21-specific hardware definitions. For those
- * hardware pieces that are common between i.MX21 and i.MX27, have a
- * look at mx2x.h.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_MX21_H__
-#define __MACH_MX21_H__
-
-#define MX21_AIPI_BASE_ADDR 0x10000000
-#define MX21_AIPI_SIZE SZ_1M
-#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
-#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
-#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
-#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
-#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
-#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
-#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
-#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
-#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
-#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
-#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
-#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
-#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
-#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
-#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
-#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
-#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
-#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
-#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
-#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
-#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
-#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
-#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
-#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
-#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
-#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
-#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
-#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
-#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
-#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
-#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
-#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
-#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
-#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
-#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
-#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
-#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
-#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX21_AVIC_BASE_ADDR 0x10040000
-
-#define MX21_SAHB1_BASE_ADDR 0x80000000
-#define MX21_SAHB1_SIZE SZ_1M
-#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
-
-/* Memory regions and CS */
-#define MX21_SDRAM_BASE_ADDR 0xc0000000
-#define MX21_CSD1_BASE_ADDR 0xc4000000
-
-#define MX21_CS0_BASE_ADDR 0xc8000000
-#define MX21_CS1_BASE_ADDR 0xcc000000
-#define MX21_CS2_BASE_ADDR 0xd0000000
-#define MX21_CS3_BASE_ADDR 0xd1000000
-#define MX21_CS4_BASE_ADDR 0xd2000000
-#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
-#define MX21_CS5_BASE_ADDR 0xdd000000
-
-/* NAND, SDRAM, WEIM etc controllers */
-#define MX21_X_MEMC_BASE_ADDR 0xdf000000
-#define MX21_X_MEMC_SIZE SZ_256K
-
-#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
-#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
-#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
-#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
-
-#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
-
-#define MX21_IO_P2V(x) IMX_IO_P2V(x)
-#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
-#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
-#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
-#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
-#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
-#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
-#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
-#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
-#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
-#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
-#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
-#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
-#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
-#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
-#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
-#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
-#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
-#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
-#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
-#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
-#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
-#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
-#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
-#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
-#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
-#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
-#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
-#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
-#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
-#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
-#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
-#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
-#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
-#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
-#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
-#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
-#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
-#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
-#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
-#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
-#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
-#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
-#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
-#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
-#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
-#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
-#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
-#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
-#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
-#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
-#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
-#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
-
-/* fixed DMA request numbers */
-#define MX21_DMA_REQ_CSPI3_RX 1
-#define MX21_DMA_REQ_CSPI3_TX 2
-#define MX21_DMA_REQ_EXT 3
-#define MX21_DMA_REQ_FIRI_RX 4
-#define MX21_DMA_REQ_SDHC2 6
-#define MX21_DMA_REQ_SDHC1 7
-#define MX21_DMA_REQ_SSI2_RX0 8
-#define MX21_DMA_REQ_SSI2_TX0 9
-#define MX21_DMA_REQ_SSI2_RX1 10
-#define MX21_DMA_REQ_SSI2_TX1 11
-#define MX21_DMA_REQ_SSI1_RX0 12
-#define MX21_DMA_REQ_SSI1_TX0 13
-#define MX21_DMA_REQ_SSI1_RX1 14
-#define MX21_DMA_REQ_SSI1_TX1 15
-#define MX21_DMA_REQ_CSPI2_RX 16
-#define MX21_DMA_REQ_CSPI2_TX 17
-#define MX21_DMA_REQ_CSPI1_RX 18
-#define MX21_DMA_REQ_CSPI1_TX 19
-#define MX21_DMA_REQ_UART4_RX 20
-#define MX21_DMA_REQ_UART4_TX 21
-#define MX21_DMA_REQ_UART3_RX 22
-#define MX21_DMA_REQ_UART3_TX 23
-#define MX21_DMA_REQ_UART2_RX 24
-#define MX21_DMA_REQ_UART2_TX 25
-#define MX21_DMA_REQ_UART1_RX 26
-#define MX21_DMA_REQ_UART1_TX 27
-#define MX21_DMA_REQ_BMI_TX 28
-#define MX21_DMA_REQ_BMI_RX 29
-#define MX21_DMA_REQ_CSI_STAT 30
-#define MX21_DMA_REQ_CSI_RX 31
-
-#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx25.h b/arch/arm/mach-imx/include/mach/mx25.h
deleted file mode 100644
index ec466400a20..00000000000
--- a/arch/arm/mach-imx/include/mach/mx25.h
+++ /dev/null
@@ -1,117 +0,0 @@
-#ifndef __MACH_MX25_H__
-#define __MACH_MX25_H__
-
-#define MX25_AIPS1_BASE_ADDR 0x43f00000
-#define MX25_AIPS1_SIZE SZ_1M
-#define MX25_AIPS2_BASE_ADDR 0x53f00000
-#define MX25_AIPS2_SIZE SZ_1M
-#define MX25_AVIC_BASE_ADDR 0x68000000
-#define MX25_AVIC_SIZE SZ_1M
-
-#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
-#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
-#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
-#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
-#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
-#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
-#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
-
-#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
-#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
-#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
-#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
-#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
-#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
-#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
-#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
-#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
-#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
-#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
-
-#define MX25_UART1_BASE_ADDR 0x43f90000
-#define MX25_UART2_BASE_ADDR 0x43f94000
-#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
-#define MX25_UART3_BASE_ADDR 0x5000c000
-#define MX25_UART4_BASE_ADDR 0x50008000
-#define MX25_UART5_BASE_ADDR 0x5002c000
-
-#define MX25_CSPI3_BASE_ADDR 0x50004000
-#define MX25_CSPI2_BASE_ADDR 0x50010000
-#define MX25_FEC_BASE_ADDR 0x50038000
-#define MX25_SSI2_BASE_ADDR 0x50014000
-#define MX25_SSI1_BASE_ADDR 0x50034000
-#define MX25_NFC_BASE_ADDR 0xbb000000
-#define MX25_IIM_BASE_ADDR 0x53ff0000
-#define MX25_DRYICE_BASE_ADDR 0x53ffc000
-#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
-#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
-#define MX25_LCDC_BASE_ADDR 0x53fbc000
-#define MX25_KPP_BASE_ADDR 0x43fa8000
-#define MX25_SDMA_BASE_ADDR 0x53fd4000
-#define MX25_USB_BASE_ADDR 0x53ff4000
-#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
-/*
- * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
- * for the host controller. Early documentation drafts specified 0x400 and
- * Freescale internal sources confirm only the latter value to work.
- */
-#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
-#define MX25_CSI_BASE_ADDR 0x53ff8000
-
-#define MX25_IO_P2V(x) IMX_IO_P2V(x)
-#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
-#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
-#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
-#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
-#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
-#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
-#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
-#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
-#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
-#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
-#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
-#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
-#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
-#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
-#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
-#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
-#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
-#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
-#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
-#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
-#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
-#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
-#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
-#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
-#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
-
-#define MX25_DMA_REQ_SSI2_RX1 22
-#define MX25_DMA_REQ_SSI2_TX1 23
-#define MX25_DMA_REQ_SSI2_RX0 24
-#define MX25_DMA_REQ_SSI2_TX0 25
-#define MX25_DMA_REQ_SSI1_RX1 26
-#define MX25_DMA_REQ_SSI1_TX1 27
-#define MX25_DMA_REQ_SSI1_RX0 28
-#define MX25_DMA_REQ_SSI1_TX0 29
-
-#ifndef __ASSEMBLY__
-extern int mx25_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx27.h b/arch/arm/mach-imx/include/mach/mx27.h
deleted file mode 100644
index e074616d54c..00000000000
--- a/arch/arm/mach-imx/include/mach/mx27.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This contains i.MX27-specific hardware definitions. For those
- * hardware pieces that are common between i.MX21 and i.MX27, have a
- * look at mx2x.h.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_MX27_H__
-#define __MACH_MX27_H__
-
-#define MX27_AIPI_BASE_ADDR 0x10000000
-#define MX27_AIPI_SIZE SZ_1M
-#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
-#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
-#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
-#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
-#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
-#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
-#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
-#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
-#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
-#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
-#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
-#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
-#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
-#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
-#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
-#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
-#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
-#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
-#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
-#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
-#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
-#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
-#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
-#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
-#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
-#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
-#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
-#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
-#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
-#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
-#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
-#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
-#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
-#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
-#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
-#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
-#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
-#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
-#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
-#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
-#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
-#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
-#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
-#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
-#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
-#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
-#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
-#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
-#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
-#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
-#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
-#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
-#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
-#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX27_AVIC_BASE_ADDR 0x10040000
-
-/* ROM patch */
-#define MX27_ROMP_BASE_ADDR 0x10041000
-
-#define MX27_SAHB1_BASE_ADDR 0x80000000
-#define MX27_SAHB1_SIZE SZ_1M
-#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
-#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
-
-/* Memory regions and CS */
-#define MX27_SDRAM_BASE_ADDR 0xa0000000
-#define MX27_CSD1_BASE_ADDR 0xb0000000
-
-#define MX27_CS0_BASE_ADDR 0xc0000000
-#define MX27_CS1_BASE_ADDR 0xc8000000
-#define MX27_CS2_BASE_ADDR 0xd0000000
-#define MX27_CS3_BASE_ADDR 0xd2000000
-#define MX27_CS4_BASE_ADDR 0xd4000000
-#define MX27_CS5_BASE_ADDR 0xd6000000
-
-/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
-#define MX27_X_MEMC_BASE_ADDR 0xd8000000
-#define MX27_X_MEMC_SIZE SZ_1M
-#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
-#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
-#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
-#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
-#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
-
-#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
-
-/* IRAM */
-#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
-
-#define MX27_IO_P2V(x) IMX_IO_P2V(x)
-#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
-#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
-#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
-#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
-#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
-#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
-#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
-#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
-#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
-#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
-#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
-#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
-#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
-#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
-#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
-#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
-#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
-#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
-#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
-#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
-#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
-#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
-#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
-#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
-#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
-#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
-#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
-#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
-#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
-#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
-#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
-#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
-#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
-#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
-#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
-#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
-#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
-#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
-#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
-#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
-#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
-#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
-#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
-#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
-#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
-#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
-#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
-#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
-#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
-#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
-#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
-#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
-#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
-#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
-#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
-#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
-#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
-#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
-#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
-#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
-#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
-#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
-
-/* fixed DMA request numbers */
-#define MX27_DMA_REQ_CSPI3_RX 1
-#define MX27_DMA_REQ_CSPI3_TX 2
-#define MX27_DMA_REQ_EXT 3
-#define MX27_DMA_REQ_MSHC 4
-#define MX27_DMA_REQ_SDHC2 6
-#define MX27_DMA_REQ_SDHC1 7
-#define MX27_DMA_REQ_SSI2_RX0 8
-#define MX27_DMA_REQ_SSI2_TX0 9
-#define MX27_DMA_REQ_SSI2_RX1 10
-#define MX27_DMA_REQ_SSI2_TX1 11
-#define MX27_DMA_REQ_SSI1_RX0 12
-#define MX27_DMA_REQ_SSI1_TX0 13
-#define MX27_DMA_REQ_SSI1_RX1 14
-#define MX27_DMA_REQ_SSI1_TX1 15
-#define MX27_DMA_REQ_CSPI2_RX 16
-#define MX27_DMA_REQ_CSPI2_TX 17
-#define MX27_DMA_REQ_CSPI1_RX 18
-#define MX27_DMA_REQ_CSPI1_TX 19
-#define MX27_DMA_REQ_UART4_RX 20
-#define MX27_DMA_REQ_UART4_TX 21
-#define MX27_DMA_REQ_UART3_RX 22
-#define MX27_DMA_REQ_UART3_TX 23
-#define MX27_DMA_REQ_UART2_RX 24
-#define MX27_DMA_REQ_UART2_TX 25
-#define MX27_DMA_REQ_UART1_RX 26
-#define MX27_DMA_REQ_UART1_TX 27
-#define MX27_DMA_REQ_ATA_TX 28
-#define MX27_DMA_REQ_ATA_RCV 29
-#define MX27_DMA_REQ_CSI_STAT 30
-#define MX27_DMA_REQ_CSI_RX 31
-#define MX27_DMA_REQ_UART5_TX 32
-#define MX27_DMA_REQ_UART5_RX 33
-#define MX27_DMA_REQ_UART6_TX 34
-#define MX27_DMA_REQ_UART6_RX 35
-#define MX27_DMA_REQ_SDHC3 36
-#define MX27_DMA_REQ_NFC 37
-
-#ifndef __ASSEMBLY__
-extern int mx27_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx2x.h b/arch/arm/mach-imx/include/mach/mx2x.h
deleted file mode 100644
index 11642f5b224..00000000000
--- a/arch/arm/mach-imx/include/mach/mx2x.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This contains hardware definitions that are common between i.MX21 and
- * i.MX27.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_MX2x_H__
-#define __MACH_MX2x_H__
-
-/* The following addresses are common between i.MX21 and i.MX27 */
-
-/* Register offsets */
-#define MX2x_AIPI_BASE_ADDR 0x10000000
-#define MX2x_AIPI_SIZE SZ_1M
-#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
-#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
-#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
-#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
-#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
-#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
-#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
-#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
-#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
-#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
-#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
-#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
-#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
-#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
-#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
-#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
-#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
-#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
-#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
-#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
-#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
-#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
-#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
-#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
-#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
-#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
-#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
-#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
-#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
-#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
-#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
-#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX2x_AVIC_BASE_ADDR 0x10040000
-
-#define MX2x_SAHB1_BASE_ADDR 0x80000000
-#define MX2x_SAHB1_SIZE SZ_1M
-#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
-#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
-#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
-#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
-#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
-#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
-#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
-#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
-#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
-#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
-#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
-#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
-#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
-#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
-#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
-#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
-#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
-#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
-#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
-#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
-#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
-#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
-#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
-#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
-#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
-#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
-#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
-#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
-#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
-#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
-#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
-#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
-#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
-#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
-#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
-#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
-#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
-#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
-#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
-#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
-#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
-#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
-
-/* fixed DMA request numbers */
-#define MX2x_DMA_REQ_CSPI3_RX 1
-#define MX2x_DMA_REQ_CSPI3_TX 2
-#define MX2x_DMA_REQ_EXT 3
-#define MX2x_DMA_REQ_SDHC2 6
-#define MX2x_DMA_REQ_SDHC1 7
-#define MX2x_DMA_REQ_SSI2_RX0 8
-#define MX2x_DMA_REQ_SSI2_TX0 9
-#define MX2x_DMA_REQ_SSI2_RX1 10
-#define MX2x_DMA_REQ_SSI2_TX1 11
-#define MX2x_DMA_REQ_SSI1_RX0 12
-#define MX2x_DMA_REQ_SSI1_TX0 13
-#define MX2x_DMA_REQ_SSI1_RX1 14
-#define MX2x_DMA_REQ_SSI1_TX1 15
-#define MX2x_DMA_REQ_CSPI2_RX 16
-#define MX2x_DMA_REQ_CSPI2_TX 17
-#define MX2x_DMA_REQ_CSPI1_RX 18
-#define MX2x_DMA_REQ_CSPI1_TX 19
-#define MX2x_DMA_REQ_UART4_RX 20
-#define MX2x_DMA_REQ_UART4_TX 21
-#define MX2x_DMA_REQ_UART3_RX 22
-#define MX2x_DMA_REQ_UART3_TX 23
-#define MX2x_DMA_REQ_UART2_RX 24
-#define MX2x_DMA_REQ_UART2_TX 25
-#define MX2x_DMA_REQ_UART1_RX 26
-#define MX2x_DMA_REQ_UART1_TX 27
-#define MX2x_DMA_REQ_CSI_STAT 30
-#define MX2x_DMA_REQ_CSI_RX 31
-
-#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx31.h b/arch/arm/mach-imx/include/mach/mx31.h
deleted file mode 100644
index ee9b1f9215d..00000000000
--- a/arch/arm/mach-imx/include/mach/mx31.h
+++ /dev/null
@@ -1,196 +0,0 @@
-#ifndef __MACH_MX31_H__
-#define __MACH_MX31_H__
-
-/*
- * IRAM
- */
-#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
-#define MX31_IRAM_SIZE SZ_16K
-
-#define MX31_L2CC_BASE_ADDR 0x30000000
-#define MX31_L2CC_SIZE SZ_1M
-
-#define MX31_AIPS1_BASE_ADDR 0x43f00000
-#define MX31_AIPS1_SIZE SZ_1M
-#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
-#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
-#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
-#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
-#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
-#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
-#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
-#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
-#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
-#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
-#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
-#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
-#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
-#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
-#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
-#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
-#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
-#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
-#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
-#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
-#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
-#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
-#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
-#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
-
-#define MX31_SPBA0_BASE_ADDR 0x50000000
-#define MX31_SPBA0_SIZE SZ_1M
-#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
-#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
-#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
-#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
-#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
-#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
-#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
-#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
-#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
-
-#define MX31_AIPS2_BASE_ADDR 0x53f00000
-#define MX31_AIPS2_SIZE SZ_1M
-#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
-#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
-#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
-#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
-#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
-#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
-#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
-#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
-#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
-#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
-#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
-#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
-#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
-#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
-#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
-#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
-#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
-#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
-#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
-#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
-#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
-
-#define MX31_ROMP_BASE_ADDR 0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
-#define MX31_ROMP_SIZE SZ_1M
-
-#define MX31_AVIC_BASE_ADDR 0x68000000
-#define MX31_AVIC_SIZE SZ_1M
-
-#define MX31_IPU_MEM_BASE_ADDR 0x70000000
-#define MX31_CSD0_BASE_ADDR 0x80000000
-#define MX31_CSD1_BASE_ADDR 0x90000000
-
-#define MX31_CS0_BASE_ADDR 0xa0000000
-#define MX31_CS1_BASE_ADDR 0xa8000000
-#define MX31_CS2_BASE_ADDR 0xb0000000
-#define MX31_CS3_BASE_ADDR 0xb2000000
-
-#define MX31_CS4_BASE_ADDR 0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
-#define MX31_CS4_SIZE SZ_32M
-
-#define MX31_CS5_BASE_ADDR 0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
-#define MX31_CS5_SIZE SZ_32M
-
-#define MX31_X_MEMC_BASE_ADDR 0xb8000000
-#define MX31_X_MEMC_SIZE SZ_64K
-#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
-#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
-#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
-#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
-#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
-#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
-
-#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
-
-#define MX31_IO_P2V(x) IMX_IO_P2V(x)
-#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
-#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
-#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
-#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
-#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
-#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
-#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
-#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
-#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
-#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
-#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
-#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
-#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
-#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
-#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
-#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
-#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
-#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
-#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
-#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
-#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
-#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
-#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
-#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
-#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
-#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
-#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
-#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
-#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
-#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
-#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
-#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
-#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
-#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
-#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
-#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
-#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
-#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
-#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
-#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
-#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
-#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
-#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
-#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
-#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
-#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
-#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
-
-#define MX31_DMA_REQ_SDHC1 20
-#define MX31_DMA_REQ_SDHC2 21
-#define MX31_DMA_REQ_SSI2_RX1 22
-#define MX31_DMA_REQ_SSI2_TX1 23
-#define MX31_DMA_REQ_SSI2_RX0 24
-#define MX31_DMA_REQ_SSI2_TX0 25
-#define MX31_DMA_REQ_SSI1_RX1 26
-#define MX31_DMA_REQ_SSI1_TX1 27
-#define MX31_DMA_REQ_SSI1_RX0 28
-#define MX31_DMA_REQ_SSI1_TX0 29
-
-#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
-
-#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx35.h b/arch/arm/mach-imx/include/mach/mx35.h
deleted file mode 100644
index 2af5d3a699c..00000000000
--- a/arch/arm/mach-imx/include/mach/mx35.h
+++ /dev/null
@@ -1,190 +0,0 @@
-#ifndef __MACH_MX35_H__
-#define __MACH_MX35_H__
-
-/*
- * IRAM
- */
-#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
-#define MX35_IRAM_SIZE SZ_128K
-
-#define MX35_L2CC_BASE_ADDR 0x30000000
-#define MX35_L2CC_SIZE SZ_1M
-
-#define MX35_AIPS1_BASE_ADDR 0x43f00000
-#define MX35_AIPS1_SIZE SZ_1M
-#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
-#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
-#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
-#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
-#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
-#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
-#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
-#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
-#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
-#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
-#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
-#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
-#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
-#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
-#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
-#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
-#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
-
-#define MX35_SPBA0_BASE_ADDR 0x50000000
-#define MX35_SPBA0_SIZE SZ_1M
-#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
-#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
-#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
-#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
-#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
-#define MX35_FEC_BASE_ADDR 0x50038000
-#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
-
-#define MX35_AIPS2_BASE_ADDR 0x53f00000
-#define MX35_AIPS2_SIZE SZ_1M
-#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
-#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
-#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
-#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
-#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
-#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
-#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
-#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
-#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
-#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
-#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
-#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
-#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
-#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
-#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
-#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
-#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
-#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
-#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
-#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
-#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
-#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
-#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
-#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
-/*
- * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
- * HS. When host support was implemented only a preliminary document was
- * available, which told 0x400. This works fine.
- */
-#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
-
-#define MX35_ROMP_BASE_ADDR 0x60000000
-#define MX35_ROMP_SIZE SZ_1M
-
-#define MX35_AVIC_BASE_ADDR 0x68000000
-#define MX35_AVIC_SIZE SZ_1M
-
-/*
- * Memory regions and CS
- */
-#define MX35_IPU_MEM_BASE_ADDR 0x70000000
-#define MX35_CSD0_BASE_ADDR 0x80000000
-#define MX35_CSD1_BASE_ADDR 0x90000000
-
-#define MX35_CS0_BASE_ADDR 0xa0000000
-#define MX35_CS1_BASE_ADDR 0xa8000000
-#define MX35_CS2_BASE_ADDR 0xb0000000
-#define MX35_CS3_BASE_ADDR 0xb2000000
-
-#define MX35_CS4_BASE_ADDR 0xb4000000
-#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
-#define MX35_CS4_SIZE SZ_32M
-
-#define MX35_CS5_BASE_ADDR 0xb6000000
-#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
-#define MX35_CS5_SIZE SZ_32M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define MX35_X_MEMC_BASE_ADDR 0xb8000000
-#define MX35_X_MEMC_SIZE SZ_64K
-#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
-#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
-#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
-#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
-#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
-
-#define MX35_NFC_BASE_ADDR 0xbb000000
-#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
-
-#define MX35_IO_P2V(x) IMX_IO_P2V(x)
-#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
-#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
-#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
-#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
-#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
-#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
-#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
-#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
-#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
-#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
-#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
-#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
-#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
-#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
-#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
-#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
-#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
-#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
-#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
-#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
-#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
-#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
-#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
-#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
-#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
-#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
-#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
-#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
-#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
-#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
-#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
-#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
-#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
-#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
-#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
-#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
-#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
-#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
-#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
-#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
-#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
-#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
-#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
-#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
-
-#define MX35_DMA_REQ_SSI2_RX1 22
-#define MX35_DMA_REQ_SSI2_TX1 23
-#define MX35_DMA_REQ_SSI2_RX0 24
-#define MX35_DMA_REQ_SSI2_TX0 25
-#define MX35_DMA_REQ_SSI1_RX1 26
-#define MX35_DMA_REQ_SSI1_TX1 27
-#define MX35_DMA_REQ_SSI1_RX0 28
-#define MX35_DMA_REQ_SSI1_TX0 29
-
-#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
-
-#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx3x.h b/arch/arm/mach-imx/include/mach/mx3x.h
deleted file mode 100644
index 96fb4fbc8ad..00000000000
--- a/arch/arm/mach-imx/include/mach/mx3x.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MX3x_H__
-#define __MACH_MX3x_H__
-
-/*
- * MX31 memory map:
- *
- * Virt Phys Size What
- * ---------------------------------------------------------------------------
- * FC000000 43F00000 1M AIPS 1
- * FC100000 50000000 1M SPBA
- * FC200000 53F00000 1M AIPS 2
- * FC500000 60000000 128M ROMPATCH
- * FC400000 68000000 128M AVIC
- * 70000000 256M IPU (MAX M2)
- * 80000000 256M CSD0 SDRAM/DDR
- * 90000000 256M CSD1 SDRAM/DDR
- * A0000000 128M CS0 Flash
- * A8000000 128M CS1 Flash
- * B0000000 32M CS2
- * B2000000 32M CS3
- * F4000000 B4000000 32M CS4
- * B6000000 32M CS5
- * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
- * C0000000 64M PCMCIA/CF
- */
-
-/*
- * L2CC
- */
-#define MX3x_L2CC_BASE_ADDR 0x30000000
-#define MX3x_L2CC_SIZE SZ_1M
-
-/*
- * AIPS 1
- */
-#define MX3x_AIPS1_BASE_ADDR 0x43f00000
-#define MX3x_AIPS1_SIZE SZ_1M
-#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
-#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
-#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
-#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
-#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
-#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
-#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
-#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
-#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
-#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
-#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
-#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
-#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
-#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
-#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
-#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
-#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
-#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX3x_SPBA0_BASE_ADDR 0x50000000
-#define MX3x_SPBA0_SIZE SZ_1M
-#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
-#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
-#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
-#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
-#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
-#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
-
-/*
- * AIPS 2
- */
-#define MX3x_AIPS2_BASE_ADDR 0x53f00000
-#define MX3x_AIPS2_SIZE SZ_1M
-#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
-#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
-#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
-#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
-#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
-#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
-#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
-#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
-#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
-#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
-#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
-#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
-#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
-#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
-#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
-#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
-
-/*
- * ROMP and AVIC
- */
-#define MX3x_ROMP_BASE_ADDR 0x60000000
-#define MX3x_ROMP_SIZE SZ_1M
-
-#define MX3x_AVIC_BASE_ADDR 0x68000000
-#define MX3x_AVIC_SIZE SZ_1M
-
-/*
- * Memory regions and CS
- */
-#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
-#define MX3x_CSD0_BASE_ADDR 0x80000000
-#define MX3x_CSD1_BASE_ADDR 0x90000000
-
-#define MX3x_CS0_BASE_ADDR 0xa0000000
-#define MX3x_CS1_BASE_ADDR 0xa8000000
-#define MX3x_CS2_BASE_ADDR 0xb0000000
-#define MX3x_CS3_BASE_ADDR 0xb2000000
-
-#define MX3x_CS4_BASE_ADDR 0xb4000000
-#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
-#define MX3x_CS4_SIZE SZ_32M
-
-#define MX3x_CS5_BASE_ADDR 0xb6000000
-#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
-#define MX3x_CS5_SIZE SZ_32M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
-#define MX3x_X_MEMC_SIZE SZ_64K
-#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
-#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
-#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
-#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
-#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
-
-#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
-#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
-#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
-#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
-#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
-#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
-#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
-#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
-#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
-#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
-#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
-#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
-#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
-#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
-#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
-#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
-#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
-#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
-#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
-#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
-#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
-#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
-#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
-#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
-#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
-#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
-#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
-#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
-
-#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
-
-/* Mandatory defines used globally */
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx35_revision(void);
-extern int mx31_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx50.h b/arch/arm/mach-imx/include/mach/mx50.h
deleted file mode 100644
index 09ac19c1570..00000000000
--- a/arch/arm/mach-imx/include/mach/mx50.h
+++ /dev/null
@@ -1,290 +0,0 @@
-#ifndef __MACH_MX50_H__
-#define __MACH_MX50_H__
-
-/*
- * IROM
- */
-#define MX50_IROM_BASE_ADDR 0x0
-#define MX50_IROM_SIZE SZ_64K
-
-/* TZIC */
-#define MX50_TZIC_BASE_ADDR 0x0fffc000
-#define MX50_TZIC_SIZE SZ_16K
-
-/*
- * IRAM
- */
-#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
-#define MX50_IRAM_PARTITIONS 16
-#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
-
-/*
- * Databahn
- */
-#define MX50_DATABAHN_BASE_ADDR 0x14000000
-
-/*
- * Graphics Memory of GPU
- */
-#define MX50_GPU2D_BASE_ADDR 0x20000000
-
-#define MX50_DEBUG_BASE_ADDR 0x40000000
-#define MX50_DEBUG_SIZE SZ_1M
-#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
-#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
-#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
-#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
-#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
-#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
-#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
-#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
-
-#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
-#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
-#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
-#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
-#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
-#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
-#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
-#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
-#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
-#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
-#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
-#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
-#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
-#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX50_SPBA0_BASE_ADDR 0x50000000
-#define MX50_SPBA0_SIZE SZ_1M
-
-#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
-#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
-#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
-#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
-#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
-#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
-#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
-
-/*
- * AIPS 1
- */
-#define MX50_AIPS1_BASE_ADDR 0x53f00000
-#define MX50_AIPS1_SIZE SZ_1M
-
-#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
-#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
-#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
-#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
-#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
-#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
-#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
-#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
-#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
-#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
-#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
-#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
-#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
-#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
-#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
-#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
-#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
-#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
-#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
-#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
-#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
-#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
-
-#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
-#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
-
-/*
- * AIPS 2
- */
-#define MX50_AIPS2_BASE_ADDR 0x63f00000
-#define MX50_AIPS2_SIZE SZ_1M
-
-#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
-#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
-#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
-#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
-#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
-#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
-#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
-#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
-#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
-#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
-#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
-#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
-#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
-#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
-#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
-#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
-#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
-
-/*
- * Memory regions and CS
- */
-#define MX50_CSD0_BASE_ADDR 0x70000000
-#define MX50_CSD1_BASE_ADDR 0xb0000000
-#define MX50_CS0_BASE_ADDR 0xf0000000
-
-#define MX50_IO_P2V(x) IMX_IO_P2V(x)
-#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX50_SPBA_SDHC1 0x04
-#define MX50_SPBA_SDHC2 0x08
-#define MX50_SPBA_UART3 0x0c
-#define MX50_SPBA_CSPI1 0x10
-#define MX50_SPBA_SSI2 0x14
-#define MX50_SPBA_SDHC3 0x20
-#define MX50_SPBA_SDHC4 0x24
-#define MX50_SPBA_SPDIF 0x28
-#define MX50_SPBA_ATA 0x30
-#define MX50_SPBA_SLIM 0x34
-#define MX50_SPBA_HSI2C 0x38
-#define MX50_SPBA_CTRL 0x3c
-
-/*
- * DMA request assignments
- */
-#define MX50_DMA_REQ_GPC 1
-#define MX50_DMA_REQ_ATA_UART4_RX 2
-#define MX50_DMA_REQ_ATA_UART4_TX 3
-#define MX50_DMA_REQ_CSPI1_RX 6
-#define MX50_DMA_REQ_CSPI1_TX 7
-#define MX50_DMA_REQ_CSPI2_RX 8
-#define MX50_DMA_REQ_CSPI2_TX 9
-#define MX50_DMA_REQ_I2C3_SDHC3 10
-#define MX50_DMA_REQ_SDHC4 11
-#define MX50_DMA_REQ_UART2_FIRI_RX 12
-#define MX50_DMA_REQ_UART2_FIRI_TX 13
-#define MX50_DMA_REQ_EXT0 14
-#define MX50_DMA_REQ_EXT1 15
-#define MX50_DMA_REQ_UART5_RX 16
-#define MX50_DMA_REQ_UART5_TX 17
-#define MX50_DMA_REQ_UART1_RX 18
-#define MX50_DMA_REQ_UART1_TX 19
-#define MX50_DMA_REQ_I2C1_SDHC1 20
-#define MX50_DMA_REQ_I2C2_SDHC2 21
-#define MX50_DMA_REQ_SSI2_RX2 22
-#define MX50_DMA_REQ_SSI2_TX2 23
-#define MX50_DMA_REQ_SSI2_RX1 24
-#define MX50_DMA_REQ_SSI2_TX1 25
-#define MX50_DMA_REQ_SSI1_RX2 26
-#define MX50_DMA_REQ_SSI1_TX2 27
-#define MX50_DMA_REQ_SSI1_RX1 28
-#define MX50_DMA_REQ_SSI1_TX1 29
-#define MX50_DMA_REQ_CSPI_RX 38
-#define MX50_DMA_REQ_CSPI_TX 39
-#define MX50_DMA_REQ_UART3_RX 42
-#define MX50_DMA_REQ_UART3_TX 43
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
-#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
-#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
-#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
-#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
-#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
-#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
-#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
-#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
-#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
-#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
-#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
-#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
-#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
-#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
-#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
-#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
-#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
-#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
-#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
-#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
-#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
-#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
-#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
-#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
-#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
-#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
-#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
-#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
-#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
-#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
-#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
-#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
-#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
-#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
-#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
-#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
-#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
-#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
-#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
-#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
-#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
-#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
-#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
-#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
-#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
-#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
-#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
-#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
-#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
-#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
-#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
-#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
-#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
-#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
-#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
-#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
-#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
-#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
-#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
-#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
-#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
-#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
-#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
-#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
-#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
-#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
-#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
-#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
-#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
-#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
-#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
-#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
-#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
-#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
-#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
-#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
-#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
-#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
-#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
-#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
-#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
-#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
-#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
-#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
-#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
-#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
-#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
-#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
-#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
-#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
-#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx50_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx51.h b/arch/arm/mach-imx/include/mach/mx51.h
deleted file mode 100644
index af844f76261..00000000000
--- a/arch/arm/mach-imx/include/mach/mx51.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef __MACH_MX51_H__
-#define __MACH_MX51_H__
-
-/*
- * IROM
- */
-#define MX51_IROM_BASE_ADDR 0x0
-#define MX51_IROM_SIZE SZ_64K
-
-/*
- * IRAM
- */
-#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
-#define MX51_IRAM_PARTITIONS 16
-#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
-
-#define MX51_GPU_BASE_ADDR 0x20000000
-#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
-
-/*
- * SPBA global module enabled #0
- */
-#define MX51_SPBA0_BASE_ADDR 0x70000000
-#define MX51_SPBA0_SIZE SZ_1M
-
-#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
-#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
-#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
-#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
-#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
-#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
-#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
-#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
-#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
-#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
-#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
-#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR 0x73f00000
-#define MX51_AIPS1_SIZE SZ_1M
-
-#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
-#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000)
-#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200)
-#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400)
-#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
-#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
-#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
-#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
-#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
-#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
-#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
-#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
-#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
-#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
-#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
-#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
-#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
-#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
-#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
-#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
-#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
-#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
-#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
-
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR 0x83f00000
-#define MX51_AIPS2_SIZE SZ_1M
-
-#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
-#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
-#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
-#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
-#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
-#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
-#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
-#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
-#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
-#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
-#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
-#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
-#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
-#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
-#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
-#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
-#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
-#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
-#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
-#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
-#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
-#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
-#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
-#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
-#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
-#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
-#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
-#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
-#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
-#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
-#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
-#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
-
-#define MX51_CSD0_BASE_ADDR 0x90000000
-#define MX51_CSD1_BASE_ADDR 0xa0000000
-#define MX51_CS0_BASE_ADDR 0xb0000000
-#define MX51_CS1_BASE_ADDR 0xb8000000
-#define MX51_CS2_BASE_ADDR 0xc0000000
-#define MX51_CS3_BASE_ADDR 0xc8000000
-#define MX51_CS4_BASE_ADDR 0xcc000000
-#define MX51_CS5_BASE_ADDR 0xce000000
-
-/*
- * NFC
- */
-#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE SZ_64K
-
-#define MX51_GPU2D_BASE_ADDR 0xd0000000
-#define MX51_TZIC_BASE_ADDR 0xe0000000
-#define MX51_TZIC_SIZE SZ_16K
-
-#define MX51_IO_P2V(x) IMX_IO_P2V(x)
-#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX51_SPBA_SDHC1 0x04
-#define MX51_SPBA_SDHC2 0x08
-#define MX51_SPBA_UART3 0x0c
-#define MX51_SPBA_CSPI1 0x10
-#define MX51_SPBA_SSI2 0x14
-#define MX51_SPBA_SDHC3 0x20
-#define MX51_SPBA_SDHC4 0x24
-#define MX51_SPBA_SPDIF 0x28
-#define MX51_SPBA_ATA 0x30
-#define MX51_SPBA_SLIM 0x34
-#define MX51_SPBA_HSI2C 0x38
-#define MX51_SPBA_CTRL 0x3c
-
-/*
- * Defines for modules using static and dynamic DMA channels
- */
-#define MX51_MXC_DMA_CHANNEL_IRAM 30
-#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
-#ifdef CONFIG_SDMA_IRAM
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
-#else /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
-#endif /*CONFIG_SDMA_IRAM */
-#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
-#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
-
-#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
-
-/*
- * DMA request assignments
- */
-#define MX51_DMA_REQ_VPU 0
-#define MX51_DMA_REQ_GPC 1
-#define MX51_DMA_REQ_ATA_RX 2
-#define MX51_DMA_REQ_ATA_TX 3
-#define MX51_DMA_REQ_ATA_TX_END 4
-#define MX51_DMA_REQ_SLIM_B 5
-#define MX51_DMA_REQ_CSPI1_RX 6
-#define MX51_DMA_REQ_CSPI1_TX 7
-#define MX51_DMA_REQ_CSPI2_RX 8
-#define MX51_DMA_REQ_CSPI2_TX 9
-#define MX51_DMA_REQ_HS_I2C_TX 10
-#define MX51_DMA_REQ_HS_I2C_RX 11
-#define MX51_DMA_REQ_FIRI_RX 12
-#define MX51_DMA_REQ_FIRI_TX 13
-#define MX51_DMA_REQ_EXTREQ1 14
-#define MX51_DMA_REQ_GPU 15
-#define MX51_DMA_REQ_UART2_RX 16
-#define MX51_DMA_REQ_UART2_TX 17
-#define MX51_DMA_REQ_UART1_RX 18
-#define MX51_DMA_REQ_UART1_TX 19
-#define MX51_DMA_REQ_SDHC1 20
-#define MX51_DMA_REQ_SDHC2 21
-#define MX51_DMA_REQ_SSI2_RX1 22
-#define MX51_DMA_REQ_SSI2_TX1 23
-#define MX51_DMA_REQ_SSI2_RX0 24
-#define MX51_DMA_REQ_SSI2_TX0 25
-#define MX51_DMA_REQ_SSI1_RX1 26
-#define MX51_DMA_REQ_SSI1_TX1 27
-#define MX51_DMA_REQ_SSI1_RX0 28
-#define MX51_DMA_REQ_SSI1_TX0 29
-#define MX51_DMA_REQ_EMI_RD 30
-#define MX51_DMA_REQ_CTI2_0 31
-#define MX51_DMA_REQ_EMI_WR 32
-#define MX51_DMA_REQ_CTI2_1 33
-#define MX51_DMA_REQ_EPIT2 34
-#define MX51_DMA_REQ_SSI3_RX1 35
-#define MX51_DMA_REQ_IPU 36
-#define MX51_DMA_REQ_SSI3_TX1 37
-#define MX51_DMA_REQ_CSPI_RX 38
-#define MX51_DMA_REQ_CSPI_TX 39
-#define MX51_DMA_REQ_SDHC3 40
-#define MX51_DMA_REQ_SDHC4 41
-#define MX51_DMA_REQ_SLIM_B_TX 42
-#define MX51_DMA_REQ_UART3_RX 43
-#define MX51_DMA_REQ_UART3_TX 44
-#define MX51_DMA_REQ_SPDIF 45
-#define MX51_DMA_REQ_SSI3_RX0 46
-#define MX51_DMA_REQ_SSI3_TX0 47
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
-#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
-#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
-#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
-#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
-#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
-#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
-#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
-#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
-#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
-#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
-#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
-#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
-#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
-#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
-#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
-#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
-#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
-#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
-#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
-#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
-#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
-#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
-#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
-#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
-#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
-#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
-#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
-#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
-#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
-#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
-#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
-#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
-#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
-#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
-#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
-#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
-#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
-#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
-#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
-#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
-#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
-#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
-#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
-#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
-#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
-#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
-#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
-#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
-#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
-#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
-#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
-#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
-#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
-#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
-#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
-#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
-#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
-#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
-#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
-#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
-#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
-#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
-#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
-#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
-#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
-#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
-#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
-#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
-#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
-#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
-#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
-#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
-#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
-#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
-#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
-#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
-#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
-#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
-#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
-#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
-#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
-#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
-#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
-#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
-#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
-#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
-#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
-#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
-#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
-#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
-#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
-#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
-#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
-#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
-#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
-#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
-#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
-#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
-#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
-#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
-#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
-#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
-
-#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx51_revision(void);
-extern void mx51_display_revision(void);
-#endif
-
-#endif /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx53.h b/arch/arm/mach-imx/include/mach/mx53.h
deleted file mode 100644
index f829d1c2250..00000000000
--- a/arch/arm/mach-imx/include/mach/mx53.h
+++ /dev/null
@@ -1,342 +0,0 @@
-#ifndef __MACH_MX53_H__
-#define __MACH_MX53_H__
-
-/*
- * IROM
- */
-#define MX53_IROM_BASE_ADDR 0x0
-#define MX53_IROM_SIZE SZ_64K
-
-/* TZIC */
-#define MX53_TZIC_BASE_ADDR 0x0FFFC000
-#define MX53_TZIC_SIZE SZ_16K
-
-/*
- * AHCI SATA
- */
-#define MX53_SATA_BASE_ADDR 0x10000000
-
-/*
- * NFC
- */
-#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
-#define MX53_NFC_AXI_SIZE SZ_64K
-
-/*
- * IRAM
- */
-#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
-#define MX53_IRAM_PARTITIONS 16
-#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
-
-/*
- * Graphics Memory of GPU
- */
-#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
-#define MX53_GPU2D_BASE_ADDR 0x20000000
-#define MX53_GPU_BASE_ADDR 0x30000000
-#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
-
-#define MX53_DEBUG_BASE_ADDR 0x40000000
-#define MX53_DEBUG_SIZE SZ_1M
-#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
-#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
-#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
-#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
-#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
-#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
-#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
-#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define MX53_SPBA0_BASE_ADDR 0x50000000
-#define MX53_SPBA0_SIZE SZ_1M
-
-#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
-#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
-#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
-#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
-#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
-#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
-#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
-#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
-#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
-#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
-#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
-#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define MX53_AIPS1_BASE_ADDR 0x53F00000
-#define MX53_AIPS1_SIZE SZ_1M
-
-#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
-#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
-#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
-#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
-#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
-#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
-#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
-#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
-#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
-#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
-#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
-#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
-#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
-
-/*
- * AIPS 2
- */
-#define MX53_AIPS2_BASE_ADDR 0x63F00000
-#define MX53_AIPS2_SIZE SZ_1M
-
-#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
-#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
-#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
-#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
-#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
-#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
-#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
-#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
-#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
-#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
-
-/*
- * Memory regions and CS
- */
-#define MX53_CSD0_BASE_ADDR 0x70000000
-#define MX53_CSD1_BASE_ADDR 0xB0000000
-#define MX53_CS0_BASE_ADDR 0xF0000000
-#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
-#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
-#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
-#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
-#define MX53_CS3_BASE_ADDR 0xF6000000
-
-#define MX53_IO_P2V(x) IMX_IO_P2V(x)
-#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
-
-/*
- * defines for SPBA modules
- */
-#define MX53_SPBA_SDHC1 0x04
-#define MX53_SPBA_SDHC2 0x08
-#define MX53_SPBA_UART3 0x0C
-#define MX53_SPBA_CSPI1 0x10
-#define MX53_SPBA_SSI2 0x14
-#define MX53_SPBA_SDHC3 0x20
-#define MX53_SPBA_SDHC4 0x24
-#define MX53_SPBA_SPDIF 0x28
-#define MX53_SPBA_ATA 0x30
-#define MX53_SPBA_SLIM 0x34
-#define MX53_SPBA_HSI2C 0x38
-#define MX53_SPBA_CTRL 0x3C
-
-/*
- * DMA request assignments
- */
-#define MX53_DMA_REQ_SSI3_TX0 47
-#define MX53_DMA_REQ_SSI3_RX0 46
-#define MX53_DMA_REQ_SSI3_TX1 45
-#define MX53_DMA_REQ_SSI3_RX1 44
-#define MX53_DMA_REQ_UART3_TX 43
-#define MX53_DMA_REQ_UART3_RX 42
-#define MX53_DMA_REQ_ESAI_TX 41
-#define MX53_DMA_REQ_ESAI_RX 40
-#define MX53_DMA_REQ_CSPI_TX 39
-#define MX53_DMA_REQ_CSPI_RX 38
-#define MX53_DMA_REQ_ASRC_DMA6 37
-#define MX53_DMA_REQ_ASRC_DMA5 36
-#define MX53_DMA_REQ_ASRC_DMA4 35
-#define MX53_DMA_REQ_ASRC_DMA3 34
-#define MX53_DMA_REQ_ASRC_DMA2 33
-#define MX53_DMA_REQ_ASRC_DMA1 32
-#define MX53_DMA_REQ_EMI_WR 31
-#define MX53_DMA_REQ_EMI_RD 30
-#define MX53_DMA_REQ_SSI1_TX0 29
-#define MX53_DMA_REQ_SSI1_RX0 28
-#define MX53_DMA_REQ_SSI1_TX1 27
-#define MX53_DMA_REQ_SSI1_RX1 26
-#define MX53_DMA_REQ_SSI2_TX0 25
-#define MX53_DMA_REQ_SSI2_RX0 24
-#define MX53_DMA_REQ_SSI2_TX1 23
-#define MX53_DMA_REQ_SSI2_RX1 22
-#define MX53_DMA_REQ_I2C2_SDHC2 21
-#define MX53_DMA_REQ_I2C1_SDHC1 20
-#define MX53_DMA_REQ_UART1_TX 19
-#define MX53_DMA_REQ_UART1_RX 18
-#define MX53_DMA_REQ_UART5_TX 17
-#define MX53_DMA_REQ_UART5_RX 16
-#define MX53_DMA_REQ_SPDIF_TX 15
-#define MX53_DMA_REQ_SPDIF_RX 14
-#define MX53_DMA_REQ_UART2_FIRI_TX 13
-#define MX53_DMA_REQ_UART2_FIRI_RX 12
-#define MX53_DMA_REQ_SDHC4 11
-#define MX53_DMA_REQ_I2C3_SDHC3 10
-#define MX53_DMA_REQ_CSPI2_TX 9
-#define MX53_DMA_REQ_CSPI2_RX 8
-#define MX53_DMA_REQ_CSPI1_TX 7
-#define MX53_DMA_REQ_CSPI1_RX 6
-#define MX53_DMA_REQ_IPU 5
-#define MX53_DMA_REQ_ATA_TX_END 4
-#define MX53_DMA_REQ_ATA_UART4_TX 3
-#define MX53_DMA_REQ_ATA_UART4_RX 2
-#define MX53_DMA_REQ_GPC 1
-#define MX53_DMA_REQ_VPU 0
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
-#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
-#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
-#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
-#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
-#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
-#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
-#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
-#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
-#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
-#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
-#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
-#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
-#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
-#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
-#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
-#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
-#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
-#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
-#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
-#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
-#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
-#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
-#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
-#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
-#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
-#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
-#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
-#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
-#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
-#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
-#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
-#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
-#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
-#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
-#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
-#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
-#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
-#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
-#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
-#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
-#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
-#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
-#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
-#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
-#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
-#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
-#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
-#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
-#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
-#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
-#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
-#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
-#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
-#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
-#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
-#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
-#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
-#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
-#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
-#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
-#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
-#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
-#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
-#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
-#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
-#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
-#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
-#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
-#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
-#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
-#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
-#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
-#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
-#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
-#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
-#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
-#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
-#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
-#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
-#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
-#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
-#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
-#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
-#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
-#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
-#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
-#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
-#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
-#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
-#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
-#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
-#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
-#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
-#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
-#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
-#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
-#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
-#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
-#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
-#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
-#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
-#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
-#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
-#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
-#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
-#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
-
-#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mx6q.h b/arch/arm/mach-imx/include/mach/mx6q.h
deleted file mode 100644
index f7e7dbac8f4..00000000000
--- a/arch/arm/mach-imx/include/mach/mx6q.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_MX6Q_H__
-#define __MACH_MX6Q_H__
-
-#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
-#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
-
-/*
- * The following are the blocks that need to be statically mapped.
- * For other blocks, the base address really should be retrieved from
- * device tree.
- */
-#define MX6Q_SCU_BASE_ADDR 0x00a00000
-#define MX6Q_SCU_SIZE 0x1000
-#define MX6Q_CCM_BASE_ADDR 0x020c4000
-#define MX6Q_CCM_SIZE 0x4000
-#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
-#define MX6Q_ANATOP_SIZE 0x1000
-#define MX6Q_UART2_BASE_ADDR 0x021e8000
-#define MX6Q_UART2_SIZE 0x4000
-#define MX6Q_UART4_BASE_ADDR 0x021f0000
-#define MX6Q_UART4_SIZE 0x4000
-
-#endif /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/include/mach/mxc.h b/arch/arm/mach-imx/include/mach/mxc.h
deleted file mode 100644
index d78298366a9..00000000000
--- a/arch/arm/mach-imx/include/mach/mxc.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_H__
-#define __ASM_ARCH_MXC_H__
-
-#include <linux/types.h>
-
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
-#define MXC_CPU_MX1 1
-#define MXC_CPU_MX21 21
-#define MXC_CPU_MX25 25
-#define MXC_CPU_MX27 27
-#define MXC_CPU_MX31 31
-#define MXC_CPU_MX35 35
-#define MXC_CPU_MX50 50
-#define MXC_CPU_MX51 51
-#define MXC_CPU_MX53 53
-
-#define IMX_CHIP_REVISION_1_0 0x10
-#define IMX_CHIP_REVISION_1_1 0x11
-#define IMX_CHIP_REVISION_1_2 0x12
-#define IMX_CHIP_REVISION_1_3 0x13
-#define IMX_CHIP_REVISION_2_0 0x20
-#define IMX_CHIP_REVISION_2_1 0x21
-#define IMX_CHIP_REVISION_2_2 0x22
-#define IMX_CHIP_REVISION_2_3 0x23
-#define IMX_CHIP_REVISION_3_0 0x30
-#define IMX_CHIP_REVISION_3_1 0x31
-#define IMX_CHIP_REVISION_3_2 0x32
-#define IMX_CHIP_REVISION_3_3 0x33
-#define IMX_CHIP_REVISION_UNKNOWN 0xff
-
-#ifndef __ASSEMBLY__
-extern unsigned int __mxc_cpu_type;
-#endif
-
-#ifdef CONFIG_SOC_IMX1
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX1
-# endif
-# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
-#else
-# define cpu_is_mx1() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX21
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX21
-# endif
-# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
-#else
-# define cpu_is_mx21() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX25
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX25
-# endif
-# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
-#else
-# define cpu_is_mx25() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX27
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX27
-# endif
-# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
-#else
-# define cpu_is_mx27() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX31
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX31
-# endif
-# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
-#else
-# define cpu_is_mx31() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX35
-# endif
-# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
-#else
-# define cpu_is_mx35() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX50
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX50
-# endif
-# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
-#else
-# define cpu_is_mx50() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX51
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX51
-# endif
-# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
-#else
-# define cpu_is_mx51() (0)
-#endif
-
-#ifdef CONFIG_SOC_IMX53
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MX53
-# endif
-# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
-#else
-# define cpu_is_mx53() (0)
-#endif
-
-#ifndef __ASSEMBLY__
-
-struct cpu_op {
- u32 cpu_rate;
-};
-
-int tzic_enable_wake(void);
-
-extern struct cpu_op *(*get_cpu_op)(int *op);
-#endif
-
-#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
-#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
-
-#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 7c3ba2b5364..cabefbc5e7c 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -22,8 +22,8 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>
-#include <mach/hardware.h>
+#include "hardware.h"
#include "iomux-mx3.h"
/*
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index 2ac5580ede3..2b156d1d9e2 100644
--- a/arch/arm/mach-imx/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -28,9 +28,9 @@
#include <linux/string.h>
#include <linux/gpio.h>
-#include <mach/hardware.h>
#include <asm/mach/map.h>
+#include "hardware.h"
#include "iomux-v1.h"
static void __iomem *imx_iomuxv1_baseaddr;
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index de1459c57a9..9dae74bf47f 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -25,9 +25,9 @@
#include <linux/string.h>
#include <linux/gpio.h>
-#include <mach/hardware.h>
#include <asm/mach/map.h>
+#include "hardware.h"
#include "iomux-v3.h"
static void __iomem *base;
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index c40a34c0048..5f1510363ee 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -14,7 +14,8 @@
#include <asm/page.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
+
+#include "hardware.h"
static struct map_desc imx_lluart_desc = {
#ifdef CONFIG_DEBUG_IMX6Q_UART2
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index a0b4c3fd289..5c9bd2c66e6 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -25,10 +25,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx1.h"
+#include "hardware.h"
#include "iomux-mx1.h"
static const int apf9328_pins[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index afa991b7d66..59bd6b06a6b 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -41,7 +41,6 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@@ -51,6 +50,7 @@
#include "common.h"
#include "devices-imx31.h"
#include "crmregs-imx3.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index b98e982918f..3a39d5aec07 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -19,14 +19,13 @@
#include <linux/init.h>
#include <linux/platform_device.h>
-#include <mach/hardware.h>
-
#include <asm/mach/time.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 37571f304c5..12a370646b4 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -34,11 +34,10 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx27.h"
#include "eukrea-baseboards.h"
+#include "hardware.h"
#include "iomux-mx27.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 86d4ac90ea6..5a31bf8c8f4 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -37,11 +37,10 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx35.h"
#include "eukrea-baseboards.h"
+#include "hardware.h"
#include "iomux-mx35.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 58ad093d059..b727de029c8 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -26,8 +26,6 @@
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>
-#include <mach/hardware.h>
-
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -37,6 +35,7 @@
#include "devices-imx51.h"
#include "cpu_op-mx51.h"
#include "eukrea-baseboards.h"
+#include "hardware.h"
#include "iomux-mx51.h"
#define USBH1_RST IMX_GPIO_NR(2, 28)
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index e754b0cbfd8..75027a5ad8b 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -27,18 +27,18 @@
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <mach/mx25.h>
#include "common.h"
#include "devices-imx25.h"
#include "eukrea-baseboards.h"
+#include "hardware.h"
#include "iomux-mx25.h"
+#include "mx25.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index ec33607ebb6..b7442267912 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -40,10 +40,10 @@
#include <asm/mach/time.h>
#include <asm/system_info.h>
#include <asm/memblock.h>
-#include <mach/hardware.h>
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
#define TVP5150_RSTN (GPIO_PORTC + 18)
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 725a87fdf13..53a86011293 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -17,8 +17,8 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
+#include "hardware.h"
#include "common.h"
#include "devices-imx27.h"
#include "iomux-mx27.h"
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index ec460301103..fc8dce93137 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -20,10 +20,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
static const int mx27lite_pins[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 0e0aadfb625..e71e62610eb 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -19,9 +19,9 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/mx53.h>
#include "common.h"
+#include "mx53.h"
/*
* Lookup table for attaching a specific name and platform_data pointer to
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index c0245abdd95..978b6dd00de 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -33,10 +33,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
-#include <mach/hardware.h>
#include "common.h"
#include "cpuidle.h"
+#include "hardware.h"
void imx6q_restart(char mode, const char *cmd)
{
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 7b973dcba93..2e536ea5344 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,10 +36,9 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 8be62f3559b..06b483783e6 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -23,10 +23,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx1.h"
+#include "hardware.h"
#include "iomux-mx1.h"
static const int mx1ads_pins[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 99adc9f893d..6adb3136bb0 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -18,7 +18,6 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@@ -26,6 +25,7 @@
#include "common.h"
#include "devices-imx21.h"
+#include "hardware.h"
#include "iomux-mx21.h"
/*
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 5a17dd66c05..b1b03aa55bb 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -31,17 +31,17 @@
#include <linux/platform_device.h>
#include <linux/usb/otg.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <mach/mx25.h>
#include "common.h"
#include "devices-imx25.h"
+#include "hardware.h"
#include "iomux-mx25.h"
+#include "mx25.h"
#define MX25PDK_CAN_PWDN IMX_GPIO_NR(4, 6)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index a54df771c23..d0e547fa925 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -36,11 +36,11 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
#include "3ds_debugboard.h"
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index beb281c250f..3d036f57f0e 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -21,7 +21,6 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@@ -29,6 +28,7 @@
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
/*
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 0333567ca5a..bc301befdd0 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -30,7 +30,6 @@
#include <media/soc_camera.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@@ -41,6 +40,7 @@
#include "3ds_debugboard.h"
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index deb89d2cc1b..8b56f8883f3 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -28,7 +28,6 @@
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#include <linux/mfd/wm8350/audio.h>
@@ -38,6 +37,7 @@
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
/* Base address of PBC controller */
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 74b5fa9bc66..08b9965c8b3 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -42,11 +42,10 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "board-mx31lilly.h"
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 6d6b6985403..bdcd92e5951 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -39,11 +39,10 @@
#include <asm/page.h>
#include <asm/setup.h>
-#include <mach/hardware.h>
-
#include "board-mx31lite.h"
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 31c7d05cc33..2517cfa9f26 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -42,12 +42,12 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
-#include <mach/hardware.h>
#include <linux/platform_data/asoc-imx-ssi.h>
#include "board-mx31moboard.h"
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index ee7d0375c70..5277da45d60 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -43,7 +43,6 @@
#include <asm/mach/map.h>
#include <asm/memblock.h>
-#include <mach/hardware.h>
#include <video/platform_lcd.h>
#include <media/soc_camera.h>
@@ -51,6 +50,7 @@
#include "3ds_debugboard.h"
#include "common.h"
#include "devices-imx35.h"
+#include "hardware.h"
#include "iomux-mx35.h"
#define GPIO_MC9S08DZ60_GPS_ENABLE 0
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
index 4a3e98e3779..0c1f88a80bd 100644
--- a/arch/arm/mach-imx/mach-mx50_rdp.c
+++ b/arch/arm/mach-imx/mach-mx50_rdp.c
@@ -24,8 +24,6 @@
#include <linux/delay.h>
#include <linux/io.h>
-#include <mach/hardware.h>
-
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
@@ -34,6 +32,7 @@
#include "common.h"
#include "devices-imx50.h"
+#include "hardware.h"
#include "iomux-mx50.h"
#define FEC_EN IMX_GPIO_NR(6, 23)
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 476c759216b..abc25bd1107 100644
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
@@ -19,11 +19,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
#include "3ds_debugboard.h"
#include "common.h"
#include "devices-imx51.h"
+#include "hardware.h"
#include "iomux-mx51.h"
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 383948a1717..d9a84ca2199 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -20,8 +20,6 @@
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
-#include <mach/hardware.h>
-
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -30,6 +28,7 @@
#include "common.h"
#include "devices-imx51.h"
#include "cpu_op-mx51.h"
+#include "hardware.h"
#include "iomux-mx51.h"
#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index f1cbe03a446..f4a8c7e108e 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -21,7 +21,6 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/irq.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@@ -31,6 +30,7 @@
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
static const int mxt_td60_pins[] __initconst = {
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 743d7e94f53..eee369fa94a 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -32,11 +32,11 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
-#include <mach/hardware.h>
#include <asm/mach/time.h>
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 525f057a11a..547fef133f6 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -42,10 +42,10 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>
-#include <mach/hardware.h>
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "pcm037.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 8bf95f5741c..4aa0d079860 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -33,11 +33,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
#include "board-pcm038.h"
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 54ac94770b7..92445440221 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -33,10 +33,9 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx35.h"
+#include "hardware.h"
#include "iomux-mx35.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 962988a8cfa..96d9a91f8a3 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -21,7 +21,6 @@
#include <linux/mtd/nand.h>
#include <linux/gpio.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
@@ -31,6 +30,7 @@
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
/* FPGA defines */
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index c4917565871..fc970409dba 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -20,10 +20,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx1.h"
+#include "hardware.h"
#include "iomux-mx1.h"
/*
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 288a920ad64..3aecf91e428 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -28,14 +28,13 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
-
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/mfd/mc13xxx.h>
#include "common.h"
#include "devices-imx35.h"
+#include "hardware.h"
#include "iomux-mx35.h"
#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 79f6c0b8f69..7a146671e65 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -22,10 +22,9 @@
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices/devices-common.h"
+#include "hardware.h"
#include "iomux-v1.h"
static struct map_desc imx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 3b97ea63b5f..8868398737c 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -21,12 +21,12 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/pinctrl/machine.h>
-#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices/devices-common.h"
+#include "hardware.h"
#include "iomux-v1.h"
/* MX21 memory map definition */
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index a08a960de23..9be33cda2e2 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -24,12 +24,11 @@
#include <asm/pgtable.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/mx25.h>
-
#include "common.h"
#include "devices/devices-common.h"
+#include "hardware.h"
#include "iomux-v3.h"
+#include "mx25.h"
/*
* This table defines static virtual address mappings for I/O regions.
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 91e8da83281..ecaa5b96d6f 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -21,12 +21,12 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/pinctrl/machine.h>
-#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include "common.h"
#include "devices/devices-common.h"
+#include "hardware.h"
#include "iomux-v1.h"
/* MX27 memory map definition */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 3e2ed2ab1ea..072b3bf4927 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -26,11 +26,10 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "crmregs-imx3.h"
#include "devices/devices-common.h"
+#include "hardware.h"
#include "iomux-v3.h"
void __iomem *mx3_ccm_base;
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index d9ef24b2260..e7395535f6b 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -18,10 +18,9 @@
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices/devices-common.h"
+#include "hardware.h"
#include "iomux-v3.h"
/*
diff --git a/arch/arm/mach-imx/mx1.h b/arch/arm/mach-imx/mx1.h
new file mode 100644
index 00000000000..45bd31cc34d
--- /dev/null
+++ b/arch/arm/mach-imx/mx1.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 1997,1998 Russell King
+ * Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MX1_H__
+#define __MACH_MX1_H__
+
+/*
+ * Memory map
+ */
+#define MX1_IO_BASE_ADDR 0x00200000
+#define MX1_IO_SIZE SZ_1M
+
+#define MX1_CS0_PHYS 0x10000000
+#define MX1_CS0_SIZE 0x02000000
+
+#define MX1_CS1_PHYS 0x12000000
+#define MX1_CS1_SIZE 0x01000000
+
+#define MX1_CS2_PHYS 0x13000000
+#define MX1_CS2_SIZE 0x01000000
+
+#define MX1_CS3_PHYS 0x14000000
+#define MX1_CS3_SIZE 0x01000000
+
+#define MX1_CS4_PHYS 0x15000000
+#define MX1_CS4_SIZE 0x01000000
+
+#define MX1_CS5_PHYS 0x16000000
+#define MX1_CS5_SIZE 0x01000000
+
+/*
+ * Register BASEs, based on OFFSETs
+ */
+#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
+#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
+#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
+#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
+#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
+#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
+#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
+#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
+#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
+#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
+#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
+#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
+#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
+#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
+#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
+#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
+#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
+#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
+#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
+#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
+#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
+#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
+#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
+#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
+#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
+#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
+#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
+
+/* macro to get at IO space when running virtually */
+#define MX1_IO_P2V(x) IMX_IO_P2V(x)
+#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
+
+/* fixed interrput numbers */
+#include <asm/irq.h>
+#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
+#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
+#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
+#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
+#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
+#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
+#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
+#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
+#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
+#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
+#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
+#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
+#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
+#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
+#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
+#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
+#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
+#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
+#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
+#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
+#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
+#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
+#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
+#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
+#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
+#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
+#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
+#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
+#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
+#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
+#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
+#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
+#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
+#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
+#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
+#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
+#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
+#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
+#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
+#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
+#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
+#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
+#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
+#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
+#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
+#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
+#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
+#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
+#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
+#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
+#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
+#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
+#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
+#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
+#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
+
+/* DMA */
+#define MX1_DMA_REQ_UART3_T 2
+#define MX1_DMA_REQ_UART3_R 3
+#define MX1_DMA_REQ_SSI2_T 4
+#define MX1_DMA_REQ_SSI2_R 5
+#define MX1_DMA_REQ_CSI_STAT 6
+#define MX1_DMA_REQ_CSI_R 7
+#define MX1_DMA_REQ_MSHC 8
+#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
+#define MX1_DMA_REQ_DSPA_DCT_DIN 10
+#define MX1_DMA_REQ_DSPA_MAC 11
+#define MX1_DMA_REQ_EXT 12
+#define MX1_DMA_REQ_SDHC 13
+#define MX1_DMA_REQ_SPI1_R 14
+#define MX1_DMA_REQ_SPI1_T 15
+#define MX1_DMA_REQ_SSI_T 16
+#define MX1_DMA_REQ_SSI_R 17
+#define MX1_DMA_REQ_ASP_DAC 18
+#define MX1_DMA_REQ_ASP_ADC 19
+#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
+#define MX1_DMA_REQ_SPI2_R 26
+#define MX1_DMA_REQ_SPI2_T 27
+#define MX1_DMA_REQ_UART2_T 28
+#define MX1_DMA_REQ_UART2_R 29
+#define MX1_DMA_REQ_UART1_T 30
+#define MX1_DMA_REQ_UART1_R 31
+
+/*
+ * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
+ * to not break drivers/usb/gadget/imx_udc. Should go
+ * away after this driver uses the new name.
+ */
+#define USBD_INT0 MX1_INT_USBD0
+
+#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/mach-imx/mx21.h b/arch/arm/mach-imx/mx21.h
new file mode 100644
index 00000000000..468738aa997
--- /dev/null
+++ b/arch/arm/mach-imx/mx21.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
+ *
+ * This contains i.MX21-specific hardware definitions. For those
+ * hardware pieces that are common between i.MX21 and i.MX27, have a
+ * look at mx2x.h.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MX21_H__
+#define __MACH_MX21_H__
+
+#define MX21_AIPI_BASE_ADDR 0x10000000
+#define MX21_AIPI_SIZE SZ_1M
+#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
+#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
+#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
+#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
+#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
+#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
+#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
+#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
+#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
+#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
+#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
+#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
+#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
+#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
+#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
+#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
+#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
+#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
+#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
+#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
+#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
+#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
+#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
+#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
+#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
+#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
+#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
+#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
+#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
+#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
+#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
+#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
+#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
+#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
+#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
+#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
+#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
+#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX21_AVIC_BASE_ADDR 0x10040000
+
+#define MX21_SAHB1_BASE_ADDR 0x80000000
+#define MX21_SAHB1_SIZE SZ_1M
+#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
+
+/* Memory regions and CS */
+#define MX21_SDRAM_BASE_ADDR 0xc0000000
+#define MX21_CSD1_BASE_ADDR 0xc4000000
+
+#define MX21_CS0_BASE_ADDR 0xc8000000
+#define MX21_CS1_BASE_ADDR 0xcc000000
+#define MX21_CS2_BASE_ADDR 0xd0000000
+#define MX21_CS3_BASE_ADDR 0xd1000000
+#define MX21_CS4_BASE_ADDR 0xd2000000
+#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
+#define MX21_CS5_BASE_ADDR 0xdd000000
+
+/* NAND, SDRAM, WEIM etc controllers */
+#define MX21_X_MEMC_BASE_ADDR 0xdf000000
+#define MX21_X_MEMC_SIZE SZ_256K
+
+#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
+#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
+#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
+#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
+
+#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
+
+#define MX21_IO_P2V(x) IMX_IO_P2V(x)
+#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
+
+/* fixed interrupt numbers */
+#include <asm/irq.h>
+#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
+#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
+#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
+#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
+#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
+#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
+#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
+#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
+#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
+#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
+#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
+#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
+#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
+#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
+#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
+#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
+#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
+#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
+#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
+#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
+#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
+#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
+#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
+#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
+#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
+#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
+#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
+#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
+#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
+#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
+#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
+#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
+#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
+#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
+#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
+#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
+#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
+#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
+#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
+#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
+#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
+#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
+#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
+#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
+#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
+#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
+#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
+#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
+#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
+#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
+#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
+#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
+
+/* fixed DMA request numbers */
+#define MX21_DMA_REQ_CSPI3_RX 1
+#define MX21_DMA_REQ_CSPI3_TX 2
+#define MX21_DMA_REQ_EXT 3
+#define MX21_DMA_REQ_FIRI_RX 4
+#define MX21_DMA_REQ_SDHC2 6
+#define MX21_DMA_REQ_SDHC1 7
+#define MX21_DMA_REQ_SSI2_RX0 8
+#define MX21_DMA_REQ_SSI2_TX0 9
+#define MX21_DMA_REQ_SSI2_RX1 10
+#define MX21_DMA_REQ_SSI2_TX1 11
+#define MX21_DMA_REQ_SSI1_RX0 12
+#define MX21_DMA_REQ_SSI1_TX0 13
+#define MX21_DMA_REQ_SSI1_RX1 14
+#define MX21_DMA_REQ_SSI1_TX1 15
+#define MX21_DMA_REQ_CSPI2_RX 16
+#define MX21_DMA_REQ_CSPI2_TX 17
+#define MX21_DMA_REQ_CSPI1_RX 18
+#define MX21_DMA_REQ_CSPI1_TX 19
+#define MX21_DMA_REQ_UART4_RX 20
+#define MX21_DMA_REQ_UART4_TX 21
+#define MX21_DMA_REQ_UART3_RX 22
+#define MX21_DMA_REQ_UART3_TX 23
+#define MX21_DMA_REQ_UART2_RX 24
+#define MX21_DMA_REQ_UART2_TX 25
+#define MX21_DMA_REQ_UART1_RX 26
+#define MX21_DMA_REQ_UART1_TX 27
+#define MX21_DMA_REQ_BMI_TX 28
+#define MX21_DMA_REQ_BMI_RX 29
+#define MX21_DMA_REQ_CSI_STAT 30
+#define MX21_DMA_REQ_CSI_RX 31
+
+#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/mach-imx/mx25.h b/arch/arm/mach-imx/mx25.h
new file mode 100644
index 00000000000..ec466400a20
--- /dev/null
+++ b/arch/arm/mach-imx/mx25.h
@@ -0,0 +1,117 @@
+#ifndef __MACH_MX25_H__
+#define __MACH_MX25_H__
+
+#define MX25_AIPS1_BASE_ADDR 0x43f00000
+#define MX25_AIPS1_SIZE SZ_1M
+#define MX25_AIPS2_BASE_ADDR 0x53f00000
+#define MX25_AIPS2_SIZE SZ_1M
+#define MX25_AVIC_BASE_ADDR 0x68000000
+#define MX25_AVIC_SIZE SZ_1M
+
+#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
+#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
+#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
+#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
+#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
+#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
+#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
+
+#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
+#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
+#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
+#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
+#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
+#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
+#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
+#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
+#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
+#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
+#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
+
+#define MX25_UART1_BASE_ADDR 0x43f90000
+#define MX25_UART2_BASE_ADDR 0x43f94000
+#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
+#define MX25_UART3_BASE_ADDR 0x5000c000
+#define MX25_UART4_BASE_ADDR 0x50008000
+#define MX25_UART5_BASE_ADDR 0x5002c000
+
+#define MX25_CSPI3_BASE_ADDR 0x50004000
+#define MX25_CSPI2_BASE_ADDR 0x50010000
+#define MX25_FEC_BASE_ADDR 0x50038000
+#define MX25_SSI2_BASE_ADDR 0x50014000
+#define MX25_SSI1_BASE_ADDR 0x50034000
+#define MX25_NFC_BASE_ADDR 0xbb000000
+#define MX25_IIM_BASE_ADDR 0x53ff0000
+#define MX25_DRYICE_BASE_ADDR 0x53ffc000
+#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
+#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
+#define MX25_LCDC_BASE_ADDR 0x53fbc000
+#define MX25_KPP_BASE_ADDR 0x43fa8000
+#define MX25_SDMA_BASE_ADDR 0x53fd4000
+#define MX25_USB_BASE_ADDR 0x53ff4000
+#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
+/*
+ * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
+ * for the host controller. Early documentation drafts specified 0x400 and
+ * Freescale internal sources confirm only the latter value to work.
+ */
+#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
+#define MX25_CSI_BASE_ADDR 0x53ff8000
+
+#define MX25_IO_P2V(x) IMX_IO_P2V(x)
+#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
+
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
+#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
+#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
+#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
+#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
+#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
+#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
+#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
+#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
+#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
+#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
+#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
+#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
+#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
+#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
+#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
+#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
+#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
+#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
+#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
+#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
+#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
+#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
+#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54)
+#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
+
+#define MX25_DMA_REQ_SSI2_RX1 22
+#define MX25_DMA_REQ_SSI2_TX1 23
+#define MX25_DMA_REQ_SSI2_RX0 24
+#define MX25_DMA_REQ_SSI2_TX0 25
+#define MX25_DMA_REQ_SSI1_RX1 26
+#define MX25_DMA_REQ_SSI1_TX1 27
+#define MX25_DMA_REQ_SSI1_RX0 28
+#define MX25_DMA_REQ_SSI1_TX0 29
+
+#ifndef __ASSEMBLY__
+extern int mx25_revision(void);
+#endif
+
+#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/mach-imx/mx27.h b/arch/arm/mach-imx/mx27.h
new file mode 100644
index 00000000000..e074616d54c
--- /dev/null
+++ b/arch/arm/mach-imx/mx27.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This contains i.MX27-specific hardware definitions. For those
+ * hardware pieces that are common between i.MX21 and i.MX27, have a
+ * look at mx2x.h.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MX27_H__
+#define __MACH_MX27_H__
+
+#define MX27_AIPI_BASE_ADDR 0x10000000
+#define MX27_AIPI_SIZE SZ_1M
+#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
+#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
+#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
+#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
+#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
+#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
+#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
+#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
+#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
+#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
+#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
+#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
+#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
+#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
+#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
+#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
+#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
+#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
+#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
+#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
+#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
+#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
+#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
+#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
+#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
+#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
+#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
+#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
+#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
+#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
+#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
+#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
+#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
+#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
+#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
+#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
+#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
+#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
+#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
+#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
+#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
+#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
+#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
+#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
+#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
+#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
+#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
+#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
+#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
+#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
+#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
+#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
+#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
+#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX27_AVIC_BASE_ADDR 0x10040000
+
+/* ROM patch */
+#define MX27_ROMP_BASE_ADDR 0x10041000
+
+#define MX27_SAHB1_BASE_ADDR 0x80000000
+#define MX27_SAHB1_SIZE SZ_1M
+#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
+#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
+
+/* Memory regions and CS */
+#define MX27_SDRAM_BASE_ADDR 0xa0000000
+#define MX27_CSD1_BASE_ADDR 0xb0000000
+
+#define MX27_CS0_BASE_ADDR 0xc0000000
+#define MX27_CS1_BASE_ADDR 0xc8000000
+#define MX27_CS2_BASE_ADDR 0xd0000000
+#define MX27_CS3_BASE_ADDR 0xd2000000
+#define MX27_CS4_BASE_ADDR 0xd4000000
+#define MX27_CS5_BASE_ADDR 0xd6000000
+
+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
+#define MX27_X_MEMC_BASE_ADDR 0xd8000000
+#define MX27_X_MEMC_SIZE SZ_1M
+#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
+#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
+#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
+#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
+#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
+
+#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
+#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
+#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
+#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
+
+#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
+
+/* IRAM */
+#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
+
+#define MX27_IO_P2V(x) IMX_IO_P2V(x)
+#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
+
+/* fixed interrupt numbers */
+#include <asm/irq.h>
+#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
+#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
+#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
+#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
+#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
+#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
+#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
+#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
+#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
+#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
+#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
+#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
+#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
+#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
+#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
+#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
+#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
+#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
+#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
+#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
+#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
+#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
+#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
+#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
+#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
+#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
+#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
+#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
+#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
+#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
+#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
+#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
+#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
+#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
+#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
+#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
+#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
+#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
+#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
+#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
+#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
+#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
+#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
+#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
+#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
+#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
+#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
+#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
+#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
+#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
+#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
+#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
+#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
+#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
+#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
+#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
+#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
+#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
+#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
+#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
+#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
+#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
+
+/* fixed DMA request numbers */
+#define MX27_DMA_REQ_CSPI3_RX 1
+#define MX27_DMA_REQ_CSPI3_TX 2
+#define MX27_DMA_REQ_EXT 3
+#define MX27_DMA_REQ_MSHC 4
+#define MX27_DMA_REQ_SDHC2 6
+#define MX27_DMA_REQ_SDHC1 7
+#define MX27_DMA_REQ_SSI2_RX0 8
+#define MX27_DMA_REQ_SSI2_TX0 9
+#define MX27_DMA_REQ_SSI2_RX1 10
+#define MX27_DMA_REQ_SSI2_TX1 11
+#define MX27_DMA_REQ_SSI1_RX0 12
+#define MX27_DMA_REQ_SSI1_TX0 13
+#define MX27_DMA_REQ_SSI1_RX1 14
+#define MX27_DMA_REQ_SSI1_TX1 15
+#define MX27_DMA_REQ_CSPI2_RX 16
+#define MX27_DMA_REQ_CSPI2_TX 17
+#define MX27_DMA_REQ_CSPI1_RX 18
+#define MX27_DMA_REQ_CSPI1_TX 19
+#define MX27_DMA_REQ_UART4_RX 20
+#define MX27_DMA_REQ_UART4_TX 21
+#define MX27_DMA_REQ_UART3_RX 22
+#define MX27_DMA_REQ_UART3_TX 23
+#define MX27_DMA_REQ_UART2_RX 24
+#define MX27_DMA_REQ_UART2_TX 25
+#define MX27_DMA_REQ_UART1_RX 26
+#define MX27_DMA_REQ_UART1_TX 27
+#define MX27_DMA_REQ_ATA_TX 28
+#define MX27_DMA_REQ_ATA_RCV 29
+#define MX27_DMA_REQ_CSI_STAT 30
+#define MX27_DMA_REQ_CSI_RX 31
+#define MX27_DMA_REQ_UART5_TX 32
+#define MX27_DMA_REQ_UART5_RX 33
+#define MX27_DMA_REQ_UART6_TX 34
+#define MX27_DMA_REQ_UART6_RX 35
+#define MX27_DMA_REQ_SDHC3 36
+#define MX27_DMA_REQ_NFC 37
+
+#ifndef __ASSEMBLY__
+extern int mx27_revision(void);
+#endif
+
+#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/mach-imx/mx2x.h b/arch/arm/mach-imx/mx2x.h
new file mode 100644
index 00000000000..11642f5b224
--- /dev/null
+++ b/arch/arm/mach-imx/mx2x.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This contains hardware definitions that are common between i.MX21 and
+ * i.MX27.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MX2x_H__
+#define __MACH_MX2x_H__
+
+/* The following addresses are common between i.MX21 and i.MX27 */
+
+/* Register offsets */
+#define MX2x_AIPI_BASE_ADDR 0x10000000
+#define MX2x_AIPI_SIZE SZ_1M
+#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
+#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
+#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
+#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
+#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
+#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
+#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
+#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
+#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
+#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
+#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
+#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
+#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
+#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
+#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
+#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
+#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
+#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
+#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
+#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
+#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
+#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
+#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
+#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
+#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
+#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
+#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
+#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
+#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
+#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
+#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
+#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
+
+#define MX2x_AVIC_BASE_ADDR 0x10040000
+
+#define MX2x_SAHB1_BASE_ADDR 0x80000000
+#define MX2x_SAHB1_SIZE SZ_1M
+#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
+
+/* fixed interrupt numbers */
+#include <asm/irq.h>
+#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
+#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
+#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
+#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
+#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
+#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
+#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
+#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
+#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
+#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
+#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
+#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
+#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
+#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
+#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
+#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
+#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
+#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
+#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
+#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
+#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
+#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
+#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
+#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
+#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
+#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
+#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
+#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
+#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
+#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
+#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
+#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
+#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
+#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
+#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
+#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
+#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
+#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
+#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
+#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
+#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
+#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
+
+/* fixed DMA request numbers */
+#define MX2x_DMA_REQ_CSPI3_RX 1
+#define MX2x_DMA_REQ_CSPI3_TX 2
+#define MX2x_DMA_REQ_EXT 3
+#define MX2x_DMA_REQ_SDHC2 6
+#define MX2x_DMA_REQ_SDHC1 7
+#define MX2x_DMA_REQ_SSI2_RX0 8
+#define MX2x_DMA_REQ_SSI2_TX0 9
+#define MX2x_DMA_REQ_SSI2_RX1 10
+#define MX2x_DMA_REQ_SSI2_TX1 11
+#define MX2x_DMA_REQ_SSI1_RX0 12
+#define MX2x_DMA_REQ_SSI1_TX0 13
+#define MX2x_DMA_REQ_SSI1_RX1 14
+#define MX2x_DMA_REQ_SSI1_TX1 15
+#define MX2x_DMA_REQ_CSPI2_RX 16
+#define MX2x_DMA_REQ_CSPI2_TX 17
+#define MX2x_DMA_REQ_CSPI1_RX 18
+#define MX2x_DMA_REQ_CSPI1_TX 19
+#define MX2x_DMA_REQ_UART4_RX 20
+#define MX2x_DMA_REQ_UART4_TX 21
+#define MX2x_DMA_REQ_UART3_RX 22
+#define MX2x_DMA_REQ_UART3_TX 23
+#define MX2x_DMA_REQ_UART2_RX 24
+#define MX2x_DMA_REQ_UART2_TX 25
+#define MX2x_DMA_REQ_UART1_RX 26
+#define MX2x_DMA_REQ_UART1_TX 27
+#define MX2x_DMA_REQ_CSI_STAT 30
+#define MX2x_DMA_REQ_CSI_RX 31
+
+#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/mach-imx/mx31.h b/arch/arm/mach-imx/mx31.h
new file mode 100644
index 00000000000..ee9b1f9215d
--- /dev/null
+++ b/arch/arm/mach-imx/mx31.h
@@ -0,0 +1,196 @@
+#ifndef __MACH_MX31_H__
+#define __MACH_MX31_H__
+
+/*
+ * IRAM
+ */
+#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
+#define MX31_IRAM_SIZE SZ_16K
+
+#define MX31_L2CC_BASE_ADDR 0x30000000
+#define MX31_L2CC_SIZE SZ_1M
+
+#define MX31_AIPS1_BASE_ADDR 0x43f00000
+#define MX31_AIPS1_SIZE SZ_1M
+#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
+#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
+#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
+#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
+#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
+#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
+#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
+#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
+#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
+#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
+#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
+#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
+#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
+#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
+#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
+#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
+#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
+#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
+#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
+#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
+#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
+#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
+#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
+
+#define MX31_SPBA0_BASE_ADDR 0x50000000
+#define MX31_SPBA0_SIZE SZ_1M
+#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
+#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
+#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
+#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
+#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
+#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
+#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
+#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
+#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
+
+#define MX31_AIPS2_BASE_ADDR 0x53f00000
+#define MX31_AIPS2_SIZE SZ_1M
+#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
+#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
+#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
+#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
+#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
+#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
+#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
+#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
+#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
+#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
+#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
+#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
+#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
+#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
+#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
+#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
+#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
+#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
+#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
+#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
+#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
+
+#define MX31_ROMP_BASE_ADDR 0x60000000
+#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
+#define MX31_ROMP_SIZE SZ_1M
+
+#define MX31_AVIC_BASE_ADDR 0x68000000
+#define MX31_AVIC_SIZE SZ_1M
+
+#define MX31_IPU_MEM_BASE_ADDR 0x70000000
+#define MX31_CSD0_BASE_ADDR 0x80000000
+#define MX31_CSD1_BASE_ADDR 0x90000000
+
+#define MX31_CS0_BASE_ADDR 0xa0000000
+#define MX31_CS1_BASE_ADDR 0xa8000000
+#define MX31_CS2_BASE_ADDR 0xb0000000
+#define MX31_CS3_BASE_ADDR 0xb2000000
+
+#define MX31_CS4_BASE_ADDR 0xb4000000
+#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
+#define MX31_CS4_SIZE SZ_32M
+
+#define MX31_CS5_BASE_ADDR 0xb6000000
+#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
+#define MX31_CS5_SIZE SZ_32M
+
+#define MX31_X_MEMC_BASE_ADDR 0xb8000000
+#define MX31_X_MEMC_SIZE SZ_64K
+#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
+#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
+#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
+#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
+#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
+
+#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
+#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
+#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
+#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
+
+#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
+
+#define MX31_IO_P2V(x) IMX_IO_P2V(x)
+#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
+
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
+#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
+#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
+#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
+#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
+#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
+#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
+#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
+#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
+#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
+#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
+#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
+#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
+#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
+#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
+#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
+#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
+#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
+#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
+#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
+#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
+#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
+#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
+#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
+#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
+#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
+#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
+#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
+#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
+#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
+#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
+#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
+#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
+#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
+#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
+#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
+#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
+#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
+#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
+#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
+#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
+#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
+#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
+#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
+#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
+#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
+#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
+
+#define MX31_DMA_REQ_SDHC1 20
+#define MX31_DMA_REQ_SDHC2 21
+#define MX31_DMA_REQ_SSI2_RX1 22
+#define MX31_DMA_REQ_SSI2_TX1 23
+#define MX31_DMA_REQ_SSI2_RX0 24
+#define MX31_DMA_REQ_SSI2_TX0 25
+#define MX31_DMA_REQ_SSI1_RX1 26
+#define MX31_DMA_REQ_SSI1_TX1 27
+#define MX31_DMA_REQ_SSI1_RX0 28
+#define MX31_DMA_REQ_SSI1_TX0 29
+
+#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
+
+#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index 8cdcf0f2522..d4361b80c5f 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -30,11 +30,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "board-mx31lilly.h"
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
/*
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index c9eb91c344b..5a160b7e4fc 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -31,11 +31,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
#include "board-mx31lite.h"
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
/*
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 6489afc85de..52d5b157472 100644
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -22,10 +22,9 @@
#include <linux/usb/otg.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index ea973c46f8e..a4f43e90f3c 100644
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -24,12 +24,11 @@
#include <linux/usb/otg.h>
-#include <mach/hardware.h>
-
#include <media/soc_camera.h>
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index 807e88274e1..04ae45dbfaa 100644
--- a/arch/arm/mach-imx/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -23,13 +23,12 @@
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
-#include <mach/hardware.h>
-
#include <media/soc_camera.h>
#include "board-mx31moboard.h"
#include "common.h"
#include "devices-imx31.h"
+#include "hardware.h"
#include "iomux-mx3.h"
#include "ulpi.h"
diff --git a/arch/arm/mach-imx/mx35.h b/arch/arm/mach-imx/mx35.h
new file mode 100644
index 00000000000..2af5d3a699c
--- /dev/null
+++ b/arch/arm/mach-imx/mx35.h
@@ -0,0 +1,190 @@
+#ifndef __MACH_MX35_H__
+#define __MACH_MX35_H__
+
+/*
+ * IRAM
+ */
+#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
+#define MX35_IRAM_SIZE SZ_128K
+
+#define MX35_L2CC_BASE_ADDR 0x30000000
+#define MX35_L2CC_SIZE SZ_1M
+
+#define MX35_AIPS1_BASE_ADDR 0x43f00000
+#define MX35_AIPS1_SIZE SZ_1M
+#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
+#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
+#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
+#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
+#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
+#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
+#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
+#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
+#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
+#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
+#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
+#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
+#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
+#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
+#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
+#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
+#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
+
+#define MX35_SPBA0_BASE_ADDR 0x50000000
+#define MX35_SPBA0_SIZE SZ_1M
+#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
+#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
+#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
+#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
+#define MX35_FEC_BASE_ADDR 0x50038000
+#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
+
+#define MX35_AIPS2_BASE_ADDR 0x53f00000
+#define MX35_AIPS2_SIZE SZ_1M
+#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
+#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
+#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
+#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
+#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
+#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
+#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
+#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
+#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
+#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
+#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
+#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
+#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
+#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
+#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
+#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
+#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
+#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
+#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
+#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
+#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
+/*
+ * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
+ * HS. When host support was implemented only a preliminary document was
+ * available, which told 0x400. This works fine.
+ */
+#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
+
+#define MX35_ROMP_BASE_ADDR 0x60000000
+#define MX35_ROMP_SIZE SZ_1M
+
+#define MX35_AVIC_BASE_ADDR 0x68000000
+#define MX35_AVIC_SIZE SZ_1M
+
+/*
+ * Memory regions and CS
+ */
+#define MX35_IPU_MEM_BASE_ADDR 0x70000000
+#define MX35_CSD0_BASE_ADDR 0x80000000
+#define MX35_CSD1_BASE_ADDR 0x90000000
+
+#define MX35_CS0_BASE_ADDR 0xa0000000
+#define MX35_CS1_BASE_ADDR 0xa8000000
+#define MX35_CS2_BASE_ADDR 0xb0000000
+#define MX35_CS3_BASE_ADDR 0xb2000000
+
+#define MX35_CS4_BASE_ADDR 0xb4000000
+#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
+#define MX35_CS4_SIZE SZ_32M
+
+#define MX35_CS5_BASE_ADDR 0xb6000000
+#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
+#define MX35_CS5_SIZE SZ_32M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX35_X_MEMC_BASE_ADDR 0xb8000000
+#define MX35_X_MEMC_SIZE SZ_64K
+#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
+#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
+#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
+#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
+#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
+
+#define MX35_NFC_BASE_ADDR 0xbb000000
+#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
+
+#define MX35_IO_P2V(x) IMX_IO_P2V(x)
+#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
+
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
+#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
+#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
+#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
+#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
+#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
+#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
+#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
+#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
+#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
+#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
+#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
+#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
+#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
+#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
+#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
+#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
+#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
+#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
+#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
+#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
+#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
+#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
+#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
+#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
+#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
+#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
+#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
+#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
+#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
+#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
+#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
+#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
+#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
+#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
+#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
+#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
+#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
+#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
+#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
+#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
+#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
+#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
+#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
+
+#define MX35_DMA_REQ_SSI2_RX1 22
+#define MX35_DMA_REQ_SSI2_TX1 23
+#define MX35_DMA_REQ_SSI2_RX0 24
+#define MX35_DMA_REQ_SSI2_TX0 25
+#define MX35_DMA_REQ_SSI1_RX1 26
+#define MX35_DMA_REQ_SSI1_TX1 27
+#define MX35_DMA_REQ_SSI1_RX0 28
+#define MX35_DMA_REQ_SSI1_TX0 29
+
+#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
+
+#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/mach-imx/mx3x.h b/arch/arm/mach-imx/mx3x.h
new file mode 100644
index 00000000000..96fb4fbc8ad
--- /dev/null
+++ b/arch/arm/mach-imx/mx3x.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MX3x_H__
+#define __MACH_MX3x_H__
+
+/*
+ * MX31 memory map:
+ *
+ * Virt Phys Size What
+ * ---------------------------------------------------------------------------
+ * FC000000 43F00000 1M AIPS 1
+ * FC100000 50000000 1M SPBA
+ * FC200000 53F00000 1M AIPS 2
+ * FC500000 60000000 128M ROMPATCH
+ * FC400000 68000000 128M AVIC
+ * 70000000 256M IPU (MAX M2)
+ * 80000000 256M CSD0 SDRAM/DDR
+ * 90000000 256M CSD1 SDRAM/DDR
+ * A0000000 128M CS0 Flash
+ * A8000000 128M CS1 Flash
+ * B0000000 32M CS2
+ * B2000000 32M CS3
+ * F4000000 B4000000 32M CS4
+ * B6000000 32M CS5
+ * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
+ * C0000000 64M PCMCIA/CF
+ */
+
+/*
+ * L2CC
+ */
+#define MX3x_L2CC_BASE_ADDR 0x30000000
+#define MX3x_L2CC_SIZE SZ_1M
+
+/*
+ * AIPS 1
+ */
+#define MX3x_AIPS1_BASE_ADDR 0x43f00000
+#define MX3x_AIPS1_SIZE SZ_1M
+#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
+#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
+#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
+#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
+#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
+#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
+#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
+#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
+#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
+#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
+#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
+#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
+#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
+#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
+#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
+#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
+#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
+#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MX3x_SPBA0_BASE_ADDR 0x50000000
+#define MX3x_SPBA0_SIZE SZ_1M
+#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
+#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
+#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
+#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
+#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
+#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
+
+/*
+ * AIPS 2
+ */
+#define MX3x_AIPS2_BASE_ADDR 0x53f00000
+#define MX3x_AIPS2_SIZE SZ_1M
+#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
+#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
+#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
+#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
+#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
+#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
+#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
+#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
+#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
+#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
+#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
+#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
+#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
+#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
+#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
+#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
+
+/*
+ * ROMP and AVIC
+ */
+#define MX3x_ROMP_BASE_ADDR 0x60000000
+#define MX3x_ROMP_SIZE SZ_1M
+
+#define MX3x_AVIC_BASE_ADDR 0x68000000
+#define MX3x_AVIC_SIZE SZ_1M
+
+/*
+ * Memory regions and CS
+ */
+#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
+#define MX3x_CSD0_BASE_ADDR 0x80000000
+#define MX3x_CSD1_BASE_ADDR 0x90000000
+
+#define MX3x_CS0_BASE_ADDR 0xa0000000
+#define MX3x_CS1_BASE_ADDR 0xa8000000
+#define MX3x_CS2_BASE_ADDR 0xb0000000
+#define MX3x_CS3_BASE_ADDR 0xb2000000
+
+#define MX3x_CS4_BASE_ADDR 0xb4000000
+#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
+#define MX3x_CS4_SIZE SZ_32M
+
+#define MX3x_CS5_BASE_ADDR 0xb6000000
+#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
+#define MX3x_CS5_SIZE SZ_32M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
+#define MX3x_X_MEMC_SIZE SZ_64K
+#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
+#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
+#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
+#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
+#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
+
+#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
+
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
+#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
+#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
+#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
+#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
+#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
+#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
+#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
+#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
+#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
+#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
+#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
+#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
+#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
+#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
+#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
+#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
+#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
+#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
+#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
+#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
+#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
+#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
+#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
+#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
+#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
+#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
+#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
+#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
+#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
+#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
+#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
+#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
+#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
+#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
+#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
+#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
+
+#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
+
+/* Mandatory defines used globally */
+
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+extern int mx35_revision(void);
+extern int mx31_revision(void);
+#endif
+
+#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/mach-imx/mx50.h b/arch/arm/mach-imx/mx50.h
new file mode 100644
index 00000000000..09ac19c1570
--- /dev/null
+++ b/arch/arm/mach-imx/mx50.h
@@ -0,0 +1,290 @@
+#ifndef __MACH_MX50_H__
+#define __MACH_MX50_H__
+
+/*
+ * IROM
+ */
+#define MX50_IROM_BASE_ADDR 0x0
+#define MX50_IROM_SIZE SZ_64K
+
+/* TZIC */
+#define MX50_TZIC_BASE_ADDR 0x0fffc000
+#define MX50_TZIC_SIZE SZ_16K
+
+/*
+ * IRAM
+ */
+#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
+#define MX50_IRAM_PARTITIONS 16
+#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
+
+/*
+ * Databahn
+ */
+#define MX50_DATABAHN_BASE_ADDR 0x14000000
+
+/*
+ * Graphics Memory of GPU
+ */
+#define MX50_GPU2D_BASE_ADDR 0x20000000
+
+#define MX50_DEBUG_BASE_ADDR 0x40000000
+#define MX50_DEBUG_SIZE SZ_1M
+#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
+#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
+#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
+#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
+#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
+#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
+#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
+#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
+
+#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
+#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
+#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
+#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
+#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
+#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
+#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
+#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
+#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
+#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
+#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
+#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
+#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
+#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MX50_SPBA0_BASE_ADDR 0x50000000
+#define MX50_SPBA0_SIZE SZ_1M
+
+#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
+#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
+#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
+#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
+#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
+#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
+#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
+
+/*
+ * AIPS 1
+ */
+#define MX50_AIPS1_BASE_ADDR 0x53f00000
+#define MX50_AIPS1_SIZE SZ_1M
+
+#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
+#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
+#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
+#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
+#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
+#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
+#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
+#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
+#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
+#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
+#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
+#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
+#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
+#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
+#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
+#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
+#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
+#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
+#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
+#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
+#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
+#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
+
+#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
+#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
+
+/*
+ * AIPS 2
+ */
+#define MX50_AIPS2_BASE_ADDR 0x63f00000
+#define MX50_AIPS2_SIZE SZ_1M
+
+#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
+#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
+#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
+#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
+#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
+#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
+#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
+#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
+#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
+#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
+#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
+#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
+#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
+#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
+#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
+#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
+#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
+
+/*
+ * Memory regions and CS
+ */
+#define MX50_CSD0_BASE_ADDR 0x70000000
+#define MX50_CSD1_BASE_ADDR 0xb0000000
+#define MX50_CS0_BASE_ADDR 0xf0000000
+
+#define MX50_IO_P2V(x) IMX_IO_P2V(x)
+#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
+
+/*
+ * defines for SPBA modules
+ */
+#define MX50_SPBA_SDHC1 0x04
+#define MX50_SPBA_SDHC2 0x08
+#define MX50_SPBA_UART3 0x0c
+#define MX50_SPBA_CSPI1 0x10
+#define MX50_SPBA_SSI2 0x14
+#define MX50_SPBA_SDHC3 0x20
+#define MX50_SPBA_SDHC4 0x24
+#define MX50_SPBA_SPDIF 0x28
+#define MX50_SPBA_ATA 0x30
+#define MX50_SPBA_SLIM 0x34
+#define MX50_SPBA_HSI2C 0x38
+#define MX50_SPBA_CTRL 0x3c
+
+/*
+ * DMA request assignments
+ */
+#define MX50_DMA_REQ_GPC 1
+#define MX50_DMA_REQ_ATA_UART4_RX 2
+#define MX50_DMA_REQ_ATA_UART4_TX 3
+#define MX50_DMA_REQ_CSPI1_RX 6
+#define MX50_DMA_REQ_CSPI1_TX 7
+#define MX50_DMA_REQ_CSPI2_RX 8
+#define MX50_DMA_REQ_CSPI2_TX 9
+#define MX50_DMA_REQ_I2C3_SDHC3 10
+#define MX50_DMA_REQ_SDHC4 11
+#define MX50_DMA_REQ_UART2_FIRI_RX 12
+#define MX50_DMA_REQ_UART2_FIRI_TX 13
+#define MX50_DMA_REQ_EXT0 14
+#define MX50_DMA_REQ_EXT1 15
+#define MX50_DMA_REQ_UART5_RX 16
+#define MX50_DMA_REQ_UART5_TX 17
+#define MX50_DMA_REQ_UART1_RX 18
+#define MX50_DMA_REQ_UART1_TX 19
+#define MX50_DMA_REQ_I2C1_SDHC1 20
+#define MX50_DMA_REQ_I2C2_SDHC2 21
+#define MX50_DMA_REQ_SSI2_RX2 22
+#define MX50_DMA_REQ_SSI2_TX2 23
+#define MX50_DMA_REQ_SSI2_RX1 24
+#define MX50_DMA_REQ_SSI2_TX1 25
+#define MX50_DMA_REQ_SSI1_RX2 26
+#define MX50_DMA_REQ_SSI1_TX2 27
+#define MX50_DMA_REQ_SSI1_RX1 28
+#define MX50_DMA_REQ_SSI1_TX1 29
+#define MX50_DMA_REQ_CSPI_RX 38
+#define MX50_DMA_REQ_CSPI_TX 39
+#define MX50_DMA_REQ_UART3_RX 42
+#define MX50_DMA_REQ_UART3_TX 43
+
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
+#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
+#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
+#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
+#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
+#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
+#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
+#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
+#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
+#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
+#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
+#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
+#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
+#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
+#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
+#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
+#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
+#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
+#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
+#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
+#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
+#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
+#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
+#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
+#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
+#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
+#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
+#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
+#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
+#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
+#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
+#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
+#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
+#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
+#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
+#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
+#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
+#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
+#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
+#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
+#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
+#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
+#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
+#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
+#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
+#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
+#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
+#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
+#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
+#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
+#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
+#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
+#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
+#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
+#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
+#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
+#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
+#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
+#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
+#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
+#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
+#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
+#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
+#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
+#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
+#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
+#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
+#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
+#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
+#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
+#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
+#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
+#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
+#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
+#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
+#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
+#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
+#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
+#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
+#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
+#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
+#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
+#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
+#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
+#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
+#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
+#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
+#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
+#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
+#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
+#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
+#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
+
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+extern int mx50_revision(void);
+#endif
+
+#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/mach-imx/mx51.h b/arch/arm/mach-imx/mx51.h
new file mode 100644
index 00000000000..af844f76261
--- /dev/null
+++ b/arch/arm/mach-imx/mx51.h
@@ -0,0 +1,346 @@
+#ifndef __MACH_MX51_H__
+#define __MACH_MX51_H__
+
+/*
+ * IROM
+ */
+#define MX51_IROM_BASE_ADDR 0x0
+#define MX51_IROM_SIZE SZ_64K
+
+/*
+ * IRAM
+ */
+#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
+#define MX51_IRAM_PARTITIONS 16
+#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
+
+#define MX51_GPU_BASE_ADDR 0x20000000
+#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
+#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MX51_SPBA0_BASE_ADDR 0x70000000
+#define MX51_SPBA0_SIZE SZ_1M
+
+#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
+#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
+#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
+#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
+#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
+#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
+#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
+#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
+#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
+#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
+#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
+
+/*
+ * AIPS 1
+ */
+#define MX51_AIPS1_BASE_ADDR 0x73f00000
+#define MX51_AIPS1_SIZE SZ_1M
+
+#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000)
+#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200)
+#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400)
+#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
+#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
+#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
+#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
+#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
+#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
+#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
+#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
+#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
+#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
+#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
+#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
+#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
+#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
+#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
+#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
+#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
+#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
+#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
+
+/*
+ * AIPS 2
+ */
+#define MX51_AIPS2_BASE_ADDR 0x83f00000
+#define MX51_AIPS2_SIZE SZ_1M
+
+#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
+#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
+#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
+#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
+#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
+#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
+#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
+#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
+#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
+#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
+#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
+#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
+#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
+#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
+#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
+#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
+#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
+#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
+#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
+#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
+#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
+#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
+#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
+#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
+#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
+#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
+#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
+#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
+#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
+#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
+
+#define MX51_CSD0_BASE_ADDR 0x90000000
+#define MX51_CSD1_BASE_ADDR 0xa0000000
+#define MX51_CS0_BASE_ADDR 0xb0000000
+#define MX51_CS1_BASE_ADDR 0xb8000000
+#define MX51_CS2_BASE_ADDR 0xc0000000
+#define MX51_CS3_BASE_ADDR 0xc8000000
+#define MX51_CS4_BASE_ADDR 0xcc000000
+#define MX51_CS5_BASE_ADDR 0xce000000
+
+/*
+ * NFC
+ */
+#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
+#define MX51_NFC_AXI_SIZE SZ_64K
+
+#define MX51_GPU2D_BASE_ADDR 0xd0000000
+#define MX51_TZIC_BASE_ADDR 0xe0000000
+#define MX51_TZIC_SIZE SZ_16K
+
+#define MX51_IO_P2V(x) IMX_IO_P2V(x)
+#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
+
+/*
+ * defines for SPBA modules
+ */
+#define MX51_SPBA_SDHC1 0x04
+#define MX51_SPBA_SDHC2 0x08
+#define MX51_SPBA_UART3 0x0c
+#define MX51_SPBA_CSPI1 0x10
+#define MX51_SPBA_SSI2 0x14
+#define MX51_SPBA_SDHC3 0x20
+#define MX51_SPBA_SDHC4 0x24
+#define MX51_SPBA_SPDIF 0x28
+#define MX51_SPBA_ATA 0x30
+#define MX51_SPBA_SLIM 0x34
+#define MX51_SPBA_HSI2C 0x38
+#define MX51_SPBA_CTRL 0x3c
+
+/*
+ * Defines for modules using static and dynamic DMA channels
+ */
+#define MX51_MXC_DMA_CHANNEL_IRAM 30
+#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
+#ifdef CONFIG_SDMA_IRAM
+#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
+#else /*CONFIG_SDMA_IRAM */
+#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
+#endif /*CONFIG_SDMA_IRAM */
+#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
+#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
+
+#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
+
+/*
+ * DMA request assignments
+ */
+#define MX51_DMA_REQ_VPU 0
+#define MX51_DMA_REQ_GPC 1
+#define MX51_DMA_REQ_ATA_RX 2
+#define MX51_DMA_REQ_ATA_TX 3
+#define MX51_DMA_REQ_ATA_TX_END 4
+#define MX51_DMA_REQ_SLIM_B 5
+#define MX51_DMA_REQ_CSPI1_RX 6
+#define MX51_DMA_REQ_CSPI1_TX 7
+#define MX51_DMA_REQ_CSPI2_RX 8
+#define MX51_DMA_REQ_CSPI2_TX 9
+#define MX51_DMA_REQ_HS_I2C_TX 10
+#define MX51_DMA_REQ_HS_I2C_RX 11
+#define MX51_DMA_REQ_FIRI_RX 12
+#define MX51_DMA_REQ_FIRI_TX 13
+#define MX51_DMA_REQ_EXTREQ1 14
+#define MX51_DMA_REQ_GPU 15
+#define MX51_DMA_REQ_UART2_RX 16
+#define MX51_DMA_REQ_UART2_TX 17
+#define MX51_DMA_REQ_UART1_RX 18
+#define MX51_DMA_REQ_UART1_TX 19
+#define MX51_DMA_REQ_SDHC1 20
+#define MX51_DMA_REQ_SDHC2 21
+#define MX51_DMA_REQ_SSI2_RX1 22
+#define MX51_DMA_REQ_SSI2_TX1 23
+#define MX51_DMA_REQ_SSI2_RX0 24
+#define MX51_DMA_REQ_SSI2_TX0 25
+#define MX51_DMA_REQ_SSI1_RX1 26
+#define MX51_DMA_REQ_SSI1_TX1 27
+#define MX51_DMA_REQ_SSI1_RX0 28
+#define MX51_DMA_REQ_SSI1_TX0 29
+#define MX51_DMA_REQ_EMI_RD 30
+#define MX51_DMA_REQ_CTI2_0 31
+#define MX51_DMA_REQ_EMI_WR 32
+#define MX51_DMA_REQ_CTI2_1 33
+#define MX51_DMA_REQ_EPIT2 34
+#define MX51_DMA_REQ_SSI3_RX1 35
+#define MX51_DMA_REQ_IPU 36
+#define MX51_DMA_REQ_SSI3_TX1 37
+#define MX51_DMA_REQ_CSPI_RX 38
+#define MX51_DMA_REQ_CSPI_TX 39
+#define MX51_DMA_REQ_SDHC3 40
+#define MX51_DMA_REQ_SDHC4 41
+#define MX51_DMA_REQ_SLIM_B_TX 42
+#define MX51_DMA_REQ_UART3_RX 43
+#define MX51_DMA_REQ_UART3_TX 44
+#define MX51_DMA_REQ_SPDIF 45
+#define MX51_DMA_REQ_SSI3_RX0 46
+#define MX51_DMA_REQ_SSI3_TX0 47
+
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
+#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
+#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
+#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
+#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
+#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
+#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
+#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
+#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
+#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
+#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
+#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
+#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
+#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
+#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
+#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
+#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
+#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
+#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
+#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
+#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
+#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
+#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
+#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
+#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
+#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
+#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
+#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
+#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
+#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
+#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
+#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
+#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
+#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
+#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
+#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
+#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
+#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
+#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
+#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
+#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
+#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
+#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
+#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
+#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
+#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
+#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
+#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
+#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
+#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
+#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
+#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
+#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
+#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
+#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
+#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
+#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
+#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
+#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
+#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
+#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
+#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
+#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
+#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
+#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
+#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
+#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
+#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
+#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
+#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
+#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
+#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
+#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
+#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
+#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
+#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
+#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
+#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
+#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
+#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
+#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
+#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
+#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
+#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
+#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
+#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
+#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
+#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
+#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
+#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
+#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
+#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
+#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
+#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
+#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
+#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
+#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
+#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
+#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
+#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
+#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
+#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
+#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
+
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+extern int mx51_revision(void);
+extern void mx51_display_revision(void);
+#endif
+
+#endif /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/mach-imx/mx53.h b/arch/arm/mach-imx/mx53.h
new file mode 100644
index 00000000000..f829d1c2250
--- /dev/null
+++ b/arch/arm/mach-imx/mx53.h
@@ -0,0 +1,342 @@
+#ifndef __MACH_MX53_H__
+#define __MACH_MX53_H__
+
+/*
+ * IROM
+ */
+#define MX53_IROM_BASE_ADDR 0x0
+#define MX53_IROM_SIZE SZ_64K
+
+/* TZIC */
+#define MX53_TZIC_BASE_ADDR 0x0FFFC000
+#define MX53_TZIC_SIZE SZ_16K
+
+/*
+ * AHCI SATA
+ */
+#define MX53_SATA_BASE_ADDR 0x10000000
+
+/*
+ * NFC
+ */
+#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
+#define MX53_NFC_AXI_SIZE SZ_64K
+
+/*
+ * IRAM
+ */
+#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
+#define MX53_IRAM_PARTITIONS 16
+#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
+
+/*
+ * Graphics Memory of GPU
+ */
+#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
+#define MX53_GPU2D_BASE_ADDR 0x20000000
+#define MX53_GPU_BASE_ADDR 0x30000000
+#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
+
+#define MX53_DEBUG_BASE_ADDR 0x40000000
+#define MX53_DEBUG_SIZE SZ_1M
+#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
+#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
+#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
+#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
+#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
+#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
+#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
+#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MX53_SPBA0_BASE_ADDR 0x50000000
+#define MX53_SPBA0_SIZE SZ_1M
+
+#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
+#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
+#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
+#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
+#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
+#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
+#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
+#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
+#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
+#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
+#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
+#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
+#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define MX53_AIPS1_BASE_ADDR 0x53F00000
+#define MX53_AIPS1_SIZE SZ_1M
+
+#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
+#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
+#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
+#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
+#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
+#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
+#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
+#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
+#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
+#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
+#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
+#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
+#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
+#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
+#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
+#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
+#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
+#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
+#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
+#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
+#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
+#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
+#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
+#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
+#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
+#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
+
+/*
+ * AIPS 2
+ */
+#define MX53_AIPS2_BASE_ADDR 0x63F00000
+#define MX53_AIPS2_SIZE SZ_1M
+
+#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
+#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
+#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
+#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
+#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
+#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
+#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
+#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
+#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
+#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
+#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
+#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
+#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
+#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
+#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
+#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
+#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
+#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
+#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
+#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
+#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
+#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
+#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
+#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
+#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
+#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
+#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
+#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
+#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
+#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
+#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
+#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
+#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
+#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
+#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
+
+/*
+ * Memory regions and CS
+ */
+#define MX53_CSD0_BASE_ADDR 0x70000000
+#define MX53_CSD1_BASE_ADDR 0xB0000000
+#define MX53_CS0_BASE_ADDR 0xF0000000
+#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
+#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
+#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
+#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
+#define MX53_CS3_BASE_ADDR 0xF6000000
+
+#define MX53_IO_P2V(x) IMX_IO_P2V(x)
+#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
+
+/*
+ * defines for SPBA modules
+ */
+#define MX53_SPBA_SDHC1 0x04
+#define MX53_SPBA_SDHC2 0x08
+#define MX53_SPBA_UART3 0x0C
+#define MX53_SPBA_CSPI1 0x10
+#define MX53_SPBA_SSI2 0x14
+#define MX53_SPBA_SDHC3 0x20
+#define MX53_SPBA_SDHC4 0x24
+#define MX53_SPBA_SPDIF 0x28
+#define MX53_SPBA_ATA 0x30
+#define MX53_SPBA_SLIM 0x34
+#define MX53_SPBA_HSI2C 0x38
+#define MX53_SPBA_CTRL 0x3C
+
+/*
+ * DMA request assignments
+ */
+#define MX53_DMA_REQ_SSI3_TX0 47
+#define MX53_DMA_REQ_SSI3_RX0 46
+#define MX53_DMA_REQ_SSI3_TX1 45
+#define MX53_DMA_REQ_SSI3_RX1 44
+#define MX53_DMA_REQ_UART3_TX 43
+#define MX53_DMA_REQ_UART3_RX 42
+#define MX53_DMA_REQ_ESAI_TX 41
+#define MX53_DMA_REQ_ESAI_RX 40
+#define MX53_DMA_REQ_CSPI_TX 39
+#define MX53_DMA_REQ_CSPI_RX 38
+#define MX53_DMA_REQ_ASRC_DMA6 37
+#define MX53_DMA_REQ_ASRC_DMA5 36
+#define MX53_DMA_REQ_ASRC_DMA4 35
+#define MX53_DMA_REQ_ASRC_DMA3 34
+#define MX53_DMA_REQ_ASRC_DMA2 33
+#define MX53_DMA_REQ_ASRC_DMA1 32
+#define MX53_DMA_REQ_EMI_WR 31
+#define MX53_DMA_REQ_EMI_RD 30
+#define MX53_DMA_REQ_SSI1_TX0 29
+#define MX53_DMA_REQ_SSI1_RX0 28
+#define MX53_DMA_REQ_SSI1_TX1 27
+#define MX53_DMA_REQ_SSI1_RX1 26
+#define MX53_DMA_REQ_SSI2_TX0 25
+#define MX53_DMA_REQ_SSI2_RX0 24
+#define MX53_DMA_REQ_SSI2_TX1 23
+#define MX53_DMA_REQ_SSI2_RX1 22
+#define MX53_DMA_REQ_I2C2_SDHC2 21
+#define MX53_DMA_REQ_I2C1_SDHC1 20
+#define MX53_DMA_REQ_UART1_TX 19
+#define MX53_DMA_REQ_UART1_RX 18
+#define MX53_DMA_REQ_UART5_TX 17
+#define MX53_DMA_REQ_UART5_RX 16
+#define MX53_DMA_REQ_SPDIF_TX 15
+#define MX53_DMA_REQ_SPDIF_RX 14
+#define MX53_DMA_REQ_UART2_FIRI_TX 13
+#define MX53_DMA_REQ_UART2_FIRI_RX 12
+#define MX53_DMA_REQ_SDHC4 11
+#define MX53_DMA_REQ_I2C3_SDHC3 10
+#define MX53_DMA_REQ_CSPI2_TX 9
+#define MX53_DMA_REQ_CSPI2_RX 8
+#define MX53_DMA_REQ_CSPI1_TX 7
+#define MX53_DMA_REQ_CSPI1_RX 6
+#define MX53_DMA_REQ_IPU 5
+#define MX53_DMA_REQ_ATA_TX_END 4
+#define MX53_DMA_REQ_ATA_UART4_TX 3
+#define MX53_DMA_REQ_ATA_UART4_RX 2
+#define MX53_DMA_REQ_GPC 1
+#define MX53_DMA_REQ_VPU 0
+
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
+#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
+#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
+#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
+#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
+#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
+#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
+#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
+#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
+#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
+#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
+#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
+#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
+#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
+#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
+#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
+#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
+#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
+#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
+#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
+#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
+#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
+#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
+#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
+#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
+#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
+#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
+#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
+#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
+#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
+#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
+#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
+#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
+#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
+#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
+#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
+#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
+#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
+#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
+#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
+#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
+#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
+#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
+#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
+#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
+#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
+#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
+#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
+#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
+#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
+#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
+#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
+#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
+#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
+#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
+#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
+#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
+#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
+#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
+#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
+#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
+#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
+#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
+#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
+#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
+#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
+#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
+#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
+#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
+#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
+#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
+#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
+#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
+#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
+#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
+#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
+#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
+#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
+#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
+#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
+#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
+#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
+#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
+#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
+#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
+#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
+#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
+#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
+#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
+#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
+#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
+#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
+#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
+#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
+#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
+#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
+#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
+#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
+#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
+#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
+#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
+#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
+#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
+#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
+#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
+#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
+#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
+#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
+
+#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h
new file mode 100644
index 00000000000..f7e7dbac8f4
--- /dev/null
+++ b/arch/arm/mach-imx/mx6q.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_MX6Q_H__
+#define __MACH_MX6Q_H__
+
+#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
+#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
+
+/*
+ * The following are the blocks that need to be statically mapped.
+ * For other blocks, the base address really should be retrieved from
+ * device tree.
+ */
+#define MX6Q_SCU_BASE_ADDR 0x00a00000
+#define MX6Q_SCU_SIZE 0x1000
+#define MX6Q_CCM_BASE_ADDR 0x020c4000
+#define MX6Q_CCM_SIZE 0x4000
+#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
+#define MX6Q_ANATOP_SIZE 0x1000
+#define MX6Q_UART2_BASE_ADDR 0x021e8000
+#define MX6Q_UART2_SIZE 0x4000
+#define MX6Q_UART4_BASE_ADDR 0x021f0000
+#define MX6Q_UART4_SIZE 0x4000
+
+#endif /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
new file mode 100644
index 00000000000..d78298366a9
--- /dev/null
+++ b/arch/arm/mach-imx/mxc.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_H__
+#define __ASM_ARCH_MXC_H__
+
+#include <linux/types.h>
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+#define MXC_CPU_MX1 1
+#define MXC_CPU_MX21 21
+#define MXC_CPU_MX25 25
+#define MXC_CPU_MX27 27
+#define MXC_CPU_MX31 31
+#define MXC_CPU_MX35 35
+#define MXC_CPU_MX50 50
+#define MXC_CPU_MX51 51
+#define MXC_CPU_MX53 53
+
+#define IMX_CHIP_REVISION_1_0 0x10
+#define IMX_CHIP_REVISION_1_1 0x11
+#define IMX_CHIP_REVISION_1_2 0x12
+#define IMX_CHIP_REVISION_1_3 0x13
+#define IMX_CHIP_REVISION_2_0 0x20
+#define IMX_CHIP_REVISION_2_1 0x21
+#define IMX_CHIP_REVISION_2_2 0x22
+#define IMX_CHIP_REVISION_2_3 0x23
+#define IMX_CHIP_REVISION_3_0 0x30
+#define IMX_CHIP_REVISION_3_1 0x31
+#define IMX_CHIP_REVISION_3_2 0x32
+#define IMX_CHIP_REVISION_3_3 0x33
+#define IMX_CHIP_REVISION_UNKNOWN 0xff
+
+#ifndef __ASSEMBLY__
+extern unsigned int __mxc_cpu_type;
+#endif
+
+#ifdef CONFIG_SOC_IMX1
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX1
+# endif
+# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
+#else
+# define cpu_is_mx1() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX21
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX21
+# endif
+# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
+#else
+# define cpu_is_mx21() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX25
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX25
+# endif
+# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
+#else
+# define cpu_is_mx25() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX27
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX27
+# endif
+# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
+#else
+# define cpu_is_mx27() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX31
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX31
+# endif
+# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
+#else
+# define cpu_is_mx31() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX35
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX35
+# endif
+# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
+#else
+# define cpu_is_mx35() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX50
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX50
+# endif
+# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
+#else
+# define cpu_is_mx50() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX51
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX51
+# endif
+# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
+#else
+# define cpu_is_mx51() (0)
+#endif
+
+#ifdef CONFIG_SOC_IMX53
+# ifdef mxc_cpu_type
+# undef mxc_cpu_type
+# define mxc_cpu_type __mxc_cpu_type
+# else
+# define mxc_cpu_type MXC_CPU_MX53
+# endif
+# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
+#else
+# define cpu_is_mx53() (0)
+#endif
+
+#ifndef __ASSEMBLY__
+
+struct cpu_op {
+ u32 cpu_rate;
+};
+
+int tzic_enable_wake(void);
+
+extern struct cpu_op *(*get_cpu_op)(int *op);
+#endif
+
+#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
+#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
+
+#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index c491f59e729..51c60823408 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -23,10 +23,9 @@
#include <asm/mach/arch.h>
-#include <mach/hardware.h>
-
#include "common.h"
#include "devices-imx27.h"
+#include "hardware.h"
#include "iomux-mx27.h"
static const int pcm970_pins[] __initconst = {
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 6147be27af4..3777b805b76 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -16,9 +16,9 @@
#include <asm/smp_scu.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
#include "common.h"
+#include "hardware.h"
static void __iomem *scu_base;
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index 6fcffa7db97..56d02d064fb 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -10,7 +10,8 @@
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
-#include <mach/hardware.h>
+
+#include "hardware.h"
static int mx27_suspend_enter(suspend_state_t state)
{
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
index e509be04c92..6a07006ff0f 100644
--- a/arch/arm/mach-imx/pm-imx3.c
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -9,11 +9,11 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/io.h>
-#include <mach/hardware.h>
#include "common.h"
#include "crmregs-imx3.h"
#include "devices/devices-common.h"
+#include "hardware.h"
/*
* Set cpu low power mode before WFI instruction. This function is called
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index a614702872f..2e063c2deb9 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -16,11 +16,11 @@
#include <asm/cacheflush.h>
#include <asm/system_misc.h>
#include <asm/tlbflush.h>
-#include <mach/hardware.h>
#include "common.h"
#include "cpuidle.h"
#include "crm-regs-imx5.h"
+#include "hardware.h"
/*
* The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 05618afb559..a17543da602 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -18,9 +18,9 @@
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>
-#include <mach/hardware.h>
#include "common.h"
+#include "hardware.h"
extern unsigned long phys_l2x0_saved_regs;
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index bbd80f25cdc..695e0d73bf8 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -22,12 +22,12 @@
#include <linux/err.h>
#include <linux/delay.h>
-#include <mach/hardware.h>
#include <asm/system_misc.h>
#include <asm/proc-fns.h>
#include <asm/mach-types.h>
#include "common.h"
+#include "hardware.h"
static void __iomem *wdog_base;
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 8ee6f3608a8..f017302f6d0 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -27,11 +27,11 @@
#include <linux/clk.h>
#include <linux/err.h>
-#include <mach/hardware.h>
#include <asm/sched_clock.h>
#include <asm/mach/time.h>
#include "common.h"
+#include "hardware.h"
/*
* There are 2 versions of the timer hardware on Freescale MXC hardware.
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 6134e962da1..c7625b4a916 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -21,10 +21,10 @@
#include <asm/mach/irq.h>
#include <asm/exception.h>
-#include <mach/hardware.h>
#include <mach/irqs.h>
#include "common.h"
+#include "hardware.h"
#include "irq-common.h"
/*
--
cgit v1.2.3-70-g09d2