From 1a5a954ce0dd8ba1fc8b5305bcdb6e4cf7d6939b Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 16 Mar 2014 20:52:25 +0000 Subject: ARM: l2c: fix register naming We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren Acked-by: Linus Walleij Acked-by: Shawn Guo Acked-by: Stephen Warren Signed-off-by: Russell King --- arch/arm/mach-imx/system.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-imx/system.c') diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index c6571f1de9f..59013a81107 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -124,7 +124,7 @@ void __init imx_init_l2cache(void) } /* Configure the L2 PREFETCH and POWER registers */ - val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); + val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val |= 0x70800000; /* * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 @@ -137,9 +137,9 @@ void __init imx_init_l2cache(void) */ if (cpu_is_imx6q()) val &= ~(1 << 30 | 1 << 23); - writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); - val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; - writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); + writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); + val = L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN; + writel_relaxed(val, l2x0_base + L310_POWER_CTRL); iounmap(l2x0_base); of_node_put(np); -- cgit v1.2.3-70-g09d2