From 94790ec25fdd51dc4126cc176f2e104f80f87fcb Mon Sep 17 00:00:00 2001 From: Jeff Ohlstein Date: Thu, 2 Dec 2010 12:05:12 -0800 Subject: msm: timer: SMP timer support for msm The msm provides timer hardware that is private to each core. Each timer has separate counter and match registers, so we create separate clock_event_devices for each core. For the global clocksource, use cpu 0's counter. Signed-off-by: Jeff Ohlstein Signed-off-by: David Brown --- arch/arm/mach-msm/io.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-msm/io.c') diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index f912d7bf188..800f327a7ec 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -105,6 +105,7 @@ static struct map_desc msm8x60_io_desc[] __initdata = { MSM_DEVICE(QGIC_DIST), MSM_DEVICE(QGIC_CPU), MSM_DEVICE(TMR), + MSM_DEVICE(TMR0), MSM_DEVICE(ACC), MSM_DEVICE(GCC), }; -- cgit v1.2.3-70-g09d2