From 9b5bc5fa4b68fe2f51a5197786a8b5df82d1b8bf Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 8 Jan 2010 15:23:06 -0700 Subject: OMAP3: clock: add clockdomains for UART1 & 2 UART1 & 2 were missing clockdomains resulting in broken omap_hwmod init for these devices. Signed-off-by: Kevin Hilman Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx_data.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-omap2/clock34xx_data.c') diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 8bdcc9cc7f9..c60b19a2723 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -1500,6 +1500,7 @@ static struct clk uart2_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1509,6 +1510,7 @@ static struct clk uart1_fck = { .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; -- cgit v1.2.3-70-g09d2 From 073463ca4011d4f6f8e2334273f3b062b2b19b85 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Jan 2010 15:23:07 -0700 Subject: OMAP3 clock: McBSP 2, 3, 4 functional clock parent is PER_96M_FCLK, not CORE_96M_FCLK The correct parent of the McBSP 2, 3, and 4 functional clocks is PER_96M_FCLK, not CORE_96M_FCLK. Fix this in the OMAP clock tree. Reported by Nicole Chalhoub . Signed-off-by: Paul Walmsley Cc: Nicole Chalhoub --- arch/arm/mach-omap2/clock34xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/clock34xx_data.c') diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index c60b19a2723..7eea9fb09e7 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -2747,7 +2747,7 @@ static struct clk mcbsp4_ick = { }; static const struct clksel mcbsp_234_clksel[] = { - { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, { .parent = NULL } }; -- cgit v1.2.3-70-g09d2 From 3e3ee1560daaf09bb5dbe3afd35ca2f75e2e116a Mon Sep 17 00:00:00 2001 From: Tuukka Toivonen Date: Fri, 8 Jan 2010 15:23:08 -0700 Subject: OMAP3 clock: Add capability to change rate of dpll4_m5_ck MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add necessary definitions to clock framework to allow changing dpll4_m5_ck rate. This is used by the camera code. Signed-off-by: Jouni Högander Signed-off-by: Tuukka Toivonen Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx_data.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-omap2/clock34xx_data.c') diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 7eea9fb09e7..c6031d74d6f 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -776,6 +776,8 @@ static struct clk dpll4_m5_ck = { .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, .clksel = div16_dpll4_clksel, .clkdm_name = "dpll4_clkdm", + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, .recalc = &omap2_clksel_recalc, }; -- cgit v1.2.3-70-g09d2