From 08f3098928c991560408e8c71d4af8b1a3ff2d67 Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Fri, 11 May 2012 00:38:49 +0530 Subject: ARM: OMAP2+: am33xx: Add AM335XEVM machine support This patch adds minimal support for AM335X machine init. During last merge window, two separate patches supporting am33xx machine init had been submitted, 1. Link to earlier Baseport patch submission (Legacy): http://www.mail-archive.com/linux-omap@vger.kernel.org/msg59325.html 2. Link to earlier DT based machine init support patch submission: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg61398.html And both had got accepted at that time, but got missed during merge window. But now, since we have taken decision to make am33xx as a separate class and not to follow omap3 family, these patches needs to changes accordingly (only changes), - Combine both the patches, since early init and timer init used in board-generic.c file requires them. - Remove dependency on AM3517EVM, and only use DT approach for machine init. - Change the config option (as changed recently) CONFIG_SOC_OMAPAM33XX --> CONFIG_SOC_AM33XX Signed-off-by: Vaibhav Hiremath Signed-off-by: Vaibhav Hiremath Cc: Benoit Cousson Cc: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/mach-omap2/io.c') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8d014ba04ab..5d6b2346bf7 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -477,6 +477,16 @@ void __init ti81xx_init_late(void) } #endif +#ifdef CONFIG_SOC_AM33XX +void __init am33xx_init_early(void) +{ + omap2_set_globals_am33xx(); + omap3xxx_check_revision(); + ti81xx_check_features(); + omap_common_init_early(); +} +#endif + #ifdef CONFIG_ARCH_OMAP4 void __init omap4430_init_early(void) { -- cgit v1.2.3-70-g09d2 From ce3fc89a4e120c1fb012efd71f403116b6bcc1ee Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 18 Jun 2012 00:47:26 -0600 Subject: ARM: OMAP AM33xx: voltagedomain: Add voltage domain data Currently dummy voltage domain data is being created in order to succeed boot process, nothing has been done w.r.t actual hardware (voltage control). Also, hook up the AM33XX voltage domain to OMAP framework. Signed-off-by: Vaibhav Hiremath Signed-off-by: Afzal Mohammed Cc: Benoit Cousson Cc: Tony Lindgren Cc: Kevin Hilman Cc: Paul Walmsley Cc: Rajendra Nayak Acked-by: Kevin Hilman [paul@pwsan.com: updated for 3.5] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/common.h | 1 + arch/arm/mach-omap2/io.c | 1 + arch/arm/mach-omap2/voltage.h | 1 + arch/arm/mach-omap2/voltagedomains33xx_data.c | 43 +++++++++++++++++++++++++++ 5 files changed, 47 insertions(+) create mode 100644 arch/arm/mach-omap2/voltagedomains33xx_data.c (limited to 'arch/arm/mach-omap2/io.c') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fa742f3c262..6a3aef66f03 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -99,6 +99,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 56f687bebd0..5d99c1b2cb4 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -129,6 +129,7 @@ void omap3430_init_early(void); void omap35xx_init_early(void); void omap3630_init_early(void); void omap3_init_early(void); /* Do not use this one */ +void am33xx_init_early(void); void am35xx_init_early(void); void ti81xx_init_early(void); void am33xx_init_early(void); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5d6b2346bf7..d15ecb3782b 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -484,6 +484,7 @@ void __init am33xx_init_early(void) omap3xxx_check_revision(); ti81xx_check_features(); omap_common_init_early(); + am33xx_voltagedomains_init(); } #endif diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 16a1b092cf3..a7c43c1042b 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -156,6 +156,7 @@ int omap_voltage_late_init(void); extern void omap2xxx_voltagedomains_init(void); extern void omap3xxx_voltagedomains_init(void); +extern void am33xx_voltagedomains_init(void); extern void omap44xx_voltagedomains_init(void); struct voltagedomain *voltdm_lookup(const char *name); diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c new file mode 100644 index 00000000000..965458dc0cb --- /dev/null +++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c @@ -0,0 +1,43 @@ +/* + * AM33XX voltage domain data + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "voltage.h" + +static struct voltagedomain am33xx_voltdm_mpu = { + .name = "mpu", +}; + +static struct voltagedomain am33xx_voltdm_core = { + .name = "core", +}; + +static struct voltagedomain am33xx_voltdm_rtc = { + .name = "rtc", +}; + +static struct voltagedomain *voltagedomains_am33xx[] __initdata = { + &am33xx_voltdm_mpu, + &am33xx_voltdm_core, + &am33xx_voltdm_rtc, + NULL, +}; + +void __init am33xx_voltagedomains_init(void) +{ + voltdm_init(voltagedomains_am33xx); +} -- cgit v1.2.3-70-g09d2 From 3f0ea7645ae6d7111ebc3e83f47fbc0f2c8a8964 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 18 Jun 2012 00:47:27 -0600 Subject: ARM: OMAP AM33xx: powerdomains: add AM335x support Add offset & mask fields to struct powerdomain In case of AM33xx family of devices, there is no consistency between PWRSTCTRL & PWRSTST register offsers in PRM space, for example - PRM_XXX PWRSTCTRL PWRSTST ======================================= PRM_PER_MOD: 0x0C, 0x08 PRM_WKUP_MOD: 0x04, 0x08 PRM_MPU_MOD: 0x00, 0x04 PRM_DEVICE_MOD: NA, NA And also, there is no consistency between bit-offsets inside PWRSTCTRL & PWRSTST register, for example - PRM_XXX LOGICRET MEMON MEMRET ======================================= GFX_PWRCTRL: 2, 17, 6 PER_PWRCTRL: 3, 25, 29 MPU_PWRCTRL: 2, 18, 22 WKUP_PWRCTRL: 3, NA, NA This means, we need to maintain and pass on all this information in powerdomain handle; so adding fields for, - PWRSTCTRL/ST register offset - Logic retention state mask - mem_on/ret/pwrst/retst mask Currently, this fields is only applicable and used for AM33XX devices. Signed-off-by: Vaibhav Hiremath Cc: Benoit Cousson Cc: Tony Lindgren Cc: Kevin Hilman Cc: Paul Walmsley Cc: Rajendra Nayak [paul@pwsan.com: this patch is a combination of "Add offset & mask fields to struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx: Add powerdomain & PRM support"; updated for 3.5] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/io.c | 1 + arch/arm/mach-omap2/powerdomain.h | 23 ++- arch/arm/mach-omap2/powerdomain33xx.c | 229 ++++++++++++++++++++++++++++ arch/arm/mach-omap2/powerdomains33xx_data.c | 185 ++++++++++++++++++++++ 5 files changed, 438 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c (limited to 'arch/arm/mach-omap2/io.c') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index cc080946ec6..b664dc8722a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -115,6 +115,8 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o +obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o # PRCM clockdomain control clockdomain-common += clockdomain.o diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index d15ecb3782b..3c885248b98 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -485,6 +485,7 @@ void __init am33xx_init_early(void) ti81xx_check_features(); omap_common_init_early(); am33xx_voltagedomains_init(); + am33xx_powerdomains_init(); } #endif diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 8f88d65c46e..a8a95184243 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -67,9 +67,9 @@ /* * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP4 is the worst case + * PER powerdomain on AM33XX is the worst case */ -#define PWRDM_MAX_CLKDMS 9 +#define PWRDM_MAX_CLKDMS 11 /* XXX A completely arbitrary number. What is reasonable here? */ #define PWRDM_TRANSITION_BAILOUT 100000 @@ -92,6 +92,15 @@ struct powerdomain; * @pwrdm_clkdms: Clockdomains in this powerdomain * @node: list_head linking all powerdomains * @voltdm_node: list_head linking all powerdomains in a voltagedomain + * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs + * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs + * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield + * in @pwrstctrl_offs + * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs + * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs + * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs + * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield + * in @pwrstctrl_offs * @state: * @state_counter: * @timer: @@ -121,6 +130,14 @@ struct powerdomain { unsigned ret_logic_off_counter; unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; + const u8 pwrstctrl_offs; + const u8 pwrstst_offs; + const u32 logicretstate_mask; + const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; + const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; + const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; + const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; + #ifdef CONFIG_PM_DEBUG s64 timer; s64 state_timer[PWRDM_MAX_PWRSTS]; @@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); extern void omap242x_powerdomains_init(void); extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); +extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; +extern struct pwrdm_ops am33xx_pwrdm_operations; extern struct pwrdm_ops omap4_pwrdm_operations; /* Common Internal functions used across OMAP rev's */ diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c new file mode 100644 index 00000000000..67c5663899b --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain33xx.c @@ -0,0 +1,229 @@ +/* + * AM33XX Powerdomain control + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include + +#include "powerdomain.h" +#include "prm33xx.h" +#include "prm-regbits-33xx.h" + + +static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + return 0; +} + +static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= OMAP_POWERSTATE_MASK; + v >>= OMAP_POWERSTATE_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= OMAP_POWERSTATEST_MASK; + v >>= OMAP_POWERSTATEST_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= AM33XX_LASTPOWERSTATEENTERED_MASK; + v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; + + return v; +} + +static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) +{ + am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, + (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + return 0; +} + +static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) +{ + am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, + AM33XX_LASTPOWERSTATEENTERED_MASK, + pwrdm->prcm_offs, pwrdm->pwrstst_offs); + return 0; +} + +static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 m; + + m = pwrdm->logicretstate_mask; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= AM33XX_LOGICSTATEST_MASK; + v >>= AM33XX_LOGICSTATEST_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + u32 v, m; + + m = pwrdm->logicretstate_mask; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = pwrdm->mem_on_mask[bank]; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = pwrdm->mem_ret_mask[bank]; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = pwrdm->mem_pwrst_mask[bank]; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = pwrdm->mem_retst_mask[bank]; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) +{ + u32 c = 0; + + /* + * REVISIT: pwrdm_wait_transition() may be better implemented + * via a callback and a periodic timer check -- how long do we expect + * powerdomain transitions to take? + */ + + /* XXX Is this udelay() value meaningful? */ + while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) + & OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); + + if (c > PWRDM_TRANSITION_BAILOUT) { + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); + return -EAGAIN; + } + + pr_debug("powerdomain: completed transition in %d loops\n", c); + + return 0; +} + +struct pwrdm_ops am33xx_pwrdm_operations = { + .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, + .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, + .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, + .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, + .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, + .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, + .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, + .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, + .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, +}; diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c new file mode 100644 index 00000000000..869adb82569 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains33xx_data.c @@ -0,0 +1,185 @@ +/* + * AM33XX Power domain data + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "powerdomain.h" +#include "prcm-common.h" +#include "prm-regbits-33xx.h" +#include "prm33xx.h" + +static struct powerdomain gfx_33xx_pwrdm = { + .name = "gfx_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_GFX_MOD, + .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, + .banks = 1, + .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, + .mem_on_mask = { + [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */ + }, + .mem_ret_mask = { + [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ + }, + .mem_pwrst_mask = { + [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */ + }, + .mem_retst_mask = { + [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ + }, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* gfx_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* gfx_mem */ + }, +}; + +static struct powerdomain rtc_33xx_pwrdm = { + .name = "rtc_pwrdm", + .voltdm = { .name = "rtc" }, + .prcm_offs = AM33XX_PRM_RTC_MOD, + .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET, + .pwrsts = PWRSTS_ON, + .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, +}; + +static struct powerdomain wkup_33xx_pwrdm = { + .name = "wkup_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_WKUP_MOD, + .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET, + .pwrsts = PWRSTS_ON, + .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, +}; + +static struct powerdomain per_33xx_pwrdm = { + .name = "per_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_PER_MOD, + .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, + .banks = 3, + .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, + .mem_on_mask = { + [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */ + }, + .mem_ret_mask = { + [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ + }, + .mem_pwrst_mask = { + [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */ + }, + .mem_retst_mask = { + [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ + }, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* pruss_mem */ + [1] = PWRSTS_OFF_RET, /* per_mem */ + [2] = PWRSTS_OFF_RET, /* ram_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* pruss_mem */ + [1] = PWRSTS_ON, /* per_mem */ + [2] = PWRSTS_ON, /* ram_mem */ + }, +}; + +static struct powerdomain mpu_33xx_pwrdm = { + .name = "mpu_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = AM33XX_PRM_MPU_MOD, + .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, + .banks = 3, + .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, + .mem_on_mask = { + [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */ + }, + .mem_ret_mask = { + [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ + }, + .mem_pwrst_mask = { + [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */ + }, + .mem_retst_mask = { + [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ + }, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l1 */ + [1] = PWRSTS_OFF_RET, /* mpu_l2 */ + [2] = PWRSTS_OFF_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* mpu_l1 */ + [1] = PWRSTS_ON, /* mpu_l2 */ + [2] = PWRSTS_ON, /* mpu_ram */ + }, +}; + +static struct powerdomain cefuse_33xx_pwrdm = { + .name = "cefuse_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_CEFUSE_MOD, + .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct powerdomain *powerdomains_am33xx[] __initdata = { + &gfx_33xx_pwrdm, + &rtc_33xx_pwrdm, + &wkup_33xx_pwrdm, + &per_33xx_pwrdm, + &mpu_33xx_pwrdm, + &cefuse_33xx_pwrdm, + NULL, +}; + +void __init am33xx_powerdomains_init(void) +{ + pwrdm_register_platform_funcs(&am33xx_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_am33xx); + pwrdm_complete_init(); +} -- cgit v1.2.3-70-g09d2 From 9c80f3aa8b7828c89c5bae5c769955d1ac58630b Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 18 Jun 2012 00:47:27 -0600 Subject: ARM: OMAP AM33xx: clockdomains: Add clockdomain data and respective operations AM33XX PRCM module consists of various clockdomains, in all total we have 18 clockdomains available, with following controlling options, - SW Sleep: sw forced sleep transition - SW Wakeup: sw forced wakeup transition This patch adds all available clockdomain data, respective clockdomain operations for AM33XX family of device, and also integrates it into existing OMAP framework. Signed-off-by: Vaibhav Hiremath Signed-off-by: Afzal Mohammed Signed-off-by: Vaibhav Bedia Cc: Kevin Hilman Cc: Rajendra Nayak CC: Tony Lindgren Cc: Paul Walmsley Cc: Benoit Cousson [paul@pwsan.com: removed CLKDM_NO_AUTODEPS from clockdomain flags, removed unnecessary .clktrctrl_offs field; updated for 3.5] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/clockdomain.h | 2 + arch/arm/mach-omap2/clockdomain33xx.c | 74 +++++++++++ arch/arm/mach-omap2/clockdomains33xx_data.c | 196 ++++++++++++++++++++++++++++ arch/arm/mach-omap2/io.c | 1 + 5 files changed, 275 insertions(+) create mode 100644 arch/arm/mach-omap2/clockdomain33xx.c create mode 100644 arch/arm/mach-omap2/clockdomains33xx_data.c (limited to 'arch/arm/mach-omap2/io.c') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b664dc8722a..a4cf93242b0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -133,6 +133,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o +obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index f7b58609bad..72cb12bbb9c 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -195,6 +195,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); +extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void _clkdm_add_autodeps(struct clockdomain *clkdm); extern void _clkdm_del_autodeps(struct clockdomain *clkdm); @@ -202,6 +203,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm); extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; extern struct clkdm_ops omap4_clkdm_operations; +extern struct clkdm_ops am33xx_clkdm_operations; extern struct clkdm_dep gfx_24xx_wkdeps[]; extern struct clkdm_dep dsp_24xx_wkdeps[]; diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c new file mode 100644 index 00000000000..aca6388fad7 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain33xx.c @@ -0,0 +1,74 @@ +/* + * AM33XX clockdomain control + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath + * + * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include "clockdomain.h" +#include "cm33xx.h" + + +static int am33xx_clkdm_sleep(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); +} + +static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); +} + +static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) +{ + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + return am33xx_clkdm_wakeup(clkdm); + + return 0; +} + +static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); + + if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) + am33xx_clkdm_sleep(clkdm); + + return 0; +} + +struct clkdm_ops am33xx_clkdm_operations = { + .clkdm_sleep = am33xx_clkdm_sleep, + .clkdm_wakeup = am33xx_clkdm_wakeup, + .clkdm_allow_idle = am33xx_clkdm_allow_idle, + .clkdm_deny_idle = am33xx_clkdm_deny_idle, + .clkdm_clk_enable = am33xx_clkdm_clk_enable, + .clkdm_clk_disable = am33xx_clkdm_clk_disable, +}; diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c new file mode 100644 index 00000000000..32c90fd9eba --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains33xx_data.c @@ -0,0 +1,196 @@ +/* + * AM33XX Clock Domain data. + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "clockdomain.h" +#include "cm.h" +#include "cm33xx.h" +#include "cm-regbits-33xx.h" + +static struct clockdomain l4ls_am33xx_clkdm = { + .name = "l4ls_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l3s_am33xx_clkdm = { + .name = "l3s_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4fw_am33xx_clkdm = { + .name = "l4fw_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l3_am33xx_clkdm = { + .name = "l3_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4hs_am33xx_clkdm = { + .name = "l4hs_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain ocpwp_l3_am33xx_clkdm = { + .name = "ocpwp_l3_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain pruss_ocp_am33xx_clkdm = { + .name = "pruss_ocp_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain cpsw_125mhz_am33xx_clkdm = { + .name = "cpsw_125mhz_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain lcdc_am33xx_clkdm = { + .name = "lcdc_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain clk_24mhz_am33xx_clkdm = { + .name = "clk_24mhz_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_wkup_am33xx_clkdm = { + .name = "l4_wkup_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .cm_inst = AM33XX_CM_WKUP_MOD, + .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l3_aon_am33xx_clkdm = { + .name = "l3_aon_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .cm_inst = AM33XX_CM_WKUP_MOD, + .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_wkup_aon_am33xx_clkdm = { + .name = "l4_wkup_aon_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .cm_inst = AM33XX_CM_WKUP_MOD, + .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain mpu_am33xx_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .cm_inst = AM33XX_CM_MPU_MOD, + .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_rtc_am33xx_clkdm = { + .name = "l4_rtc_clkdm", + .pwrdm = { .name = "rtc_pwrdm" }, + .cm_inst = AM33XX_CM_RTC_MOD, + .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain gfx_l3_am33xx_clkdm = { + .name = "gfx_l3_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .cm_inst = AM33XX_CM_GFX_MOD, + .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = { + .name = "gfx_l4ls_gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .cm_inst = AM33XX_CM_GFX_MOD, + .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_cefuse_am33xx_clkdm = { + .name = "l4_cefuse_clkdm", + .pwrdm = { .name = "cefuse_pwrdm" }, + .cm_inst = AM33XX_CM_CEFUSE_MOD, + .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain *clockdomains_am33xx[] __initdata = { + &l4ls_am33xx_clkdm, + &l3s_am33xx_clkdm, + &l4fw_am33xx_clkdm, + &l3_am33xx_clkdm, + &l4hs_am33xx_clkdm, + &ocpwp_l3_am33xx_clkdm, + &pruss_ocp_am33xx_clkdm, + &cpsw_125mhz_am33xx_clkdm, + &lcdc_am33xx_clkdm, + &clk_24mhz_am33xx_clkdm, + &l4_wkup_am33xx_clkdm, + &l3_aon_am33xx_clkdm, + &l4_wkup_aon_am33xx_clkdm, + &mpu_am33xx_clkdm, + &l4_rtc_am33xx_clkdm, + &gfx_l3_am33xx_clkdm, + &gfx_l4ls_gfx_am33xx_clkdm, + &l4_cefuse_am33xx_clkdm, + NULL, +}; + +void __init am33xx_clockdomains_init(void) +{ + clkdm_register_platform_funcs(&am33xx_clkdm_operations); + clkdm_register_clkdms(clockdomains_am33xx); + clkdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3c885248b98..cb6c11cd8df 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -486,6 +486,7 @@ void __init am33xx_init_early(void) omap_common_init_early(); am33xx_voltagedomains_init(); am33xx_powerdomains_init(); + am33xx_clockdomains_init(); } #endif -- cgit v1.2.3-70-g09d2 From e30384abd63dfa11508a38243e1d78f1d70486b1 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 29 May 2012 15:26:41 +0530 Subject: ARM: OMAP3+: clock33xx: Add AM33XX clock tree data AM33XX clock implementation is different than any existing OMAP family of devices. Although DPLL module is similar to OMAP4 device, but the usage is very much different than OMAP4. AM33XX has different peripheral set and each module gets integrated to the clock framework differently than OMAP family of devices. This patch adds full Clock tree data for AM33XX family of devices and also integrates it into existing OMAP framework. Signed-off-by: Vaibhav Hiremath Signed-off-by: Afzal Mohammed Signed-off-by: Vaibhav Bedia Cc: Kevin Hilman Cc: Rajendra Nayak CC: Tony Lindgren Cc: Paul Walmsley Cc: Benoit Cousson [paul@pwsan.com: updated to apply; changed 'soc_is_am33xx' to 'cpu_is_am33xx' to match usage in Tony's current am33xx branch] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/clock.h | 2 + arch/arm/mach-omap2/clock33xx_data.c | 1105 +++++++++++++++++++++++++ arch/arm/mach-omap2/io.c | 2 + arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 + 5 files changed, 1112 insertions(+) create mode 100644 arch/arm/mach-omap2/clock33xx_data.c (limited to 'arch/arm/mach-omap2/io.c') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index a4cf93242b0..b167152ca69 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -152,6 +152,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 980b0a436c2..35ec5f3d9a7 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -167,4 +167,6 @@ extern const struct clksel_rate div31_1to31_rates[]; extern struct clk virt_19200000_ck; extern struct clk virt_26000000_ck; +extern int am33xx_clk_init(void); + #endif diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c new file mode 100644 index 00000000000..9c8ac7dc9f3 --- /dev/null +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -0,0 +1,1105 @@ +/* + * AM33XX Clock data + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "iomap.h" +#include "control.h" +#include "clock.h" +#include "cm.h" +#include "cm33xx.h" +#include "cm-regbits-33xx.h" +#include "prm.h" + +/* Maximum DPLL multiplier, divider values for AM33XX */ +#define AM33XX_MAX_DPLL_MULT 2047 +#define AM33XX_MAX_DPLL_DIV 128 + +/* Modulemode control */ +#define AM33XX_MODULEMODE_HWCTRL 0 +#define AM33XX_MODULEMODE_SWCTRL 1 + +/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always + * physically present, in such a case HWMOD enabling of + * clock would be failure with default parent. And timer + * probe thinks clock is already enabled, this leads to + * crash upon accessing timer 3 & 6 registers in probe. + * Fix by setting parent of both these timers to master + * oscillator clock. + */ +static inline void am33xx_init_timer_parent(struct clk *clk) +{ + omap2_clksel_set_parent(clk, clk->parent); +} + +/* Root clocks */ + +/* RTC 32k */ +static struct clk clk_32768_ck = { + .name = "clk_32768_ck", + .clkdm_name = "l4_rtc_clkdm", + .rate = 32768, + .ops = &clkops_null, +}; + +/* On-Chip 32KHz RC OSC */ +static struct clk clk_rc32k_ck = { + .name = "clk_rc32k_ck", + .rate = 32000, + .ops = &clkops_null, +}; + +/* Crystal input clks */ +static struct clk virt_24000000_ck = { + .name = "virt_24000000_ck", + .rate = 24000000, + .ops = &clkops_null, +}; + +static struct clk virt_25000000_ck = { + .name = "virt_25000000_ck", + .rate = 25000000, + .ops = &clkops_null, +}; + +/* Oscillator clock */ +/* 19.2, 24, 25 or 26 MHz */ +static const struct clksel sys_clkin_sel[] = { + { .parent = &virt_19200000_ck, .rates = div_1_0_rates }, + { .parent = &virt_24000000_ck, .rates = div_1_1_rates }, + { .parent = &virt_25000000_ck, .rates = div_1_2_rates }, + { .parent = &virt_26000000_ck, .rates = div_1_3_rates }, + { .parent = NULL }, +}; + +/* External clock - 12 MHz */ +static struct clk tclkin_ck = { + .name = "tclkin_ck", + .rate = 12000000, + .ops = &clkops_null, +}; + +/* + * sys_clk in: input to the dpll and also used as funtional clock for, + * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse + * + */ +static struct clk sys_clkin_ck = { + .name = "sys_clkin_ck", + .parent = &virt_24000000_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), + .clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK, + .clksel = sys_clkin_sel, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKDCOLDO output */ +static struct clk dpll_core_ck = { + .name = "dpll_core_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_core_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_omap3_core_dpll_ops, + .recalc = &omap3_dpll_recalc, +}; + +static struct clk dpll_core_x2_ck = { + .name = "dpll_core_x2_ck", + .parent = &dpll_core_ck, + .flags = CLOCK_CLKOUTX2, + .ops = &clkops_null, + .recalc = &omap3_clkoutx2_recalc, +}; + + +static const struct clksel dpll_core_m4_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_core_m4_ck = { + .name = "dpll_core_m4_ck", + .parent = &dpll_core_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel = dpll_core_m4_div, + .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE, + .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel dpll_core_m5_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_core_m5_ck = { + .name = "dpll_core_m5_ck", + .parent = &dpll_core_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel = dpll_core_m5_div, + .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE, + .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel dpll_core_m6_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_core_m6_ck = { + .name = "dpll_core_m6_ck", + .parent = &dpll_core_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel = dpll_core_m6_div, + .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE, + .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_mpu_ck = { + .name = "dpll_mpu_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_mpu_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_omap3_noncore_dpll_ops, + .recalc = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +static const struct clksel dpll_mpu_m2_div[] = { + { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_mpu_m2_ck = { + .name = "dpll_mpu_m2_ck", + .clkdm_name = "mpu_clkdm", + .parent = &dpll_mpu_ck, + .clksel = dpll_mpu_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* DPLL_DDR */ +static struct dpll_data dpll_ddr_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_ddr_ck = { + .name = "dpll_ddr_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_ddr_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_null, + .recalc = &omap3_dpll_recalc, +}; + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +static const struct clksel dpll_ddr_m2_div[] = { + { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_ddr_m2_ck = { + .name = "dpll_ddr_m2_ck", + .parent = &dpll_ddr_ck, + .clksel = dpll_ddr_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* emif_fck functional clock */ +static struct clk dpll_ddr_m2_div2_ck = { + .name = "dpll_ddr_m2_div2_ck", + .clkdm_name = "l3_clkdm", + .parent = &dpll_ddr_m2_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +/* DPLL_DISP */ +static struct dpll_data dpll_disp_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_disp_ck = { + .name = "dpll_disp_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_disp_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_null, + .recalc = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +static const struct clksel dpll_disp_m2_div[] = { + { .parent = &dpll_disp_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_disp_m2_ck = { + .name = "dpll_disp_m2_ck", + .parent = &dpll_disp_ck, + .clksel = dpll_disp_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, + .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, + .div1_mask = AM33XX_DPLL_PER_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, + .flags = DPLL_J_TYPE, +}; + +/* CLKDCOLDO */ +static struct clk dpll_per_ck = { + .name = "dpll_per_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_per_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_null, + .recalc = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +/* CLKOUT: fdpll/M2 */ +static const struct clksel dpll_per_m2_div[] = { + { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_per_m2_ck = { + .name = "dpll_per_m2_ck", + .parent = &dpll_per_ck, + .clksel = dpll_per_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk dpll_per_m2_div4_wkupdm_ck = { + .name = "dpll_per_m2_div4_wkupdm_ck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &dpll_per_m2_ck, + .fixed_div = 4, + .ops = &clkops_null, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk dpll_per_m2_div4_ck = { + .name = "dpll_per_m2_div4_ck", + .clkdm_name = "l4ls_clkdm", + .parent = &dpll_per_m2_ck, + .fixed_div = 4, + .ops = &clkops_null, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk l3_gclk = { + .name = "l3_gclk", + .clkdm_name = "l3_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk dpll_core_m4_div2_ck = { + .name = "dpll_core_m4_div2_ck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk l4_rtc_gclk = { + .name = "l4_rtc_gclk", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk clk_24mhz = { + .name = "clk_24mhz", + .parent = &dpll_per_m2_ck, + .fixed_div = 8, + .ops = &clkops_null, + .recalc = &omap_fixed_divisor_recalc, +}; + +/* + * Below clock nodes describes clockdomains derived out + * of core clock. + */ +static struct clk l4hs_gclk = { + .name = "l4hs_gclk", + .clkdm_name = "l4hs_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk l3s_gclk = { + .name = "l3s_gclk", + .clkdm_name = "l3s_clkdm", + .parent = &dpll_core_m4_div2_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk l4fw_gclk = { + .name = "l4fw_gclk", + .clkdm_name = "l4fw_clkdm", + .parent = &dpll_core_m4_div2_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk l4ls_gclk = { + .name = "l4ls_gclk", + .clkdm_name = "l4ls_clkdm", + .parent = &dpll_core_m4_div2_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk sysclk_div_ck = { + .name = "sysclk_div_ck", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +/* + * In order to match the clock domain with hwmod clockdomain entry, + * separate clock nodes is required for the modules which are + * directly getting their funtioncal clock from sys_clkin. + */ +static struct clk adc_tsc_fck = { + .name = "adc_tsc_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk dcan0_fck = { + .name = "dcan0_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk dcan1_fck = { + .name = "dcan1_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk mcasp0_fck = { + .name = "mcasp0_fck", + .clkdm_name = "l3s_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk mcasp1_fck = { + .name = "mcasp1_fck", + .clkdm_name = "l3s_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk smartreflex0_fck = { + .name = "smartreflex0_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk smartreflex1_fck = { + .name = "smartreflex1_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +/* + * Modules clock nodes + * + * The following clock leaf nodes are added for the moment because: + * + * - hwmod data is not present for these modules, either hwmod + * control is not required or its not populated. + * - Driver code is not yet migrated to use hwmod/runtime pm + * - Modules outside kernel access (to disable them by default) + * + * - debugss + * - mmu (gfx domain) + * - cefuse + * - usbotg_fck (its additional clock and not really a modulemode) + * - ieee5000 + */ +static struct clk debugss_ick = { + .name = "debugss_ick", + .clkdm_name = "l3_aon_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_omap2_dflt, + .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .recalc = &followparent_recalc, +}; + +static struct clk mmu_fck = { + .name = "mmu_fck", + .clkdm_name = "gfx_l3_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_omap2_dflt, + .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .recalc = &followparent_recalc, +}; + +static struct clk cefuse_fck = { + .name = "cefuse_fck", + .clkdm_name = "l4_cefuse_clkdm", + .parent = &sys_clkin_ck, + .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +/* + * clkdiv32 is generated from fixed division of 732.4219 + */ +static struct clk clkdiv32k_ick = { + .name = "clkdiv32k_ick", + .clkdm_name = "clk_24mhz_clkdm", + .rate = 32768, + .parent = &clk_24mhz, + .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .ops = &clkops_omap2_dflt, +}; + +static struct clk usbotg_fck = { + .name = "usbotg_fck", + .clkdm_name = "l3s_clkdm", + .parent = &dpll_per_ck, + .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER, + .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk ieee5000_fck = { + .name = "ieee5000_fck", + .clkdm_name = "l3s_clkdm", + .parent = &dpll_core_m4_div2_ck, + .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +/* Timers */ +static const struct clksel timer1_clkmux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = &tclkin_ck, .rates = div_1_2_rates }, + { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, + { .parent = &clk_32768_ck, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static struct clk timer1_fck = { + .name = "timer1_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer1_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, + .clksel_mask = AM33XX_CLKSEL_0_2_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel timer2_to_7_clk_sel[] = { + { .parent = &tclkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk timer2_fck = { + .name = "timer2_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer3_fck = { + .name = "timer3_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &am33xx_init_timer_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer4_fck = { + .name = "timer4_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer5_fck = { + .name = "timer5_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer6_fck = { + .name = "timer6_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &am33xx_init_timer_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer7_fck = { + .name = "timer7_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk cpsw_125mhz_gclk = { + .name = "cpsw_125mhz_gclk", + .clkdm_name = "cpsw_125mhz_clkdm", + .parent = &dpll_core_m5_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { + { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk cpsw_cpts_rft_clk = { + .name = "cpsw_cpts_rft_clk", + .clkdm_name = "cpsw_125mhz_clkdm", + .parent = &dpll_core_m5_ck, + .clksel = cpsw_cpts_rft_clkmux_sel, + .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +/* gpio */ +static const struct clksel gpio0_dbclk_mux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clk_32768_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk gpio0_dbclk_mux_ck = { + .name = "gpio0_dbclk_mux_ck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &clk_rc32k_ck, + .init = &omap2_init_clksel_parent, + .clksel = gpio0_dbclk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpio0_dbclk = { + .name = "gpio0_dbclk", + .clkdm_name = "l4_wkup_clkdm", + .parent = &gpio0_dbclk_mux_ck, + .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk gpio1_dbclk = { + .name = "gpio1_dbclk", + .clkdm_name = "l4ls_clkdm", + .parent = &clkdiv32k_ick, + .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk gpio2_dbclk = { + .name = "gpio2_dbclk", + .clkdm_name = "l4ls_clkdm", + .parent = &clkdiv32k_ick, + .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk gpio3_dbclk = { + .name = "gpio3_dbclk", + .clkdm_name = "l4ls_clkdm", + .parent = &clkdiv32k_ick, + .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static const struct clksel pruss_ocp_clk_mux_sel[] = { + { .parent = &l3_gclk, .rates = div_1_0_rates }, + { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk pruss_ocp_gclk = { + .name = "pruss_ocp_gclk", + .clkdm_name = "pruss_ocp_clkdm", + .parent = &l3_gclk, + .init = &omap2_init_clksel_parent, + .clksel = pruss_ocp_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static const struct clksel lcd_clk_mux_sel[] = { + { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk lcd_gclk = { + .name = "lcd_gclk", + .clkdm_name = "lcdc_clkdm", + .parent = &dpll_disp_m2_ck, + .init = &omap2_init_clksel_parent, + .clksel = lcd_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk mmc_clk = { + .name = "mmc_clk", + .clkdm_name = "l4ls_clkdm", + .parent = &dpll_per_m2_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk mmc2_fck = { + .name = "mmc2_fck", + .clkdm_name = "l3s_clkdm", + .parent = &mmc_clk, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static const struct clksel gfx_clksel_sel[] = { + { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk gfx_fclk_clksel_ck = { + .name = "gfx_fclk_clksel_ck", + .parent = &dpll_core_m4_ck, + .clksel = gfx_clksel_sel, + .ops = &clkops_null, + .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, + .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate div_1_0_2_1_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, + { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, + { .div = 0 }, +}; + +static const struct clksel gfx_div_sel[] = { + { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates }, + { .parent = NULL }, +}; + +static struct clk gfx_fck_div_ck = { + .name = "gfx_fck_div_ck", + .clkdm_name = "gfx_l3_clkdm", + .parent = &gfx_fclk_clksel_ck, + .init = &omap2_init_clksel_parent, + .clksel = gfx_div_sel, + .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .ops = &clkops_null, +}; + +static const struct clksel sysclkout_pre_sel[] = { + { .parent = &clk_32768_ck, .rates = div_1_0_rates }, + { .parent = &l3_gclk, .rates = div_1_1_rates }, + { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, + { .parent = &lcd_gclk, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static struct clk sysclkout_pre_ck = { + .name = "sysclkout_pre_ck", + .parent = &clk_32768_ck, + .init = &omap2_init_clksel_parent, + .clksel = sysclkout_pre_sel, + .clksel_reg = AM33XX_CM_CLKOUT_CTRL, + .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +/* Divide by 8 clock rates with default clock is 1/1*/ +static const struct clksel_rate div8_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, + { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, + { .div = 3, .val = 2, .flags = RATE_IN_AM33XX }, + { .div = 4, .val = 3, .flags = RATE_IN_AM33XX }, + { .div = 5, .val = 4, .flags = RATE_IN_AM33XX }, + { .div = 6, .val = 5, .flags = RATE_IN_AM33XX }, + { .div = 7, .val = 6, .flags = RATE_IN_AM33XX }, + { .div = 8, .val = 7, .flags = RATE_IN_AM33XX }, + { .div = 0 }, +}; + +static const struct clksel clkout2_div[] = { + { .parent = &sysclkout_pre_ck, .rates = div8_rates }, + { .parent = NULL }, +}; + +static struct clk clkout2_ck = { + .name = "clkout2_ck", + .parent = &sysclkout_pre_ck, + .ops = &clkops_omap2_dflt, + .clksel = clkout2_div, + .clksel_reg = AM33XX_CM_CLKOUT_CTRL, + .clksel_mask = AM33XX_CLKOUT2DIV_MASK, + .enable_reg = AM33XX_CM_CLKOUT_CTRL, + .enable_bit = AM33XX_CLKOUT2EN_SHIFT, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel wdt_clkmux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk wdt1_fck = { + .name = "wdt1_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &clk_rc32k_ck, + .init = &omap2_init_clksel_parent, + .clksel = wdt_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +/* + * clkdev + */ +static struct omap_clk am33xx_clks[] = { + CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), + CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), + CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), + CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), + CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), + CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), + CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), + CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), + CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), + CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), + CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), + CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX), + CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX), + CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX), + CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), + CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), + CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), + CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX), + CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX), + CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX), + CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX), + CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX), + CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX), + CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX), + CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), + CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), + CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), + CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), + CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), + CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), + CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), + CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), + CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), + CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), + CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), + CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), + CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), + CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), + CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), + CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), + CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), + CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), + CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), + CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), + CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX), +}; + +int __init am33xx_clk_init(void) +{ + struct omap_clk *c; + u32 cpu_clkflg; + + if (cpu_is_am33xx()) { + cpu_mask = RATE_IN_AM33XX; + cpu_clkflg = CK_AM33XX; + } + + clk_init(&omap2_clk_functions); + + for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) + clk_preinit(c->lk.clk); + + for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); + omap2_init_clk_clkdm(c->lk.clk); + } + } + + recalculate_root_clocks(); + + /* + * Only enable those clocks we will need, let the drivers + * enable other clocks as necessary + */ + clk_enable_init_clocks(); + + return 0; +} diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cb6c11cd8df..eb007d03ec9 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -38,6 +38,7 @@ #include "powerdomain.h" #include "clockdomain.h" #include "common.h" +#include "clock.h" #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" @@ -487,6 +488,7 @@ void __init am33xx_init_early(void) am33xx_voltagedomains_init(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); + am33xx_clk_init(); } #endif diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index d0ed8c443a6..025d85a3ee8 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -39,6 +39,7 @@ struct omap_clk { #define CK_443X (1 << 11) #define CK_TI816X (1 << 12) #define CK_446X (1 << 13) +#define CK_AM33XX (1 << 14) /* AM33xx specific clocks */ #define CK_1710 (1 << 15) /* 1710 extra for rate selection */ -- cgit v1.2.3-70-g09d2 From 05e152c76a1efaa3165afecf5acf535c8283f386 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Tue, 5 Jun 2012 16:21:32 +0530 Subject: ARM: OMAP5: Add minimal support for OMAP5430 SOC OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller. OMAP5432 is another variant of OMAP5430, with a memory controller supporting DDR3 and SATA. Patch includes: - The machine specific headers and sources updates. - Platform header updates. - Minimum initialisation support for serial. - IO table init Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/Makefile | 23 +++++++++++--- arch/arm/mach-omap2/common.c | 24 ++++++++++++++ arch/arm/mach-omap2/common.h | 11 +++++++ arch/arm/mach-omap2/include/mach/debug-macro.S | 8 ++--- arch/arm/mach-omap2/io.c | 44 ++++++++++++++++++++++++++ arch/arm/mach-omap2/iomap.h | 27 ++++++++++++++++ arch/arm/mach-omap2/omap_hwmod.c | 2 +- arch/arm/mach-omap2/prcm-common.h | 2 +- arch/arm/mach-omap2/prcm.c | 2 +- arch/arm/plat-omap/include/plat/hardware.h | 1 + arch/arm/plat-omap/include/plat/multi.h | 9 ++++++ arch/arm/plat-omap/include/plat/omap54xx.h | 32 +++++++++++++++++++ arch/arm/plat-omap/include/plat/serial.h | 10 ++++++ arch/arm/plat-omap/include/plat/uncompress.h | 6 ++++ arch/arm/plat-omap/sram.c | 11 +++++-- 15 files changed, 198 insertions(+), 14 deletions(-) create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h (limited to 'arch/arm/mach-omap2/io.c') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 240f1969f2a..085e17175ef 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) +obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -29,8 +30,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o +omap-4-5-common = omap4-common.o omap-wakeupgen.o \ + sleep44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -70,6 +73,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o @@ -85,14 +89,16 @@ endif endif # PRCM +omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \ + prcm_mpu44xx.o prminst44xx.o \ + vc44xx_data.o vp44xx_data.o obj-y += prm_common.o obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o -obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o -obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -104,6 +110,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -121,6 +128,8 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) +obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -139,6 +148,8 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) +obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o @@ -157,6 +168,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_OMAP5) += $(clock-common) +obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 73d2a0b9ca0..069f9725b1c 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -178,3 +178,27 @@ void __init omap4_map_io(void) } #endif +#if defined(CONFIG_SOC_OMAP5) +static struct omap_globals omap5_globals = { + .class = OMAP54XX_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + .ctrl = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE), + .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE), + .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), + .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE), + .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE), +}; + +void __init omap2_set_globals_5xxx(void) +{ + omap2_set_globals_tap(&omap5_globals); + omap2_set_globals_control(&omap5_globals); + omap2_set_globals_prcm(&omap5_globals); +} + +void __init omap5_map_io(void) +{ + omap5_map_common_io(); +} +#endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 404f172d95a..399e5bb1383 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -115,6 +115,14 @@ static inline int omap_mux_late_init(void) } #endif +#ifdef CONFIG_SOC_OMAP5 +extern void omap5_map_common_io(void); +#else +static inline void omap5_map_common_io(void) +{ +} +#endif + extern void omap2_init_common_infrastructure(void); extern struct sys_timer omap2_timer; @@ -134,6 +142,7 @@ void am35xx_init_early(void); void ti81xx_init_early(void); void am33xx_init_early(void); void omap4430_init_early(void); +void omap5_init_early(void); void omap3_init_late(void); /* Do not use this one */ void omap4430_init_late(void); void omap2420_init_late(void); @@ -169,6 +178,7 @@ void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_3xxx(void); void omap2_set_globals_443x(void); +void omap2_set_globals_5xxx(void); void omap2_set_globals_ti81xx(void); void omap2_set_globals_am33xx(void); @@ -188,6 +198,7 @@ void omap243x_map_io(void); void omap3_map_io(void); void am33xx_map_io(void); void omap4_map_io(void); +void omap5_map_io(void); void ti81xx_map_io(void); void omap_barriers_init(void); diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index d7f844a99a7..93d10de7129 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -60,12 +60,12 @@ omap_uart_lsr: .word 0 beq 23f @ configure OMAP2UART3 cmp \rp, #OMAP3UART3 @ only on 34xx beq 33f @ configure OMAP3UART3 - cmp \rp, #OMAP4UART3 @ only on 44xx - beq 43f @ configure OMAP4UART3 + cmp \rp, #OMAP4UART3 @ only on 44xx/54xx + beq 43f @ configure OMAP4/5UART3 cmp \rp, #OMAP3UART4 @ only on 36xx beq 34f @ configure OMAP3UART4 - cmp \rp, #OMAP4UART4 @ only on 44xx - beq 44f @ configure OMAP4UART4 + cmp \rp, #OMAP4UART4 @ only on 44xx/54xx + beq 44f @ configure OMAP4/5UART4 cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different beq 81f @ configure UART1 cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cb6c11cd8df..8976be90c8e 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -233,6 +233,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = { }; #endif +#ifdef CONFIG_SOC_OMAP5 +static struct map_desc omap54xx_io_desc[] __initdata = { + { + .virtual = L3_54XX_VIRT, + .pfn = __phys_to_pfn(L3_54XX_PHYS), + .length = L3_54XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_54XX_VIRT, + .pfn = __phys_to_pfn(L4_54XX_PHYS), + .length = L4_54XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_WK_54XX_VIRT, + .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), + .length = L4_WK_54XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_PER_54XX_VIRT, + .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), + .length = L4_PER_54XX_SIZE, + .type = MT_DEVICE, + }, +}; +#endif + #ifdef CONFIG_SOC_OMAP2420 void __init omap242x_map_common_io(void) { @@ -278,6 +307,12 @@ void __init omap44xx_map_common_io(void) } #endif +#ifdef CONFIG_SOC_OMAP5 +void __init omap5_map_common_io(void) +{ + iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); +} +#endif /* * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters * @@ -513,6 +548,15 @@ void __init omap4430_init_late(void) } #endif +#ifdef CONFIG_SOC_OMAP5 +void __init omap5_init_early(void) +{ + omap2_set_globals_5xxx(); + omap5xxx_check_revision(); + omap_common_init_early(); +} +#endif + void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h index 80b88921fab..cce2b65039f 100644 --- a/arch/arm/mach-omap2/iomap.h +++ b/arch/arm/mach-omap2/iomap.h @@ -1,6 +1,14 @@ /* * IO mappings for OMAP2+ * + * IO definitions for TI OMAP processors and boards + * + * Copied from arch/arm/mach-sa1100/include/mach/io.h + * Copyright (C) 1997-1999 Russell King + * + * Copyright (C) 2009-2012 Texas Instruments + * Added OMAP4/5 support - Santosh Shilimkar + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -166,4 +174,23 @@ /* 0x49000000 --> 0xfb000000 */ #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) #define L4_ABE_44XX_SIZE SZ_1M +/* + * ---------------------------------------------------------------------------- + * Omap5 specific IO mapping + * ---------------------------------------------------------------------------- + */ +#define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */ +#define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET) +#define L3_54XX_SIZE SZ_1M + +#define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */ +#define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_54XX_SIZE SZ_4M + +#define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */ +#define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_WK_54XX_SIZE SZ_2M +#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */ +#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_PER_54XX_SIZE SZ_4M diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index ff76ef1d723..2ada3642c67 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3619,7 +3619,7 @@ void __init omap_hwmod_init(void) soc_ops.assert_hardreset = _omap2_assert_hardreset; soc_ops.deassert_hardreset = _omap2_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; - } else if (cpu_is_omap44xx()) { + } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; soc_ops.wait_target_ready = _omap4_wait_target_ready; diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 6da3ba483ad..44485a8f255 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -416,7 +416,7 @@ extern void __iomem *cm_base; extern void __iomem *cm2_base; extern void __iomem *prcm_mpu_base; -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5) +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) extern void omap_prm_base_init(void); extern void omap_cm_base_init(void); #else diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 28cbfb2b573..053e24ed3c4 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -160,7 +160,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) if (omap2_globals->prcm_mpu) prcm_mpu_base = omap2_globals->prcm_mpu; - if (cpu_is_omap44xx()) { + if (cpu_is_omap44xx() || soc_is_omap54xx()) { omap_prm_base_init(); omap_cm_base_init(); } diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index e897978371c..ddbde38e1e3 100644 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -288,5 +288,6 @@ #include #include #include +#include #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h index 999ffba2690..045e320f106 100644 --- a/arch/arm/plat-omap/include/plat/multi.h +++ b/arch/arm/plat-omap/include/plat/multi.h @@ -99,4 +99,13 @@ # endif #endif +#ifdef CONFIG_SOC_OMAP5 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap5 +# endif +#endif + #endif /* __PLAT_OMAP_MULTI_H */ diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h new file mode 100644 index 00000000000..a2582bb3cab --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap54xx.h @@ -0,0 +1,32 @@ +/*: + * Address mappings and base address for OMAP5 interconnects + * and peripherals. + * + * Copyright (C) 2012 Texas Instruments + * Santosh Shilimkar + * Sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_SOC_OMAP54XX_H +#define __ASM_SOC_OMAP54XX_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ +#define L4_54XX_BASE 0x4a000000 +#define L4_WK_54XX_BASE 0x4ae00000 +#define L4_PER_54XX_BASE 0x48000000 +#define L3_54XX_BASE 0x44000000 +#define OMAP54XX_32KSYNCT_BASE 0x4ae04000 +#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 +#define OMAP54XX_CM_CORE_BASE 0x4a008000 +#define OMAP54XX_PRM_BASE 0x4ae06000 +#define OMAP54XX_PRCM_MPU_BASE 0x48243000 +#define OMAP54XX_SCM_BASE 0x4a002000 +#define OMAP54XX_CTRL_BASE 0x4a002800 + +#endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 28e2d250c2f..65fce44dce3 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -63,6 +63,14 @@ /* AM33XX serial port */ #define AM33XX_UART1_BASE 0x44E09000 +/* OMAP5 serial ports */ +#define OMAP5_UART1_BASE OMAP2_UART1_BASE +#define OMAP5_UART2_BASE OMAP2_UART2_BASE +#define OMAP5_UART3_BASE OMAP4_UART3_BASE +#define OMAP5_UART4_BASE OMAP4_UART4_BASE +#define OMAP5_UART5_BASE 0x48066000 +#define OMAP5_UART6_BASE 0x48068000 + /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 @@ -97,6 +105,8 @@ #define TI81XXUART2 82 #define TI81XXUART3 83 #define AM33XXUART1 84 +#define OMAP5UART3 OMAP4UART3 +#define OMAP5UART4 OMAP4UART4 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ac432339021..b8d19a13678 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -95,6 +95,9 @@ static inline void flush(void) _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \ OMAP4UART##p) +#define DEBUG_LL_OMAP5(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP5UART##p) /* Zoom2/3 shift is different for UART1 and external port */ #define DEBUG_LL_ZOOM(mach) \ _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) @@ -177,6 +180,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_OMAP4(3, omap_4430sdp); DEBUG_LL_OMAP4(3, omap4_panda); + /* omap5 based boards using UART3 */ + DEBUG_LL_OMAP5(3, omap5_sevm); + /* zoom2/3 external uart */ DEBUG_LL_ZOOM(omap_zoom2); DEBUG_LL_ZOOM(omap_zoom3); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 70cf825bdd8..766181cb5c9 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -6,8 +6,8 @@ * Copyright (C) 2005 Nokia Corporation * Written by Tony Lindgren * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar + * Copyright (C) 2009-2012 Texas Instruments + * Added OMAP4/5 support - Santosh Shilimkar * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -44,6 +44,7 @@ #else #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #endif +#define OMAP5_SRAM_PA 0x40300000 #if defined(CONFIG_ARCH_OMAP2PLUS) #define SRAM_BOOTLOADER_SZ 0x00 @@ -118,6 +119,9 @@ static void __init omap_detect_sram(void) } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PUB_PA; omap_sram_size = 0xa000; /* 40K */ + } else if (soc_is_omap54xx()) { + omap_sram_start = OMAP5_SRAM_PA; + omap_sram_size = SZ_128K; /* 128KB */ } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ @@ -132,6 +136,9 @@ static void __init omap_detect_sram(void) } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PA; omap_sram_size = 0xe000; /* 56K */ + } else if (soc_is_omap54xx()) { + omap_sram_start = OMAP5_SRAM_PA; + omap_sram_size = SZ_128K; /* 128KB */ } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) -- cgit v1.2.3-70-g09d2