From b580b899dd05a007ad232ee49a07b32d91876462 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Dec 2010 15:55:14 +0000 Subject: ARM: GIC: provide a single initialization function for boot CPU Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/mach-omap2/omap4-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2/omap4-common.c') diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 2f895553e6a..3fd3df7a769 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -35,12 +35,12 @@ void __init gic_init_irq(void) /* Static mapping, never released */ gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); BUG_ON(!gic_dist_base_addr); - gic_dist_init(0, gic_dist_base_addr, 29); /* Static mapping, never released */ gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); BUG_ON(!gic_cpu_base_addr); - gic_cpu_init(0, gic_cpu_base_addr); + + gic_init(0, 29, gic_dist_base_addr, gic_cpu_base_addr); } #ifdef CONFIG_CACHE_L2X0 -- cgit v1.2.3-70-g09d2 From ff2e27ae0b17f53a6a289c87d325f706598f3788 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Dec 2010 16:13:29 +0000 Subject: ARM: GIC: consolidate gic_cpu_base_addr to common GIC code Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/common/gic.c | 5 +++++ arch/arm/include/asm/hardware/gic.h | 2 ++ arch/arm/mach-cns3xxx/core.c | 5 +---- arch/arm/mach-cns3xxx/core.h | 1 - arch/arm/mach-msm/board-msm8x60.c | 6 ++---- arch/arm/mach-omap2/include/mach/omap4-common.h | 1 - arch/arm/mach-omap2/omap4-common.c | 9 +++++---- arch/arm/mach-realview/core.c | 3 --- arch/arm/mach-realview/core.h | 1 - arch/arm/mach-realview/realview_eb.c | 6 ++---- arch/arm/mach-realview/realview_pb1176.c | 3 +-- arch/arm/mach-realview/realview_pb11mp.c | 3 +-- arch/arm/mach-realview/realview_pba8.c | 1 - arch/arm/mach-realview/realview_pbx.c | 2 -- arch/arm/mach-s5pv310/cpu.c | 3 --- arch/arm/mach-s5pv310/include/mach/smp.h | 2 -- arch/arm/mach-vexpress/core.h | 2 -- arch/arm/mach-vexpress/ct-ca9x4.c | 6 ++---- 18 files changed, 21 insertions(+), 40 deletions(-) (limited to 'arch/arm/mach-omap2/omap4-common.c') diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index dd0d18d560a..9105d48c02d 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -35,6 +35,9 @@ static DEFINE_SPINLOCK(irq_controller_lock); +/* Address of GIC 0 CPU interface */ +void __iomem *gic_cpu_base_addr; + struct gic_chip_data { unsigned int irq_offset; void __iomem *dist_base; @@ -317,6 +320,8 @@ static void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) void __init gic_init(unsigned int gic_nr, unsigned int irq_start, void __iomem *dist_base, void __iomem *cpu_base) { + if (gic_nr == 0) + gic_cpu_base_addr = cpu_base; gic_dist_init(gic_nr, dist_base, irq_start); gic_cpu_init(gic_nr, cpu_base); } diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 48876a3fbda..a82a7770354 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -33,6 +33,8 @@ #define GIC_DIST_SOFTINT 0xf00 #ifndef __ASSEMBLY__ +extern void __iomem *gic_cpu_base_addr; + void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index e9c491552ca..da30078a80c 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -69,13 +69,10 @@ void __init cns3xxx_map_io(void) } /* used by entry-macro.S */ -void __iomem *gic_cpu_base_addr; - void __init cns3xxx_init_irq(void) { - gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT); gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), - gic_cpu_base_addr); + __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); } void cns3xxx_power_off(void) diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h index 6b33ec11346..ef9e5116b1a 100644 --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h @@ -11,7 +11,6 @@ #ifndef __CNS3XXX_CORE_H #define __CNS3XXX_CORE_H -extern void __iomem *gic_cpu_base_addr; extern struct sys_timer cns3xxx_timer; void __init cns3xxx_map_io(void); diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index aaf8ec8a149..9b5eb2b4ae1 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -28,8 +28,6 @@ #include #include -void __iomem *gic_cpu_base_addr; - unsigned long clk_get_max_axi_khz(void) { return 0; @@ -44,8 +42,8 @@ static void __init msm8x60_init_irq(void) { unsigned int i; - gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, gic_cpu_base_addr); + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index 2744dfee1ff..5b0270b2893 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -24,7 +24,6 @@ extern void __iomem *l2cache_base; #endif -extern void __iomem *gic_cpu_base_addr; extern void __iomem *gic_dist_base_addr; extern void __init gic_init_irq(void); diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 3fd3df7a769..666e852988d 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -26,21 +26,22 @@ void __iomem *l2cache_base; #endif -void __iomem *gic_cpu_base_addr; void __iomem *gic_dist_base_addr; void __init gic_init_irq(void) { + void __iomem *gic_cpu_base; + /* Static mapping, never released */ gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); BUG_ON(!gic_dist_base_addr); /* Static mapping, never released */ - gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); - BUG_ON(!gic_cpu_base_addr); + gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); + BUG_ON(!gic_cpu_base); - gic_init(0, 29, gic_dist_base_addr, gic_cpu_base_addr); + gic_init(0, 29, gic_dist_base_addr, gic_cpu_base); } #ifdef CONFIG_CACHE_L2X0 diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 07c08151dfe..e292eb8c3c4 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -54,9 +54,6 @@ #include "core.h" -/* used by entry-macro.S and platsmp.c */ -void __iomem *gic_cpu_base_addr; - #ifdef CONFIG_ZONE_DMA /* * Adjust the zones if there are restrictions for DMA access. diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 781bca68a9f..693239ddc39 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -53,7 +53,6 @@ extern struct platform_device realview_i2c_device; extern struct mmci_platform_data realview_mmc0_plat_data; extern struct mmci_platform_data realview_mmc1_plat_data; extern struct clcd_board clcd_plat_data; -extern void __iomem *gic_cpu_base_addr; extern void __iomem *timer0_va_base; extern void __iomem *timer1_va_base; extern void __iomem *timer2_va_base; diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 241bcbc73f6..6ef5c5e528b 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -364,9 +364,8 @@ static void __init gic_init_irq(void) writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); /* core tile GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE); gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), - gic_cpu_base_addr); + __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB /* board GIC, secondary */ @@ -376,9 +375,8 @@ static void __init gic_init_irq(void) #endif } else { /* board GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE), - gic_cpu_base_addr); + __io_address(REALVIEW_EB_GIC_CPU_BASE)); } } diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 8047b198f84..cbdc97a5685 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -304,10 +304,9 @@ static struct platform_device char_lcd_device = { static void __init gic_init_irq(void) { /* ARM1176 DevChip GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE); gic_init(0, IRQ_DC1176_GIC_START, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), - gic_cpu_base_addr); + __io_address(REALVIEW_DC1176_GIC_CPU_BASE)); /* board GIC, secondary */ gic_init(1, IRQ_PB1176_GIC_START, diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 61204265b4e..8e8ab7d29a6 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -309,9 +309,8 @@ static void __init gic_init_irq(void) writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); /* ARM11MPCore test chip GIC, primary */ - gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE); gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), - gic_cpu_base_addr); + __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); /* board GIC, secondary */ gic_init(1, IRQ_PB11MP_GIC_START, diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 90f492a35d4..841118e3e11 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -273,7 +273,6 @@ static struct platform_device pmu_device = { static void __init gic_init_irq(void) { /* ARM PB-A8 on-board GIC */ - gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE); gic_init(0, IRQ_PBA8_GIC_START, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), __io_address(REALVIEW_PBA8_GIC_CPU_BASE)); diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 86f28f725a2..02b755b009d 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -313,11 +313,9 @@ static void __init gic_init_irq(void) { /* ARM PBX on-board GIC */ if (core_tile_pbx11mp() || core_tile_pbxa9mp()) { - gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE); gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE), __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE)); } else { - gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE); gic_init(0, IRQ_PBX_GIC_START, __io_address(REALVIEW_PBX_GIC_DIST_BASE), __io_address(REALVIEW_PBX_GIC_CPU_BASE)); diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index bce3e91be43..72ab289e781 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -24,8 +24,6 @@ #include -void __iomem *gic_cpu_base_addr; - extern int combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); @@ -122,7 +120,6 @@ void __init s5pv310_init_irq(void) { int irq; - gic_cpu_base_addr = S5P_VA_GIC_CPU; gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); for (irq = 0; irq < MAX_COMBINER_NR; irq++) { diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h index b7ec252384f..e1cc6a251c6 100644 --- a/arch/arm/mach-s5pv310/include/mach/smp.h +++ b/arch/arm/mach-s5pv310/include/mach/smp.h @@ -9,8 +9,6 @@ #include #include -extern void __iomem *gic_cpu_base_addr; - /* * We use IRQ1 as the IPI */ diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h index 57dd95ce41f..362780d868d 100644 --- a/arch/arm/mach-vexpress/core.h +++ b/arch/arm/mach-vexpress/core.h @@ -22,5 +22,3 @@ struct map_desc; void v2m_map_io(struct map_desc *tile, size_t num); extern struct sys_timer v2m_timer; - -extern void __iomem *gic_cpu_base_addr; diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index 25a3ca6e5a4..8e0a3b7c863 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -60,12 +60,10 @@ static void __init ct_ca9x4_map_io(void) v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); } -void __iomem *gic_cpu_base_addr; - static void __init ct_ca9x4_init_irq(void) { - gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU); - gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST), gic_cpu_base_addr); + gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST), + MMIO_P2V(A9_MPCORE_GIC_CPU)); } #if 0 -- cgit v1.2.3-70-g09d2 From 1773e60a816b28f4084810f96e9195aaaa7fb8c3 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Fri, 19 Nov 2010 23:01:03 +0530 Subject: omap4: l2x0: Construct the AUXCTRL value using defines This patch removes the hardcoded value of auxctrl value and construct it using bitfields Bit 25 is reserved and is always set to 1. Same value of this bit is retained in this patch Signed-off-by: Santosh Shilimkar Tested-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap4-common.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2/omap4-common.c') diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 2f895553e6a..c81460445c4 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -53,6 +53,8 @@ static void omap4_l2x0_disable(void) static int __init omap_l2_cache_init(void) { + u32 aux_ctrl = 0; + /* * To avoid code running on other OMAPs in * multi-omap builds @@ -72,10 +74,17 @@ static int __init omap_l2_cache_init(void) * Way size - 32KB (es1.0) * Way size - 64KB (es2.0 +) */ + aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | + (0x1 << 25) | + (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | + (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); + if (omap_rev() == OMAP4430_REV_ES1_0) - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; else - l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); + aux_ctrl |= 0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; + + l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); /* * Override default outer_cache.disable with a OMAP4 -- cgit v1.2.3-70-g09d2 From 11e0264046e00544eb044fafc27125babd105e41 Mon Sep 17 00:00:00 2001 From: Mans Rullgard Date: Fri, 19 Nov 2010 23:01:04 +0530 Subject: omap4: l2x0: enable instruction and data prefetching Enabling L2 prefetching improves performance as shown on Panda ES2.1 board with mem test, and it has measurable impact on performances. I think we should consider it, even though it damages "writes" a bit. (rebased to k.org) Usually the prefetch is used at both levels together L1 + L2, however, to enable the CP15 prefetch engines, these are under security, and on GP devices, we cannot enable it(e.g. on PandaBoard). However, just enabling PL310 prefetch seems to provide performance improvement, as shown in the data below (from Ubuntu) and would be a great thing to pull in. What prefetch does is enable automatic next line prefetching. With this enabled, whenever the PL310 receives a cachable read request, it automatically prefetches the following cache line as well. Measurement Data: == STOCK 10.10 WITHOUT PATCH ======================== ~# ./memspeed size 8388608 8192k 8M offset 8388608, 0 buffers 0x2aaad000 0x2b2ad000 copy libc 133 MB/s copy Android v5 273 MB/s copy Android NEON 235 MB/s copy INT32 116 MB/s copy ASM ARM 187 MB/s copy ASM VLDM 64 204 MB/s copy ASM VLDM 128 173 MB/s copy ASM VLD1 216 MB/s read ASM ARM 286 MB/s read ASM VLDM 242 MB/s read ASM VLD1 286 MB/s write libc 1947 MB/s write ASM ARM 1943 MB/s write ASM VSTM 1942 MB/s write ASM VST1 1935 MB/s 10.10 + PATCH ============= ~# ./memspeed size 8388608 8192k 8M offset 8388608, 0 buffers 0x2ab17000 0x2b317000 copy libc 129 MB/s copy Android v5 256 MB/s copy Android NEON 356 MB/s copy INT32 127 MB/s copy ASM ARM 321 MB/s copy ASM VLDM 64 337 MB/s copy ASM VLDM 128 321 MB/s copy ASM VLD1 350 MB/s read ASM ARM 496 MB/s read ASM VLDM 470 MB/s read ASM VLD1 488 MB/s write libc 1701 MB/s write ASM ARM 1682 MB/s write ASM VSTM 1693 MB/s write ASM VST1 1681 MB/s Signed-off-by: Mans Rullgard Signed-off-by: Santosh Shilimkar Tested-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap4-common.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-omap2/omap4-common.c') diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index c81460445c4..b3cea78b5f0 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -66,9 +66,6 @@ static int __init omap_l2_cache_init(void) l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); BUG_ON(!l2cache_base); - /* Enable PL310 L2 Cache controller */ - omap_smc1(0x102, 0x1); - /* * 16-way associativity, parity disabled * Way size - 32KB (es1.0) @@ -79,10 +76,18 @@ static int __init omap_l2_cache_init(void) (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); - if (omap_rev() == OMAP4430_REV_ES1_0) + if (omap_rev() == OMAP4430_REV_ES1_0) { aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; - else - aux_ctrl |= 0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; + } else { + aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | + (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | + (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT)); + } + if (omap_rev() != OMAP4430_REV_ES1_0) + omap_smc1(0x109, aux_ctrl); + + /* Enable PL310 L2 Cache controller */ + omap_smc1(0x102, 0x1); l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); -- cgit v1.2.3-70-g09d2 From b0f20ff9d7e347c284ea7718597c978a2969ad7b Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Fri, 19 Nov 2010 23:01:05 +0530 Subject: omap4: l2x0: Set share override bit Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption Signed-off-by: Santosh Shilimkar Tested-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap4-common.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-omap2/omap4-common.c') diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index b3cea78b5f0..2006da10f5f 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -80,6 +80,7 @@ static int __init omap_l2_cache_init(void) aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; } else { aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | + (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT)); } -- cgit v1.2.3-70-g09d2 From b89cd71a159b5edca4c429687e4af01708eb1b26 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Fri, 19 Nov 2010 23:01:06 +0530 Subject: omap4: l2x0: Enable early BRESP bit The AXI protocol specifies that the write response can only be sent back to an AXI master when the last write data has been accepted. This optimization enables the PL310 to send the write response of certain write transactions as soon as the store buffer accepts the write address. This behavior is not compatible with the AXI protocol and is disabled by default. You enable this optimization by setting the Early BRESP Enable bit in the Auxiliary Control Register (bit [30]). Signed-off-by: Santosh Shilimkar Signed-off-by: Mans Rullgard Tested-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap4-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/omap4-common.c') diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 2006da10f5f..e7a9b7f13b5 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -82,7 +82,8 @@ static int __init omap_l2_cache_init(void) aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | - (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT)); + (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | + (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); } if (omap_rev() != OMAP4430_REV_ES1_0) omap_smc1(0x109, aux_ctrl); -- cgit v1.2.3-70-g09d2