From d99de7f552fac43e24fd4fb8048d8f21abaea691 Mon Sep 17 00:00:00 2001 From: Fernando Guzman Lugo Date: Fri, 13 Apr 2012 05:08:03 -0600 Subject: ARM: OMAP2+: hwmod: add softreset delay field and OMAP4 data Due to HW limitation, some IPs should not be accessed just after a softreset. Since the current hwmod sequence is accessing the sysconfig register just after the reset, it might lead to OCP bus error in that case. Add a new field in the sysconfig structure to specify a delay in usecs needed after doing a softreset. In the case of the ISS and FDIF modules, the L3 OCP port will be disconnected upon a SW reset. That issue was confirmed with HW simulation and an errata should be available soon. The HW recommendation to avoid that is to wait for 100 OCP clk cycles, before accessing the IP. Considering the worse case (OPP50), the L3 bus will run at 100 MHz, so a 1 usec delay is needed. Add an x2 margin to be safe. Acked-by: Benoit Cousson Signed-off-by: Fernando Guzman Lugo [paul@pwsan.com: dropped FDIF change for now since the hwmod data is not yet upstream; the FDIF change will need to be added later once the FDIF data is merged] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-omap2/omap_hwmod.c') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2c27fdb61e6..45f1d9c44e9 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh) goto dis_opt_clks; _write_sysconfig(v, oh); + if (oh->class->sysc->srst_udelay) + udelay(oh->class->sysc->srst_udelay); + if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) -- cgit v1.2.3-70-g09d2 From 3c55c1baffa5f719eb2ae9729088bc867f972f53 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 13 Apr 2012 05:08:43 -0600 Subject: ARM: OMAP2+: hwmod: Revert "ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status" This reverts commit f9a2f9c3fa76eec55928e8e06f3094c8f01df7cb. This commit caused a regression in the I2C hwmod reset on OMAP2/3/4, logging messages similar to these during boot: [ 0.200378] omap_hwmod: i2c1: softreset failed (waited 10000 usec) [ 0.222076] omap_hwmod: i2c2: softreset failed (waited 10000 usec) While the original patch was intended to fix some reset-related timing issues, it's believed that these problems were actually fixed by commit 2800852a079504f35f88e44faf5c9c96318c0cca ("ARM: OMAP2+: hwmod: Restore sysc after a reset"): http://marc.info/?l=linux-arm-kernel&m=133410322617245&w=2 Cc: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2/omap_hwmod.c') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 45f1d9c44e9..7144ae651d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1906,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) */ int omap_hwmod_softreset(struct omap_hwmod *oh) { - if (!oh) + u32 v; + int ret; + + if (!oh || !(oh->_sysc_cache)) return -EINVAL; - return _ocp_softreset(oh); + v = oh->_sysc_cache; + ret = _set_softreset(oh, &v); + if (ret) + goto error; + _write_sysconfig(v, oh); + +error: + return ret; } /** -- cgit v1.2.3-70-g09d2