From eed0de27726a55f145490619510c8ec58c9dc767 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 4 Jul 2012 18:32:32 +0530 Subject: ARM: OMAP4: Add local timer support for Device Tree Add cortex-a9 local timer support for all OMAP4 based SOCs using DT. Signed-off-by: Santosh Shilimkar Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/mach-omap2/timer.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-omap2/timer.c') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2ff6d41ec6c..31f9c936125 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -386,6 +387,11 @@ static void __init omap4_timer_init(void) if (omap_rev() != OMAP4430_REV_ES1_0) { int err; + if (of_have_populated_dt()) { + twd_local_timer_of_register(); + return; + } + err = twd_local_timer_register(&twd_local_timer); if (err) pr_err("twd_local_timer_register failed %d\n", err); -- cgit v1.2.3-70-g09d2 From fa6d79d27614223d82418023b7f5300f1a1530d3 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 13 Aug 2012 14:24:24 +0530 Subject: ARM: OMAP: Add initialisation for the real-time counter. The real time counter also called master counter, is a free-running counter. It produces the count used by the CPU local timer peripherals in the MPU cluster. The timer counts at a rate of 6.144 MHz. The ratio registers needs to be configured based on system clock only onetime. After initialisation, hardware takes care of adjusting the clock in different low power modes to keep counter rate constant. Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/Kconfig | 4 ++ arch/arm/mach-omap2/timer.c | 90 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 93 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/timer.c') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 346fd26f3aa..4b773fd5697 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -24,6 +24,9 @@ config ARCH_OMAP2PLUS_TYPICAL config SOC_HAS_OMAP2_SDRC bool "OMAP2 SDRAM Controller support" +config SOC_HAS_REALTIME_COUNTER + bool "Real time free running counter" + config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_OMAP2PLUS @@ -70,6 +73,7 @@ config SOC_OMAP5 select ARM_GIC select HAVE_SMP select ARM_CPU_SUSPEND if PM + select SOC_HAS_REALTIME_COUNTER comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2ba4f57dda8..026fcfff669 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -69,6 +69,11 @@ #define OMAP3_SECURE_TIMER 1 #endif +#define REALTIME_COUNTER_BASE 0x48243200 +#define INCREMENTER_NUMERATOR_OFFSET 0x10 +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 +#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 + /* Clockevent code */ static struct omap_dm_timer clkev; @@ -346,6 +351,84 @@ static void __init omap2_clocksource_init(int gptimer_id, omap2_gptimer_clocksource_init(gptimer_id, fck_source); } +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER +/* + * The realtime counter also called master counter, is a free-running + * counter, which is related to real time. It produces the count used + * by the CPU local timer peripherals in the MPU cluster. The timer counts + * at a rate of 6.144 MHz. Because the device operates on different clocks + * in different power modes, the master counter shifts operation between + * clocks, adjusting the increment per clock in hardware accordingly to + * maintain a constant count rate. + */ +static void __init realtime_counter_init(void) +{ + void __iomem *base; + static struct clk *sys_clk; + unsigned long rate; + unsigned int reg, num, den; + + base = ioremap(REALTIME_COUNTER_BASE, SZ_32); + if (!base) { + pr_err("%s: ioremap failed\n", __func__); + return; + } + sys_clk = clk_get(NULL, "sys_clkin_ck"); + if (!sys_clk) { + pr_err("%s: failed to get system clock handle\n", __func__); + iounmap(base); + return; + } + + rate = clk_get_rate(sys_clk); + /* Numerator/denumerator values refer TRM Realtime Counter section */ + switch (rate) { + case 1200000: + num = 64; + den = 125; + break; + case 1300000: + num = 768; + den = 1625; + break; + case 19200000: + num = 8; + den = 25; + break; + case 2600000: + num = 384; + den = 1625; + break; + case 2700000: + num = 256; + den = 1125; + break; + case 38400000: + default: + /* Program it for 38.4 MHz */ + num = 4; + den = 25; + break; + } + + /* Program numerator and denumerator registers */ + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= num; + __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); + + reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + NUMERATOR_DENUMERATOR_MASK; + reg |= den; + __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); + + iounmap(base); +} +#else +static inline void __init realtime_counter_init(void) +{} +#endif + #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ clksrc_nr, clksrc_src) \ static void __init omap##name##_timer_init(void) \ @@ -403,7 +486,12 @@ OMAP_SYS_TIMER(4) #endif #ifdef CONFIG_SOC_OMAP5 -OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE) +static void __init omap5_timer_init(void) +{ + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); + omap2_clocksource_init(2, OMAP4_MPU_SOURCE); + realtime_counter_init(); +} OMAP_SYS_TIMER(5) #endif -- cgit v1.2.3-70-g09d2 From 3c7c5dab44d6c8861bc86dab924353d8d40344f8 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 13 Aug 2012 14:39:03 +0530 Subject: ARM: OMAP5: Enable arch timer support Enable Cortex A15 generic timer support for OMAP5 based SOCs. The CPU local timers run on the free running real time counter clock. Acked-by: Benoit Cousson Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/omap5.dtsi | 12 ++++++++++++ arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/timer.c | 7 +++++++ 3 files changed, 20 insertions(+) (limited to 'arch/arm/mach-omap2/timer.c') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 57e52708374..7b986eddd0b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -33,9 +33,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; cpu@1 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; }; diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4b773fd5697..4609163b039 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -74,6 +74,7 @@ config SOC_OMAP5 select HAVE_SMP select ARM_CPU_SUSPEND if PM select SOC_HAS_REALTIME_COUNTER + select ARM_ARCH_TIMER comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 026fcfff669..2c5a45d8ca8 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "common.h" #include #include @@ -488,9 +489,15 @@ OMAP_SYS_TIMER(4) #ifdef CONFIG_SOC_OMAP5 static void __init omap5_timer_init(void) { + int err; + omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); omap2_clocksource_init(2, OMAP4_MPU_SOURCE); realtime_counter_init(); + + err = arch_timer_of_register(); + if (err) + pr_err("%s: arch_timer_register failed %d\n", __func__, err); } OMAP_SYS_TIMER(5) #endif -- cgit v1.2.3-70-g09d2