From 59b479e0985f0b795d68331d6443a7f89c47768d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 27 Jan 2011 16:39:40 -0800 Subject: omap: Start using CONFIG_SOC_OMAP We want to have just CONFIG_ARCH_OMAP2, 3 and 4. The rest are nowadays just subcategories of these. Search and replace the following: ARCH_OMAP2420 SOC_OMAP2420 ARCH_OMAP2430 SOC_OMAP2430 ARCH_OMAP3430 SOC_OMAP3430 No functional changes. Signed-off-by: Tony Lindgren Signed-off-by: Thomas Weber Acked-by: Sourav Poddar --- arch/arm/mach-omap2/Kconfig | 16 ++++++++-------- arch/arm/mach-omap2/Makefile | 20 ++++++++++---------- arch/arm/mach-omap2/clock2xxx.h | 4 ++-- arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 16 ++++++++-------- arch/arm/mach-omap2/common.c | 4 ++-- arch/arm/mach-omap2/devices.c | 6 +++--- arch/arm/mach-omap2/io.c | 8 ++++---- arch/arm/mach-omap2/mailbox.c | 2 +- arch/arm/mach-omap2/mcbsp.c | 4 ++-- arch/arm/mach-omap2/opp2xxx.h | 2 +- arch/arm/mach-omap2/powerdomains2xxx_data.c | 6 +++--- 11 files changed, 44 insertions(+), 44 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1a2cf6226a5..ae7f47d1c97 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -53,20 +53,20 @@ config ARCH_OMAP4 comment "OMAP Core Type" depends on ARCH_OMAP2 -config ARCH_OMAP2420 +config SOC_OMAP2420 bool "OMAP2420 support" depends on ARCH_OMAP2 default y select OMAP_DM_TIMER select ARCH_OMAP_OTG -config ARCH_OMAP2430 +config SOC_OMAP2430 bool "OMAP2430 support" depends on ARCH_OMAP2 default y select ARCH_OMAP_OTG -config ARCH_OMAP3430 +config SOC_OMAP3430 bool "OMAP3430 support" depends on ARCH_OMAP3 default y @@ -106,25 +106,25 @@ config MACH_OMAP_GENERIC config MACH_OMAP2_TUSB6010 bool - depends on ARCH_OMAP2 && ARCH_OMAP2420 + depends on ARCH_OMAP2 && SOC_OMAP2420 default y if MACH_NOKIA_N8X0 config MACH_OMAP_H4 bool "OMAP 2420 H4 board" - depends on ARCH_OMAP2420 + depends on SOC_OMAP2420 default y select OMAP_PACKAGE_ZAF select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" - depends on ARCH_OMAP2420 + depends on SOC_OMAP2420 default y select OMAP_PACKAGE_ZAC config MACH_OMAP_2430SDP bool "OMAP 2430 SDP board" - depends on ARCH_OMAP2430 + depends on SOC_OMAP2430 default y select OMAP_PACKAGE_ZAC @@ -219,7 +219,7 @@ config MACH_NOKIA_N810_WIMAX config MACH_NOKIA_N8X0 bool "Nokia N800/N810" - depends on ARCH_OMAP2420 + depends on SOC_OMAP2420 default y select OMAP_PACKAGE_ZAC select MACH_NOKIA_N800 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1c0c2b02d87..9eeabaf5e11 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -31,8 +31,8 @@ AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec) # Functions loaded to SRAM -obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o -obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o +obj-$(CONFIG_SOC_OMAP2420) += sram242x.o +obj-$(CONFIG_SOC_OMAP2430) += sram243x.o obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o AFLAGS_sram242x.o :=-Wa,-march=armv6 @@ -40,8 +40,8 @@ AFLAGS_sram243x.o :=-Wa,-march=armv6 AFLAGS_sram34xx.o :=-Wa,-march=armv7-a # Pin multiplexing -obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o -obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o +obj-$(CONFIG_SOC_OMAP2420) += mux2420.o +obj-$(CONFIG_SOC_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o @@ -113,8 +113,8 @@ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ clkt2xxx_dpllcore.o \ clkt2xxx_virt_prcm_set.o \ clkt2xxx_apll.o clkt2xxx_osc.o -obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o -obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o +obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o +obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ clock34xx.o clkt34xx_dpll3m2.o \ clock3517.o clock36xx.o \ @@ -123,12 +123,12 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ dpll3xxx.o # OMAP2 clock rate set data (old "OPP" data) -obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o -obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o +obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o +obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data -obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o -obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o +obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o +obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 6a658b890c1..cc5c8d422c5 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -20,13 +20,13 @@ u32 omap2xxx_get_apll_clkin(void); u32 omap2xxx_get_sysclkdiv(void); void omap2xxx_clk_prepare_for_reboot(void); -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 int omap2420_clk_init(void); #else #define omap2420_clk_init() 0 #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 int omap2430_clk_init(void); #else #define omap2430_clk_init() 0 diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index e4a7133ea3b..e6f0d18d5e8 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -171,7 +171,7 @@ static struct clkdm_dep core_24xx_wkdeps[] = { /* 2430-specific possible wakeup dependencies */ -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ static struct clkdm_dep mdm_2430_wkdeps[] = { @@ -194,7 +194,7 @@ static struct clkdm_dep mdm_2430_wkdeps[] = { { NULL }, }; -#endif /* CONFIG_ARCH_OMAP2430 */ +#endif /* CONFIG_SOC_OMAP2430 */ /* OMAP3-specific possible dependencies */ @@ -450,7 +450,7 @@ static struct clockdomain cm_clkdm = { * 2420-only clockdomains */ -#if defined(CONFIG_ARCH_OMAP2420) +#if defined(CONFIG_SOC_OMAP2420) static struct clockdomain mpu_2420_clkdm = { .name = "mpu_clkdm", @@ -514,14 +514,14 @@ static struct clockdomain dss_2420_clkdm = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; -#endif /* CONFIG_ARCH_OMAP2420 */ +#endif /* CONFIG_SOC_OMAP2420 */ /* * 2430-only clockdomains */ -#if defined(CONFIG_ARCH_OMAP2430) +#if defined(CONFIG_SOC_OMAP2430) static struct clockdomain mpu_2430_clkdm = { .name = "mpu_clkdm", @@ -600,7 +600,7 @@ static struct clockdomain dss_2430_clkdm = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; -#endif /* CONFIG_ARCH_OMAP2430 */ +#endif /* CONFIG_SOC_OMAP2430 */ /* @@ -811,7 +811,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = { &cm_clkdm, &prm_clkdm, -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 &mpu_2420_clkdm, &iva1_2420_clkdm, &dsp_2420_clkdm, @@ -821,7 +821,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = { &dss_2420_clkdm, #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 &mpu_2430_clkdm, &mdm_clkdm, &dsp_2430_clkdm, diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 778929f7e92..d5eaee3dff7 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -40,7 +40,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals) #endif -#if defined(CONFIG_ARCH_OMAP2420) +#if defined(CONFIG_SOC_OMAP2420) static struct omap_globals omap242x_globals = { .class = OMAP242X_CLASS, @@ -61,7 +61,7 @@ void __init omap2_set_globals_242x(void) } #endif -#if defined(CONFIG_ARCH_OMAP2430) +#if defined(CONFIG_SOC_OMAP2430) static struct omap_globals omap243x_globals = { .class = OMAP243X_CLASS, diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2c9c912f2c4..e0f0ef952bc 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -333,7 +333,7 @@ static struct platform_device omap2_mcspi2 = { }, }; -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ +#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ defined(CONFIG_ARCH_OMAP4) static struct omap2_mcspi_platform_config omap2_mcspi3_config = { .num_cs = 2, @@ -400,7 +400,7 @@ static inline void omap4_mcspi_fixup(void) } #endif -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ +#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ defined(CONFIG_ARCH_OMAP4) static inline void omap2_mcspi3_init(void) { @@ -895,7 +895,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, /*-------------------------------------------------------------------------*/ #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) +#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) #define OMAP_HDQ_BASE 0x480B2000 #endif static struct resource omap_hdq_resources[] = { diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c2032041d26..11decd85f18 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -66,7 +66,7 @@ static struct map_desc omap24xx_io_desc[] __initdata = { }, }; -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 static struct map_desc omap242x_io_desc[] __initdata = { { .virtual = DSP_MEM_2420_VIRT, @@ -90,7 +90,7 @@ static struct map_desc omap242x_io_desc[] __initdata = { #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 static struct map_desc omap243x_io_desc[] __initdata = { { .virtual = L4_WK_243X_VIRT, @@ -241,7 +241,7 @@ static void __init _omap2_map_common_io(void) omap_sram_init(); } -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 void __init omap242x_map_common_io(void) { iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); @@ -250,7 +250,7 @@ void __init omap242x_map_common_io(void) } #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 void __init omap243x_map_common_io(void) { iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 394413dc7de..29b9dc3917a 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -310,7 +310,7 @@ struct omap_mbox mbox_dsp_info = { struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; #endif -#if defined(CONFIG_ARCH_OMAP2420) +#if defined(CONFIG_SOC_OMAP2420) /* IVA */ static struct omap_mbox2_priv omap2_mbox_iva_priv = { .tx_fifo = { diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index f9c9df5b5ff..0526b758bdc 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -104,7 +104,7 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); /* Platform data */ -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { { .phys_base = OMAP24XX_MCBSP1_BASE, @@ -129,7 +129,7 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { #define OMAP2420_MCBSP_REG_NUM 0 #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { { .phys_base = OMAP24XX_MCBSP1_BASE, diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h index 38b73055050..8affc66a92c 100644 --- a/arch/arm/mach-omap2/opp2xxx.h +++ b/arch/arm/mach-omap2/opp2xxx.h @@ -418,7 +418,7 @@ struct prcm_config { extern const struct prcm_config omap2420_rate_table[]; -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 extern const struct prcm_config omap2430_rate_table[]; #else #define omap2430_rate_table NULL diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c index 9b1a3350057..78739e10f5b 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -78,7 +78,7 @@ static struct powerdomain core_24xx_pwrdm = { * 2430-specific powerdomains */ -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ @@ -97,7 +97,7 @@ static struct powerdomain mdm_pwrdm = { }, }; -#endif /* CONFIG_ARCH_OMAP2430 */ +#endif /* CONFIG_SOC_OMAP2430 */ /* As powerdomains are added or removed above, this list must also be changed */ static struct powerdomain *powerdomains_omap2xxx[] __initdata = { @@ -111,7 +111,7 @@ static struct powerdomain *powerdomains_omap2xxx[] __initdata = { &core_24xx_pwrdm, #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 &mdm_pwrdm, #endif NULL -- cgit v1.2.3-70-g09d2 From ee23b93dff539b82fd9e225e5235ee6d2fb01346 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 27 Jan 2011 16:39:43 -0800 Subject: arm: omap2: irq: fix compile warning: Fix the following compile warning: arch/arm/mach-omap2/irq.c:64:31: warning: 'intc_context' defined but not used Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 23049c487c4..d151aac291c 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -61,8 +61,6 @@ struct omap3_intc_regs { u32 mir[INTCPS_NR_MIR_REGS]; }; -static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; - /* INTC bank register get/set */ static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) @@ -229,6 +227,8 @@ void __init omap_init_irq(void) } #ifdef CONFIG_ARCH_OMAP3 +static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; + void omap_intc_save_context(void) { int ind = 0, i = 0; -- cgit v1.2.3-70-g09d2 From ee54dba9c360944b34e06478c05c6f283bf64eda Mon Sep 17 00:00:00 2001 From: Russell King - ARM Linux Date: Thu, 27 Jan 2011 16:39:45 -0800 Subject: ARM: OMAP: Allow platforms to hook reset cleanly This adds a clean method to allow platforms to hook into the reset code if they require to. Signed-off-by: Russell King Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/Makefile | 2 +- arch/arm/mach-omap1/board-voiceblue.c | 106 +++++++++++++++++-------------- arch/arm/mach-omap1/reset.c | 25 ++++++++ arch/arm/mach-omap2/prcm.c | 5 +- arch/arm/plat-omap/include/plat/prcm.h | 1 - arch/arm/plat-omap/include/plat/system.h | 38 +---------- 6 files changed, 91 insertions(+), 86 deletions(-) create mode 100644 arch/arm/mach-omap1/reset.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index ba6009f2767..af98117043d 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o -obj-y += clock.o clock_data.o opp_data.o +obj-y += clock.o clock_data.o opp_data.o reset.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 815a69ce821..67128171409 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -163,52 +164,6 @@ static void __init voiceblue_init_irq(void) omap_init_irq(); } -static void __init voiceblue_init(void) -{ - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - /* Watchdog */ - gpio_request(0, "Watchdog"); - /* smc91x reset */ - gpio_request(7, "SMC91x reset"); - gpio_direction_output(7, 1); - udelay(2); /* wait at least 100ns */ - gpio_set_value(7, 0); - mdelay(50); /* 50ms until PHY ready */ - /* smc91x interrupt pin */ - gpio_request(8, "SMC91x irq"); - /* 16C554 reset*/ - gpio_request(6, "16C554 reset"); - gpio_direction_output(6, 0); - /* 16C554 interrupt pins */ - gpio_request(12, "16C554 irq"); - gpio_request(13, "16C554 irq"); - gpio_request(14, "16C554 irq"); - gpio_request(15, "16C554 irq"); - set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); - - platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); - omap_board_config = voiceblue_config; - omap_board_config_size = ARRAY_SIZE(voiceblue_config); - omap_serial_init(); - omap1_usb_init(&voiceblue_usb_config); - omap_register_i2c_bus(1, 100, NULL, 0); - - /* There is a good chance board is going up, so enable power LED - * (it is connected through invertor) */ - omap_writeb(0x00, OMAP_LPG1_LCR); - omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ -} - static void __init voiceblue_map_io(void) { omap1_map_common_io(); @@ -275,8 +230,17 @@ void voiceblue_wdt_ping(void) gpio_set_value(0, wdt_gpio_state); } -void voiceblue_reset(void) +static void voiceblue_reset(char mode, const char *cmd) { + /* + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 + * "Global Software Reset Affects Traffic Controller Frequency". + */ + if (cpu_is_omap5912()) { + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); + omap_writew(0x8, ARM_RSTCT1); + } + set_bit(MACHINE_REBOOT, &machine_state); voiceblue_wdt_enable(); while (1) ; @@ -286,6 +250,54 @@ EXPORT_SYMBOL(voiceblue_wdt_enable); EXPORT_SYMBOL(voiceblue_wdt_disable); EXPORT_SYMBOL(voiceblue_wdt_ping); +static void __init voiceblue_init(void) +{ + /* mux pins for uarts */ + omap_cfg_reg(UART1_TX); + omap_cfg_reg(UART1_RTS); + omap_cfg_reg(UART2_TX); + omap_cfg_reg(UART2_RTS); + omap_cfg_reg(UART3_TX); + omap_cfg_reg(UART3_RX); + + /* Watchdog */ + gpio_request(0, "Watchdog"); + /* smc91x reset */ + gpio_request(7, "SMC91x reset"); + gpio_direction_output(7, 1); + udelay(2); /* wait at least 100ns */ + gpio_set_value(7, 0); + mdelay(50); /* 50ms until PHY ready */ + /* smc91x interrupt pin */ + gpio_request(8, "SMC91x irq"); + /* 16C554 reset*/ + gpio_request(6, "16C554 reset"); + gpio_direction_output(6, 0); + /* 16C554 interrupt pins */ + gpio_request(12, "16C554 irq"); + gpio_request(13, "16C554 irq"); + gpio_request(14, "16C554 irq"); + gpio_request(15, "16C554 irq"); + set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); + + platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); + omap_board_config = voiceblue_config; + omap_board_config_size = ARRAY_SIZE(voiceblue_config); + omap_serial_init(); + omap1_usb_init(&voiceblue_usb_config); + omap_register_i2c_bus(1, 100, NULL, 0); + + /* There is a good chance board is going up, so enable power LED + * (it is connected through invertor) */ + omap_writeb(0x00, OMAP_LPG1_LCR); + omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ + + arch_reset = voiceblue_reset; +} + MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") /* Maintainer: Ladislav Michl */ .boot_params = 0x10000100, diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c new file mode 100644 index 00000000000..ad951ee6920 --- /dev/null +++ b/arch/arm/mach-omap1/reset.c @@ -0,0 +1,25 @@ +/* + * OMAP1 reset support + */ +#include +#include + +#include +#include +#include + +void omap1_arch_reset(char mode, const char *cmd) +{ + /* + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 + * "Global Software Reset Affects Traffic Controller Frequency". + */ + if (cpu_is_omap5912()) { + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); + omap_writew(0x8, ARM_RSTCT1); + } + + omap_writew(1, ARM_RSTCT1); +} + +void (*arch_reset)(char, const char *) = omap1_arch_reset; diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 679bcd28576..6be14389e4f 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -57,7 +58,7 @@ u32 omap_prcm_get_reset_sources(void) EXPORT_SYMBOL(omap_prcm_get_reset_sources); /* Resets clock rates and reboots the system. Only called from system.h */ -void omap_prcm_arch_reset(char mode, const char *cmd) +static void omap_prcm_arch_reset(char mode, const char *cmd) { s16 prcm_offs = 0; @@ -108,6 +109,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd) omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ } +void (*arch_reset)(char, const char *) = omap_prcm_arch_reset; + /** * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness * @reg: physical address of module IDLEST register diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index 2fdf8c80d39..267f43bb2a4 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h @@ -28,7 +28,6 @@ #define __ASM_ARM_ARCH_OMAP_PRCM_H u32 omap_prcm_get_reset_sources(void); -void omap_prcm_arch_reset(char mode, const char *cmd); int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, const char *name); diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h index d0a119f735b..c5fa9e92900 100644 --- a/arch/arm/plat-omap/include/plat/system.h +++ b/arch/arm/plat-omap/include/plat/system.h @@ -4,48 +4,14 @@ */ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H -#include -#include -#include - -#include - -#ifndef CONFIG_MACH_VOICEBLUE -#define voiceblue_reset() do {} while (0) -#else -extern void voiceblue_reset(void); -#endif +#include static inline void arch_idle(void) { cpu_do_idle(); } -static inline void omap1_arch_reset(char mode, const char *cmd) -{ - /* - * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 - * "Global Software Reset Affects Traffic Controller Frequency". - */ - if (cpu_is_omap5912()) { - omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), - DPLL_CTL); - omap_writew(0x8, ARM_RSTCT1); - } - - if (machine_is_voiceblue()) - voiceblue_reset(); - else - omap_writew(1, ARM_RSTCT1); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - if (!cpu_class_is_omap2()) - omap1_arch_reset(mode, cmd); - else - omap_prcm_arch_reset(mode, cmd); -} +extern void (*arch_reset)(char, const char *); #endif -- cgit v1.2.3-70-g09d2 From 3dc3bad6f1b316d79d9d1d596a590b5097cb3dc4 Mon Sep 17 00:00:00 2001 From: Russell King - ARM Linux Date: Mon, 14 Feb 2011 15:40:20 -0800 Subject: ARM: OMAP2: use early init hook Move non-mapping and non-irq initialization code out of .map_io and .init_irq respectively into the new init_early hook. Signed-off-by: Russell King Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 8 ++++---- arch/arm/mach-omap2/board-3430sdp.c | 8 ++++---- arch/arm/mach-omap2/board-3630sdp.c | 8 ++++---- arch/arm/mach-omap2/board-4430sdp.c | 8 ++++---- arch/arm/mach-omap2/board-am3517crane.c | 8 ++++---- arch/arm/mach-omap2/board-am3517evm.c | 8 ++++---- arch/arm/mach-omap2/board-apollon.c | 8 ++++---- arch/arm/mach-omap2/board-cm-t35.c | 8 ++++---- arch/arm/mach-omap2/board-cm-t3517.c | 8 ++++---- arch/arm/mach-omap2/board-devkit8000.c | 9 +++++++-- arch/arm/mach-omap2/board-generic.c | 8 ++++---- arch/arm/mach-omap2/board-h4.c | 9 +++++++-- arch/arm/mach-omap2/board-igep0020.c | 8 ++++---- arch/arm/mach-omap2/board-igep0030.c | 6 +++--- arch/arm/mach-omap2/board-ldp.c | 8 ++++---- arch/arm/mach-omap2/board-n8x0.c | 18 ++++++++++-------- arch/arm/mach-omap2/board-omap3beagle.c | 9 +++++++-- arch/arm/mach-omap2/board-omap3evm.c | 8 ++++---- arch/arm/mach-omap2/board-omap3logic.c | 9 +++++---- arch/arm/mach-omap2/board-omap3pandora.c | 8 ++++---- arch/arm/mach-omap2/board-omap3stalker.c | 7 ++++++- arch/arm/mach-omap2/board-omap3touchbook.c | 9 +++++++-- arch/arm/mach-omap2/board-omap4panda.c | 6 +++--- arch/arm/mach-omap2/board-overo.c | 8 ++++---- arch/arm/mach-omap2/board-rm680.c | 8 ++++---- arch/arm/mach-omap2/board-rx51.c | 8 ++++---- arch/arm/mach-omap2/board-zoom.c | 14 +++++++------- 27 files changed, 130 insertions(+), 102 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index e0661777f59..ec74c0f2051 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -139,13 +139,12 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = { {OMAP_TAG_LCD, &sdp2430_lcd_config}, }; -static void __init omap_2430sdp_init_irq(void) +static void __init omap_2430sdp_init_early(void) { omap_board_config = sdp2430_config; omap_board_config_size = ARRAY_SIZE(sdp2430_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } static struct twl4030_gpio_platform_data sdp2430_gpio_data = { @@ -253,9 +252,10 @@ static void __init omap_2430sdp_map_io(void) MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") /* Maintainer: Syed Khasim - Texas Instruments Inc */ .boot_params = 0x80000100, - .map_io = omap_2430sdp_map_io, .reserve = omap_reserve, - .init_irq = omap_2430sdp_init_irq, + .map_io = omap_2430sdp_map_io, + .init_early = omap_2430sdp_init_early, + .init_irq = omap_init_irq, .init_machine = omap_2430sdp_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index d4e41ef86aa..31085883199 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -327,14 +327,13 @@ static struct platform_device *sdp3430_devices[] __initdata = { static struct omap_board_config_kernel sdp3430_config[] __initdata = { }; -static void __init omap_3430sdp_init_irq(void) +static void __init omap_3430sdp_init_early(void) { omap_board_config = sdp3430_config; omap_board_config_size = ARRAY_SIZE(sdp3430_config); omap3_pm_init_cpuidle(omap3_cpuidle_params_table); omap2_init_common_infrastructure(); omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); - omap_init_irq(); } static int sdp3430_batt_table[] = { @@ -822,9 +821,10 @@ static void __init omap_3430sdp_init(void) MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") /* Maintainer: Syed Khasim - Texas Instruments Inc */ .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = omap_3430sdp_init_irq, + .map_io = omap3_map_io, + .init_early = omap_3430sdp_init_early, + .init_irq = omap_init_irq, .init_machine = omap_3430sdp_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 62645640f5e..16538757291 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -69,14 +69,13 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { static struct omap_board_config_kernel sdp_config[] __initdata = { }; -static void __init omap_sdp_init_irq(void) +static void __init omap_sdp_init_early(void) { omap_board_config = sdp_config; omap_board_config_size = ARRAY_SIZE(sdp_config); omap2_init_common_infrastructure(); omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); - omap_init_irq(); } #ifdef CONFIG_OMAP_MUX @@ -216,9 +215,10 @@ static void __init omap_sdp_init(void) MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = omap_sdp_init_irq, + .map_io = omap3_map_io, + .init_early = omap_sdp_init_early, + .init_irq = omap_init_irq, .init_machine = omap_sdp_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 07d1b20b114..12d99e582cd 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -239,7 +239,7 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = { { OMAP_TAG_LCD, &sdp4430_lcd_config }, }; -static void __init omap_4430sdp_init_irq(void) +static void __init omap_4430sdp_init_early(void) { omap_board_config = sdp4430_config; omap_board_config_size = ARRAY_SIZE(sdp4430_config); @@ -248,7 +248,6 @@ static void __init omap_4430sdp_init_irq(void) #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(1); #endif - gic_init_irq(); } static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -605,9 +604,10 @@ static void __init omap_4430sdp_map_io(void) MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ .boot_params = 0x80000100, - .map_io = omap_4430sdp_map_io, .reserve = omap_reserve, - .init_irq = omap_4430sdp_init_irq, + .map_io = omap_4430sdp_map_io, + .init_early = omap_4430sdp_init_early, + .init_irq = gic_init_irq, .init_machine = omap_4430sdp_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 71acb5ab281..ae3a83d47da 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -49,14 +49,13 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif -static void __init am3517_crane_init_irq(void) +static void __init am3517_crane_init_early(void) { omap_board_config = am3517_crane_config; omap_board_config_size = ARRAY_SIZE(am3517_crane_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { @@ -108,9 +107,10 @@ static void __init am3517_crane_init(void) MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = am3517_crane_init_irq, + .map_io = omap3_map_io, + .init_early = am3517_crane_init_early, + .init_irq = omap_init_irq, .init_machine = am3517_crane_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 10d60b7743c..d0d0f552813 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -396,13 +396,12 @@ static struct platform_device *am3517_evm_devices[] __initdata = { &am3517_evm_dss_device, }; -static void __init am3517_evm_init_irq(void) +static void __init am3517_evm_init_early(void) { omap_board_config = am3517_evm_config; omap_board_config_size = ARRAY_SIZE(am3517_evm_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } static struct omap_musb_board_data musb_board_data = { @@ -521,9 +520,10 @@ static void __init am3517_evm_init(void) MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = am3517_evm_init_irq, + .map_io = omap3_map_io, + .init_early = am3517_evm_init_early, + .init_irq = omap_init_irq, .init_machine = am3517_evm_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 9f55b68687f..4ef4aad4e71 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -274,13 +274,12 @@ static struct omap_board_config_kernel apollon_config[] __initdata = { { OMAP_TAG_LCD, &apollon_lcd_config }, }; -static void __init omap_apollon_init_irq(void) +static void __init omap_apollon_init_early(void) { omap_board_config = apollon_config; omap_board_config_size = ARRAY_SIZE(apollon_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } static void __init apollon_led_init(void) @@ -355,9 +354,10 @@ static void __init omap_apollon_map_io(void) MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") /* Maintainer: Kyungmin Park */ .boot_params = 0x80000100, - .map_io = omap_apollon_map_io, .reserve = omap_reserve, - .init_irq = omap_apollon_init_irq, + .map_io = omap_apollon_map_io, + .init_early = omap_apollon_init_early, + .init_irq = omap_init_irq, .init_machine = omap_apollon_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index dac14161066..9e4de92a579 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -683,7 +683,7 @@ static void __init cm_t35_init_i2c(void) static struct omap_board_config_kernel cm_t35_config[] __initdata = { }; -static void __init cm_t35_init_irq(void) +static void __init cm_t35_init_early(void) { omap_board_config = cm_t35_config; omap_board_config_size = ARRAY_SIZE(cm_t35_config); @@ -691,7 +691,6 @@ static void __init cm_t35_init_irq(void) omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); - omap_init_irq(); } static struct omap_board_mux board_mux[] __initdata = { @@ -815,9 +814,10 @@ static void __init cm_t35_init(void) MACHINE_START(CM_T35, "Compulab CM-T35") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = cm_t35_init_irq, + .map_io = omap3_map_io, + .init_early = cm_t35_init_early, + .init_irq = omap_init_irq, .init_machine = cm_t35_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 8f9a64d650e..38bef6d004c 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -254,14 +254,13 @@ static inline void cm_t3517_init_nand(void) {} static struct omap_board_config_kernel cm_t3517_config[] __initdata = { }; -static void __init cm_t3517_init_irq(void) +static void __init cm_t3517_init_early(void) { omap_board_config = cm_t3517_config; omap_board_config_size = ARRAY_SIZE(cm_t3517_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } static struct omap_board_mux board_mux[] __initdata = { @@ -303,9 +302,10 @@ static void __init cm_t3517_init(void) MACHINE_START(CM_T3517, "Compulab CM-T3517") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = cm_t3517_init_irq, + .map_io = omap3_map_io, + .init_early = cm_t3517_init_early, + .init_irq = omap_init_irq, .init_machine = cm_t3517_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 9a2a31e011c..af742887e83 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -456,11 +456,15 @@ static struct platform_device keys_gpio = { }; -static void __init devkit8000_init_irq(void) +static void __init devkit8000_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); +} + +static void __init devkit8000_init_irq(void) +{ omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); @@ -813,8 +817,9 @@ static void __init devkit8000_init(void) MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = devkit8000_init_early, .init_irq = devkit8000_init_irq, .init_machine = devkit8000_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 0e3d81e09f8..682da9251db 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -33,13 +33,12 @@ static struct omap_board_config_kernel generic_config[] = { }; -static void __init omap_generic_init_irq(void) +static void __init omap_generic_init_early(void) { omap_board_config = generic_config; omap_board_config_size = ARRAY_SIZE(generic_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } static void __init omap_generic_init(void) @@ -68,9 +67,10 @@ static void __init omap_generic_map_io(void) MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") /* Maintainer: Paul Mundt */ .boot_params = 0x80000100, - .map_io = omap_generic_map_io, .reserve = omap_reserve, - .init_irq = omap_generic_init_irq, + .map_io = omap_generic_map_io, + .init_early = omap_generic_init_early, + .init_irq = omap_init_irq, .init_machine = omap_generic_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 25cc9dad4b0..f6a3872f72f 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -290,12 +290,16 @@ static struct omap_board_config_kernel h4_config[] __initdata = { { OMAP_TAG_LCD, &h4_lcd_config }, }; -static void __init omap_h4_init_irq(void) +static void __init omap_h4_init_early(void) { omap_board_config = h4_config; omap_board_config_size = ARRAY_SIZE(h4_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); +} + +static void __init omap_h4_init_irq(void) +{ omap_init_irq(); h4_init_flash(); } @@ -378,8 +382,9 @@ static void __init omap_h4_map_io(void) MACHINE_START(OMAP_H4, "OMAP2420 H4 board") /* Maintainer: Paul Mundt */ .boot_params = 0x80000100, - .map_io = omap_h4_map_io, .reserve = omap_reserve, + .map_io = omap_h4_map_io, + .init_early = omap_h4_init_early, .init_irq = omap_h4_init_irq, .init_machine = omap_h4_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 3be85a1f55f..dd0b1ac3b66 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -525,12 +525,11 @@ static struct platform_device *igep2_devices[] __initdata = { &igep2_vwlan_device, }; -static void __init igep2_init_irq(void) +static void __init igep2_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); - omap_init_irq(); } static struct twl4030_codec_audio_data igep2_audio_data = { @@ -716,9 +715,10 @@ static void __init igep2_init(void) MACHINE_START(IGEP0020, "IGEP v2 board") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = igep2_init_irq, + .map_io = omap3_map_io, + .init_early = igep2_init_early, + .init_irq = omap_init_irq, .init_machine = igep2_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index 4dc62a9b9cb..d75028e48f5 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -331,12 +331,11 @@ static struct platform_device *igep3_devices[] __initdata = { &igep3_vwlan_device, }; -static void __init igep3_init_irq(void) +static void __init igep3_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); - omap_init_irq(); } static struct twl4030_platform_data igep3_twl4030_pdata = { @@ -452,7 +451,8 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module") .boot_params = 0x80000100, .reserve = omap_reserve, .map_io = omap3_map_io, - .init_irq = igep3_init_irq, + .init_early = igep3_init_early, + .init_irq = omap_init_irq, .init_machine = igep3_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index e5dc74875f9..d8eb2cb7cbc 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -288,13 +288,12 @@ static struct omap_board_config_kernel ldp_config[] __initdata = { { OMAP_TAG_LCD, &ldp_lcd_config }, }; -static void __init omap_ldp_init_irq(void) +static void __init omap_ldp_init_early(void) { omap_board_config = ldp_config; omap_board_config_size = ARRAY_SIZE(ldp_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } static struct twl4030_usb_data ldp_usb_data = { @@ -443,9 +442,10 @@ static void __init omap_ldp_init(void) MACHINE_START(OMAP_LDP, "OMAP LDP board") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = omap_ldp_init_irq, + .map_io = omap3_map_io, + .init_early = omap_ldp_init_early, + .init_irq = omap_init_irq, .init_machine = omap_ldp_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index f396756872b..b36cbd21e2d 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -628,11 +628,10 @@ static void __init n8x0_map_io(void) omap242x_map_common_io(); } -static void __init n8x0_init_irq(void) +static void __init n8x0_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } #ifdef CONFIG_OMAP_MUX @@ -703,27 +702,30 @@ static void __init n8x0_init_machine(void) MACHINE_START(NOKIA_N800, "Nokia N800") .boot_params = 0x80000100, - .map_io = n8x0_map_io, .reserve = omap_reserve, - .init_irq = n8x0_init_irq, + .map_io = n8x0_map_io, + .init_early = n8x0_init_early, + .init_irq = omap_init_irq, .init_machine = n8x0_init_machine, .timer = &omap_timer, MACHINE_END MACHINE_START(NOKIA_N810, "Nokia N810") .boot_params = 0x80000100, - .map_io = n8x0_map_io, .reserve = omap_reserve, - .init_irq = n8x0_init_irq, + .map_io = n8x0_map_io, + .init_early = n8x0_init_early, + .init_irq = omap_init_irq, .init_machine = n8x0_init_machine, .timer = &omap_timer, MACHINE_END MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") .boot_params = 0x80000100, - .map_io = n8x0_map_io, .reserve = omap_reserve, - .init_irq = n8x0_init_irq, + .map_io = n8x0_map_io, + .init_early = n8x0_init_early, + .init_irq = omap_init_irq, .init_machine = n8x0_init_machine, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 46d814ab565..19bcd004d60 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -536,11 +536,15 @@ static struct platform_device keys_gpio = { }, }; -static void __init omap3_beagle_init_irq(void) +static void __init omap3_beagle_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); +} + +static void __init omap3_beagle_init_irq(void) +{ omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); @@ -638,8 +642,9 @@ static void __init omap3_beagle_init(void) MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3_beagle_init_early, .init_irq = omap3_beagle_init_irq, .init_machine = omap3_beagle_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 323c3809ce3..c2a0fca4aa5 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -625,13 +625,12 @@ static struct spi_board_info omap3evm_spi_board_info[] = { static struct omap_board_config_kernel omap3_evm_config[] __initdata = { }; -static void __init omap3_evm_init_irq(void) +static void __init omap3_evm_init_early(void) { omap_board_config = omap3_evm_config; omap_board_config_size = ARRAY_SIZE(omap3_evm_config); omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); - omap_init_irq(); } static struct platform_device *omap3_evm_devices[] __initdata = { @@ -720,9 +719,10 @@ static void __init omap3_evm_init(void) MACHINE_START(OMAP3EVM, "OMAP3 EVM") /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = omap3_evm_init_irq, + .map_io = omap3_map_io, + .init_early = omap3_evm_init_early, + .init_irq = omap_init_irq, .init_machine = omap3_evm_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 15e4b08e99b..b726943d7c9 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -195,11 +195,10 @@ static inline void __init board_smsc911x_init(void) gpmc_smsc911x_init(&board_smsc911x_data); } -static void __init omap3logic_init_irq(void) +static void __init omap3logic_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - omap_init_irq(); } #ifdef CONFIG_OMAP_MUX @@ -225,7 +224,8 @@ static void __init omap3logic_init(void) MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") .boot_params = 0x80000100, .map_io = omap3_map_io, - .init_irq = omap3logic_init_irq, + .init_early = omap3logic_init_early, + .init_irq = omap_init_irq, .init_machine = omap3logic_init, .timer = &omap_timer, MACHINE_END @@ -233,7 +233,8 @@ MACHINE_END MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") .boot_params = 0x80000100, .map_io = omap3_map_io, - .init_irq = omap3logic_init_irq, + .init_early = omap3logic_init_early, + .init_irq = omap_init_irq, .init_machine = omap3logic_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 0b34beded11..b91f74ce3a9 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -634,12 +634,11 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { } }; -static void __init omap3pandora_init_irq(void) +static void __init omap3pandora_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); - omap_init_irq(); } static void __init pandora_wl1251_init(void) @@ -727,9 +726,10 @@ static void __init omap3pandora_init(void) MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = omap3pandora_init_irq, + .map_io = omap3_map_io, + .init_early = omap3pandora_init_early, + .init_irq = omap_init_irq, .init_machine = omap3pandora_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 2a2dad447e8..5d1ccef6916 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -591,12 +591,16 @@ static struct spi_board_info omap3stalker_spi_board_info[] = { static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { }; -static void __init omap3_stalker_init_irq(void) +static void __init omap3_stalker_init_early(void) { omap_board_config = omap3_stalker_config; omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); +} + +static void __init omap3_stalker_init_irq(void) +{ omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); @@ -666,6 +670,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER") /* Maintainer: Jason Lam -lzg@ema-tech.com */ .boot_params = 0x80000100, .map_io = omap3_map_io, + .init_early = omap3_stalker_init_early, .init_irq = omap3_stalker_init_irq, .init_machine = omap3_stalker_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index db1f74fe6c4..6a60f79dccc 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -415,7 +415,7 @@ static struct omap_board_mux board_mux[] __initdata = { }; #endif -static void __init omap3_touchbook_init_irq(void) +static void __init omap3_touchbook_init_early(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_board_config = omap3_touchbook_config; @@ -423,6 +423,10 @@ static void __init omap3_touchbook_init_irq(void) omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); +} + +static void __init omap3_touchbook_init_irq(void) +{ omap_init_irq(); #ifdef CONFIG_OMAP_32K_TIMER omap2_gp_clockevent_set_gptimer(12); @@ -538,8 +542,9 @@ static void __init omap3_touchbook_init(void) MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3_touchbook_init_early, .init_irq = omap3_touchbook_init_irq, .init_machine = omap3_touchbook_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index e944025d5ef..fca5b9e80c1 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -76,11 +76,10 @@ static struct platform_device *panda_devices[] __initdata = { &leds_gpio, }; -static void __init omap4_panda_init_irq(void) +static void __init omap4_panda_init_early(void) { omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); - gic_init_irq(); } static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -424,7 +423,8 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") .boot_params = 0x80000100, .reserve = omap_reserve, .map_io = omap4_panda_map_io, - .init_irq = omap4_panda_init_irq, + .init_early = omap4_panda_init_early, + .init_irq = gic_init_irq, .init_machine = omap4_panda_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index cb26e5d8268..a33ec0edec1 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -409,14 +409,13 @@ static struct omap_board_config_kernel overo_config[] __initdata = { { OMAP_TAG_LCD, &overo_lcd_config }, }; -static void __init overo_init_irq(void) +static void __init overo_init_early(void) { omap_board_config = overo_config; omap_board_config_size = ARRAY_SIZE(overo_config); omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); - omap_init_irq(); } static struct platform_device *overo_devices[] __initdata = { @@ -501,9 +500,10 @@ static void __init overo_init(void) MACHINE_START(OVERO, "Gumstix Overo") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = overo_init_irq, + .map_io = omap3_map_io, + .init_early = overo_init_early, + .init_irq = omap_init_irq, .init_machine = overo_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 39a71bb8a30..bdebcb7328e 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -138,14 +138,13 @@ static void __init rm680_peripherals_init(void) omap2_hsmmc_init(mmc); } -static void __init rm680_init_irq(void) +static void __init rm680_init_early(void) { struct omap_sdrc_params *sdrc_params; omap2_init_common_infrastructure(); sdrc_params = nokia_get_sdram_timings(); omap2_init_common_devices(sdrc_params, sdrc_params); - omap_init_irq(); } #ifdef CONFIG_OMAP_MUX @@ -176,9 +175,10 @@ static void __init rm680_map_io(void) MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") .boot_params = 0x80000100, - .map_io = rm680_map_io, .reserve = omap_reserve, - .init_irq = rm680_init_irq, + .map_io = rm680_map_io, + .init_early = rm680_init_early, + .init_irq = omap_init_irq, .init_machine = rm680_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index f53fc551c58..3cf72fe6d75 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -98,7 +98,7 @@ static struct omap_board_config_kernel rx51_config[] = { { OMAP_TAG_LCD, &rx51_lcd_config }, }; -static void __init rx51_init_irq(void) +static void __init rx51_init_early(void) { struct omap_sdrc_params *sdrc_params; @@ -108,7 +108,6 @@ static void __init rx51_init_irq(void) omap2_init_common_infrastructure(); sdrc_params = nokia_get_sdram_timings(); omap2_init_common_devices(sdrc_params, sdrc_params); - omap_init_irq(); } extern void __init rx51_peripherals_init(void); @@ -149,9 +148,10 @@ static void __init rx51_map_io(void) MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") /* Maintainer: Lauri Leukkunen */ .boot_params = 0x80000100, - .map_io = rx51_map_io, .reserve = omap_reserve, - .init_irq = rx51_init_irq, + .map_io = rx51_map_io, + .init_early = rx51_init_early, + .init_irq = omap_init_irq, .init_machine = rx51_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index e26754c24ee..85d4170f30a 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -33,7 +33,7 @@ #define ZOOM3_EHCI_RESET_GPIO 64 -static void __init omap_zoom_init_irq(void) +static void __init omap_zoom_init_early(void) { omap2_init_common_infrastructure(); if (machine_is_omap_zoom2()) @@ -42,8 +42,6 @@ static void __init omap_zoom_init_irq(void) else if (machine_is_omap_zoom3()) omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); - - omap_init_irq(); } #ifdef CONFIG_OMAP_MUX @@ -135,18 +133,20 @@ static void __init omap_zoom_init(void) MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = omap_zoom_init_irq, + .map_io = omap3_map_io, + .init_early = omap_zoom_init_early, + .init_irq = omap_init_irq, .init_machine = omap_zoom_init, .timer = &omap_timer, MACHINE_END MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .boot_params = 0x80000100, - .map_io = omap3_map_io, .reserve = omap_reserve, - .init_irq = omap_zoom_init_irq, + .map_io = omap3_map_io, + .init_early = omap_zoom_init_early, + .init_irq = omap_init_irq, .init_machine = omap_zoom_init, .timer = &omap_timer, MACHINE_END -- cgit v1.2.3-70-g09d2 From 44dc046e93eb98d41048954f700b1927f7e288ed Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Feb 2011 15:40:20 -0800 Subject: omap2+: Make omap_hwmod_late_init into core_initcall Otherwise things will fail with early_init changes. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 2 -- arch/arm/mach-omap2/omap_hwmod.c | 3 ++- arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 - 3 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c2032041d26..f89173ab4ab 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -400,8 +400,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, { omap_serial_early_init(); - omap_hwmod_late_init(); - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e282e35769f..eacdfd3a14d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1628,7 +1628,7 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs) * to struct clk pointers for each registered omap_hwmod. Also calls * _setup() on each hwmod. Returns 0. */ -int omap_hwmod_late_init(void) +static int __init omap_hwmod_late_init(void) { int r; @@ -1644,6 +1644,7 @@ int omap_hwmod_late_init(void) return 0; } +core_initcall(omap_hwmod_late_init); /** * omap_hwmod_enable - enable an omap_hwmod diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 1eee85a8abb..fedd82971c9 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -539,7 +539,6 @@ int omap_hwmod_init(struct omap_hwmod **ohs); struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); -int omap_hwmod_late_init(void); int omap_hwmod_enable(struct omap_hwmod *oh); int _omap_hwmod_enable(struct omap_hwmod *oh); -- cgit v1.2.3-70-g09d2 From 3e16f92536334ccb464ed88cf4d8cc0dd43da106 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Feb 2011 15:40:20 -0800 Subject: omap2+: Fix omap_serial_early_init to work with init_early hook The new init_early hook happens at the end of setup_arch, which is too early for kzalloc. However, there's no need to call omap_serial_early_init that early, so fix this by setting it up as a core_initcall. Signed-off-by: Tony Lindgren Tested-by: Kevin Hilman --- arch/arm/mach-omap2/io.c | 2 -- arch/arm/mach-omap2/serial.c | 7 +++++-- arch/arm/plat-omap/include/plat/serial.h | 1 - 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index f89173ab4ab..26a61cf2729 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -398,8 +398,6 @@ void __init omap2_init_common_infrastructure(void) void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { - omap_serial_early_init(); - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 32e91a9c8b6..74e25cd4bd3 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -655,7 +655,7 @@ static void serial_out_override(struct uart_port *up, int offset, int value) } #endif -void __init omap_serial_early_init(void) +static int __init omap_serial_early_init(void) { int i = 0; @@ -672,7 +672,7 @@ void __init omap_serial_early_init(void) uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); if (WARN_ON(!uart)) - return; + return -ENODEV; uart->oh = oh; uart->num = i++; @@ -691,7 +691,10 @@ void __init omap_serial_early_init(void) */ uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; } while (1); + + return 0; } +core_initcall(omap_serial_early_init); /** * omap_serial_init_port() - initialize single serial port diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index cec5d56db2e..a1a118d052e 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -96,7 +96,6 @@ struct omap_board_data; -extern void __init omap_serial_early_init(void); extern void omap_serial_init(void); extern void omap_serial_init_port(struct omap_board_data *bdata); extern int omap_uart_can_sleep(void); -- cgit v1.2.3-70-g09d2 From e7c7d760859e78a4f47e7be647df683491e420fb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Feb 2011 15:40:21 -0800 Subject: omap: hwmod: Populate _mpu_rt_va later on in omap_hwmod_late_init Otherwise ioremap can fail with early_init patch unless we have a static mapping for everything. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index eacdfd3a14d..9e89a58711b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1467,12 +1467,10 @@ static int __init _register(struct omap_hwmod *oh) return -EEXIST; ms_id = _find_mpu_port_index(oh); - if (!IS_ERR_VALUE(ms_id)) { + if (!IS_ERR_VALUE(ms_id)) oh->_mpu_port_index = ms_id; - oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); - } else { + else oh->_int_flags |= _HWMOD_NO_MPU_PORT; - } list_add_tail(&oh->node, &omap_hwmod_list); @@ -1621,6 +1619,26 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs) return 0; } +/* + * _populate_mpu_rt_base - populate the virtual address for a hwmod + * + * Must be called only from omap_hwmod_late_init so ioremap works properly. + * Assumes the caller takes care of locking if needed. + * + */ +static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) +{ + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return 0; + + oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); + if (!oh->_mpu_rt_va) + pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n", + __func__, oh->name); + + return 0; +} + /** * omap_hwmod_late_init - do some post-clock framework initialization * @@ -1632,6 +1650,8 @@ static int __init omap_hwmod_late_init(void) { int r; + r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); + /* XXX check return value */ r = omap_hwmod_for_each(_init_clocks, NULL); WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); -- cgit v1.2.3-70-g09d2 From 4bd7be22f4b25fc87e236a29da3a625621699074 Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Wed, 16 Feb 2011 08:31:39 -0800 Subject: TI816X: Update common omap platform files This patch updates the common platform files with TI816X support. The approach taken in this patch is to add TI816X as part of OMAP3 variant where the cpu class is considered as OMAP34XX and the type is TI816X. This means, both cpu_is_omap34xx() and cpu_is_ti816x() checks return success on TI816X. A kernel config option CONFIG_SOC_OMAPTI816X is added under OMAP3 to include support for TI816X build. Signed-off-by: Hemant Pedanekar Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 5 +++++ arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 + arch/arm/plat-omap/include/plat/clock.h | 1 + arch/arm/plat-omap/include/plat/common.h | 1 + arch/arm/plat-omap/include/plat/cpu.h | 18 ++++++++++++++++++ 5 files changed, 26 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1a2cf6226a5..23548b60bb1 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -72,6 +72,11 @@ config ARCH_OMAP3430 default y select ARCH_OMAP_OTG +config SOC_OMAPTI816X + bool "TI816X support" + depends on ARCH_OMAP3 + default y + config OMAP_PACKAGE_ZAF bool diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 256ab3f1ec8..f1899a3e417 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -38,6 +38,7 @@ struct omap_clk { #define CK_3517 (1 << 9) #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ #define CK_443X (1 << 11) +#define CK_TI816X (1 << 12) #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 8eb0adab19e..d43e6234dbb 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -53,6 +53,7 @@ struct clkops { #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ #define RATE_IN_36XX (1 << 4) #define RATE_IN_4430 (1 << 5) +#define RATE_IN_TI816X (1 << 6) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 29b2afb4288..1dd97e7461c 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -66,6 +66,7 @@ void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_3xxx(void); void omap2_set_globals_443x(void); +void omap2_set_globals_ti816x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ void omap2_set_globals_tap(struct omap_globals *); diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 3fd8b405572..ac7dcd9a80c 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -105,6 +105,12 @@ static inline int is_omap ##subclass (void) \ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ } +#define IS_TI_SUBCLASS(subclass, id) \ +static inline int is_ti ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + IS_OMAP_CLASS(7xx, 0x07) IS_OMAP_CLASS(15xx, 0x15) IS_OMAP_CLASS(16xx, 0x16) @@ -118,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343) IS_OMAP_SUBCLASS(363x, 0x363) IS_OMAP_SUBCLASS(443x, 0x443) +IS_TI_SUBCLASS(816x, 0x816) + #define cpu_is_omap7xx() 0 #define cpu_is_omap15xx() 0 #define cpu_is_omap16xx() 0 @@ -126,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) #define cpu_is_omap243x() 0 #define cpu_is_omap34xx() 0 #define cpu_is_omap343x() 0 +#define cpu_is_ti816x() 0 #define cpu_is_omap44xx() 0 #define cpu_is_omap443x() 0 @@ -330,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517) # undef cpu_is_omap3530 # undef cpu_is_omap3505 # undef cpu_is_omap3517 +# undef cpu_is_ti816x # define cpu_is_omap3430() is_omap3430() # define cpu_is_omap3503() (cpu_is_omap3430() && \ (!omap3_has_iva()) && \ @@ -345,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517) # define cpu_is_omap3517() is_omap3517() # undef cpu_is_omap3630 # define cpu_is_omap3630() is_omap363x() +# define cpu_is_ti816x() is_ti816x() #endif # if defined(CONFIG_ARCH_OMAP4) @@ -389,6 +400,10 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) +#define TI816X_CLASS 0x81600034 +#define TI8168_REV_ES1_0 TI816X_CLASS +#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) + #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 OMAP443X_CLASS #define OMAP4430_REV_ES2_0 0x44301044 @@ -419,6 +434,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP4430ES2 (1 << 11) +#define CHIP_IS_TI816X (1 << 14) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -455,6 +471,7 @@ extern u32 omap3_features; #define OMAP3_HAS_ISP BIT(4) #define OMAP3_HAS_192MHZ_CLK BIT(5) #define OMAP3_HAS_IO_WAKEUP BIT(6) +#define OMAP3_HAS_SDRC BIT(7) #define OMAP3_HAS_FEATURE(feat,flag) \ static inline unsigned int omap3_has_ ##feat(void) \ @@ -469,5 +486,6 @@ OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) +OMAP3_HAS_FEATURE(sdrc, SDRC) #endif -- cgit v1.2.3-70-g09d2 From 01001712c96f82e6317b1e09729d8fc4bcc66957 Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Wed, 16 Feb 2011 08:31:39 -0800 Subject: TI816X: Update common OMAP machine specific sources This patch updates the common machine specific source files with support for TI816X. Signed-off-by: Hemant Pedanekar Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock3xxx_data.c | 5 +++- arch/arm/mach-omap2/common.c | 21 ++++++++++++++++ arch/arm/mach-omap2/control.h | 6 +++++ arch/arm/mach-omap2/id.c | 33 ++++++++++++++++++++++++-- arch/arm/mach-omap2/include/mach/entry-macro.S | 13 ++++++++++ arch/arm/mach-omap2/io.c | 22 ++++++++++++++++- arch/arm/mach-omap2/irq.c | 5 +++- arch/arm/mach-omap2/serial.c | 8 +++---- arch/arm/plat-omap/include/plat/hardware.h | 1 + arch/arm/plat-omap/include/plat/io.h | 8 +++++++ arch/arm/plat-omap/include/plat/ti816x.h | 27 +++++++++++++++++++++ arch/arm/plat-omap/io.c | 5 +++- 12 files changed, 144 insertions(+), 10 deletions(-) create mode 100644 arch/arm/plat-omap/include/plat/ti816x.h (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 403a4a1d3f9..f14d986f0b5 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3471,6 +3471,9 @@ int __init omap3xxx_clk_init(void) } else if (cpu_is_omap3630()) { cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); cpu_clkflg = CK_36XX; + } else if (cpu_is_ti816x()) { + cpu_mask = RATE_IN_TI816X; + cpu_clkflg = CK_TI816X; } else if (cpu_is_omap34xx()) { if (omap_rev() == OMAP3430_REV_ES1_0) { cpu_mask = RATE_IN_3430ES1; @@ -3550,7 +3553,7 @@ int __init omap3xxx_clk_init(void) /* * Lock DPLL5 and put it in autoidle. */ - if (omap_rev() >= OMAP3430_REV_ES2_0) + if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 778929f7e92..79fb948f814 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -108,6 +108,27 @@ void __init omap3_map_io(void) omap2_set_globals_3xxx(); omap34xx_map_common_io(); } + +/* + * Adjust TAP register base such that omap3_check_revision accesses the correct + * TI816X register for checking device ID (it adds 0x204 to tap base while + * TI816X DEVICE ID register is at offset 0x600 from control base). + */ +#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \ + TI816X_CONTROL_DEVICE_ID - 0x204) + +static struct omap_globals ti816x_globals = { + .class = OMAP343X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), + .ctrl = TI816X_CTRL_BASE, + .prm = TI816X_PRCM_BASE, + .cm = TI816X_PRCM_BASE, +}; + +void __init omap2_set_globals_ti816x(void) +{ + __omap2_set_globals(&ti816x_globals); +} #endif #if defined(CONFIG_ARCH_OMAP4) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index f0629ae0410..c2804c1c4ef 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -52,6 +52,9 @@ #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 +/* TI816X spefic control submodules */ +#define TI816X_CONTROL_DEVCONF 0x600 + /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) @@ -241,6 +244,9 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 +/* TI816X CONTROL_DEVCONF register offsets */ +#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000) + /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 5f9086c65e4..5c25f1b5523 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -191,12 +191,19 @@ static void __init omap3_check_features(void) if (!cpu_is_omap3505() && !cpu_is_omap3517()) omap3_features |= OMAP3_HAS_IO_WAKEUP; + omap3_features |= OMAP3_HAS_SDRC; + /* * TODO: Get additional info (where applicable) * e.g. Size of L2 cache. */ } +static void __init ti816x_check_features(void) +{ + omap3_features = OMAP3_HAS_NEON; +} + static void __init omap3_check_revision(void) { u32 cpuid, idcode; @@ -287,6 +294,20 @@ static void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; } break; + case 0xb81e: + omap_chip.oc = CHIP_IS_TI816X; + + switch (rev) { + case 0: + omap_revision = TI8168_REV_ES1_0; + break; + case 1: + omap_revision = TI8168_REV_ES1_1; + break; + default: + omap_revision = TI8168_REV_ES1_1; + } + break; default: /* Unknown default to latest silicon rev as default*/ omap_revision = OMAP3630_REV_ES1_2; @@ -372,6 +393,8 @@ static void __init omap3_cpuinfo(void) /* Already set in omap3_check_revision() */ strcpy(cpu_name, "AM3505"); } + } else if (cpu_is_ti816x()) { + strcpy(cpu_name, "TI816X"); } else if (omap3_has_iva() && omap3_has_sgx()) { /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ strcpy(cpu_name, "OMAP3430/3530"); @@ -386,7 +409,7 @@ static void __init omap3_cpuinfo(void) strcpy(cpu_name, "OMAP3503"); } - if (cpu_is_omap3630()) { + if (cpu_is_omap3630() || cpu_is_ti816x()) { switch (rev) { case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); @@ -462,7 +485,13 @@ void __init omap2_check_revision(void) omap24xx_check_revision(); } else if (cpu_is_omap34xx()) { omap3_check_revision(); - omap3_check_features(); + + /* TI816X doesn't have feature register */ + if (!cpu_is_ti816x()) + omap3_check_features(); + else + ti816x_check_features(); + omap3_cpuinfo(); return; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 81985a665cb..a48690b9099 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -61,6 +61,14 @@ bne 9998f ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ cmp \irqnr, #0x0 + bne 9998f + + /* + * ti816x has additional IRQ pending register. Checking this + * register on omap2 & omap3 has no effect (read as 0). + */ + ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ + cmp \irqnr, #0x0 9998: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ @@ -133,6 +141,11 @@ bne 9999f ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ cmp \irqnr, #0x0 +#ifdef CONFIG_SOC_OMAPTI816X + bne 9999f + ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ + cmp \irqnr, #0x0 +#endif 9999: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 26a61cf2729..f992a81c393 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -175,6 +175,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = { #endif }; #endif + +#ifdef CONFIG_SOC_OMAPTI816X +static struct map_desc omapti816x_io_desc[] __initdata = { + { + .virtual = L4_34XX_VIRT, + .pfn = __phys_to_pfn(L4_34XX_PHYS), + .length = L4_34XX_SIZE, + .type = MT_DEVICE + }, +}; +#endif + #ifdef CONFIG_ARCH_OMAP4 static struct map_desc omap44xx_io_desc[] __initdata = { { @@ -267,6 +279,14 @@ void __init omap34xx_map_common_io(void) } #endif +#ifdef CONFIG_SOC_OMAPTI816X +void __init omapti816x_map_common_io(void) +{ + iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); + _omap2_map_common_io(); +} +#endif + #ifdef CONFIG_ARCH_OMAP4 void __init omap44xx_map_common_io(void) { @@ -398,7 +418,7 @@ void __init omap2_init_common_infrastructure(void) void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + if (cpu_is_omap24xx() || omap3_has_sdrc()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); } diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 23049c487c4..0b9a23d721f 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -110,7 +110,7 @@ static void omap_mask_irq(struct irq_data *d) unsigned int irq = d->irq; int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() && !cpu_is_ti816x()) { int spurious = 0; /* @@ -205,6 +205,9 @@ void __init omap_init_irq(void) BUG_ON(!base); + if (cpu_is_ti816x()) + bank->nr_irqs = 128; + /* Static mapping, never released */ bank->base_reg = ioremap(base, SZ_4K); if (!bank->base_reg) { diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 74e25cd4bd3..47eef48b883 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) mod_timer(&uart->timer, jiffies + uart->timeout); omap_uart_smart_idle_enable(uart, 0); - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() && !cpu_is_ti816x()) { u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; u32 wk_mask = 0; u32 padconf = 0; @@ -762,13 +762,13 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) p->private_data = uart; /* - * omap44xx: Never read empty UART fifo + * omap44xx, ti816x: Never read empty UART fifo * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ uart->regshift = p->regshift; uart->membase = p->membase; - if (cpu_is_omap44xx()) + if (cpu_is_omap44xx() || cpu_is_ti816x()) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) @@ -850,7 +850,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) } /* Enable the MDR1 errata for OMAP3 */ - if (cpu_is_omap34xx()) + if (cpu_is_omap34xx() && !cpu_is_ti816x()) uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; } diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index d5b26adfb89..e87efe1499b 100644 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -286,5 +286,6 @@ #include #include #include +#include #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index ef4106c1318..427fc8a7c07 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void) } #endif +#ifdef CONFIG_SOC_OMAPTI816X +extern void omapti816x_map_common_io(void); +#else +static inline void omapti816x_map_common_io(void) +{ +} +#endif + #ifdef CONFIG_ARCH_OMAP4 extern void omap44xx_map_common_io(void); #else diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h new file mode 100644 index 00000000000..50510f5dda1 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/ti816x.h @@ -0,0 +1,27 @@ +/* + * This file contains the address data for various TI816X modules. + * + * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_TI816X_H +#define __ASM_ARCH_TI816X_H + +#define L4_SLOW_TI816X_BASE 0x48000000 + +#define TI816X_SCM_BASE 0x48140000 +#define TI816X_CTRL_BASE TI816X_SCM_BASE +#define TI816X_PRCM_BASE 0x48180000 + +#define TI816X_ARM_INTC_BASE 0x48200000 + +#endif /* __ASM_ARCH_TI816X_H */ diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index f1295fafcd3..f1ecfa9fc61 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c @@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) } #endif #ifdef CONFIG_ARCH_OMAP3 - if (cpu_is_omap34xx()) { + if (cpu_is_ti816x()) { + if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) + return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); + } else if (cpu_is_omap34xx()) { if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE)) return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) -- cgit v1.2.3-70-g09d2 From 2c87fb2e644d9141c8723a44a320bb5850790b67 Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Tue, 15 Feb 2011 23:06:08 +0530 Subject: TI816X: Create board support and enable build for TI816X EVM This patch adds minimal support and build configuration for TI816X EVM. Signed-off-by: Hemant Pedanekar Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 5 +++ arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/board-ti8168evm.c | 57 +++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) create mode 100644 arch/arm/mach-omap2/board-ti8168evm.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 23548b60bb1..7a82a76522a 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -299,6 +299,11 @@ config MACH_OMAP_3630SDP default y select OMAP_PACKAGE_CBP +config MACH_TI8168EVM + bool "TI8168 Evaluation Module" + depends on SOC_OMAPTI816X + default y + config MACH_OMAP_4430SDP bool "OMAP 4430 SDP board" default y diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1c0c2b02d87..b577e001d20 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -224,6 +224,7 @@ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ hsmmc.o +obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o # Platform specific device init code usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o obj-y += $(usbfs-m) $(usbfs-y) diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c new file mode 100644 index 00000000000..6282cc4a977 --- /dev/null +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -0,0 +1,57 @@ +/* + * Code for TI8168 EVM. + * + * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +static struct omap_board_config_kernel ti8168_evm_config[] __initdata = { +}; + +static void __init ti8168_evm_init_irq(void) +{ + omap_board_config = ti8168_evm_config; + omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); + omap2_init_common_infrastructure(); + omap2_init_common_devices(NULL, NULL); + omap_init_irq(); +} + +static void __init ti8168_evm_init(void) +{ + omap_serial_init(); +} + +static void __init ti8168_evm_map_io(void) +{ + omap2_set_globals_ti816x(); + omapti816x_map_common_io(); +} + +MACHINE_START(TI8168EVM, "ti8168evm") + /* Maintainer: Texas Instruments */ + .boot_params = 0x80000100, + .map_io = ti8168_evm_map_io, + .init_irq = ti8168_evm_init_irq, + .timer = &omap_timer, + .init_machine = ti8168_evm_init, +MACHINE_END -- cgit v1.2.3-70-g09d2 From 4d887a250d6294d4e17851da46d6eab4de83c91e Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Tue, 15 Feb 2011 23:06:17 +0530 Subject: TI816X: Add low level debug support This patch adds support for low level debugging on TI816X boards. Currently the support for UART3 console on TI816X EVM is added. Signed-off-by: Hemant Pedanekar Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/debug-macro.S | 12 ++++++++++++ arch/arm/plat-omap/include/plat/serial.h | 8 ++++++++ arch/arm/plat-omap/include/plat/uncompress.h | 7 +++++++ 3 files changed, 27 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 6a4d4136002..e1b0f17b092 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -69,6 +69,12 @@ omap_uart_lsr: .word 0 beq 34f @ configure OMAP3UART4 cmp \rp, #OMAP4UART4 @ only on 44xx beq 44f @ configure OMAP4UART4 + cmp \rp, #TI816XUART1 @ ti816x UART offsets different + beq 81f @ configure UART1 + cmp \rp, #TI816XUART2 @ ti816x UART offsets different + beq 82f @ configure UART2 + cmp \rp, #TI816XUART3 @ ti816x UART offsets different + beq 83f @ configure UART3 cmp \rp, #ZOOM_UART @ only on zoom2/3 beq 95f @ configure ZOOM_UART @@ -91,6 +97,12 @@ omap_uart_lsr: .word 0 b 98f 44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) b 98f +81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE) + b 98f +82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE) + b 98f +83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) + b 98f 95: ldr \rp, =ZOOM_UART_BASE mrc p15, 0, \rv, c1, c0 tst \rv, #1 @ MMU enabled? diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index a1a118d052e..8061695aa52 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -51,6 +51,11 @@ #define OMAP4_UART3_BASE 0x48020000 #define OMAP4_UART4_BASE 0x4806e000 +/* TI816X serial ports */ +#define TI816X_UART1_BASE 0x48020000 +#define TI816X_UART2_BASE 0x48022000 +#define TI816X_UART3_BASE 0x48024000 + /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 @@ -81,6 +86,9 @@ #define OMAP4UART2 OMAP2UART2 #define OMAP4UART3 43 #define OMAP4UART4 44 +#define TI816XUART1 81 +#define TI816XUART2 82 +#define TI816XUART3 83 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ad98b85cae2..30b891c4a93 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -93,6 +93,10 @@ static inline void flush(void) #define DEBUG_LL_ZOOM(mach) \ _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) +#define DEBUG_LL_TI816X(p, mach) \ + _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \ + TI816XUART##p) + static inline void __arch_decomp_setup(unsigned long arch_id) { int port = 0; @@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_ZOOM(omap_zoom2); DEBUG_LL_ZOOM(omap_zoom3); + /* TI8168 base boards using UART3 */ + DEBUG_LL_TI816X(3, ti8168evm); + } while (0); } -- cgit v1.2.3-70-g09d2 From e811d3272dbed154b8c56a37392bb1d23c9bd71e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 16 Feb 2011 08:45:46 -0800 Subject: TI816X: Update to use init_early Update to use init_early Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-ti8168evm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index 6282cc4a977..f2b097190e0 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -27,12 +27,16 @@ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = { }; -static void __init ti8168_evm_init_irq(void) +static void __init ti8168_init_early(void) { omap_board_config = ti8168_evm_config; omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); +} + +static void __init ti8168_evm_init_irq(void) +{ omap_init_irq(); } @@ -51,6 +55,7 @@ MACHINE_START(TI8168EVM, "ti8168evm") /* Maintainer: Texas Instruments */ .boot_params = 0x80000100, .map_io = ti8168_evm_map_io, + .init_early = ti8168_init_early, .init_irq = ti8168_evm_init_irq, .timer = &omap_timer, .init_machine = ti8168_evm_init, -- cgit v1.2.3-70-g09d2 From 405505c2b7b9f8a2d2b90e9e7fb4590b059e15dd Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Sun, 16 Jan 2011 13:22:03 +0200 Subject: arm: omap2: clksel: fix compile warningOrganization: Texas Instruments\n Fix the following compile warning: arch/arm/mach-omap2/clkt_clksel.c: In function '_get_div_and_fieldval': arch/arm/mach-omap2/clkt_clksel.c:100:35: warning: 'max_clkr' may be used uninitialized in this function Acked-by: Paul Walmsley Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clkt_clksel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index a781cd6795a..e25364de028 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, u32 *field_val) { const struct clksel *clks; - const struct clksel_rate *clkr, *max_clkr; + const struct clksel_rate *clkr, *max_clkr = NULL; u8 max_div = 0; clks = _get_clksel_by_parent(clk, src_clk); -- cgit v1.2.3-70-g09d2 From d11c217f1a8f9ea2b2c89b8a533396482a36e8c0 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 2 Feb 2011 12:04:36 +0000 Subject: OMAP4: hwmod data: Add hwspinlock Add hwspinlock hwmod data for OMAP4 chip Signed-off-by: Cousson, Benoit Signed-off-by: Hari Kanigeri Signed-off-by: Ohad Ben-Cohen Cc: Paul Walmsley [b-cousson@ti.com: Move the data to keep the original order and add missing SIDLE_SMART_WKUP flag] --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 65 +++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c2806bd11fb..46da576ffaf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -555,7 +555,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * sl2if * slimbus1 * slimbus2 - * spinlock * timer1 * timer10 * timer11 @@ -1638,6 +1637,67 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'spinlock' class + * spinlock provides hardware assistance for synchronizing the processes + * running on multiple processors + */ + +static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { + .name = "spinlock", + .sysc = &omap44xx_spinlock_sysc, +}; + +/* spinlock */ +static struct omap_hwmod omap44xx_spinlock_hwmod; +static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { + { + .pa_start = 0x4a0f6000, + .pa_end = 0x4a0f6fff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_cfg -> spinlock */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_spinlock_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_spinlock_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* spinlock slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { + &omap44xx_l4_cfg__spinlock, +}; + +static struct omap_hwmod omap44xx_spinlock_hwmod = { + .name = "spinlock", + .class = &omap44xx_spinlock_hwmod_class, + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, + }, + }, + .slaves = omap44xx_spinlock_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'uart' class * universal asynchronous receiver/transmitter (uart) @@ -2058,6 +2118,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_smartreflex_iva_hwmod, &omap44xx_smartreflex_mpu_hwmod, + /* spinlock class */ + &omap44xx_spinlock_hwmod, + /* uart class */ &omap44xx_uart1_hwmod, &omap44xx_uart2_hwmod, -- cgit v1.2.3-70-g09d2 From fe5a4901c20c09b4380b7d4a0197efb6489c4ce8 Mon Sep 17 00:00:00 2001 From: Hema HK Date: Wed, 16 Feb 2011 17:34:40 +0530 Subject: usb: musb: AM35x: moving internal phy functions out of usb_musb.c file Moved all the board specific internal PHY functions out of usb_musb.c file as this file is shared between the OMAP2+ and AM35xx platforms. There exists a file which has the functions specific to internal PHY used for OMAP4 platform. Moved all phy specific functions to this file and passing these functions through board data in the board file. Signed-off-by: Hema HK Cc: Paul Walmsley Cc: Tony Lindgren Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/board-am3517evm.c | 4 ++ arch/arm/mach-omap2/omap_phy_internal.c | 93 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/usb-musb.c | 97 --------------------------------- arch/arm/plat-omap/include/plat/usb.h | 4 ++ 5 files changed, 103 insertions(+), 98 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1c0c2b02d87..43d4e14d0ec 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -218,7 +218,8 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ hsmmc.o \ omap_phy_internal.o -obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o +obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \ + omap_phy_internal.o \ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 10d60b7743c..3413bf993c7 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -409,6 +409,10 @@ static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_ULPI, .mode = MUSB_OTG, .power = 500, + .set_phy_power = am35x_musb_phy_power, + .clear_irq = am35x_musb_clear_irq, + .set_mode = am35x_musb_set_mode, + .reset = am35x_musb_reset, }; static __init void am3517_evm_musb_init(void) diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index 745252c60e3..f172ec06c06 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -29,6 +29,7 @@ #include #include +#include "control.h" /* OMAP control module register for UTMI PHY */ #define CONTROL_DEV_CONF 0x300 @@ -147,3 +148,95 @@ int omap4430_phy_exit(struct device *dev) return 0; } + +void am35x_musb_reset(void) +{ + u32 regval; + + /* Reset the musb interface */ + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + + regval |= AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval &= ~AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); +} + +void am35x_musb_phy_power(u8 on) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(100); + u32 devconf2; + + if (on) { + /* + * Start the on-chip PHY and its PLL. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); + devconf2 |= CONF2_PHY_PLLON; + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + + pr_info(KERN_INFO "Waiting for PHY clock good...\n"); + while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) + & CONF2_PHYCLKGD)) { + cpu_relax(); + + if (time_after(jiffies, timeout)) { + pr_err(KERN_ERR "musb PHY clock good timed out\n"); + break; + } + } + } else { + /* + * Power down the on-chip PHY. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_PHY_PLLON; + devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + } +} + +void am35x_musb_clear_irq(void) +{ + u32 regval; + + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + regval |= AM35XX_USBOTGSS_INT_CLR; + omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +} + +void am35x_musb_set_mode(u8 musb_mode) +{ + u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_OTGMODE; + switch (musb_mode) { +#ifdef CONFIG_USB_MUSB_HDRC_HCD + case MUSB_HOST: /* Force VBUS valid, ID = 0 */ + devconf2 |= CONF2_FORCE_HOST; + break; +#endif +#ifdef CONFIG_USB_GADGET_MUSB_HDRC + case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ + devconf2 |= CONF2_FORCE_DEVICE; + break; +#endif +#ifdef CONFIG_USB_MUSB_OTG + case MUSB_OTG: /* Don't override the VBUS/ID comparators */ + devconf2 |= CONF2_NO_OVERRIDE; + break; +#endif + default: + pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); + } + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); +} diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 5298949d4b1..9107883287f 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -30,102 +30,9 @@ #include #include #include -#include "control.h" #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) -static void am35x_musb_reset(void) -{ - u32 regval; - - /* Reset the musb interface */ - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); - - regval |= AM35XX_USBOTGSS_SW_RST; - omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); - - regval &= ~AM35XX_USBOTGSS_SW_RST; - omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); - - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); -} - -static void am35x_musb_phy_power(u8 on) -{ - unsigned long timeout = jiffies + msecs_to_jiffies(100); - u32 devconf2; - - if (on) { - /* - * Start the on-chip PHY and its PLL. - */ - devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); - devconf2 |= CONF2_PHY_PLLON; - - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); - - pr_info(KERN_INFO "Waiting for PHY clock good...\n"); - while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) - & CONF2_PHYCLKGD)) { - cpu_relax(); - - if (time_after(jiffies, timeout)) { - pr_err(KERN_ERR "musb PHY clock good timed out\n"); - break; - } - } - } else { - /* - * Power down the on-chip PHY. - */ - devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~CONF2_PHY_PLLON; - devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); - } -} - -static void am35x_musb_clear_irq(void) -{ - u32 regval; - - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - regval |= AM35XX_USBOTGSS_INT_CLR; - omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -} - -static void am35x_musb_set_mode(u8 musb_mode) -{ - u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~CONF2_OTGMODE; - switch (musb_mode) { -#ifdef CONFIG_USB_MUSB_HDRC_HCD - case MUSB_HOST: /* Force VBUS valid, ID = 0 */ - devconf2 |= CONF2_FORCE_HOST; - break; -#endif -#ifdef CONFIG_USB_GADGET_MUSB_HDRC - case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ - devconf2 |= CONF2_FORCE_DEVICE; - break; -#endif -#ifdef CONFIG_USB_MUSB_OTG - case MUSB_OTG: /* Don't override the VBUS/ID comparators */ - devconf2 |= CONF2_NO_OVERRIDE; - break; -#endif - default: - pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); - } - - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -} - static struct resource musb_resources[] = { [0] = { /* start and end set dynamically */ .flags = IORESOURCE_MEM, @@ -189,10 +96,6 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) musb_device.name = "musb-am35x"; musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; musb_resources[1].start = INT_35XX_USBOTG_IRQ; - board_data->set_phy_power = am35x_musb_phy_power; - board_data->clear_irq = am35x_musb_clear_irq; - board_data->set_mode = am35x_musb_set_mode; - board_data->reset = am35x_musb_reset; } else if (cpu_is_omap34xx()) { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 450a332f100..077192759af 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -91,6 +91,10 @@ extern int omap4430_phy_exit(struct device *dev); #endif +extern void am35x_musb_reset(void); +extern void am35x_musb_phy_power(u8 on); +extern void am35x_musb_clear_irq(void); +extern void am35x_musb_set_mode(u8 musb_mode); /* * FIXME correct answer depends on hmc_mode, -- cgit v1.2.3-70-g09d2 From 2aae4221eebf926ad1058546e2cb81dae8f3e696 Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Wed, 16 Feb 2011 15:42:15 +0530 Subject: arm: omap4: usb: explicitly configure MUSB pads Use the mux framework APIs to explicitly configure the MUSB pads. The MUSB controller in OMAP4 can use either the old ULPI interface, or the new internal PHY. Configure the pads accordingly. Signed-off-by: Anand Gadiyar Cc: Tony Lindgren Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/usb-musb.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 9107883287f..9788b494185 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -30,6 +30,7 @@ #include #include #include +#include "mux.h" #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) @@ -88,6 +89,43 @@ static struct platform_device musb_device = { .resource = musb_resources, }; +static void usb_musb_mux_init(struct omap_musb_board_data *board_data) +{ + switch (board_data->interface_type) { + case MUSB_INTERFACE_UTMI: + omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT); + omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT); + break; + case MUSB_INTERFACE_ULPI: + omap_mux_init_signal("usba0_ulpiphy_clk", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_stp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dir", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_nxt", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat0", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat1", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat2", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat3", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat4", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat5", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat6", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usba0_ulpiphy_dat7", + OMAP_PIN_INPUT_PULLDOWN); + break; + default: + break; + } +} void __init usb_musb_init(struct omap_musb_board_data *board_data) { if (cpu_is_omap243x()) { @@ -102,6 +140,8 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; + + usb_musb_mux_init(board_data); } musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; -- cgit v1.2.3-70-g09d2 From 1dbea0f5e23b6c647db72fa4a048cb7140625e13 Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Wed, 16 Feb 2011 16:47:19 +0530 Subject: arm: omap4: 4430sdp: drop ehci support Most revisions of the OMAP4 Blaze/SDP platform do not have the EHCI signals routed by default. The pads are routed for the alternate HSI functionality instead, and explicit board modifications are needed to route the signals to the USB PHY on the board. Also, turning on the PHY connected to the EHCI port causes a board reboot during bootup due to an unintended short on the rails - this affects many initial revisions of the board, and needs a minor board mod to fix (or as a workaround, one should not attempt to power on the USB PHY). Given that these boards need explicit board mods to even get EHCI working (separate from the accidental short above), we should not attempt to enable EHCI by default. So drop the EHCI support from the board files for the Blaze/SDP platforms. Signed-off-by: Anand Gadiyar Cc: Keshava Munegowda Cc: Tony Lindgren Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/board-4430sdp.c | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 07d1b20b114..674c183f813 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -44,7 +44,6 @@ #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 -#define OMAP4SDP_MDM_PWR_EN_GPIO 157 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 #define OMAP4_SFH7741_ENABLE_GPIO 188 @@ -251,16 +250,6 @@ static void __init omap_4430sdp_init_irq(void) gic_init_irq(); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .phy_reset = false, - .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = -EINVAL, - .reset_gpio_port[2] = -EINVAL, -}; - static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, .mode = MUSB_OTG, @@ -576,14 +565,6 @@ static void __init omap_4430sdp_init(void) omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); - /* Power on the ULPI PHY */ - status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); - if (status) - pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__); - else - gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); - - usb_ehci_init(&ehci_pdata); usb_musb_init(&musb_board_data); status = omap_ethernet_init(); -- cgit v1.2.3-70-g09d2 From 44d02acf54114e4d5c905b6b1a6473a7d302312d Mon Sep 17 00:00:00 2001 From: Hema HK Date: Thu, 17 Feb 2011 12:07:17 +0530 Subject: OMAP2430: hwmod data: Add USBOTG OMAP2430 hwmod data structures are populated with base address, L3 and L4 interface clocks, IRQs and sysconfig register details. As per OMAP USBOTG specification, need to configure the USBOTG to smart idle/standby or no idle/standby during data transfer and force idle/standby when not in use to support retention and off-mode. By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags, framework will take care of configuring to no idle/standby when module is enabled and force idle/standby when suspended. Signed-off-by: Hema HK Cc: Tony Lindgren Cc: Kevin Hilman Cc: Cousson, Benoit Cc: Paul Walmsley Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 98 ++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 8ecfbcde13b..76bbf8a4703 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -89,6 +89,16 @@ static struct omap_hwmod omap2430_uart3_hwmod; static struct omap_hwmod omap2430_i2c1_hwmod; static struct omap_hwmod omap2430_i2c2_hwmod; +static struct omap_hwmod omap2430_usbhsotg_hwmod; + +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { + .master = &omap2430_usbhsotg_hwmod, + .slave = &omap2430_l3_main_hwmod, + .clk = "core_l3_ck", + .user = OCP_USER_MPU, +}; + /* I2C IP block address space length (in bytes) */ #define OMAP2_I2C_AS_LEN 128 @@ -189,6 +199,35 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* +* usbhsotg interface data +*/ +static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { + { + .pa_start = OMAP243X_HS_BASE, + .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core ->usbhsotg interface */ +static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_usbhsotg_hwmod, + .clk = "usb_l4_ick", + .addr = omap2430_usbhsotg_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { + &omap2430_usbhsotg__l3, +}; + +static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { + &omap2430_l4_core__usbhsotg, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { &omap2430_l3_main__l4_core, @@ -919,6 +958,62 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * usbhsotg + */ +static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap2430_usbhsotg_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, +}; + +static struct omap_hwmod omap2430_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap2430_usbhsotg_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs), + .main_clk = "usbhs_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_USBHS_MASK, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, + }, + }, + .masters = omap2430_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), + .slaves = omap2430_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), + .class = &usbotg_class, + /* + * Erratum ID: i479 idle_req / idle_ack mechanism potentially + * broken when autoidle is enabled + * workaround is to disable the autoidle bit at module level. + */ + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE + | HWMOD_SWSUP_MSTANDBY, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, @@ -941,6 +1036,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { /* dma_system class*/ &omap2430_dma_system_hwmod, + + /* usbotg class*/ + &omap2430_usbhsotg_hwmod, NULL, }; -- cgit v1.2.3-70-g09d2 From 870ea2b8e750f40fe5681b902ce0d5445297e610 Mon Sep 17 00:00:00 2001 From: Hema HK Date: Thu, 17 Feb 2011 12:07:18 +0530 Subject: OMAP3xxx: hwmod data: Add USBOTG OMAP3 hwmod data structures are populated for USBOTG with base address, L3 and L4 interface clocks, IRQs and sysconfig register details. This is applicable for OMAP3430 amd OMAP3630. As per OMAP USBOTG specification, need to configure the USBOTG to smart idle/standby or no idle/standby during data transfer and force idle/standby when not in use to support retention and offmode. By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags, framework will take care of configuring to no idle/standby when module is enabled and force idle/standby when idled. Signed-off-by: Hema HK Cc: Tony Lindgren Cc: Kevin Hilman Cc: Cousson, Benoit Cc: Paul Walmsley Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 101 +++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 8d8181334f8..cce09fdb904 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -107,6 +107,15 @@ static struct omap_hwmod omap3xxx_uart1_hwmod; static struct omap_hwmod omap3xxx_uart2_hwmod; static struct omap_hwmod omap3xxx_uart3_hwmod; static struct omap_hwmod omap3xxx_uart4_hwmod; +static struct omap_hwmod omap3xxx_usbhsotg_hwmod; + +/* l3_core -> usbhsotg interface */ +static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { + .master = &omap3xxx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -301,6 +310,36 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { .user = OCP_USER_MPU, }; +/* +* usbhsotg interface data +*/ + +static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { + { + .pa_start = OMAP34XX_HSUSB_OTG_BASE, + .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = omap3xxx_usbhsotg_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { + &omap3xxx_usbhsotg__l3, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { + &omap3xxx_l4_core__usbhsotg, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -1356,6 +1395,64 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; +/* + * usbhsotg + */ +static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class usbotg_class = { + .name = "usbotg", + .sysc = &omap3xxx_usbhsotg_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 92 }, + { .name = "dma", .irq = 93 }, +}; + +static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { + .name = "usb_otg_hs", + .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs), + .main_clk = "hsotgusb_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT + }, + }, + .masters = omap3xxx_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), + .slaves = omap3xxx_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), + .class = &usbotg_class, + + /* + * Erratum ID: i479 idle_req / idle_ack mechanism potentially + * broken when autoidle is enabled + * workaround is to disable the autoidle bit at module level. + */ + .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE + | HWMOD_SWSUP_MSTANDBY, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -1387,6 +1484,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { /* dma_system class*/ &omap3xxx_dma_system_hwmod, + + /* usbotg class */ + &omap3xxx_usbhsotg_hwmod, + NULL, }; -- cgit v1.2.3-70-g09d2 From 273ff8c3bc04cf358c131f49ee7a11efa7ec73d7 Mon Sep 17 00:00:00 2001 From: Hema HK Date: Thu, 17 Feb 2011 12:07:19 +0530 Subject: AM35xx: hwmod data: Add USBOTG AM35xx hwmod data structures are populated for USBOTG with base address, L3 and L4 interface clocks and IRQ. Signed-off-by: Hema HK Cc: Tony Lindgren Cc: Kevin Hilman Cc: Cousson, Benoit Cc: Paul Walmsley Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 65 ++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index cce09fdb904..b4cd8ddf963 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -28,6 +28,7 @@ #include "prm-regbits-34xx.h" #include "cm-regbits-34xx.h" #include "wd_timer.h" +#include /* * OMAP3xxx hardware module integration data @@ -55,6 +56,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod; static struct omap_hwmod omap3xxx_gpio6_hwmod; static struct omap_hwmod omap34xx_sr1_hwmod; static struct omap_hwmod omap34xx_sr2_hwmod; +static struct omap_hwmod am35xx_usbhsotg_hwmod; + static struct omap_hwmod omap3xxx_dma_system_hwmod; @@ -117,6 +120,13 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { .user = OCP_USER_MPU, }; +/* l3_core -> am35xx_usbhsotg interface */ +static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { + .master = &am35xx_usbhsotg_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .clk = "core_l3_ick", + .user = OCP_USER_MPU, +}; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .master = &omap3xxx_l4_core_hwmod, @@ -340,6 +350,31 @@ static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { &omap3xxx_l4_core__usbhsotg, }; +static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { + { + .pa_start = AM35XX_IPSS_USBOTGSS_BASE, + .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> usbhsotg */ +static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &am35xx_usbhsotg_hwmod, + .clk = "l4_ick", + .addr = am35xx_usbhsotg_addrs, + .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { + &am35xx_usbhsotg__l3, +}; + +static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { + &am35xx_l4_core__usbhsotg, +}; /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -1452,6 +1487,33 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | HWMOD_SWSUP_MSTANDBY, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* usb_otg_hs */ +static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { + + { .name = "mc", .irq = 71 }, +}; + +static struct omap_hwmod_class am35xx_usbotg_class = { + .name = "am35xx_usbotg", + .sysc = NULL, +}; + +static struct omap_hwmod am35xx_usbhsotg_hwmod = { + .name = "am35x_otg_hs", + .mpu_irqs = am35xx_usbhsotg_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs), + .main_clk = NULL, + .prcm = { + .omap2 = { + }, + }, + .masters = am35xx_usbhsotg_masters, + .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), + .slaves = am35xx_usbhsotg_slaves, + .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), + .class = &am35xx_usbotg_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) +}; static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, @@ -1488,6 +1550,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { /* usbotg class */ &omap3xxx_usbhsotg_hwmod, + /* usbotg for am35x */ + &am35xx_usbhsotg_hwmod, + NULL, }; -- cgit v1.2.3-70-g09d2 From 18a26892d62d2786c2b259ba4605ee10bba0ba13 Mon Sep 17 00:00:00 2001 From: Hema HK Date: Thu, 17 Feb 2011 12:07:21 +0530 Subject: OMAP2+: musb: hwmod adaptation for musb registration Using omap_device_build API instead of platform_device_register for OMAP2430,OMAP3xxx, OMAP4430 and AM35x musb device registration. The device specific resources defined in centralized database will be used. Signed-off-by: Hema HK Cc: Tony Lindgren Cc: Kevin Hilman Cc: Cousson, Benoit Cc: Paul Walmsley Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/usb-musb.c | 84 ++++++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 40 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 9788b494185..a9d4d143086 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -30,26 +30,11 @@ #include #include #include +#include #include "mux.h" #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) -static struct resource musb_resources[] = { - [0] = { /* start and end set dynamically */ - .flags = IORESOURCE_MEM, - }, - [1] = { /* general IRQ */ - .start = INT_243X_HS_USB_MC, - .flags = IORESOURCE_IRQ, - .name = "mc", - }, - [2] = { /* DMA IRQ */ - .start = INT_243X_HS_USB_DMA, - .flags = IORESOURCE_IRQ, - .name = "dma", - }, -}; - static struct musb_hdrc_config musb_config = { .multipoint = 1, .dyn_fifo = 1, @@ -77,16 +62,12 @@ static struct musb_hdrc_platform_data musb_plat = { static u64 musb_dmamask = DMA_BIT_MASK(32); -static struct platform_device musb_device = { - .name = "musb-omap2430", - .id = -1, - .dev = { - .dma_mask = &musb_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &musb_plat, +static struct omap_device_pm_latency omap_musb_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, - .num_resources = ARRAY_SIZE(musb_resources), - .resource = musb_resources, }; static void usb_musb_mux_init(struct omap_musb_board_data *board_data) @@ -126,24 +107,20 @@ static void usb_musb_mux_init(struct omap_musb_board_data *board_data) break; } } + void __init usb_musb_init(struct omap_musb_board_data *board_data) { - if (cpu_is_omap243x()) { - musb_resources[0].start = OMAP243X_HS_BASE; - } else if (cpu_is_omap3517() || cpu_is_omap3505()) { - musb_device.name = "musb-am35x"; - musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; - musb_resources[1].start = INT_35XX_USBOTG_IRQ; - } else if (cpu_is_omap34xx()) { - musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; - } else if (cpu_is_omap44xx()) { - musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; - musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; - musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; + struct omap_hwmod *oh; + struct omap_device *od; + struct platform_device *pdev; + struct device *dev; + int bus_id = -1; + const char *oh_name, *name; + if (cpu_is_omap3517() || cpu_is_omap3505()) { + } else if (cpu_is_omap44xx()) { usb_musb_mux_init(board_data); } - musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; /* * REVISIT: This line can be removed once all the platforms using @@ -155,8 +132,35 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) musb_plat.mode = board_data->mode; musb_plat.extvbus = board_data->extvbus; - if (platform_device_register(&musb_device) < 0) - printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); + if (cpu_is_omap3517() || cpu_is_omap3505()) { + oh_name = "am35x_otg_hs"; + name = "musb-am35x"; + } else { + oh_name = "usb_otg_hs"; + name = "musb-omap2430"; + } + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return; + } + + od = omap_device_build(name, bus_id, oh, &musb_plat, + sizeof(musb_plat), omap_musb_latency, + ARRAY_SIZE(omap_musb_latency), false); + if (IS_ERR(od)) { + pr_err("Could not build omap_device for %s %s\n", + name, oh_name); + return; + } + + pdev = &od->pdev; + dev = &pdev->dev; + get_device(dev); + dev->dma_mask = &musb_dmamask; + dev->coherent_dma_mask = musb_dmamask; + put_device(dev); } #else -- cgit v1.2.3-70-g09d2 From 9bcbd7f0d577b3f6d5742188563457a083b8ae7f Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 2 Feb 2011 17:52:13 +0530 Subject: OMAP4: hwmod data: Add McSPI Update omap4 hwmod file with McSPI info. Signed-off-by: Benoit Cousson Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Grant Likely Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 249 ++++++++++++++++++++++++++++- 1 file changed, 245 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 46da576ffaf..8199eb26fd3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -534,10 +534,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * mcbsp3 * mcbsp4 * mcpdm - * mcspi1 - * mcspi2 - * mcspi3 - * mcspi4 * mmc1 * mmc2 * mmc3 @@ -1433,6 +1429,245 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { + .name = "mcspi", + .sysc = &omap44xx_mcspi_sysc, +}; + +/* mcspi1 */ +static struct omap_hwmod omap44xx_mcspi1_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { + { .irq = 65 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { + { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, + { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, + { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, + { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, + { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, + { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, + { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, + { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480981ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcspi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { + &omap44xx_l4_per__mcspi1, +}; + +static struct omap_hwmod omap44xx_mcspi1_hwmod = { + .name = "mcspi1", + .class = &omap44xx_mcspi_hwmod_class, + .mpu_irqs = omap44xx_mcspi1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs), + .sdma_reqs = omap44xx_mcspi1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs), + .main_clk = "mcspi1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, + }, + }, + .slaves = omap44xx_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcspi2 */ +static struct omap_hwmod omap44xx_mcspi2_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { + { .irq = 66 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { + { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, + { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, + { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, + { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a1ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcspi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { + &omap44xx_l4_per__mcspi2, +}; + +static struct omap_hwmod omap44xx_mcspi2_hwmod = { + .name = "mcspi2", + .class = &omap44xx_mcspi_hwmod_class, + .mpu_irqs = omap44xx_mcspi2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs), + .sdma_reqs = omap44xx_mcspi2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs), + .main_clk = "mcspi2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, + }, + }, + .slaves = omap44xx_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcspi3 */ +static struct omap_hwmod omap44xx_mcspi3_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { + { .irq = 91 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { + { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, + { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, + { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, + { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { + { + .pa_start = 0x480b8000, + .pa_end = 0x480b81ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcspi3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { + &omap44xx_l4_per__mcspi3, +}; + +static struct omap_hwmod omap44xx_mcspi3_hwmod = { + .name = "mcspi3", + .class = &omap44xx_mcspi_hwmod_class, + .mpu_irqs = omap44xx_mcspi3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs), + .sdma_reqs = omap44xx_mcspi3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs), + .main_clk = "mcspi3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, + }, + }, + .slaves = omap44xx_mcspi3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcspi4 */ +static struct omap_hwmod omap44xx_mcspi4_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { + { .irq = 48 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { + { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, + { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba1ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcspi4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcspi4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcspi4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcspi4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { + &omap44xx_l4_per__mcspi4, +}; + +static struct omap_hwmod omap44xx_mcspi4_hwmod = { + .name = "mcspi4", + .class = &omap44xx_mcspi_hwmod_class, + .mpu_irqs = omap44xx_mcspi4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs), + .sdma_reqs = omap44xx_mcspi4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs), + .main_clk = "mcspi4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, + }, + }, + .slaves = omap44xx_mcspi4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'mpu' class * mpu sub-system @@ -2110,6 +2345,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_iva_seq0_hwmod, &omap44xx_iva_seq1_hwmod, + /* mcspi class */ + &omap44xx_mcspi1_hwmod, + &omap44xx_mcspi2_hwmod, + &omap44xx_mcspi3_hwmod, + &omap44xx_mcspi4_hwmod, + /* mpu class */ &omap44xx_mpu_hwmod, -- cgit v1.2.3-70-g09d2 From 35d1a66a9cc03167ff5266e5fcb0dea639123d84 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Fri, 11 Feb 2011 11:17:14 +0000 Subject: OMAP4: hwmod data: Add timer Add the data for the 11 timers IPs. OMAP4 contains two differents IP variants for the timers: - 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11) - 3 x 1ms timer (1, 2 & 10) The regular timers registers programming model was changed due to the adaptation to the new IP interface. Unfortunately the 1ms version still use the previous programming model. The driver will have to take care of theses differences. Please note that the capability and the partitioning is also different depending of the instance. - timer 1 is inside the wakeup domain - timers 5, 6, 7 & 8 are inside in the ABE (audio backend) - timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain The timer was previously named gptimerX or dmtimerX, it is now simply named timerX. Signed-off-by: Benoit Cousson Signed-off-by: Tarun Kanti DebBarma [b-cousson@ti.com: Fix alignement in class attribute, re-order flags and update the changelog] --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 633 ++++++++++++++++++++++++++++- 1 file changed, 622 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 8199eb26fd3..37b30246a06 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -551,17 +551,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * sl2if * slimbus1 * slimbus2 - * timer1 - * timer10 - * timer11 - * timer2 - * timer3 - * timer4 - * timer5 - * timer6 - * timer7 - * timer8 - * timer9 * usb_host_fs * usb_host_hs * usb_otg_hs @@ -1933,6 +1922,615 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'timer' class + * general purpose timer module with accurate 1ms tick + * This class contains several variants: ['timer_1ms', 'timer'] + */ + +static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { + .name = "timer", + .sysc = &omap44xx_timer_1ms_sysc, +}; + +static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap44xx_timer_sysc, +}; + +/* timer1 */ +static struct omap_hwmod omap44xx_timer1_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { + { .irq = 37 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { + { + .pa_start = 0x4a318000, + .pa_end = 0x4a31807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_timer1_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_timer1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { + &omap44xx_l4_wkup__timer1, +}; + +static struct omap_hwmod omap44xx_timer1_hwmod = { + .name = "timer1", + .class = &omap44xx_timer_1ms_hwmod_class, + .mpu_irqs = omap44xx_timer1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), + .main_clk = "timer1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + }, + }, + .slaves = omap44xx_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer2 */ +static struct omap_hwmod omap44xx_timer2_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { + { .irq = 38 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { + { + .pa_start = 0x48032000, + .pa_end = 0x4803207f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { + &omap44xx_l4_per__timer2, +}; + +static struct omap_hwmod omap44xx_timer2_hwmod = { + .name = "timer2", + .class = &omap44xx_timer_1ms_hwmod_class, + .mpu_irqs = omap44xx_timer2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs), + .main_clk = "timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + }, + }, + .slaves = omap44xx_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer3 */ +static struct omap_hwmod omap44xx_timer3_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { + { .irq = 39 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { + { + .pa_start = 0x48034000, + .pa_end = 0x4803407f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { + &omap44xx_l4_per__timer3, +}; + +static struct omap_hwmod omap44xx_timer3_hwmod = { + .name = "timer3", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs), + .main_clk = "timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + }, + }, + .slaves = omap44xx_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer4 */ +static struct omap_hwmod omap44xx_timer4_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { + { .irq = 40 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { + { + .pa_start = 0x48036000, + .pa_end = 0x4803607f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { + &omap44xx_l4_per__timer4, +}; + +static struct omap_hwmod omap44xx_timer4_hwmod = { + .name = "timer4", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs), + .main_clk = "timer4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + }, + }, + .slaves = omap44xx_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer5 */ +static struct omap_hwmod omap44xx_timer5_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { + { .irq = 41 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { + { + .pa_start = 0x40138000, + .pa_end = 0x4013807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x4903807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer5 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer5_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer5_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer5 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { + &omap44xx_l4_abe__timer5, + &omap44xx_l4_abe__timer5_dma, +}; + +static struct omap_hwmod omap44xx_timer5_hwmod = { + .name = "timer5", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs), + .main_clk = "timer5_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + }, + }, + .slaves = omap44xx_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer6 */ +static struct omap_hwmod omap44xx_timer6_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { + { .irq = 42 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { + { + .pa_start = 0x4013a000, + .pa_end = 0x4013a07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer6 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { + { + .pa_start = 0x4903a000, + .pa_end = 0x4903a07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer6 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer6_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer6_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer6 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { + &omap44xx_l4_abe__timer6, + &omap44xx_l4_abe__timer6_dma, +}; + +static struct omap_hwmod omap44xx_timer6_hwmod = { + .name = "timer6", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer6_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), + .main_clk = "timer6_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + }, + }, + .slaves = omap44xx_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer7 */ +static struct omap_hwmod omap44xx_timer7_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { + { .irq = 43 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { + { + .pa_start = 0x4013c000, + .pa_end = 0x4013c07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer7 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { + { + .pa_start = 0x4903c000, + .pa_end = 0x4903c07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer7 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer7_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer7_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer7 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { + &omap44xx_l4_abe__timer7, + &omap44xx_l4_abe__timer7_dma, +}; + +static struct omap_hwmod omap44xx_timer7_hwmod = { + .name = "timer7", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer7_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs), + .main_clk = "timer7_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + }, + }, + .slaves = omap44xx_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer8 */ +static struct omap_hwmod omap44xx_timer8_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { + { .irq = 44 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { + { + .pa_start = 0x4013e000, + .pa_end = 0x4013e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer8 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { + { + .pa_start = 0x4903e000, + .pa_end = 0x4903e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> timer8 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_timer8_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_timer8_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* timer8 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { + &omap44xx_l4_abe__timer8, + &omap44xx_l4_abe__timer8_dma, +}; + +static struct omap_hwmod omap44xx_timer8_hwmod = { + .name = "timer8", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer8_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs), + .main_clk = "timer8_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + }, + }, + .slaves = omap44xx_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer9 */ +static struct omap_hwmod omap44xx_timer9_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { + { .irq = 45 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { + { + .pa_start = 0x4803e000, + .pa_end = 0x4803e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer9_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer9_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { + &omap44xx_l4_per__timer9, +}; + +static struct omap_hwmod omap44xx_timer9_hwmod = { + .name = "timer9", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer9_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs), + .main_clk = "timer9_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + }, + }, + .slaves = omap44xx_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer10 */ +static struct omap_hwmod omap44xx_timer10_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { + { .irq = 46 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x4808607f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer10 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer10_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer10_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer10 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { + &omap44xx_l4_per__timer10, +}; + +static struct omap_hwmod omap44xx_timer10_hwmod = { + .name = "timer10", + .class = &omap44xx_timer_1ms_hwmod_class, + .mpu_irqs = omap44xx_timer10_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs), + .main_clk = "timer10_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + }, + }, + .slaves = omap44xx_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* timer11 */ +static struct omap_hwmod omap44xx_timer11_hwmod; +static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { + { .irq = 47 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x4808807f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer11 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_timer11_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_timer11_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer11 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { + &omap44xx_l4_per__timer11, +}; + +static struct omap_hwmod omap44xx_timer11_hwmod = { + .name = "timer11", + .class = &omap44xx_timer_hwmod_class, + .mpu_irqs = omap44xx_timer11_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs), + .main_clk = "timer11_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + }, + }, + .slaves = omap44xx_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'uart' class * universal asynchronous receiver/transmitter (uart) @@ -2362,6 +2960,19 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* spinlock class */ &omap44xx_spinlock_hwmod, + /* timer class */ + &omap44xx_timer1_hwmod, + &omap44xx_timer2_hwmod, + &omap44xx_timer3_hwmod, + &omap44xx_timer4_hwmod, + &omap44xx_timer5_hwmod, + &omap44xx_timer6_hwmod, + &omap44xx_timer7_hwmod, + &omap44xx_timer8_hwmod, + &omap44xx_timer9_hwmod, + &omap44xx_timer10_hwmod, + &omap44xx_timer11_hwmod, + /* uart class */ &omap44xx_uart1_hwmod, &omap44xx_uart2_hwmod, -- cgit v1.2.3-70-g09d2 From d63bd74fbb5fb2161d9cb90cd7a93a2c5db47c63 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Thu, 27 Jan 2011 11:17:03 +0000 Subject: OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods. In OMAP4 there are severals IPs that can be reached by differents interconnect paths depending of the access initiator (MPU vs. SDMA). In the case of the DSS, both L3 direct path and L4 CFG path can be used to access all the DSS IPs. The two ocp_ip already exists to support the two address spaces. +------------+-- L3_MAIN --+ MPU IP | | +-- L4_CFG --+ L3 main address range is specified first, since it is used by default. dss is also considered as an IP as dispc, rfbi, and named as dss_core. Signed-off-by: Benoit Cousson Signed-off-by: Mayuresh Janorkar Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal [b-cousson@ti.com: Re-organize structures to match file convention and remove irq entry from dss_hwmod] --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 612 ++++++++++++++++++++++++++++- 1 file changed, 604 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 37b30246a06..aafe60dc711 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1,7 +1,7 @@ /* * Hardware modules present on the OMAP44xx chips * - * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Texas Instruments, Inc. * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley @@ -43,6 +43,7 @@ static struct omap_hwmod omap44xx_dma_system_hwmod; static struct omap_hwmod omap44xx_dmm_hwmod; static struct omap_hwmod omap44xx_dsp_hwmod; +static struct omap_hwmod omap44xx_dss_hwmod; static struct omap_hwmod omap44xx_emif_fw_hwmod; static struct omap_hwmod omap44xx_iva_hwmod; static struct omap_hwmod omap44xx_l3_instr_hwmod; @@ -213,6 +214,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* dss -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { + .master = &omap44xx_dss_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 -> l3_main_1 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { .master = &omap44xx_l3_main_2_hwmod, @@ -240,6 +249,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { /* l3_main_1 slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { &omap44xx_dsp__l3_main_1, + &omap44xx_dss__l3_main_1, &omap44xx_l3_main_2__l3_main_1, &omap44xx_l4_cfg__l3_main_1, &omap44xx_mpu__l3_main_1, @@ -507,13 +517,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * ctrl_module_wkup * debugss * dmic - * dss - * dss_dispc - * dss_dsi1 - * dss_dsi2 - * dss_hdmi - * dss_rfbi - * dss_venc * efuse_ctrl_cust * efuse_ctrl_std * elm @@ -730,6 +733,590 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { + .rev_offs = 0x0000, + .syss_offs = 0x0014, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class omap44xx_dss_hwmod_class = { + .name = "dss", + .sysc = &omap44xx_dss_sysc, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { + &omap44xx_dss__l3_main_1, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { + { + .pa_start = 0x58000000, + .pa_end = 0x5800007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dss_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs), + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { + { + .pa_start = 0x48040000, + .pa_end = 0x4804007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> dss */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs), + .user = OCP_USER_MPU, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { + &omap44xx_l3_main_2__dss, + &omap44xx_l4_per__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_sys_clk" }, + { .role = "tv_clk", .clk = "dss_tv_clk" }, + { .role = "dss_clk", .clk = "dss_dss_clk" }, + { .role = "video_clk", .clk = "dss_48mhz_clk" }, +}; + +static struct omap_hwmod omap44xx_dss_hwmod = { + .name = "dss_core", + .class = &omap44xx_dss_hwmod_class, + .main_clk = "dss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap44xx_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), + .masters = omap44xx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap44xx_dispc_sysc, +}; + +/* dss_dispc */ +static struct omap_hwmod omap44xx_dss_dispc_hwmod; +static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { + { .irq = 25 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { + { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { + { + .pa_start = 0x58001000, + .pa_end = 0x58001fff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dss_dispc_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs), + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { + { + .pa_start = 0x48041000, + .pa_end = 0x48041fff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> dss_dispc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dispc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs), + .user = OCP_USER_MPU, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { + &omap44xx_l3_main_2__dss_dispc, + &omap44xx_l4_per__dss_dispc, +}; + +static struct omap_hwmod omap44xx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap44xx_dispc_hwmod_class, + .mpu_irqs = omap44xx_dss_dispc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs), + .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), + .main_clk = "dss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, + .slaves = omap44xx_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'dsi' class + * display serial interface controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { + .name = "dsi", + .sysc = &omap44xx_dsi_sysc, +}; + +/* dss_dsi1 */ +static struct omap_hwmod omap44xx_dss_dsi1_hwmod; +static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { + { .irq = 53 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { + { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { + { + .pa_start = 0x58004000, + .pa_end = 0x580041ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dss_dsi1_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs), + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { + { + .pa_start = 0x48044000, + .pa_end = 0x480441ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs), + .user = OCP_USER_MPU, +}; + +/* dss_dsi1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { + &omap44xx_l3_main_2__dss_dsi1, + &omap44xx_l4_per__dss_dsi1, +}; + +static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { + .name = "dss_dsi1", + .class = &omap44xx_dsi_hwmod_class, + .mpu_irqs = omap44xx_dss_dsi1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs), + .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), + .main_clk = "dss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, + .slaves = omap44xx_dss_dsi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* dss_dsi2 */ +static struct omap_hwmod omap44xx_dss_dsi2_hwmod; +static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { + { .irq = 84 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { + { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { + { + .pa_start = 0x58005000, + .pa_end = 0x580051ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dss_dsi2_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs), + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { + { + .pa_start = 0x48045000, + .pa_end = 0x480451ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> dss_dsi2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_dsi2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_dsi2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs), + .user = OCP_USER_MPU, +}; + +/* dss_dsi2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { + &omap44xx_l3_main_2__dss_dsi2, + &omap44xx_l4_per__dss_dsi2, +}; + +static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { + .name = "dss_dsi2", + .class = &omap44xx_dsi_hwmod_class, + .mpu_irqs = omap44xx_dss_dsi2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs), + .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), + .main_clk = "dss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, + .slaves = omap44xx_dss_dsi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'hdmi' class + * hdmi controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { + .name = "hdmi", + .sysc = &omap44xx_hdmi_sysc, +}; + +/* dss_hdmi */ +static struct omap_hwmod omap44xx_dss_hdmi_hwmod; +static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { + { .irq = 101 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { + { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { + { + .pa_start = 0x58006000, + .pa_end = 0x58006fff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dss_hdmi_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs), + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { + { + .pa_start = 0x48046000, + .pa_end = 0x48046fff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> dss_hdmi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_hdmi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_hdmi_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs), + .user = OCP_USER_MPU, +}; + +/* dss_hdmi slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { + &omap44xx_l3_main_2__dss_hdmi, + &omap44xx_l4_per__dss_hdmi, +}; + +static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { + .name = "dss_hdmi", + .class = &omap44xx_hdmi_hwmod_class, + .mpu_irqs = omap44xx_dss_hdmi_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs), + .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), + .main_clk = "dss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, + .slaves = omap44xx_dss_hdmi_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap44xx_rfbi_sysc, +}; + +/* dss_rfbi */ +static struct omap_hwmod omap44xx_dss_rfbi_hwmod; +static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { + { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { + { + .pa_start = 0x58002000, + .pa_end = 0x580020ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dss_rfbi_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs), + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48042000, + .pa_end = 0x480420ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_rfbi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs), + .user = OCP_USER_MPU, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { + &omap44xx_l3_main_2__dss_rfbi, + &omap44xx_l4_per__dss_rfbi, +}; + +static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap44xx_rfbi_hwmod_class, + .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs), + .main_clk = "dss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, + .slaves = omap44xx_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap44xx_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod omap44xx_dss_venc_hwmod; +static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { + { + .pa_start = 0x58003000, + .pa_end = 0x580030ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_dss_venc_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs), + .user = OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { + { + .pa_start = 0x48043000, + .pa_end = 0x480430ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> dss_venc */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_dss_venc_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs), + .user = OCP_USER_MPU, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { + &omap44xx_l3_main_2__dss_venc, + &omap44xx_l4_per__dss_venc, +}; + +static struct omap_hwmod omap44xx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap44xx_venc_hwmod_class, + .main_clk = "dss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + }, + }, + .slaves = omap44xx_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'gpio' class * general purpose io module @@ -2924,6 +3511,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_dsp_hwmod, &omap44xx_dsp_c0_hwmod, + /* dss class */ + &omap44xx_dss_hwmod, + &omap44xx_dss_dispc_hwmod, + &omap44xx_dss_dsi1_hwmod, + &omap44xx_dss_dsi2_hwmod, + &omap44xx_dss_hdmi_hwmod, + &omap44xx_dss_rfbi_hwmod, + &omap44xx_dss_venc_hwmod, + /* gpio class */ &omap44xx_gpio1_hwmod, &omap44xx_gpio2_hwmod, -- cgit v1.2.3-70-g09d2 From ec5df927a8f3d3eca9514c9a9ad6db830ae20acc Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 2 Feb 2011 19:27:21 +0000 Subject: OMAP4: hwmod data: Add mailbox Mailbox hwmod data for omap4. Signed-off-by: Benoit Cousson Signed-off-by: Omar Ramirez Luna [b-cousson@ti.com: Re-order the structures and remove the irq line name] --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 68 +++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index aafe60dc711..efdf26655b4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -530,7 +530,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * ipu * iss * kbd - * mailbox * mcasp * mcbsp1 * mcbsp2 @@ -2005,6 +2004,70 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors using a + * queued mailbox-interrupt mechanism. + */ + +static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap44xx_mailbox_sysc, +}; + +/* mailbox */ +static struct omap_hwmod omap44xx_mailbox_hwmod; +static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { + { .irq = 26 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { + { + .pa_start = 0x4a0f4000, + .pa_end = 0x4a0f41ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_cfg -> mailbox */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_mailbox_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mailbox_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { + &omap44xx_l4_cfg__mailbox, +}; + +static struct omap_hwmod omap44xx_mailbox_hwmod = { + .name = "mailbox", + .class = &omap44xx_mailbox_hwmod_class, + .mpu_irqs = omap44xx_mailbox_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs), + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, + }, + }, + .slaves = omap44xx_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'mcspi' class * multichannel serial port interface (mcspi) / master/slave synchronous serial @@ -3539,6 +3602,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_iva_seq0_hwmod, &omap44xx_iva_seq1_hwmod, + /* mailbox class */ + &omap44xx_mailbox_hwmod, + /* mcspi class */ &omap44xx_mcspi1_hwmod, &omap44xx_mcspi2_hwmod, -- cgit v1.2.3-70-g09d2 From 8ca476da04e452a01d984dd5b5333b3a562207a7 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 25 Jan 2011 22:01:00 +0000 Subject: OMAP4: hwmod data: Add DMIC Add HWMOD entries for the OMAP DMIC. The HWMOD entires define the system resource requirements for the driver such as DMA addresses, channels, and IRQ's. Placing this information in the HWMOD database allows for more generic drivers to be written and having the specific implementation details defined in HWMOD. Signed-off-by: Benoit Cousson Signed-off-by: David Lambert [b-cousson@ti.com: Change the wrong hwmod name, add missing flag and re-order structures] --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 94 +++++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index efdf26655b4..1488438e4b0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -516,7 +516,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * ctrl_module_pad_wkup * ctrl_module_wkup * debugss - * dmic * efuse_ctrl_cust * efuse_ctrl_std * elm @@ -647,6 +646,96 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'dmic' class + * digital microphone controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { + .name = "dmic", + .sysc = &omap44xx_dmic_sysc, +}; + +/* dmic */ +static struct omap_hwmod omap44xx_dmic_hwmod; +static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { + { .irq = 114 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { + { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { + { + .pa_start = 0x4012e000, + .pa_end = 0x4012e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> dmic */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { + { + .pa_start = 0x4902e000, + .pa_end = 0x4902e07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> dmic (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_dmic_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_dmic_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* dmic slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { + &omap44xx_l4_abe__dmic, + &omap44xx_l4_abe__dmic_dma, +}; + +static struct omap_hwmod omap44xx_dmic_hwmod = { + .name = "dmic", + .class = &omap44xx_dmic_hwmod_class, + .mpu_irqs = omap44xx_dmic_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs), + .sdma_reqs = omap44xx_dmic_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs), + .main_clk = "dmic_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, + }, + }, + .slaves = omap44xx_dmic_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'dsp' class * dsp sub-system @@ -3570,6 +3659,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* dma class */ &omap44xx_dma_system_hwmod, + /* dmic class */ + &omap44xx_dmic_hwmod, + /* dsp class */ &omap44xx_dsp_hwmod, &omap44xx_dsp_c0_hwmod, -- cgit v1.2.3-70-g09d2 From 4ddff4932b31b8f21d1c57155ca5d4088693ce4b Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 31 Jan 2011 14:50:30 +0000 Subject: OMAP4: hwmod data: Add McBSP Add mcbsp data including a revision member in hwmod_class in order to provide mcbsp revision information in different omap. Signed-off-by: Benoit Cousson Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Charulatha V [b-cousson@ti.com: Remove the mcbsp4 memory name, re-order properly the structures] --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 293 ++++++++++++++++++++++++++++- 1 file changed, 289 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 1488438e4b0..f108614f02f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -530,10 +530,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * iss * kbd * mcasp - * mcbsp1 - * mcbsp2 - * mcbsp3 - * mcbsp4 * mcpdm * mmc1 * mmc2 @@ -2157,6 +2153,289 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap44xx_mcbsp_sysc, +}; + +/* mcbsp1 */ +static struct omap_hwmod omap44xx_mcbsp1_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { + { .irq = 17 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { + { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { + { + .pa_start = 0x40122000, + .pa_end = 0x401220ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { + { + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp1 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { + &omap44xx_l4_abe__mcbsp1, + &omap44xx_l4_abe__mcbsp1_dma, +}; + +static struct omap_hwmod omap44xx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs), + .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcbsp2 */ +static struct omap_hwmod omap44xx_mcbsp2_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { + { .irq = 22 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { + { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { + { + .pa_start = 0x40124000, + .pa_end = 0x401240ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { + { + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp2 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { + &omap44xx_l4_abe__mcbsp2, + &omap44xx_l4_abe__mcbsp2_dma, +}; + +static struct omap_hwmod omap44xx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs), + .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcbsp3 */ +static struct omap_hwmod omap44xx_mcbsp3_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { + { .irq = 23 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { + { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { + { + .pa_start = 0x40126000, + .pa_end = 0x401260ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { + { + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { + &omap44xx_l4_abe__mcbsp3, + &omap44xx_l4_abe__mcbsp3_dma, +}; + +static struct omap_hwmod omap44xx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs), + .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcbsp4 */ +static struct omap_hwmod omap44xx_mcbsp4_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { + { .irq = 16 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { + { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { + { + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcbsp4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcbsp4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { + &omap44xx_l4_per__mcbsp4, +}; + +static struct omap_hwmod omap44xx_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs), + .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs), + .main_clk = "mcbsp4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'mcspi' class * multichannel serial port interface (mcspi) / master/slave synchronous serial @@ -3697,6 +3976,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* mailbox class */ &omap44xx_mailbox_hwmod, + /* mcbsp class */ + &omap44xx_mcbsp1_hwmod, + &omap44xx_mcbsp2_hwmod, + &omap44xx_mcbsp3_hwmod, + &omap44xx_mcbsp4_hwmod, + /* mcspi class */ &omap44xx_mcspi1_hwmod, &omap44xx_mcspi2_hwmod, -- cgit v1.2.3-70-g09d2 From 407a6888f7362cb3dabe69ea6d9dcf3c750dc56a Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 15 Feb 2011 22:39:48 +0100 Subject: OMAP4: hwmod data: Add AESS, McPDM, bandgap, counter_32k, MMC, KBD, ISS & IPU Add more hwmod structures but keep them commented out for the moment until the driver adaptation to hwmod / omap_device is done. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1009 +++++++++++++++++++++++++++- 1 file changed, 993 insertions(+), 16 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index f108614f02f..989bc967043 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -40,11 +40,15 @@ #define OMAP44XX_DMA_REQ_START 1 /* Backward references (IPs with Bus Master capability) */ +static struct omap_hwmod omap44xx_aess_hwmod; static struct omap_hwmod omap44xx_dma_system_hwmod; static struct omap_hwmod omap44xx_dmm_hwmod; static struct omap_hwmod omap44xx_dsp_hwmod; static struct omap_hwmod omap44xx_dss_hwmod; static struct omap_hwmod omap44xx_emif_fw_hwmod; +static struct omap_hwmod omap44xx_hsi_hwmod; +static struct omap_hwmod omap44xx_ipu_hwmod; +static struct omap_hwmod omap44xx_iss_hwmod; static struct omap_hwmod omap44xx_iva_hwmod; static struct omap_hwmod omap44xx_l3_instr_hwmod; static struct omap_hwmod omap44xx_l3_main_1_hwmod; @@ -54,6 +58,8 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod; static struct omap_hwmod omap44xx_l4_cfg_hwmod; static struct omap_hwmod omap44xx_l4_per_hwmod; static struct omap_hwmod omap44xx_l4_wkup_hwmod; +static struct omap_hwmod omap44xx_mmc1_hwmod; +static struct omap_hwmod omap44xx_mmc2_hwmod; static struct omap_hwmod omap44xx_mpu_hwmod; static struct omap_hwmod omap44xx_mpu_private_hwmod; @@ -238,6 +244,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* mmc1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { + .master = &omap44xx_mmc1_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { + .master = &omap44xx_mmc2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* mpu -> l3_main_1 */ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { .master = &omap44xx_mpu_hwmod, @@ -252,6 +274,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { &omap44xx_dss__l3_main_1, &omap44xx_l3_main_2__l3_main_1, &omap44xx_l4_cfg__l3_main_1, + &omap44xx_mmc1__l3_main_1, + &omap44xx_mmc2__l3_main_1, &omap44xx_mpu__l3_main_1, }; @@ -272,6 +296,30 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* hsi -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { + .master = &omap44xx_hsi_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { + .master = &omap44xx_ipu_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iss -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { + .master = &omap44xx_iss_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* iva -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { .master = &omap44xx_iva_hwmod, @@ -299,6 +347,9 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { /* l3_main_2 slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { &omap44xx_dma_system__l3_main_2, + &omap44xx_hsi__l3_main_2, + &omap44xx_ipu__l3_main_2, + &omap44xx_iss__l3_main_2, &omap44xx_iva__l3_main_2, &omap44xx_l3_main_1__l3_main_2, &omap44xx_l4_cfg__l3_main_2, @@ -361,6 +412,14 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { }; /* l4_abe interface data */ +/* aess -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { + .master = &omap44xx_aess_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* dsp -> l4_abe */ static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { .master = &omap44xx_dsp_hwmod, @@ -387,6 +446,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { /* l4_abe slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { + &omap44xx_aess__l4_abe, &omap44xx_dsp__l4_abe, &omap44xx_l3_main_1__l4_abe, &omap44xx_mpu__l4_abe, @@ -504,13 +564,10 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * - They still need to be validated with the driver * properly adapted to omap_hwmod / omap_device * - * aess - * bandgap * c2c * c2c_target_fw * cm_core * cm_core_aon - * counter_32k * ctrl_module_core * ctrl_module_pad_core * ctrl_module_pad_wkup @@ -526,22 +583,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * gpu * hdq1w * hsi - * ipu - * iss - * kbd - * mcasp - * mcpdm - * mmc1 - * mmc2 - * mmc3 - * mmc4 - * mmc5 - * mpu_c0 - * mpu_c1 * ocmc_ram * ocp2scp_usb_phy * ocp_wp_noc - * prcm * prcm_mpu * prm * scrm @@ -556,6 +600,194 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * usim */ +/* + * 'aess' class + * audio engine sub system + */ + +static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_aess_hwmod_class = { + .name = "aess", + .sysc = &omap44xx_aess_sysc, +}; + +/* aess */ +static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { + { .irq = 99 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { + { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, + { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, + { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, + { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, + { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, + { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, + { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, + { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, +}; + +/* aess master ports */ +static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { + &omap44xx_aess__l4_abe, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { + { + .pa_start = 0x401f1000, + .pa_end = 0x401f13ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> aess */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_aess_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_aess_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { + { + .pa_start = 0x490f1000, + .pa_end = 0x490f13ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> aess (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_aess_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_aess_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* aess slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { + &omap44xx_l4_abe__aess, + &omap44xx_l4_abe__aess_dma, +}; + +static struct omap_hwmod omap44xx_aess_hwmod = { + .name = "aess", + .class = &omap44xx_aess_hwmod_class, + .mpu_irqs = omap44xx_aess_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs), + .sdma_reqs = omap44xx_aess_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs), + .main_clk = "aess_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, + }, + }, + .slaves = omap44xx_aess_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), + .masters = omap44xx_aess_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'bandgap' class + * bangap reference for ldo regulators + */ + +static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { + .name = "bandgap", +}; + +/* bandgap */ +static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { + { .role = "fclk", .clk = "bandgap_fclk" }, +}; + +static struct omap_hwmod omap44xx_bandgap_hwmod = { + .name = "bandgap", + .class = &omap44xx_bandgap_hwmod_class, + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + }, + }, + .opt_clks = bandgap_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'counter' class + * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock + */ + +static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0004, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_counter_hwmod_class = { + .name = "counter", + .sysc = &omap44xx_counter_sysc, +}; + +/* counter_32k */ +static struct omap_hwmod omap44xx_counter_32k_hwmod; +static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { + { + .pa_start = 0x4a304000, + .pa_end = 0x4a30401f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_counter_32k_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_counter_32k_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* counter_32k slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { + &omap44xx_l4_wkup__counter_32k, +}; + +static struct omap_hwmod omap44xx_counter_32k_hwmod = { + .name = "counter_32k", + .class = &omap44xx_counter_hwmod_class, + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, + }, + }, + .slaves = omap44xx_counter_32k_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'dma' class * dma controller for data exchange between memory to memory (i.e. internal or @@ -1747,6 +1979,83 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'hsi' class + * mipi high-speed synchronous serial interface (multichannel and full-duplex + * serial if) + */ + +static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | + SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { + .name = "hsi", + .sysc = &omap44xx_hsi_sysc, +}; + +/* hsi */ +static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { + { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, + { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, + { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, +}; + +/* hsi master ports */ +static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { + &omap44xx_hsi__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { + { + .pa_start = 0x4a058000, + .pa_end = 0x4a05bfff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_cfg -> hsi */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_hsi_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_hsi_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* hsi slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { + &omap44xx_l4_cfg__hsi, +}; + +static struct omap_hwmod omap44xx_hsi_hwmod = { + .name = "hsi", + .class = &omap44xx_hsi_hwmod_class, + .mpu_irqs = omap44xx_hsi_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs), + .main_clk = "hsi_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, + }, + }, + .slaves = omap44xx_hsi_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), + .masters = omap44xx_hsi_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'i2c' class * multimaster high-speed i2c controller @@ -1980,6 +2289,188 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'ipu' class + * imaging processor unit + */ + +static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { + .name = "ipu", +}; + +/* ipu */ +static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { + { .irq = 100 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { + { .name = "cpu0", .rst_shift = 0 }, +}; + +static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { + { .name = "cpu1", .rst_shift = 1 }, +}; + +static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +/* ipu master ports */ +static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { + &omap44xx_ipu__l3_main_2, +}; + +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_ipu_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { + &omap44xx_l3_main_2__ipu, +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_ipu_c0_hwmod = { + .name = "ipu_c0", + .class = &omap44xx_ipu_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_ipu_c0_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), + .prcm = { + .omap4 = { + .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, + }, + }, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* Pseudo hwmod for reset control purpose only */ +static struct omap_hwmod omap44xx_ipu_c1_hwmod = { + .name = "ipu_c1", + .class = &omap44xx_ipu_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .rst_lines = omap44xx_ipu_c1_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), + .prcm = { + .omap4 = { + .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, + }, + }, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static struct omap_hwmod omap44xx_ipu_hwmod = { + .name = "ipu", + .class = &omap44xx_ipu_hwmod_class, + .mpu_irqs = omap44xx_ipu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs), + .rst_lines = omap44xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), + .main_clk = "ipu_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, + }, + }, + .slaves = omap44xx_ipu_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), + .masters = omap44xx_ipu_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'iss' class + * external images sensor pixel data processor + */ + +static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_iss_hwmod_class = { + .name = "iss", + .sysc = &omap44xx_iss_sysc, +}; + +/* iss */ +static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { + { .irq = 24 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { + { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, + { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, + { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, + { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, +}; + +/* iss master ports */ +static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { + &omap44xx_iss__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { + { + .pa_start = 0x52000000, + .pa_end = 0x520000ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> iss */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_iss_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_iss_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* iss slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { + &omap44xx_l3_main_2__iss, +}; + +static struct omap_hwmod_opt_clk iss_opt_clks[] = { + { .role = "ctrlclk", .clk = "iss_ctrlclk" }, +}; + +static struct omap_hwmod omap44xx_iss_hwmod = { + .name = "iss", + .class = &omap44xx_iss_hwmod_class, + .mpu_irqs = omap44xx_iss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs), + .sdma_reqs = omap44xx_iss_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs), + .main_clk = "iss_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, + }, + }, + .opt_clks = iss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), + .slaves = omap44xx_iss_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), + .masters = omap44xx_iss_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'iva' class * multi-standard video encoder/decoder hardware accelerator @@ -2089,6 +2580,73 @@ static struct omap_hwmod omap44xx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'kbd' class + * keyboard controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { + .name = "kbd", + .sysc = &omap44xx_kbd_sysc, +}; + +/* kbd */ +static struct omap_hwmod omap44xx_kbd_hwmod; +static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { + { .irq = 120 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { + { + .pa_start = 0x4a31c000, + .pa_end = 0x4a31c07f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> kbd */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_kbd_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_kbd_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* kbd slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { + &omap44xx_l4_wkup__kbd, +}; + +static struct omap_hwmod omap44xx_kbd_hwmod = { + .name = "kbd", + .class = &omap44xx_kbd_hwmod_class, + .mpu_irqs = omap44xx_kbd_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs), + .main_clk = "kbd_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, + }, + }, + .slaves = omap44xx_kbd_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'mailbox' class * mailbox module allowing communication between the on-chip processors using a @@ -2436,6 +2994,98 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'mcpdm' class + * multi channel pdm controller (proprietary interface with phoenix power + * ic) + */ + +static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { + .name = "mcpdm", + .sysc = &omap44xx_mcpdm_sysc, +}; + +/* mcpdm */ +static struct omap_hwmod omap44xx_mcpdm_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { + { .irq = 112 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { + { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, + { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { + { + .pa_start = 0x40132000, + .pa_end = 0x4013207f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcpdm */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x4903207f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcpdm (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcpdm_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcpdm_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* mcpdm slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { + &omap44xx_l4_abe__mcpdm, + &omap44xx_l4_abe__mcpdm_dma, +}; + +static struct omap_hwmod omap44xx_mcpdm_hwmod = { + .name = "mcpdm", + .class = &omap44xx_mcpdm_hwmod_class, + .mpu_irqs = omap44xx_mcpdm_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs), + .sdma_reqs = omap44xx_mcpdm_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs), + .main_clk = "mcpdm_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, + }, + }, + .slaves = omap44xx_mcpdm_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'mcspi' class * multichannel serial port interface (mcspi) / master/slave synchronous serial @@ -2675,6 +3325,300 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'mmc' class + * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { + .name = "mmc", + .sysc = &omap44xx_mmc_sysc, +}; + +/* mmc1 */ +static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { + { .irq = 83 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { + { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, +}; + +/* mmc1 master ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { + &omap44xx_mmc1__l3_main_1, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c3ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mmc1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { + &omap44xx_l4_per__mmc1, +}; + +static struct omap_hwmod omap44xx_mmc1_hwmod = { + .name = "mmc1", + .class = &omap44xx_mmc_hwmod_class, + .mpu_irqs = omap44xx_mmc1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs), + .sdma_reqs = omap44xx_mmc1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs), + .main_clk = "mmc1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, + }, + }, + .slaves = omap44xx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), + .masters = omap44xx_mmc1_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mmc2 */ +static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { + { .irq = 86 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { + { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, +}; + +/* mmc2 master ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { + &omap44xx_mmc2__l3_main_1, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b43ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mmc2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { + &omap44xx_l4_per__mmc2, +}; + +static struct omap_hwmod omap44xx_mmc2_hwmod = { + .name = "mmc2", + .class = &omap44xx_mmc_hwmod_class, + .mpu_irqs = omap44xx_mmc2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs), + .sdma_reqs = omap44xx_mmc2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs), + .main_clk = "mmc2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, + }, + }, + .slaves = omap44xx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), + .masters = omap44xx_mmc2_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mmc3 */ +static struct omap_hwmod omap44xx_mmc3_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { + { .irq = 94 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { + { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad3ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mmc3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { + &omap44xx_l4_per__mmc3, +}; + +static struct omap_hwmod omap44xx_mmc3_hwmod = { + .name = "mmc3", + .class = &omap44xx_mmc_hwmod_class, + .mpu_irqs = omap44xx_mmc3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs), + .sdma_reqs = omap44xx_mmc3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs), + .main_clk = "mmc3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, + }, + }, + .slaves = omap44xx_mmc3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mmc4 */ +static struct omap_hwmod omap44xx_mmc4_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { + { .irq = 96 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { + { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { + { + .pa_start = 0x480d1000, + .pa_end = 0x480d13ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mmc4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { + &omap44xx_l4_per__mmc4, +}; + +static struct omap_hwmod omap44xx_mmc4_hwmod = { + .name = "mmc4", + .class = &omap44xx_mmc_hwmod_class, + .mpu_irqs = omap44xx_mmc4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs), + .sdma_reqs = omap44xx_mmc4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs), + .main_clk = "mmc4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, + }, + }, + .slaves = omap44xx_mmc4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mmc5 */ +static struct omap_hwmod omap44xx_mmc5_hwmod; +static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { + { .irq = 59 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { + { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { + { + .pa_start = 0x480d5000, + .pa_end = 0x480d53ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mmc5 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mmc5_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mmc5_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mmc5 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { + &omap44xx_l4_per__mmc5, +}; + +static struct omap_hwmod omap44xx_mmc5_hwmod = { + .name = "mmc5", + .class = &omap44xx_mmc_hwmod_class, + .mpu_irqs = omap44xx_mmc5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs), + .sdma_reqs = omap44xx_mmc5_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs), + .main_clk = "mmc5_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, + }, + }, + .slaves = omap44xx_mmc5_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'mpu' class * mpu sub-system @@ -3935,6 +4879,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* mpu_bus class */ &omap44xx_mpu_private_hwmod, + /* aess class */ +/* &omap44xx_aess_hwmod, */ + + /* bandgap class */ + &omap44xx_bandgap_hwmod, + + /* counter class */ +/* &omap44xx_counter_32k_hwmod, */ + /* dma class */ &omap44xx_dma_system_hwmod, @@ -3962,17 +4915,31 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_gpio5_hwmod, &omap44xx_gpio6_hwmod, + /* hsi class */ +/* &omap44xx_hsi_hwmod, */ + /* i2c class */ &omap44xx_i2c1_hwmod, &omap44xx_i2c2_hwmod, &omap44xx_i2c3_hwmod, &omap44xx_i2c4_hwmod, + /* ipu class */ + &omap44xx_ipu_hwmod, + &omap44xx_ipu_c0_hwmod, + &omap44xx_ipu_c1_hwmod, + + /* iss class */ +/* &omap44xx_iss_hwmod, */ + /* iva class */ &omap44xx_iva_hwmod, &omap44xx_iva_seq0_hwmod, &omap44xx_iva_seq1_hwmod, + /* kbd class */ +/* &omap44xx_kbd_hwmod, */ + /* mailbox class */ &omap44xx_mailbox_hwmod, @@ -3982,12 +4949,22 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_mcbsp3_hwmod, &omap44xx_mcbsp4_hwmod, + /* mcpdm class */ +/* &omap44xx_mcpdm_hwmod, */ + /* mcspi class */ &omap44xx_mcspi1_hwmod, &omap44xx_mcspi2_hwmod, &omap44xx_mcspi3_hwmod, &omap44xx_mcspi4_hwmod, + /* mmc class */ +/* &omap44xx_mmc1_hwmod, */ +/* &omap44xx_mmc2_hwmod, */ +/* &omap44xx_mmc3_hwmod, */ +/* &omap44xx_mmc4_hwmod, */ +/* &omap44xx_mmc5_hwmod, */ + /* mpu class */ &omap44xx_mpu_hwmod, -- cgit v1.2.3-70-g09d2 From 5844c4ead25f53a1fa92a4a8f0e363f9b6b87aea Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Thu, 17 Feb 2011 12:41:05 +0000 Subject: OMAP4: hwmod data: Add USBOTG OMAP4 hwmod data structures are populated with base address, L3 and L4 interface clocks, IRQs and sysconfig register details. As per OMAP USBOTG specification, need to configure the USBOTG to smart idle/standby or no idle/standby during data transfer and force idle/standby when not in use to support retention and offmode. By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags,framework will take care of configuring to no idle/standby when module is enabled and force idle/standby when idled. Signed-off-by: Cousson, Benoit Signed-off-by: Hema HK Cc: Tony Lindgren Cc: Kevin Hilman Cc: Paul Walmsley Signed-off-by: Felipe Balbi [b-cousson@ti.com: Fix position, opt_clk, and author] --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 96 +++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 989bc967043..84e795cf064 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -62,6 +62,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod; static struct omap_hwmod omap44xx_mmc2_hwmod; static struct omap_hwmod omap44xx_mpu_hwmod; static struct omap_hwmod omap44xx_mpu_private_hwmod; +static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; /* * Interconnects omap_hwmod structures @@ -344,6 +345,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* usb_otg_hs -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { + .master = &omap44xx_usb_otg_hs_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 slave ports */ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { &omap44xx_dma_system__l3_main_2, @@ -353,6 +362,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { &omap44xx_iva__l3_main_2, &omap44xx_l3_main_1__l3_main_2, &omap44xx_l4_cfg__l3_main_2, + &omap44xx_usb_otg_hs__l3_main_2, }; static struct omap_hwmod omap44xx_l3_main_2_hwmod = { @@ -594,7 +604,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * slimbus2 * usb_host_fs * usb_host_hs - * usb_otg_hs * usb_phy_cm * usb_tll_hs * usim @@ -4724,6 +4733,88 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'usb_otg_hs' class + * high-speed on-the-go universal serial bus (usb_otg_hs) controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { + .rev_offs = 0x0400, + .sysc_offs = 0x0404, + .syss_offs = 0x0408, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { + .name = "usb_otg_hs", + .sysc = &omap44xx_usb_otg_hs_sysc, +}; + +/* usb_otg_hs */ +static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { + { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, + { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, +}; + +/* usb_otg_hs master ports */ +static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { + &omap44xx_usb_otg_hs__l3_main_2, +}; + +static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { + { + .pa_start = 0x4a0ab000, + .pa_end = 0x4a0ab003, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_cfg -> usb_otg_hs */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_usb_otg_hs_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_usb_otg_hs_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* usb_otg_hs slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { + &omap44xx_l4_cfg__usb_otg_hs, +}; + +static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { + { .role = "xclk", .clk = "usb_otg_hs_xclk" }, +}; + +static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { + .name = "usb_otg_hs", + .class = &omap44xx_usb_otg_hs_hwmod_class, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .mpu_irqs = omap44xx_usb_otg_hs_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs), + .main_clk = "usb_otg_hs_ick", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + }, + }, + .opt_clks = usb_otg_hs_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), + .slaves = omap44xx_usb_otg_hs_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), + .masters = omap44xx_usb_otg_hs_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'wd_timer' class * 32-bit watchdog upward counter that generates a pulse on the reset pin on @@ -4995,6 +5086,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_uart3_hwmod, &omap44xx_uart4_hwmod, + /* usb_otg_hs class */ + &omap44xx_usb_otg_hs_hwmod, + /* wd_timer class */ &omap44xx_wd_timer2_hwmod, &omap44xx_wd_timer3_hwmod, -- cgit v1.2.3-70-g09d2 From 7bb412a64281c599dcf00af2eed61ea997b282c2 Mon Sep 17 00:00:00 2001 From: Simon Que Date: Thu, 17 Feb 2011 09:52:03 -0800 Subject: omap: add hwspinlock device Build and register an hwspinlock platform device. Although only OMAP4 supports the hardware spinlock module (for now), it is still safe to run this initcall on all omaps, because hwmod lookup will simply fail on hwspinlock-less platforms. Signed-off-by: Simon Que Signed-off-by: Hari Kanigeri Signed-off-by: Ohad Ben-Cohen Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/hwspinlock.c | 63 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 arch/arm/mach-omap2/hwspinlock.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index a9e3974d015..ec24999eefe 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -243,3 +243,4 @@ obj-y += $(smc91x-m) $(smc91x-y) smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o obj-y += $(smsc911x-m) $(smsc911x-y) +obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c new file mode 100644 index 00000000000..06d4a80660a --- /dev/null +++ b/arch/arm/mach-omap2/hwspinlock.c @@ -0,0 +1,63 @@ +/* + * OMAP hardware spinlock device initialization + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com + * + * Contact: Simon Que + * Hari Kanigeri + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include + +#include +#include + +struct omap_device_pm_latency omap_spinlock_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + } +}; + +int __init hwspinlocks_init(void) +{ + int retval = 0; + struct omap_hwmod *oh; + struct omap_device *od; + const char *oh_name = "spinlock"; + const char *dev_name = "omap_hwspinlock"; + + /* + * Hwmod lookup will fail in case our platform doesn't support the + * hardware spinlock module, so it is safe to run this initcall + * on all omaps + */ + oh = omap_hwmod_lookup(oh_name); + if (oh == NULL) + return -EINVAL; + + od = omap_device_build(dev_name, 0, oh, NULL, 0, + omap_spinlock_latency, + ARRAY_SIZE(omap_spinlock_latency), false); + if (IS_ERR(od)) { + pr_err("Can't build omap_device for %s:%s\n", dev_name, + oh_name); + retval = PTR_ERR(od); + } + + return retval; +} +/* early board code might need to reserve specific hwspinlock instances */ +postcore_initcall(hwspinlocks_init); -- cgit v1.2.3-70-g09d2 From 617871deacea4e1a5713dd37564dc94a392d80c3 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 17 Feb 2011 09:53:09 -0800 Subject: OMAP2420: hwmod data: Add McSPI Update the omap2420 hwmod data with the McSPI info. Add a device attribute structure which will be used for passing number of chipselects from hwmod data. Add revision macros to be passed from rev field from hwmod. Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Grant Likely Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 156 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcspi.h | 8 ++ 2 files changed, 164 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index b85c630b64d..7fffd340c76 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -44,6 +45,8 @@ static struct omap_hwmod omap2420_gpio2_hwmod; static struct omap_hwmod omap2420_gpio3_hwmod; static struct omap_hwmod omap2420_gpio4_hwmod; static struct omap_hwmod omap2420_dma_system_hwmod; +static struct omap_hwmod omap2420_mcspi1_hwmod; +static struct omap_hwmod omap2420_mcspi2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -88,6 +91,42 @@ static struct omap_hwmod omap2420_uart3_hwmod; static struct omap_hwmod omap2420_i2c1_hwmod; static struct omap_hwmod omap2420_i2c2_hwmod; +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480980ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2420_mcspi1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a0ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2420_mcspi2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { .master = &omap2420_l4_core_hwmod, @@ -864,6 +903,119 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_mcspi_class = { + .name = "mcspi", + .sysc = &omap2420_mcspi_sysc, + .rev = OMAP2_MCSPI_REV, +}; + +/* mcspi1 */ +static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { + { .irq = 65 }, +}; + +static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { + { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ + { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ + { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ + { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ + { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ + { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ + { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ + { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { + &omap2420_l4_core__mcspi1, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap2420_mcspi1_hwmod = { + .name = "mcspi1_hwmod", + .mpu_irqs = omap2420_mcspi1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), + .sdma_reqs = omap2420_mcspi1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .slaves = omap2420_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), + .class = &omap2420_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* mcspi2 */ +static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { + { .irq = 66 }, +}; + +static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { + { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ + { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ + { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ + { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { + &omap2420_l4_core__mcspi2, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2420_mcspi2_hwmod = { + .name = "mcspi2_hwmod", + .mpu_irqs = omap2420_mcspi2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), + .sdma_reqs = omap2420_mcspi2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .slaves = omap2420_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), + .class = &omap2420_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, @@ -885,6 +1037,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { /* dma_system class*/ &omap2420_dma_system_hwmod, + + /* mcspi class */ + &omap2420_mcspi1_hwmod, + &omap2420_mcspi2_hwmod, NULL, }; diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h index 1254e4945b6..560e266da8a 100644 --- a/arch/arm/plat-omap/include/plat/mcspi.h +++ b/arch/arm/plat-omap/include/plat/mcspi.h @@ -1,10 +1,18 @@ #ifndef _OMAP2_MCSPI_H #define _OMAP2_MCSPI_H +#define OMAP2_MCSPI_REV 0 +#define OMAP3_MCSPI_REV 1 +#define OMAP4_MCSPI_REV 2 + struct omap2_mcspi_platform_config { unsigned short num_cs; }; +struct omap2_mcspi_dev_attr { + unsigned short num_chipselect; +}; + struct omap2_mcspi_device_config { unsigned turbo_mode:1; -- cgit v1.2.3-70-g09d2 From 7f904c78d65e5cff8d9e76567797a7a7fe2fd774 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 17 Feb 2011 09:53:10 -0800 Subject: OMAP2430: hwmod data: Add McSPI Update the 2430 hwmod data file with McSPI info. Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Grant Likely Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 219 +++++++++++++++++++++++++++++ 1 file changed, 219 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 8ecfbcde13b..60fe4aac1f5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -45,6 +46,9 @@ static struct omap_hwmod omap2430_gpio3_hwmod; static struct omap_hwmod omap2430_gpio4_hwmod; static struct omap_hwmod omap2430_gpio5_hwmod; static struct omap_hwmod omap2430_dma_system_hwmod; +static struct omap_hwmod omap2430_mcspi1_hwmod; +static struct omap_hwmod omap2430_mcspi2_hwmod; +static struct omap_hwmod omap2430_mcspi3_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -223,6 +227,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { }; +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480980ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2430_mcspi1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a0ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2430_mcspi2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = { + { + .pa_start = 0x480b8000, + .pa_end = 0x480b80ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcspi3_hwmod, + .clk = "mcspi3_ick", + .addr = omap2430_mcspi3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* L4 WKUP */ static struct omap_hwmod omap2430_l4_wkup_hwmod = { .name = "l4_wkup", @@ -919,6 +977,162 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mcspi_class = { + .name = "mcspi", + .sysc = &omap2430_mcspi_sysc, + .rev = OMAP2_MCSPI_REV, +}; + +/* mcspi1 */ +static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { + { .irq = 65 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { + { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ + { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ + { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ + { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ + { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ + { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ + { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ + { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { + &omap2430_l4_core__mcspi1, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap2430_mcspi1_hwmod = { + .name = "mcspi1_hwmod", + .mpu_irqs = omap2430_mcspi1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), + .sdma_reqs = omap2430_mcspi1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .slaves = omap2430_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), + .class = &omap2430_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcspi2 */ +static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { + { .irq = 66 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { + { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ + { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ + { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ + { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { + &omap2430_l4_core__mcspi2, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2430_mcspi2_hwmod = { + .name = "mcspi2_hwmod", + .mpu_irqs = omap2430_mcspi2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), + .sdma_reqs = omap2430_mcspi2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .slaves = omap2430_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), + .class = &omap2430_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcspi3 */ +static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { + { .irq = 91 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { + { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ + { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ + { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ + { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ +}; + +static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { + &omap2430_l4_core__mcspi3, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2430_mcspi3_hwmod = { + .name = "mcspi3_hwmod", + .mpu_irqs = omap2430_mcspi3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), + .sdma_reqs = omap2430_mcspi3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), + .main_clk = "mcspi3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MCSPI3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, + }, + }, + .slaves = omap2430_mcspi3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), + .class = &omap2430_mcspi_class, + .dev_attr = &omap_mcspi3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, @@ -941,6 +1155,11 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { /* dma_system class*/ &omap2430_dma_system_hwmod, + + /* mcspi class */ + &omap2430_mcspi1_hwmod, + &omap2430_mcspi2_hwmod, + &omap2430_mcspi3_hwmod, NULL, }; -- cgit v1.2.3-70-g09d2 From 0f616a4e17ea244f882056656964b792edde8364 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 17 Feb 2011 09:53:10 -0800 Subject: OMAP3: hwmod data: Add McSPI Update omap3 hwmod data file with McSPI info. Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Grant Likely Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 280 +++++++++++++++++++++++++++++ 1 file changed, 280 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 8d8181334f8..800eda4adb5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -55,6 +56,10 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod; static struct omap_hwmod omap3xxx_gpio6_hwmod; static struct omap_hwmod omap34xx_sr1_hwmod; static struct omap_hwmod omap34xx_sr2_hwmod; +static struct omap_hwmod omap34xx_mcspi1; +static struct omap_hwmod omap34xx_mcspi2; +static struct omap_hwmod omap34xx_mcspi3; +static struct omap_hwmod omap34xx_mcspi4; static struct omap_hwmod omap3xxx_dma_system_hwmod; @@ -1356,6 +1361,275 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480980ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi1, + .clk = "mcspi1_ick", + .addr = omap34xx_mcspi1_addr_space, + .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a0ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi2, + .clk = "mcspi2_ick", + .addr = omap34xx_mcspi2_addr_space, + .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi3 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = { + { + .pa_start = 0x480b8000, + .pa_end = 0x480b80ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi3, + .clk = "mcspi3_ick", + .addr = omap34xx_mcspi3_addr_space, + .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi4 interface */ +static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { + { + .pa_start = 0x480ba000, + .pa_end = 0x480ba0ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_mcspi4, + .clk = "mcspi4_ick", + .addr = omap34xx_mcspi4_addr_space, + .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap34xx_mcspi_class = { + .name = "mcspi", + .sysc = &omap34xx_mcspi_sysc, + .rev = OMAP3_MCSPI_REV, +}; + +/* mcspi1 */ +static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = { + { .name = "irq", .irq = 65 }, +}; + +static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = { + { .name = "tx0", .dma_req = 35 }, + { .name = "rx0", .dma_req = 36 }, + { .name = "tx1", .dma_req = 37 }, + { .name = "rx1", .dma_req = 38 }, + { .name = "tx2", .dma_req = 39 }, + { .name = "rx2", .dma_req = 40 }, + { .name = "tx3", .dma_req = 41 }, + { .name = "rx3", .dma_req = 42 }, +}; + +static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { + &omap34xx_l4_core__mcspi1, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap34xx_mcspi1 = { + .name = "mcspi1", + .mpu_irqs = omap34xx_mcspi1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), + .sdma_reqs = omap34xx_mcspi1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs), + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, + }, + }, + .slaves = omap34xx_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcspi2 */ +static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = { + { .name = "irq", .irq = 66 }, +}; + +static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = { + { .name = "tx0", .dma_req = 43 }, + { .name = "rx0", .dma_req = 44 }, + { .name = "tx1", .dma_req = 45 }, + { .name = "rx1", .dma_req = 46 }, +}; + +static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { + &omap34xx_l4_core__mcspi2, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap34xx_mcspi2 = { + .name = "mcspi2", + .mpu_irqs = omap34xx_mcspi2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), + .sdma_reqs = omap34xx_mcspi2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs), + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, + }, + }, + .slaves = omap34xx_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcspi3 */ +static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { + { .name = "irq", .irq = 91 }, /* 91 */ +}; + +static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { + { .name = "tx0", .dma_req = 15 }, + { .name = "rx0", .dma_req = 16 }, + { .name = "tx1", .dma_req = 23 }, + { .name = "rx1", .dma_req = 24 }, +}; + +static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { + &omap34xx_l4_core__mcspi3, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap34xx_mcspi3 = { + .name = "mcspi3", + .mpu_irqs = omap34xx_mcspi3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs), + .sdma_reqs = omap34xx_mcspi3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs), + .main_clk = "mcspi3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, + }, + }, + .slaves = omap34xx_mcspi3_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* SPI4 */ +static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { + { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ +}; + +static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { + { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ + { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ +}; + +static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { + &omap34xx_l4_core__mcspi4, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { + .num_chipselect = 1, +}; + +static struct omap_hwmod omap34xx_mcspi4 = { + .name = "mcspi4", + .mpu_irqs = omap34xx_mcspi4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs), + .sdma_reqs = omap34xx_mcspi4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs), + .main_clk = "mcspi4_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCSPI4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, + }, + }, + .slaves = omap34xx_mcspi4_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), + .class = &omap34xx_mcspi_class, + .dev_attr = &omap_mcspi4_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -1387,6 +1661,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { /* dma_system class*/ &omap3xxx_dma_system_hwmod, + + /* mcspi class */ + &omap34xx_mcspi1, + &omap34xx_mcspi2, + &omap34xx_mcspi3, + &omap34xx_mcspi4, NULL, }; -- cgit v1.2.3-70-g09d2 From 1a5d81905aec1536783fb6ab875f31910f449941 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Wed, 2 Feb 2011 17:52:14 +0530 Subject: OMAP: devices: Modify McSPI device to adapt to hwmod framework Cleans up all base address definitions for omap_mcspi and adapts the device registration and driver to hwmod framework. Changes involves: 1) Removing all base address macro defines. 2) Using omap-device layer to register device and utilizing data from hwmod data file for base address, dma channel number, Irq_number, device attribute(number of chipselect). 3) Appending base address with pdata reg_offset for omap4 boards. For omap4 all regs used in driver deviate with reg_offset_macros defined with an value of 0x100. So pass this offset through pdata and append the same to base address retrieved from hwmod data file and we are not mapping *_HL_* regs which are not used in driver. Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Grant Likely Reviewed-by: Partha Basak Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 187 +++++++------------------------- arch/arm/plat-omap/include/plat/mcspi.h | 3 + drivers/spi/omap2_mcspi.c | 112 +++++-------------- 3 files changed, 72 insertions(+), 230 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index e0f0ef952bc..71f099b85e7 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -279,163 +280,55 @@ static inline void omap_init_audio(void) {} #include -#define OMAP2_MCSPI1_BASE 0x48098000 -#define OMAP2_MCSPI2_BASE 0x4809a000 -#define OMAP2_MCSPI3_BASE 0x480b8000 -#define OMAP2_MCSPI4_BASE 0x480ba000 - -#define OMAP4_MCSPI1_BASE 0x48098100 -#define OMAP4_MCSPI2_BASE 0x4809a100 -#define OMAP4_MCSPI3_BASE 0x480b8100 -#define OMAP4_MCSPI4_BASE 0x480ba100 - -static struct omap2_mcspi_platform_config omap2_mcspi1_config = { - .num_cs = 4, -}; - -static struct resource omap2_mcspi1_resources[] = { - { - .start = OMAP2_MCSPI1_BASE, - .end = OMAP2_MCSPI1_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi1 = { - .name = "omap2_mcspi", - .id = 1, - .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), - .resource = omap2_mcspi1_resources, - .dev = { - .platform_data = &omap2_mcspi1_config, - }, -}; - -static struct omap2_mcspi_platform_config omap2_mcspi2_config = { - .num_cs = 2, -}; - -static struct resource omap2_mcspi2_resources[] = { - { - .start = OMAP2_MCSPI2_BASE, - .end = OMAP2_MCSPI2_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi2 = { - .name = "omap2_mcspi", - .id = 2, - .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), - .resource = omap2_mcspi2_resources, - .dev = { - .platform_data = &omap2_mcspi2_config, - }, -}; - -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) -static struct omap2_mcspi_platform_config omap2_mcspi3_config = { - .num_cs = 2, -}; - -static struct resource omap2_mcspi3_resources[] = { - { - .start = OMAP2_MCSPI3_BASE, - .end = OMAP2_MCSPI3_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi3 = { - .name = "omap2_mcspi", - .id = 3, - .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), - .resource = omap2_mcspi3_resources, - .dev = { - .platform_data = &omap2_mcspi3_config, - }, -}; -#endif - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -static struct omap2_mcspi_platform_config omap2_mcspi4_config = { - .num_cs = 1, -}; - -static struct resource omap2_mcspi4_resources[] = { - { - .start = OMAP2_MCSPI4_BASE, - .end = OMAP2_MCSPI4_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi4 = { - .name = "omap2_mcspi", - .id = 4, - .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), - .resource = omap2_mcspi4_resources, - .dev = { - .platform_data = &omap2_mcspi4_config, +struct omap_device_pm_latency omap_mcspi_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, }; -#endif -#ifdef CONFIG_ARCH_OMAP4 -static inline void omap4_mcspi_fixup(void) +static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) { - omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; - omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; - omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; - omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; - omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; - omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; - omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; - omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; -} -#else -static inline void omap4_mcspi_fixup(void) -{ -} -#endif + struct omap_device *od; + char *name = "omap2_mcspi"; + struct omap2_mcspi_platform_config *pdata; + static int spi_num; + struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + pr_err("Memory allocation for McSPI device failed\n"); + return -ENOMEM; + } -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) -static inline void omap2_mcspi3_init(void) -{ - platform_device_register(&omap2_mcspi3); -} -#else -static inline void omap2_mcspi3_init(void) -{ -} -#endif + pdata->num_cs = mcspi_attrib->num_chipselect; + switch (oh->class->rev) { + case OMAP2_MCSPI_REV: + case OMAP3_MCSPI_REV: + pdata->regs_offset = 0; + break; + case OMAP4_MCSPI_REV: + pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; + break; + default: + pr_err("Invalid McSPI Revision value\n"); + return -EINVAL; + } -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -static inline void omap2_mcspi4_init(void) -{ - platform_device_register(&omap2_mcspi4); -} -#else -static inline void omap2_mcspi4_init(void) -{ + spi_num++; + od = omap_device_build(name, spi_num, oh, pdata, + sizeof(*pdata), omap_mcspi_latency, + ARRAY_SIZE(omap_mcspi_latency), 0); + WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", + name, oh->name); + kfree(pdata); + return 0; } -#endif static void omap_init_mcspi(void) { - if (cpu_is_omap44xx()) - omap4_mcspi_fixup(); - - platform_device_register(&omap2_mcspi1); - platform_device_register(&omap2_mcspi2); - - if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) - omap2_mcspi3_init(); - - if (cpu_is_omap343x() || cpu_is_omap44xx()) - omap2_mcspi4_init(); + omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); } #else diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h index 560e266da8a..3d51b18131c 100644 --- a/arch/arm/plat-omap/include/plat/mcspi.h +++ b/arch/arm/plat-omap/include/plat/mcspi.h @@ -5,8 +5,11 @@ #define OMAP3_MCSPI_REV 1 #define OMAP4_MCSPI_REV 2 +#define OMAP4_MCSPI_REG_OFFSET 0x100 + struct omap2_mcspi_platform_config { unsigned short num_cs; + unsigned int regs_offset; }; struct omap2_mcspi_dev_attr { diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index f076cc5c6fb..f7851325c61 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -3,7 +3,7 @@ * * Copyright (C) 2005, 2006 Nokia Corporation * Author: Samuel Ortiz and - * Juha Yrjölä + * Juha Yrj�l� * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1087,91 +1087,14 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) return 0; } -static u8 __initdata spi1_rxdma_id [] = { - OMAP24XX_DMA_SPI1_RX0, - OMAP24XX_DMA_SPI1_RX1, - OMAP24XX_DMA_SPI1_RX2, - OMAP24XX_DMA_SPI1_RX3, -}; - -static u8 __initdata spi1_txdma_id [] = { - OMAP24XX_DMA_SPI1_TX0, - OMAP24XX_DMA_SPI1_TX1, - OMAP24XX_DMA_SPI1_TX2, - OMAP24XX_DMA_SPI1_TX3, -}; - -static u8 __initdata spi2_rxdma_id[] = { - OMAP24XX_DMA_SPI2_RX0, - OMAP24XX_DMA_SPI2_RX1, -}; - -static u8 __initdata spi2_txdma_id[] = { - OMAP24XX_DMA_SPI2_TX0, - OMAP24XX_DMA_SPI2_TX1, -}; - -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ - || defined(CONFIG_ARCH_OMAP4) -static u8 __initdata spi3_rxdma_id[] = { - OMAP24XX_DMA_SPI3_RX0, - OMAP24XX_DMA_SPI3_RX1, -}; - -static u8 __initdata spi3_txdma_id[] = { - OMAP24XX_DMA_SPI3_TX0, - OMAP24XX_DMA_SPI3_TX1, -}; -#endif - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -static u8 __initdata spi4_rxdma_id[] = { - OMAP34XX_DMA_SPI4_RX0, -}; - -static u8 __initdata spi4_txdma_id[] = { - OMAP34XX_DMA_SPI4_TX0, -}; -#endif static int __init omap2_mcspi_probe(struct platform_device *pdev) { struct spi_master *master; + struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data; struct omap2_mcspi *mcspi; struct resource *r; int status = 0, i; - const u8 *rxdma_id, *txdma_id; - unsigned num_chipselect; - - switch (pdev->id) { - case 1: - rxdma_id = spi1_rxdma_id; - txdma_id = spi1_txdma_id; - num_chipselect = 4; - break; - case 2: - rxdma_id = spi2_rxdma_id; - txdma_id = spi2_txdma_id; - num_chipselect = 2; - break; -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ - || defined(CONFIG_ARCH_OMAP4) - case 3: - rxdma_id = spi3_rxdma_id; - txdma_id = spi3_txdma_id; - num_chipselect = 2; - break; -#endif -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - case 4: - rxdma_id = spi4_rxdma_id; - txdma_id = spi4_txdma_id; - num_chipselect = 1; - break; -#endif - default: - return -EINVAL; - } master = spi_alloc_master(&pdev->dev, sizeof *mcspi); if (master == NULL) { @@ -1188,7 +1111,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) master->setup = omap2_mcspi_setup; master->transfer = omap2_mcspi_transfer; master->cleanup = omap2_mcspi_cleanup; - master->num_chipselect = num_chipselect; + master->num_chipselect = pdata->num_cs; dev_set_drvdata(&pdev->dev, master); @@ -1206,6 +1129,8 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) goto err1; } + r->start += pdata->regs_offset; + r->end += pdata->regs_offset; mcspi->phys = r->start; mcspi->base = ioremap(r->start, r->end - r->start + 1); if (!mcspi->base) { @@ -1240,11 +1165,32 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) if (mcspi->dma_channels == NULL) goto err3; - for (i = 0; i < num_chipselect; i++) { + for (i = 0; i < master->num_chipselect; i++) { + char dma_ch_name[14]; + struct resource *dma_res; + + sprintf(dma_ch_name, "rx%d", i); + dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, + dma_ch_name); + if (!dma_res) { + dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); + status = -ENODEV; + break; + } + mcspi->dma_channels[i].dma_rx_channel = -1; - mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; + mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; + sprintf(dma_ch_name, "tx%d", i); + dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, + dma_ch_name); + if (!dma_res) { + dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); + status = -ENODEV; + break; + } + mcspi->dma_channels[i].dma_tx_channel = -1; - mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; + mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; } if (omap2_mcspi_reset(mcspi) < 0) -- cgit v1.2.3-70-g09d2 From 59556765cd30467ff64a391906ad8eb68f886ad3 Mon Sep 17 00:00:00 2001 From: Syed Rafiuddin Date: Mon, 27 Dec 2010 05:51:45 +0000 Subject: OMAP4: keypad: Add the board support -Add the platform changes for the keypad driver -Register keyboard device with hwmod framework. Signed-off-by: Syed Rafiuddin Signed-off-by: Abraham Arce Signed-off-by: Shubhrajyoti D Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-4430sdp.c | 89 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/devices.c | 41 +++++++++++++++++ 2 files changed, 130 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 12d99e582cd..dcc8b27e303 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -48,6 +49,90 @@ #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 #define OMAP4_SFH7741_ENABLE_GPIO 188 +static const int sdp4430_keymap[] = { + KEY(0, 0, KEY_E), + KEY(0, 1, KEY_R), + KEY(0, 2, KEY_T), + KEY(0, 3, KEY_HOME), + KEY(0, 4, KEY_F5), + KEY(0, 5, KEY_UNKNOWN), + KEY(0, 6, KEY_I), + KEY(0, 7, KEY_LEFTSHIFT), + + KEY(1, 0, KEY_D), + KEY(1, 1, KEY_F), + KEY(1, 2, KEY_G), + KEY(1, 3, KEY_SEND), + KEY(1, 4, KEY_F6), + KEY(1, 5, KEY_UNKNOWN), + KEY(1, 6, KEY_K), + KEY(1, 7, KEY_ENTER), + + KEY(2, 0, KEY_X), + KEY(2, 1, KEY_C), + KEY(2, 2, KEY_V), + KEY(2, 3, KEY_END), + KEY(2, 4, KEY_F7), + KEY(2, 5, KEY_UNKNOWN), + KEY(2, 6, KEY_DOT), + KEY(2, 7, KEY_CAPSLOCK), + + KEY(3, 0, KEY_Z), + KEY(3, 1, KEY_KPPLUS), + KEY(3, 2, KEY_B), + KEY(3, 3, KEY_F1), + KEY(3, 4, KEY_F8), + KEY(3, 5, KEY_UNKNOWN), + KEY(3, 6, KEY_O), + KEY(3, 7, KEY_SPACE), + + KEY(4, 0, KEY_W), + KEY(4, 1, KEY_Y), + KEY(4, 2, KEY_U), + KEY(4, 3, KEY_F2), + KEY(4, 4, KEY_VOLUMEUP), + KEY(4, 5, KEY_UNKNOWN), + KEY(4, 6, KEY_L), + KEY(4, 7, KEY_LEFT), + + KEY(5, 0, KEY_S), + KEY(5, 1, KEY_H), + KEY(5, 2, KEY_J), + KEY(5, 3, KEY_F3), + KEY(5, 4, KEY_F9), + KEY(5, 5, KEY_VOLUMEDOWN), + KEY(5, 6, KEY_M), + KEY(5, 7, KEY_RIGHT), + + KEY(6, 0, KEY_Q), + KEY(6, 1, KEY_A), + KEY(6, 2, KEY_N), + KEY(6, 3, KEY_BACK), + KEY(6, 4, KEY_BACKSPACE), + KEY(6, 5, KEY_UNKNOWN), + KEY(6, 6, KEY_P), + KEY(6, 7, KEY_UP), + + KEY(7, 0, KEY_PROG1), + KEY(7, 1, KEY_PROG2), + KEY(7, 2, KEY_PROG3), + KEY(7, 3, KEY_PROG4), + KEY(7, 4, KEY_F4), + KEY(7, 5, KEY_UNKNOWN), + KEY(7, 6, KEY_OK), + KEY(7, 7, KEY_DOWN), +}; + +static struct matrix_keymap_data sdp4430_keymap_data = { + .keymap = sdp4430_keymap, + .keymap_size = ARRAY_SIZE(sdp4430_keymap), +}; + +static struct omap4_keypad_platform_data sdp4430_keypad_data = { + .keymap_data = &sdp4430_keymap_data, + .rows = 8, + .cols = 8, +}; static struct gpio_led sdp4430_gpio_leds[] = { { .name = "omap4:green:debug0", @@ -593,6 +678,10 @@ static void __init omap_4430sdp_init(void) spi_register_board_info(sdp4430_spi_board_info, ARRAY_SIZE(sdp4430_spi_board_info)); } + + status = omap4_keyboard_init(&sdp4430_keypad_data); + if (status) + pr_err("Keypad initialization failed: %d\n", status); } static void __init omap_4430sdp_map_io(void) diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index e0f0ef952bc..8800486f946 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "mux.h" #include "control.h" @@ -141,6 +142,46 @@ static inline void omap_init_camera(void) } #endif +struct omap_device_pm_latency omap_keyboard_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +int __init omap4_keyboard_init(struct omap4_keypad_platform_data + *sdp4430_keypad_data) +{ + struct omap_device *od; + struct omap_hwmod *oh; + struct omap4_keypad_platform_data *keypad_data; + unsigned int id = -1; + char *oh_name = "kbd"; + char *name = "omap4-keypad"; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return -ENODEV; + } + + keypad_data = sdp4430_keypad_data; + + od = omap_device_build(name, id, oh, keypad_data, + sizeof(struct omap4_keypad_platform_data), + omap_keyboard_latency, + ARRAY_SIZE(omap_keyboard_latency), 0); + + if (IS_ERR(od)) { + WARN(1, "Cant build omap_device for %s:%s.\n", + name, oh->name); + return PTR_ERR(od); + } + + return 0; +} + #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) #define MBOX_REG_SIZE 0x120 -- cgit v1.2.3-70-g09d2 From 741927f753a41c644840589a382a1d3500f86206 Mon Sep 17 00:00:00 2001 From: Eyal Reizer Date: Thu, 27 Jan 2011 09:49:49 +0000 Subject: omap3evm: add support for the WL12xx WLAN module to the AM/DM3xx Evaluation Module Adds platform initialization for working with the WLAN module attached to the evaluation module. The patch includes MMC2 initialization, SDIO and control pins muxing and platform device registration Signed-off-by: Eyal Reizer Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 78 ++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index c2a0fca4aa5..ac50bf94944 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -30,6 +30,8 @@ #include #include +#include +#include #include #include @@ -381,6 +383,16 @@ static struct omap2_hsmmc_info mmc[] = { .gpio_cd = -EINVAL, .gpio_wp = 63, }, +#ifdef CONFIG_WL12XX_PLATFORM_DATA + { + .name = "wl1271", + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .nonremovable = true, + }, +#endif {} /* Terminator */ }; @@ -538,6 +550,50 @@ static struct regulator_init_data omap3_evm_vpll2 = { .consumer_supplies = &omap3_evm_vpll2_supply, }; +#ifdef CONFIG_WL12XX_PLATFORM_DATA + +#define OMAP3EVM_WLAN_PMENA_GPIO (150) +#define OMAP3EVM_WLAN_IRQ_GPIO (149) + +static struct regulator_consumer_supply omap3evm_vmmc2_supply = { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", +}; + +/* VMMC2 for driving the WL12xx module */ +static struct regulator_init_data omap3evm_vmmc2 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3evm_vmmc2_supply, +}; + +static struct fixed_voltage_config omap3evm_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.80V */ + .gpio = OMAP3EVM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70ms */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &omap3evm_vmmc2, +}; + +static struct platform_device omap3evm_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &omap3evm_vwlan, + }, +}; + +struct wl12xx_platform_data omap3evm_wlan_data __initdata = { + .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO), + /* ref clock is 38.4 MHz */ + .board_ref_clock = 2, +}; +#endif + static struct twl4030_platform_data omap3evm_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -657,6 +713,21 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP_PIN_OFF_WAKEUPENABLE), OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), +#ifdef CONFIG_WL12XX_PLATFORM_DATA + /* WLAN IRQ - GPIO 149 */ + OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + + /* WLAN POWER ENABLE - GPIO 150 */ + OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + /* MMC2 SDIO pin muxes for WL12xx */ + OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), +#endif { .reg_offset = OMAP_MUX_TERMINATOR }, }; #endif @@ -714,6 +785,13 @@ static void __init omap3_evm_init(void) ads7846_dev_init(); omap3evm_init_smsc911x(); omap3_evm_display_init(); + +#ifdef CONFIG_WL12XX_PLATFORM_DATA + /* WL12xx WLAN Init */ + if (wl12xx_set_platform_data(&omap3evm_wlan_data)) + pr_err("error setting wl12xx data\n"); + platform_device_register(&omap3evm_vwlan_device); +#endif } MACHINE_START(OMAP3EVM, "OMAP3 EVM") -- cgit v1.2.3-70-g09d2 From 9bc64b89cd730a09b02c66af730229e0abc9e2bb Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 24 Jan 2011 19:25:55 +0000 Subject: OMAP3EVM: Reset the smsc911x ethernet controller in board_init With addition of hwmod support to gpio, the ethernet controller goes undetected for OMAP35xEVM. So explicitly assert the reset signal to ethernet controller smsc911x - - GPIO7 (>=RevG version of EVM's) - GPIO64 (<=RevD version of EVM's) Tested this patch on RevG version of EVM with ES3.1 Si. This patch is based on intial version from Charulatha V, reference to original discussion - http://www.mail-archive.com/linux-omap@vger.kernel.org/msg35784.html Signed-off-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 39 +++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index ac50bf94944..b9f954e839d 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -60,6 +60,13 @@ #define OMAP3EVM_ETHR_ID_REV 0x50 #define OMAP3EVM_ETHR_GPIO_IRQ 176 #define OMAP3EVM_SMSC911X_CS 5 +/* + * Eth Reset signal + * 64 = Generation 1 (<=RevD) + * 7 = Generation 2 (>=RevE) + */ +#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 +#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 static u8 omap3_evm_version; @@ -126,10 +133,15 @@ static struct platform_device omap3evm_smsc911x_device = { static inline void __init omap3evm_init_smsc911x(void) { - int eth_cs; + int eth_cs, eth_rst; struct clk *l3ck; unsigned int rate; + if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) + eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST; + else + eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST; + eth_cs = OMAP3EVM_SMSC911X_CS; l3ck = clk_get(NULL, "l3_ck"); @@ -138,6 +150,27 @@ static inline void __init omap3evm_init_smsc911x(void) else rate = clk_get_rate(l3ck); + /* Configure ethernet controller reset gpio */ + if (cpu_is_omap3430()) { + if (gpio_request(eth_rst, "SMSC911x gpio") < 0) { + pr_err(KERN_ERR "Failed to request %d for smsc911x\n", + eth_rst); + return; + } + + if (gpio_direction_output(eth_rst, 1) < 0) { + pr_err(KERN_ERR "Failed to set direction of %d for" \ + " smsc911x\n", eth_rst); + return; + } + /* reset pulse to ethernet controller*/ + usleep_range(150, 220); + gpio_set_value(eth_rst, 0); + usleep_range(150, 220); + gpio_set_value(eth_rst, 1); + usleep_range(1, 2); + } + if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", OMAP3EVM_ETHR_GPIO_IRQ); @@ -713,6 +746,10 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP_PIN_OFF_WAKEUPENABLE), OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), + OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_NONE), + OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_NONE), #ifdef CONFIG_WL12XX_PLATFORM_DATA /* WLAN IRQ - GPIO 149 */ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), -- cgit v1.2.3-70-g09d2 From f186e9b24f84e771124c6ee47e19dac5de35f987 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 25 Jan 2011 17:37:37 +0000 Subject: omap3evm: Change TWL related gpio API's to gpio*_cansleep Since TWL GPIO's can go into sleep, and using normal gpio_get/set_value() API will lead to kernel dump (WARN_ON()). So replacing standard gpio_get/set_value() to gpio_get/set_value_cansleep(). Signed-off-by: Vaibhav Hiremath Reviewed-by: Charulatha V Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index b9f954e839d..80c9f8a7d05 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -270,9 +270,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev) gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) - gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); + gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); else - gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); + gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); lcd_enabled = 1; return 0; @@ -283,9 +283,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev) gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) - gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); + gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); else - gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); + gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); lcd_enabled = 0; } @@ -324,7 +324,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) return -EINVAL; } - gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); + gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); dvi_enabled = 1; return 0; @@ -332,7 +332,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) { - gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); + gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); dvi_enabled = 0; } -- cgit v1.2.3-70-g09d2 From 410491d408ee98a31c6eeff5072ae0c13e0a2324 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 25 Jan 2011 17:37:38 +0000 Subject: OMAP3EVM: Add vio regulator supply required for ads7846 TSC driver Add vio regulator supply, needed for ads7846 touchscreen controller driver. Tested on OMAP3 (ES3.1 Si) RevG version of EVM. Signed-off-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 80c9f8a7d05..bbdf3ad299c 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -583,6 +583,25 @@ static struct regulator_init_data omap3_evm_vpll2 = { .consumer_supplies = &omap3_evm_vpll2_supply, }; +/* ads7846 on SPI */ +static struct regulator_consumer_supply omap3evm_vio_supply = + REGULATOR_SUPPLY("vcc", "spi1.0"); + +/* VIO for ads7846 */ +static struct regulator_init_data omap3evm_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3evm_vio_supply, +}; + #ifdef CONFIG_WL12XX_PLATFORM_DATA #define OMAP3EVM_WLAN_PMENA_GPIO (150) @@ -639,6 +658,7 @@ static struct twl4030_platform_data omap3evm_twldata = { .codec = &omap3evm_codec_data, .vdac = &omap3_evm_vdac, .vpll2 = &omap3_evm_vpll2, + .vio = &omap3evm_vio, }; static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { -- cgit v1.2.3-70-g09d2 From 904c545c22dc4926e73c5c869efed0ca6a778bda Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 25 Jan 2011 17:37:39 +0000 Subject: AM/DM37x: DSS mux configuration for >Rev-B processor cards To support higher resolution (e.g 720P@60), on OMAP36x (AM/DM37x) DSS data bus has been muxed with sys_boot pins. DSS[18-23] => DSS[0-5] sys_boot[0,1 3-5] => DSS[18-23] EVM revision >=RevB adopt this mux changes, which is going to ship outside. Signed-off-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index bbdf3ad299c..36dac55b235 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -760,7 +760,7 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { }; #ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { +static struct omap_board_mux omap35x_board_mux[] __initdata = { OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | OMAP_PIN_OFF_WAKEUPENABLE), @@ -787,6 +787,32 @@ static struct omap_board_mux board_mux[] __initdata = { #endif { .reg_offset = OMAP_MUX_TERMINATOR }, }; + +static struct omap_board_mux omap36x_board_mux[] __initdata = { + OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), + /* AM/DM37x EVM: DSS data bus muxed with sys_boot */ + OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), + + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap35x_board_mux NULL +#define omap36x_board_mux NULL #endif static struct omap_musb_board_data musb_board_data = { @@ -798,7 +824,11 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_evm_init(void) { omap3_evm_get_revision(); - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + if (cpu_is_omap3630()) + omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB); + else + omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB); omap3_evm_i2c_init(); -- cgit v1.2.3-70-g09d2 From 42fc8cab020c4d848a969b7c0a80b591c35bb263 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 25 Jan 2011 17:37:40 +0000 Subject: OMAP3EVM: Made backlight GPIO default state to off If you choose default output to DVI, the LCD backlight used to stay on, since panel->disable function never gets called. So, during init put backlight GPIO to off state and the driver code will decide which output to enable. Signed-off-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 36dac55b235..4f2574c35dd 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -456,6 +456,8 @@ static struct platform_device leds_gpio = { static int omap3evm_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { + int r; + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ omap_mux_init_gpio(63, OMAP_PIN_INPUT); mmc[0].gpio_cd = gpio + 0; @@ -471,8 +473,12 @@ static int omap3evm_twl_gpio_setup(struct device *dev, */ /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ - gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); + r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); + if (!r) + r = gpio_direction_output(gpio + TWL4030_GPIO_MAX, + (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0); + if (r) + printk(KERN_ERR "failed to get/set lcd_bkl gpio\n"); /* gpio + 7 == DVI Enable */ gpio_request(gpio + 7, "EN_DVI"); -- cgit v1.2.3-70-g09d2 From 854c122f54d0074afb9e9a8f2ab7d6258c1f218f Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 25 Jan 2011 17:37:41 +0000 Subject: OMAP3EVM: Set TSC wakeup option in pad config Set OMAP_PIN_OFF_WAKEUPENABLE to enable the wake-up functionality from touchscreen controller. Signed-off-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 4f2574c35dd..d4a11571229 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -771,7 +771,8 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = { OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | OMAP_PIN_OFF_WAKEUPENABLE), OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_NONE), OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | @@ -799,7 +800,8 @@ static struct omap_board_mux omap36x_board_mux[] __initdata = { OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | OMAP_PIN_OFF_WAKEUPENABLE), OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | + OMAP_PIN_OFF_WAKEUPENABLE), /* AM/DM37x EVM: DSS data bus muxed with sys_boot */ OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -- cgit v1.2.3-70-g09d2 From d5ce2b6592c49935462cba7317fa67fe8ee474ec Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:03 +0530 Subject: omap3630: nand: fix device size to work in polled mode zoom3 and 3630-sdp having the x16 nand device. This patch configure gpmc as x16 and select the currect function in driver for polled mode (without prefetch enable) transfer. Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-3430sdp.c | 2 +- arch/arm/mach-omap2/board-3630sdp.c | 3 ++- arch/arm/mach-omap2/board-flash.c | 10 ++++++---- arch/arm/mach-omap2/board-flash.h | 4 ++-- arch/arm/mach-omap2/board-ldp.c | 2 +- arch/arm/mach-omap2/board-zoom.c | 5 +++-- arch/arm/mach-omap2/gpmc-nand.c | 7 +++++-- drivers/mtd/nand/omap2.c | 2 +- 8 files changed, 21 insertions(+), 14 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 31085883199..4a37c70e38b 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -812,7 +812,7 @@ static void __init omap_3430sdp_init(void) omap_serial_init(); usb_musb_init(&musb_board_data); board_smc91x_init(); - board_flash_init(sdp_flash_partitions, chip_sel_3430); + board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); sdp3430_display_init(); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 16538757291..8d1c4358ecf 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -208,7 +209,7 @@ static void __init omap_sdp_init(void) zoom_peripherals_init(); zoom_display_init(); board_smc91x_init(); - board_flash_init(sdp_flash_partitions, chip_sel_sdp); + board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); } diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index fd38c05bb47..f6b72533c08 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -139,11 +139,13 @@ static struct omap_nand_platform_data board_nand_data = { }; void -__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) +__init board_nand_init(struct mtd_partition *nand_parts, + u8 nr_parts, u8 cs, int nand_type) { board_nand_data.cs = cs; board_nand_data.parts = nand_parts; - board_nand_data.nr_parts = nr_parts; + board_nand_data.nr_parts = nr_parts; + board_nand_data.devsize = nand_type; gpmc_nand_init(&board_nand_data); } @@ -194,7 +196,7 @@ unmap: * @return - void. */ void board_flash_init(struct flash_partitions partition_info[], - char chip_sel_board[][GPMC_CS_NUM]) + char chip_sel_board[][GPMC_CS_NUM], int nand_type) { u8 cs = 0; u8 norcs = GPMC_CS_NUM + 1; @@ -250,5 +252,5 @@ void board_flash_init(struct flash_partitions partition_info[], "in GPMC\n"); else board_nand_init(partition_info[2].parts, - partition_info[2].nr_parts, nandcs); + partition_info[2].nr_parts, nandcs, nand_type); } diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h index 69befe00dd2..c240a3f8d16 100644 --- a/arch/arm/mach-omap2/board-flash.h +++ b/arch/arm/mach-omap2/board-flash.h @@ -25,6 +25,6 @@ struct flash_partitions { }; extern void board_flash_init(struct flash_partitions [], - char chip_sel[][GPMC_CS_NUM]); + char chip_sel[][GPMC_CS_NUM], int nand_type); extern void board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs); + u8 nr_parts, u8 cs, int nand_type); diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index d8eb2cb7cbc..a3fae5697a7 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -433,7 +433,7 @@ static void __init omap_ldp_init(void) omap_serial_init(); usb_musb_init(&musb_board_data); board_nand_init(ldp_nand_partitions, - ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); + ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index 85d4170f30a..7e3f1595d77 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -124,8 +125,8 @@ static void __init omap_zoom_init(void) usb_ehci_init(&ehci_pdata); } - board_nand_init(zoom_nand_partitions, - ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); + board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions), + ZOOM_NAND_CS, NAND_BUSWIDTH_16); zoom_debugboard_init(); zoom_peripherals_init(); zoom_display_init(); diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 2bb29c16070..c1791d08ae5 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -12,6 +12,7 @@ #include #include #include +#include #include @@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void) t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); /* Configure GPMC */ - gpmc_cs_configure(gpmc_nand_data->cs, - GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); + if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); + else + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 15682ec8530..7c04cd6fb7a 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -804,7 +804,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->mtd.name = dev_name(&pdev->dev); info->mtd.owner = THIS_MODULE; - info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0; + info->nand.options = pdata->devsize; info->nand.options |= NAND_SKIP_BBTSCAN; /* NAND write protect off */ -- cgit v1.2.3-70-g09d2 From db97eb7dfe13f6c04f0a0e77c32e2691f563ab8b Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:05 +0530 Subject: omap: gpmc: enable irq mode in gpmc add support the irq mode in GPMC. gpmc_init() function move after omap_init_irq() as it has dependecy on irq. Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 45 +++++++++++++++++++++++++++++++--- arch/arm/mach-omap2/io.c | 2 -- arch/arm/plat-omap/include/plat/gpmc.h | 5 +++- arch/arm/plat-omap/include/plat/irqs.h | 9 ++++++- 4 files changed, 54 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 1b7b3e7d02f..382dea83e4f 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -14,6 +14,7 @@ */ #undef DEBUG +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -100,6 +102,8 @@ static void __iomem *gpmc_base; static struct clk *gpmc_l3_clk; +static irqreturn_t gpmc_handle_irq(int irq, void *dev); + static void gpmc_write_reg(int idx, u32 val) { __raw_writel(val, gpmc_base + idx); @@ -497,6 +501,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval) u32 regval = 0; switch (cmd) { + case GPMC_ENABLE_IRQ: + gpmc_write_reg(GPMC_IRQENABLE, wval); + break; + case GPMC_SET_IRQ_STATUS: gpmc_write_reg(GPMC_IRQSTATUS, wval); break; @@ -678,9 +686,10 @@ static void __init gpmc_mem_init(void) } } -void __init gpmc_init(void) +static int __init gpmc_init(void) { - u32 l; + u32 l, irq; + int cs, ret = -EINVAL; char *ck = NULL; if (cpu_is_omap24xx()) { @@ -698,7 +707,7 @@ void __init gpmc_init(void) } if (WARN_ON(!ck)) - return; + return ret; gpmc_l3_clk = clk_get(NULL, ck); if (IS_ERR(gpmc_l3_clk)) { @@ -723,6 +732,36 @@ void __init gpmc_init(void) l |= (0x02 << 3) | (1 << 0); gpmc_write_reg(GPMC_SYSCONFIG, l); gpmc_mem_init(); + + /* initalize the irq_chained */ + irq = OMAP_GPMC_IRQ_BASE; + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + set_irq_handler(irq, handle_simple_irq); + set_irq_flags(irq, IRQF_VALID); + irq++; + } + + ret = request_irq(INT_34XX_GPMC_IRQ, + gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); + if (ret) + pr_err("gpmc: irq-%d could not claim: err %d\n", + INT_34XX_GPMC_IRQ, ret); + return ret; +} +postcore_initcall(gpmc_init); + +static irqreturn_t gpmc_handle_irq(int irq, void *dev) +{ + u8 cs; + + if (irq != INT_34XX_GPMC_IRQ) + return IRQ_HANDLED; + /* check cs to invoke the irq */ + cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; + if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) + generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); + + return IRQ_HANDLED; } #ifdef CONFIG_ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b8b49e4ae92..657f3c84687 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -30,7 +30,6 @@ #include #include -#include #include #include "clock2xxx.h" @@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); } - gpmc_init(); omap_irq_base_init(); } diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 85ded598853..9c060da0a87 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -41,6 +41,8 @@ #define GPMC_NAND_ADDRESS 0x0000000b #define GPMC_NAND_DATA 0x0000000c +#define GPMC_ENABLE_IRQ 0x0000000d + /* ECC commands */ #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ @@ -78,6 +80,8 @@ #define WR_RD_PIN_MONITORING 0x00600000 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) +#define GPMC_IRQ_FIFOEVENTENABLE 0x01 +#define GPMC_IRQ_COUNT_EVENT 0x02 /* * Note that all values in this struct are in nanoseconds except sync_clk @@ -135,7 +139,6 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode, extern int gpmc_prefetch_reset(int cs); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); -extern void gpmc_init(void); extern int gpmc_read_status(int cmd); extern int gpmc_cs_configure(int cs, int cmd, int wval); extern int gpmc_nand_read(int cs, int cmd); diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 2910de921c5..1b911681e91 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -318,6 +318,7 @@ #define INT_34XX_PRCM_MPU_IRQ 11 #define INT_34XX_MCBSP1_IRQ 16 #define INT_34XX_MCBSP2_IRQ 17 +#define INT_34XX_GPMC_IRQ 20 #define INT_34XX_MCBSP3_IRQ 22 #define INT_34XX_MCBSP4_IRQ 23 #define INT_34XX_CAM_IRQ 24 @@ -411,7 +412,13 @@ #define TWL_IRQ_END TWL6030_IRQ_END #endif -#define NR_IRQS TWL_IRQ_END +/* GPMC related */ +#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END) +#define OMAP_GPMC_NR_IRQS 7 +#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) + + +#define NR_IRQS OMAP_GPMC_IRQ_END #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) -- cgit v1.2.3-70-g09d2 From 4e070376165a9b7f245fada77645b81352c6ec78 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:06 +0530 Subject: omap3: nand: prefetch in irq mode support This patch enable prefetch-irq mode for nand transfer(read, write) Signed-off-by: Vimal Singh Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-flash.c | 2 + arch/arm/plat-omap/include/plat/nand.h | 4 +- drivers/mtd/nand/omap2.c | 198 +++++++++++++++++++++++++++++++-- 3 files changed, 194 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index f6b72533c08..19645095d59 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -147,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.nr_parts = nr_parts; board_nand_data.devsize = nand_type; + board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; gpmc_nand_init(&board_nand_data); } #else diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 78c0bdb98c1..ae5e0538303 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -13,7 +13,8 @@ enum nand_io { NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ NAND_OMAP_POLLED, /* polled mode, without prefetch */ - NAND_OMAP_PREFETCH_DMA /* prefetch enabled sDMA mode */ + NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */ + NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */ }; struct omap_nand_platform_data { @@ -26,6 +27,7 @@ struct omap_nand_platform_data { int (*nand_setup)(void); int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; + int gpmc_irq; enum nand_io xfer_type; unsigned long phys_base; int devsize; diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 60bac8e6e9f..fbe84146717 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #define DRIVER_NAME "omap2-nand" +#define OMAP_NAND_TIMEOUT_MS 5000 #define NAND_Ecc_P1e (1 << 0) #define NAND_Ecc_P2e (1 << 1) @@ -108,6 +110,13 @@ struct omap_nand_info { unsigned long phys_base; struct completion comp; int dma_ch; + int gpmc_irq; + enum { + OMAP_NAND_IO_READ = 0, /* read */ + OMAP_NAND_IO_WRITE, /* write */ + } iomode; + u_char *buf; + int buf_len; }; /** @@ -267,9 +276,10 @@ static void omap_write_buf_pref(struct mtd_info *mtd, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - uint32_t pref_count = 0, w_count = 0; + uint32_t w_count = 0; int i = 0, ret = 0; u16 *p; + unsigned long tim, limit; /* take care of subpage writes */ if (len % 2 != 0) { @@ -295,9 +305,12 @@ static void omap_write_buf_pref(struct mtd_info *mtd, iowrite16(*p++, info->nand.IO_ADDR_W); } /* wait for data to flushed-out before reset the prefetch */ - do { - pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT); - } while (pref_count); + tim = 0; + limit = (loops_per_jiffy * + msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); + while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + cpu_relax(); + /* disable and stop the PFPW engine */ gpmc_prefetch_reset(info->gpmc_cs); } @@ -326,11 +339,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - uint32_t prefetch_status = 0; enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; dma_addr_t dma_addr; int ret; + unsigned long tim, limit; /* The fifo depth is 64 bytes. We have a sync at each frame and frame * length is 64 bytes. @@ -376,7 +389,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, /* configure and start prefetch transfer */ ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); if (ret) - /* PFPW engine is busy, use cpu copy methode */ + /* PFPW engine is busy, use cpu copy method */ goto out_copy; init_completion(&info->comp); @@ -385,10 +398,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, /* setup and start DMA using dma_addr */ wait_for_completion(&info->comp); + tim = 0; + limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); + while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + cpu_relax(); - do { - prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT); - } while (prefetch_status); /* disable and stop the PFPW engine */ gpmc_prefetch_reset(info->gpmc_cs); @@ -436,6 +450,155 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd, omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); } +/* + * omap_nand_irq - GMPC irq handler + * @this_irq: gpmc irq number + * @dev: omap_nand_info structure pointer is passed here + */ +static irqreturn_t omap_nand_irq(int this_irq, void *dev) +{ + struct omap_nand_info *info = (struct omap_nand_info *) dev; + u32 bytes; + u32 irq_stat; + + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); + bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); + bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ + if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ + if (irq_stat & 0x2) + goto done; + + if (info->buf_len && (info->buf_len < bytes)) + bytes = info->buf_len; + else if (!info->buf_len) + bytes = 0; + iowrite32_rep(info->nand.IO_ADDR_W, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + info->buf_len -= bytes; + + } else { + ioread32_rep(info->nand.IO_ADDR_R, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + + if (irq_stat & 0x2) + goto done; + } + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); + + return IRQ_HANDLED; + +done: + complete(&info->comp); + /* disable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); + + /* clear status */ + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); + + return IRQ_HANDLED; +} + +/* + * omap_read_buf_irq_pref - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + int ret = 0; + + if (len <= mtd->oobsize) { + omap_read_buf_pref(mtd, buf, len); + return; + } + + info->iomode = OMAP_NAND_IO_READ; + info->buf = buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + if (ret) + /* PFPW engine is busy, use cpu copy method */ + goto out_copy; + + info->buf_len = len; + /* enable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + /* waiting for read to complete */ + wait_for_completion(&info->comp); + + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_read_buf16(mtd, buf, len); + else + omap_read_buf8(mtd, buf, len); +} + +/* + * omap_write_buf_irq_pref - write buffer to NAND controller + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void omap_write_buf_irq_pref(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + int ret = 0; + unsigned long tim, limit; + + if (len <= mtd->oobsize) { + omap_write_buf_pref(mtd, buf, len); + return; + } + + info->iomode = OMAP_NAND_IO_WRITE; + info->buf = (u_char *) buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + if (ret) + /* PFPW engine is busy, use cpu copy method */ + goto out_copy; + + info->buf_len = len; + /* enable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + /* waiting for write to complete */ + wait_for_completion(&info->comp); + /* wait for data to flushed-out before reset the prefetch */ + tim = 0; + limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); + while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + cpu_relax(); + + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_write_buf16(mtd, buf, len); + else + omap_write_buf8(mtd, buf, len); +} + /** * omap_verify_buf - Verify chip data against buffer * @mtd: MTD device structure @@ -846,6 +1009,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } break; + case NAND_OMAP_PREFETCH_IRQ: + err = request_irq(pdata->gpmc_irq, + omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); + if (err) { + dev_err(&pdev->dev, "requesting irq(%d) error:%d", + pdata->gpmc_irq, err); + goto out_release_mem_region; + } else { + info->gpmc_irq = pdata->gpmc_irq; + info->nand.read_buf = omap_read_buf_irq_pref; + info->nand.write_buf = omap_write_buf_irq_pref; + } + break; + default: dev_err(&pdev->dev, "xfer_type(%d) not supported!\n", pdata->xfer_type); @@ -911,6 +1088,9 @@ static int omap_nand_remove(struct platform_device *pdev) if (info->dma_ch != -1) omap_free_dma(info->dma_ch); + if (info->gpmc_irq) + free_irq(info->gpmc_irq, info); + /* Release NAND device, its internal structures and partitions */ nand_release(&info->mtd); iounmap(info->nand.IO_ADDR_R); -- cgit v1.2.3-70-g09d2 From 317379a975c07fe63bc4f86dabd668df96ff3df2 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:07 +0530 Subject: omap3: nand: configurable fifo threshold to gain the throughput Configure the FIFO THREASHOLD value different for read and write to keep busy both filling and to drain out of FIFO at reading and writing. Signed-off-by: Vimal Singh Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 11 +++++++---- arch/arm/plat-omap/include/plat/gpmc.h | 5 ++++- drivers/mtd/nand/omap2.c | 22 ++++++++++++++-------- 3 files changed, 25 insertions(+), 13 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 382dea83e4f..674174365f7 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -60,7 +60,6 @@ #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ #define GPMC_SECTION_SHIFT 28 /* 128 MB */ -#define PREFETCH_FIFOTHRESHOLD (0x40 << 8) #define CS_NUM_SHIFT 24 #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 @@ -606,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write); /** * gpmc_prefetch_enable - configures and starts prefetch transfer * @cs: cs (chip select) number + * @fifo_th: fifo threshold to be used for read/ write * @dma_mode: dma mode enable (1) or disable (0) * @u32_count: number of bytes to be transferred * @is_write: prefetch read(0) or write post(1) mode */ -int gpmc_prefetch_enable(int cs, int dma_mode, +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, unsigned int u32_count, int is_write) { - if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { + pr_err("gpmc: fifo threshold is not supported\n"); + return -1; + } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { /* Set the amount of bytes to be prefetched */ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); @@ -622,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode, * enable the engine. Set which cs is has requested for. */ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | - PREFETCH_FIFOTHRESHOLD | + PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) | (0x1 & is_write))); diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 9c060da0a87..a2434639063 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -83,6 +83,9 @@ #define GPMC_IRQ_FIFOEVENTENABLE 0x01 #define GPMC_IRQ_COUNT_EVENT 0x02 +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 +#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) + /* * Note that all values in this struct are in nanoseconds except sync_clk * (which is in picoseconds), while the register values are in gpmc_fck cycles. @@ -134,7 +137,7 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); extern int gpmc_cs_set_reserved(int cs, int reserved); extern int gpmc_cs_reserved(int cs); -extern int gpmc_prefetch_enable(int cs, int dma_mode, +extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, unsigned int u32_count, int is_write); extern int gpmc_prefetch_reset(int cs); extern void omap3_gpmc_save_context(void); diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index fbe84146717..f1648fd5924 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -244,7 +244,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -289,7 +290,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd, } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -345,8 +347,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, int ret; unsigned long tim, limit; - /* The fifo depth is 64 bytes. We have a sync at each frame and frame - * length is 64 bytes. + /* The fifo depth is 64 bytes max. + * But configure the FIFO-threahold to 32 to get a sync at each frame + * and frame length is 32 bytes. */ int buf_len = len >> 6; @@ -387,7 +390,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; @@ -522,7 +526,8 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) init_completion(&info->comp); /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; @@ -569,8 +574,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd, info->buf = (u_char *) buf; init_completion(&info->comp); - /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + /* configure and start prefetch transfer : size=24 */ + ret = gpmc_prefetch_enable(info->gpmc_cs, + (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; -- cgit v1.2.3-70-g09d2 From f3d73f362d689a1d044e77964864f0a8ea0217f3 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:08 +0530 Subject: omap3: nand: ecc layout select from board file This patch makes it possible to select sw or hw (different layout options) ecc scheme supported by omap nand driver. Signed-off-by: Vimal Singh Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-flash.c | 1 + arch/arm/plat-omap/include/plat/gpmc.h | 6 ++++++ arch/arm/plat-omap/include/plat/nand.h | 2 ++ drivers/mtd/nand/omap2.c | 26 +++++++++++--------------- 4 files changed, 20 insertions(+), 15 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 19645095d59..a7681981201 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -148,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.nr_parts = nr_parts; board_nand_data.devsize = nand_type; + board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; gpmc_nand_init(&board_nand_data); } diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index a2434639063..773351bc25a 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -86,6 +86,12 @@ #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) +enum omap_ecc { + /* 1-bit ecc: stored at end of spare area */ + OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ + OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ +}; + /* * Note that all values in this struct are in nanoseconds except sync_clk * (which is in picoseconds), while the register values are in gpmc_fck cycles. diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index ae5e0538303..d86d1ecf006 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ +#include #include enum nand_io { @@ -31,6 +32,7 @@ struct omap_nand_platform_data { enum nand_io xfer_type; unsigned long phys_base; int devsize; + enum omap_ecc ecc_opt; }; /* minimum size for IO mapping */ diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index f1648fd5924..6d4a42e3938 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -626,8 +626,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) return 0; } -#ifdef CONFIG_MTD_NAND_OMAP_HWECC - /** * gen_true_ecc - This function will generate true ECC value * @ecc_buf: buffer to store ecc code @@ -847,8 +845,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); } -#endif - /** * omap_wait - wait until the command is done * @mtd: MTD device structure @@ -1038,17 +1034,17 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.verify_buf = omap_verify_buf; -#ifdef CONFIG_MTD_NAND_OMAP_HWECC - info->nand.ecc.bytes = 3; - info->nand.ecc.size = 512; - info->nand.ecc.calculate = omap_calculate_ecc; - info->nand.ecc.hwctl = omap_enable_hwecc; - info->nand.ecc.correct = omap_correct_data; - info->nand.ecc.mode = NAND_ECC_HW; - -#else - info->nand.ecc.mode = NAND_ECC_SOFT; -#endif + /* selsect the ecc type */ + if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) + info->nand.ecc.mode = NAND_ECC_SOFT; + else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) { + info->nand.ecc.bytes = 3; + info->nand.ecc.size = 512; + info->nand.ecc.calculate = omap_calculate_ecc; + info->nand.ecc.hwctl = omap_enable_hwecc; + info->nand.ecc.correct = omap_correct_data; + info->nand.ecc.mode = NAND_ECC_HW; + } /* DIP switches on some boards change between 8 and 16 bit * bus widths for flash. Try the other width if the first try fails. -- cgit v1.2.3-70-g09d2 From 4b087ff8572c7e7095787ca14aa72e39c80859bd Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 3 Feb 2011 12:45:21 +0000 Subject: omap3sdp: Fix regulator mapping for ads7846 TS controller On the OMAP3430SDP board, the ads7846 touchscreen controller is powered by VAUX3 regulator (supplying 2.8v). Fix this mapping in the board file, and hence prevent the ads7846 driver init to fail with the below error.. ads7846 spi1.0: unable to get regulator: -19 Signed-off-by: Rajendra Nayak Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-3430sdp.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 31085883199..7f8c7a73c53 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -426,6 +426,11 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = { .irq_line = 1, }; +/* ads7846 on SPI */ +static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { + REGULATOR_SUPPLY("vcc", "spi1.0"), +}; + /* * Apply all the fixed voltages since most versions of U-Boot * don't bother with that initialization. @@ -468,6 +473,8 @@ static struct regulator_init_data sdp3430_vaux3 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, + .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies), + .consumer_supplies = sdp3430_vaux3_supplies, }; /* VAUX4 for OMAP VDD_CSI2 (camera) */ -- cgit v1.2.3-70-g09d2 From 1435ca0fc1a269f9496343e24223a0fc430aff7a Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 7 Feb 2011 10:46:58 +0200 Subject: OMAP: OneNAND: fix 104MHz support 104MHz needs a latency of 8 clock cycles and the VHF flag must be set. Also t_rdyo is specified as "not applicable" so pick a lower value, and force at least 1 clk between AVD High to OE Low. Signed-off-by: Adrian Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-onenand.c | 23 +++++++++++++++++------ include/linux/mtd/onenand_regs.h | 1 + 2 files changed, 18 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 3a7d25fb00e..3a4307b8f7c 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) } static void set_onenand_cfg(void __iomem *onenand_base, int latency, - int sync_read, int sync_write, int hf) + int sync_read, int sync_write, int hf, int vhf) { u32 reg; @@ -114,6 +114,10 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency, reg |= ONENAND_SYS_CFG1_HF; else reg &= ~ONENAND_SYS_CFG1_HF; + if (vhf) + reg |= ONENAND_SYS_CFG1_VHF; + else + reg &= ~ONENAND_SYS_CFG1_VHF; writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); } @@ -130,7 +134,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, const int t_wph = 30; int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; - int first_time = 0, hf = 0, sync_read = 0, sync_write = 0; + int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; int err, ticks_cez; int cs = cfg->cs; u32 reg; @@ -180,7 +184,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, t_avdh = 2; t_ach = 3; t_aavdh = 6; - t_rdyo = 9; + t_rdyo = 6; break; case 83: min_gpmc_clk_period = 12000; /* 83 MHz */ @@ -217,7 +221,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, gpmc_clk_ns = gpmc_ticks_to_ns(div); if (gpmc_clk_ns < 15) /* >66Mhz */ hf = 1; - if (hf) + if (gpmc_clk_ns < 12) /* >83Mhz */ + vhf = 1; + if (vhf) + latency = 8; + else if (hf) latency = 6; else if (gpmc_clk_ns >= 25) /* 40 MHz*/ latency = 3; @@ -226,7 +234,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, if (first_time) set_onenand_cfg(onenand_base, latency, - sync_read, sync_write, hf); + sync_read, sync_write, hf, vhf); if (div == 1) { reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); @@ -264,6 +272,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, /* Read */ t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); + /* Force at least 1 clk between AVD High to OE Low */ + if (t.oe_on <= t.adv_rd_off) + t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1); t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); t.oe_off = t.access + gpmc_round_ns_to_ticks(1); t.cs_rd_off = t.oe_off; @@ -317,7 +328,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, if (err) return err; - set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf); + set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); return 0; } diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index cd6f3b43119..d60130f88ee 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -168,6 +168,7 @@ #define ONENAND_SYS_CFG1_INT (1 << 6) #define ONENAND_SYS_CFG1_IOBE (1 << 5) #define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) +#define ONENAND_SYS_CFG1_VHF (1 << 3) #define ONENAND_SYS_CFG1_HF (1 << 2) #define ONENAND_SYS_CFG1_SYNC_WRITE (1 << 1) -- cgit v1.2.3-70-g09d2 From 3ad2d861362031dac8b2bba78a8f4c575300948f Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 7 Feb 2011 10:46:59 +0200 Subject: OMAP: OneNAND: determine frequency in one place OneNAND frequency is determined when calculating GPMC timings. Return that value instead of determining it again in the OMAP OneNAND driver. Signed-off-by: Adrian Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-onenand.c | 10 ++++++---- arch/arm/plat-omap/include/plat/onenand.h | 2 +- drivers/mtd/onenand/omap2.c | 28 +++++----------------------- 3 files changed, 12 insertions(+), 28 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 3a4307b8f7c..46786a606e9 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -123,7 +123,7 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency, static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, void __iomem *onenand_base, - int freq) + int *freq_ptr) { struct gpmc_timings t; const int t_cer = 15; @@ -136,7 +136,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; int err, ticks_cez; - int cs = cfg->cs; + int cs = cfg->cs, freq = *freq_ptr; u32 reg; if (cfg->flags & ONENAND_SYNC_READ) { @@ -330,16 +330,18 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); + *freq_ptr = freq; + return 0; } -static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) +static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) { struct device *dev = &gpmc_onenand_device.dev; /* Set sync timings in GPMC */ if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, - freq) < 0) { + freq_ptr) < 0) { dev_err(dev, "Unable to set synchronous mode\n"); return -EINVAL; } diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index affe87e9ece..86118dc3f19 100644 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h @@ -20,7 +20,7 @@ struct omap_onenand_platform_data { int gpio_irq; struct mtd_partition *parts; int nr_parts; - int (*onenand_setup)(void __iomem *, int freq); + int (*onenand_setup)(void __iomem *, int *freq_ptr); int dma_channel; u8 flags; u8 regulator_can_sleep; diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c index ac31f461cc1..3e1bb956882 100644 --- a/drivers/mtd/onenand/omap2.c +++ b/drivers/mtd/onenand/omap2.c @@ -63,7 +63,7 @@ struct omap2_onenand { struct completion dma_done; int dma_channel; int freq; - int (*setup)(void __iomem *base, int freq); + int (*setup)(void __iomem *base, int *freq_ptr); struct regulator *regulator; }; @@ -581,7 +581,7 @@ static int __adjust_timing(struct device *dev, void *data) /* DMA is not in use so this is all that is needed */ /* Revisit for OMAP3! */ - ret = c->setup(c->onenand.base, c->freq); + ret = c->setup(c->onenand.base, &c->freq); return ret; } @@ -673,7 +673,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev) } if (pdata->onenand_setup != NULL) { - r = pdata->onenand_setup(c->onenand.base, c->freq); + r = pdata->onenand_setup(c->onenand.base, &c->freq); if (r < 0) { dev_err(&pdev->dev, "Onenand platform setup failed: " "%d\n", r); @@ -718,8 +718,8 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev) } dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual " - "base %p\n", c->gpmc_cs, c->phys_base, - c->onenand.base); + "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base, + c->onenand.base, c->freq); c->pdev = pdev; c->mtd.name = dev_name(&pdev->dev); @@ -754,24 +754,6 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev) if ((r = onenand_scan(&c->mtd, 1)) < 0) goto err_release_regulator; - switch ((c->onenand.version_id >> 4) & 0xf) { - case 0: - c->freq = 40; - break; - case 1: - c->freq = 54; - break; - case 2: - c->freq = 66; - break; - case 3: - c->freq = 83; - break; - case 4: - c->freq = 104; - break; - } - #ifdef CONFIG_MTD_PARTITIONS r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0); if (r > 0) -- cgit v1.2.3-70-g09d2 From 5714b7ed6b3e3c00c0d4719bb66757e64c30ecf6 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 7 Feb 2011 10:47:00 +0200 Subject: OMAP: OneNAND: let boards determine OneNAND frequency OneNAND version ID may not give the highest frequency supported and some OneNAND's have setup times that are clock dependent. Let the board provide that information. Signed-off-by: Adrian Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-onenand.c | 80 +++++++++++++++++++++++-------- arch/arm/plat-omap/include/plat/onenand.h | 8 ++++ 2 files changed, 67 insertions(+), 21 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 46786a606e9..d776ded9830 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -121,6 +121,47 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency, writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); } +static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, + void __iomem *onenand_base, bool *clk_dep) +{ + u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); + int freq = 0; + + if (cfg->get_freq) { + struct onenand_freq_info fi; + + fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID); + fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID); + fi.ver_id = ver; + freq = cfg->get_freq(&fi, clk_dep); + if (freq) + return freq; + } + + switch ((ver >> 4) & 0xf) { + case 0: + freq = 40; + break; + case 1: + freq = 54; + break; + case 2: + freq = 66; + break; + case 3: + freq = 83; + break; + case 4: + freq = 104; + break; + default: + freq = 54; + break; + } + + return freq; +} + static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, void __iomem *onenand_base, int *freq_ptr) @@ -138,6 +179,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, int err, ticks_cez; int cs = cfg->cs, freq = *freq_ptr; u32 reg; + bool clk_dep = false; if (cfg->flags & ONENAND_SYNC_READ) { sync_read = 1; @@ -152,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, err = omap2_onenand_set_async_mode(cs, onenand_base); if (err) return err; - reg = readw(onenand_base + ONENAND_REG_VERSION_ID); - switch ((reg >> 4) & 0xf) { - case 0: - freq = 40; - break; - case 1: - freq = 54; - break; - case 2: - freq = 66; - break; - case 3: - freq = 83; - break; - case 4: - freq = 104; - break; - default: - freq = 54; - break; - } + freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep); first_time = 1; } @@ -232,6 +254,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, else latency = 4; + if (clk_dep) { + if (gpmc_clk_ns < 12) { /* >83Mhz */ + t_ces = 3; + t_avds = 4; + } else if (gpmc_clk_ns < 15) { /* >66Mhz */ + t_ces = 5; + t_avds = 4; + } else if (gpmc_clk_ns < 25) { /* >40Mhz */ + t_ces = 6; + t_avds = 5; + } else { + t_ces = 7; + t_avds = 7; + } + } + if (first_time) set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index 86118dc3f19..cbe897ca7f9 100644 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h @@ -15,12 +15,20 @@ #define ONENAND_SYNC_READ (1 << 0) #define ONENAND_SYNC_READWRITE (1 << 1) +struct onenand_freq_info { + u16 maf_id; + u16 dev_id; + u16 ver_id; +}; + struct omap_onenand_platform_data { int cs; int gpio_irq; struct mtd_partition *parts; int nr_parts; int (*onenand_setup)(void __iomem *, int *freq_ptr); + int (*get_freq)(const struct onenand_freq_info *freq_info, + bool *clk_dep); int dma_channel; u8 flags; u8 regulator_can_sleep; -- cgit v1.2.3-70-g09d2 From f69eefd18d5201cd512c862a4bd27b8e8febd20b Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Tue, 15 Feb 2011 10:57:31 +0000 Subject: omap3: fix minor typos This patch fixes typos that were remaining after the file and functions were renamed. Signed-off-by: Sanjeev Premi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-flash.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index fd38c05bb47..ce61200ae68 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -1,5 +1,5 @@ /* - * board-sdp-flash.c + * board-flash.c * Modified from mach-omap2/board-3430sdp-flash.c * * Copyright (C) 2009 Nokia Corporation @@ -189,7 +189,7 @@ unmap: } /** - * sdp3430_flash_init - Identify devices connected to GPMC and register. + * board_flash_init - Identify devices connected to GPMC and register. * * @return - void. */ -- cgit v1.2.3-70-g09d2 From adc5430b473db2842a96fcce1ffbd43049757d3b Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Tue, 15 Feb 2011 10:57:32 +0000 Subject: omap3: flash: use pr_err instead of printk Change all occurences of printf() to pr_err(). Includes minor formatting changes as result of this change. Signed-off-by: Sanjeev Premi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-flash.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index ce61200ae68..86d1020da15 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -73,11 +73,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) + FLASH_SIZE_SDPV1 - 1; } if (err < 0) { - printk(KERN_ERR "NOR: Can't request GPMC CS\n"); + pr_err("NOR: Can't request GPMC CS\n"); return; } if (platform_device_register(&board_nor_device) < 0) - printk(KERN_ERR "Unable to register NOR device\n"); + pr_err("Unable to register NOR device\n"); } #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ @@ -208,7 +208,7 @@ void board_flash_init(struct flash_partitions partition_info[], */ idx = get_gpmc0_type(); if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { - printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); + pr_err("%s: Invalid chip select: %d\n", __func__, cs); return; } config_sel = (unsigned char *)(chip_sel_board[idx]); @@ -232,22 +232,19 @@ void board_flash_init(struct flash_partitions partition_info[], } if (norcs > GPMC_CS_NUM) - printk(KERN_INFO "NOR: Unable to find configuration " - "in GPMC\n"); + pr_err("NOR: Unable to find configuration in GPMC\n"); else board_nor_init(partition_info[0].parts, partition_info[0].nr_parts, norcs); if (onenandcs > GPMC_CS_NUM) - printk(KERN_INFO "OneNAND: Unable to find configuration " - "in GPMC\n"); + pr_err("OneNAND: Unable to find configuration in GPMC\n"); else board_onenand_init(partition_info[1].parts, partition_info[1].nr_parts, onenandcs); if (nandcs > GPMC_CS_NUM) - printk(KERN_INFO "NAND: Unable to find configuration " - "in GPMC\n"); + pr_err("NAND: Unable to find configuration in GPMC\n"); else board_nand_init(partition_info[2].parts, partition_info[2].nr_parts, nandcs); -- cgit v1.2.3-70-g09d2 From e49c4d27ab5ffd0d8707685af9ca2866a95660e8 Mon Sep 17 00:00:00 2001 From: Nishant Kamat Date: Thu, 17 Feb 2011 09:55:03 -0800 Subject: omap: Add chip id recognition for OMAP4 ES2.1 and ES2.2 Allow OMAP4 ES2.1 and ES2.2 revisions to be recognized in the omap4_check_revision() function. Mainly, ES2.1 has fixes that allow LPDDR to be used at 100% OPP (400MHz). ES2.2 additionally has a couple of power management fixes (to reduce leakage), an I2C1 SDA line state fix, and a floating point write corruption fix (cortex erratum). Even though the current mainline support doesn't need to distinguish between ES2.X versions, it's still useful to know the correct silicon rev when issues are reported. Moreover, these id checks can be used by power management code that selects suitable OPPs considering the memory speed limitation on ES2.0. For details about the silicon errata on OMAP4430, refer http://focus.ti.com/pdfs/wtbu/SWPZ009A_OMAP4430_Errata_Public_vA.pdf Signed-off-by: Nishant Kamat Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/id.c | 31 ++++++++++++++++++++----------- arch/arm/plat-omap/include/plat/cpu.h | 16 +++++++++++----- 2 files changed, 31 insertions(+), 16 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 5c25f1b5523..3168b17bc26 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -6,7 +6,7 @@ * Copyright (C) 2005 Nokia Corporation * Written by Tony Lindgren * - * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2009-11 Texas Instruments * Added OMAP4 support - Santosh Shilimkar * * This program is free software; you can redistribute it and/or modify @@ -328,7 +328,7 @@ static void __init omap4_check_revision(void) */ idcode = read_tap_reg(OMAP_TAP_IDCODE); hawkeye = (idcode >> 12) & 0xffff; - rev = (idcode >> 28) & 0xff; + rev = (idcode >> 28) & 0xf; /* * Few initial ES2.0 samples IDCODE is same as ES1.0 @@ -347,22 +347,31 @@ static void __init omap4_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP4430ES1; break; case 1: + default: omap_revision = OMAP4430_REV_ES2_0; omap_chip.oc |= CHIP_IS_OMAP4430ES2; + } + break; + case 0xb95c: + switch (rev) { + case 3: + omap_revision = OMAP4430_REV_ES2_1; + omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; break; + case 4: default: - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; - } - break; + omap_revision = OMAP4430_REV_ES2_2; + omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; + } + break; default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; + /* Unknown default to latest silicon rev as default */ + omap_revision = OMAP4430_REV_ES2_2; + omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; } - pr_info("OMAP%04x ES%d.0\n", - omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); + pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, + ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); } #define OMAP3_SHOW_FEATURE(feat) \ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index be99438d385..8198bb6cdb5 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -5,7 +5,7 @@ * * Copyright (C) 2004, 2008 Nokia Corporation * - * Copyright (C) 2009 Texas Instruments. + * Copyright (C) 2009-11 Texas Instruments. * * Written by Tony Lindgren * @@ -405,8 +405,10 @@ IS_OMAP_TYPE(3517, 0x3517) #define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) #define OMAP443X_CLASS 0x44300044 -#define OMAP4430_REV_ES1_0 OMAP443X_CLASS -#define OMAP4430_REV_ES2_0 0x44301044 +#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) +#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) +#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) +#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) /* * omap_chip bits @@ -434,12 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP4430ES2 (1 << 11) +#define CHIP_IS_OMAP4430ES2_1 (1 << 12) +#define CHIP_IS_OMAP4430ES2_2 (1 << 13) #define CHIP_IS_TI816X (1 << 14) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ - CHIP_IS_OMAP4430ES2) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ + CHIP_IS_OMAP4430ES2 | \ + CHIP_IS_OMAP4430ES2_1 | \ + CHIP_IS_OMAP4430ES2_2) /* * "GE" here represents "greater than or equal to" in terms of ES -- cgit v1.2.3-70-g09d2 From 905a74d9a0452b15bb4087a0ea48d017430e4e23 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Fri, 18 Feb 2011 14:01:06 +0100 Subject: OMAP4: hwmod data: Add rev and dev_attr fields in McSPI - Add a rev attribute to identify various McSPI IP version. - Add a dev_attr structure to provide the number of chipselect supported by the instance. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Govindraj.R Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 84e795cf064..182aa79d5e5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -3114,6 +3115,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { .name = "mcspi", .sysc = &omap44xx_mcspi_sysc, + .rev = OMAP4_MCSPI_REV, }; /* mcspi1 */ @@ -3156,6 +3158,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { &omap44xx_l4_per__mcspi1, }; +/* mcspi1 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { + .num_chipselect = 4, +}; + static struct omap_hwmod omap44xx_mcspi1_hwmod = { .name = "mcspi1", .class = &omap44xx_mcspi_hwmod_class, @@ -3169,6 +3176,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, }, }, + .dev_attr = &mcspi1_dev_attr, .slaves = omap44xx_mcspi1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -3210,6 +3218,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { &omap44xx_l4_per__mcspi2, }; +/* mcspi2 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { + .num_chipselect = 2, +}; + static struct omap_hwmod omap44xx_mcspi2_hwmod = { .name = "mcspi2", .class = &omap44xx_mcspi_hwmod_class, @@ -3223,6 +3236,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, }, }, + .dev_attr = &mcspi2_dev_attr, .slaves = omap44xx_mcspi2_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -3264,6 +3278,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { &omap44xx_l4_per__mcspi3, }; +/* mcspi3 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { + .num_chipselect = 2, +}; + static struct omap_hwmod omap44xx_mcspi3_hwmod = { .name = "mcspi3", .class = &omap44xx_mcspi_hwmod_class, @@ -3277,6 +3296,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, }, }, + .dev_attr = &mcspi3_dev_attr, .slaves = omap44xx_mcspi3_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -3316,6 +3336,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { &omap44xx_l4_per__mcspi4, }; +/* mcspi4 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { + .num_chipselect = 1, +}; + static struct omap_hwmod omap44xx_mcspi4_hwmod = { .name = "mcspi4", .class = &omap44xx_mcspi_hwmod_class, @@ -3329,6 +3354,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, }, }, + .dev_attr = &mcspi4_dev_attr, .slaves = omap44xx_mcspi4_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -- cgit v1.2.3-70-g09d2 From 73a92aa4f1d6786eaa5b4e637eee648db0dfd7a7 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 3 Feb 2011 12:45:22 +0000 Subject: omap3sdp: clean regulator supply mapping in board file clean the regulator supply mapping data in the 3430sdp board file (which is spread all over) by moving all of them together. Also use the REGULATOR_SUPPLY macro and remove instances of mapping dev pointers at run time. Additonally define all regulator_consumer_supply as array's and use ARRAY_SIZE macro to define num_consumer_supplies. Signed-off-by: Rajendra Nayak Reviewed-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-3430sdp.c | 71 ++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 40 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 7f8c7a73c53..a15f115f1ba 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -315,11 +315,6 @@ static struct platform_device sdp3430_dss_device = { }, }; -static struct regulator_consumer_supply sdp3430_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &sdp3430_dss_device.dev, -}; - static struct platform_device *sdp3430_devices[] __initdata = { &sdp3430_dss_device, }; @@ -369,18 +364,6 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct regulator_consumer_supply sdp3430_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply sdp3430_vsim_supply = { - .supply = "vmmc_aux", -}; - -static struct regulator_consumer_supply sdp3430_vmmc2_supply = { - .supply = "vmmc", -}; - static int sdp3430_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -391,13 +374,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev, mmc[1].gpio_cd = gpio + 1; omap2_hsmmc_init(mmc); - /* link regulators to MMC adapters ... we "know" the - * regulators will be set up only *after* we return. - */ - sdp3430_vmmc1_supply.dev = mmc[0].dev; - sdp3430_vsim_supply.dev = mmc[0].dev; - sdp3430_vmmc2_supply.dev = mmc[1].dev; - /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ gpio_request(gpio + 7, "sub_lcd_en_bkl"); gpio_direction_output(gpio + 7, 0); @@ -426,11 +402,34 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = { .irq_line = 1, }; +/* regulator consumer mappings */ + /* ads7846 on SPI */ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { REGULATOR_SUPPLY("vcc", "spi1.0"), }; +static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = { + REGULATOR_SUPPLY("vdda_dac", "omapdss"), +}; + +/* VPLL2 for digital video outputs */ +static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), +}; + +static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"), +}; + +static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { + REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.0"), +}; + +static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), +}; + /* * Apply all the fixed voltages since most versions of U-Boot * don't bother with that initialization. @@ -501,8 +500,8 @@ static struct regulator_init_data sdp3430_vmmc1 = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &sdp3430_vmmc1_supply, + .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies), + .consumer_supplies = sdp3430_vmmc1_supplies, }; /* VMMC2 for MMC2 card */ @@ -516,8 +515,8 @@ static struct regulator_init_data sdp3430_vmmc2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &sdp3430_vmmc2_supply, + .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies), + .consumer_supplies = sdp3430_vmmc2_supplies, }; /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ @@ -531,8 +530,8 @@ static struct regulator_init_data sdp3430_vsim = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &sdp3430_vsim_supply, + .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies), + .consumer_supplies = sdp3430_vsim_supplies, }; /* VDAC for DSS driving S-Video */ @@ -546,16 +545,8 @@ static struct regulator_init_data sdp3430_vdac = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 1, - .consumer_supplies = &sdp3430_vdda_dac_supply, -}; - -/* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { - { - .supply = "vdds_dsi", - .dev = &sdp3430_dss_device.dev, - } + .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies), + .consumer_supplies = sdp3430_vdda_dac_supplies, }; static struct regulator_init_data sdp3430_vpll2 = { -- cgit v1.2.3-70-g09d2 From 530a5a50168e5e14ba2fedd5e66796156b1df565 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Mon, 7 Feb 2011 20:59:59 +0530 Subject: OMAP4: Fix -EINVAL for vana, vcxio, vdac Fixed regulators in twl6030 do not have set_voltage hook. Regulator core returns -22 if set_voltage is NULL and apply_uV is set while applying the constraint to set voltage resulting in failure during probe of these regulators. Do not set apply_uV for fixed regulators which don't have set_voltage. machine_constraints_voltage: VANA: failed to apply 2100000uV constraint twl_reg twl_reg.43: can't register VANA, -22 twl_reg: probe of twl_reg.43 failed with error -22 machine_constraints_voltage: VCXIO: failed to apply 1800000uV constraint twl_reg twl_reg.44: can't register VCXIO, -22 twl_reg: probe of twl_reg.44 failed with error -22 machine_constraints_voltage: VDAC: failed to apply 1800000uV constraint twl_reg twl_reg.45: can't register VDAC, -22 twl_reg: probe of twl_reg.45 failed with error -22 Signed-off-by: Balaji T K Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-4430sdp.c | 3 --- arch/arm/mach-omap2/board-omap4panda.c | 3 --- 2 files changed, 6 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 12d99e582cd..27d9583811c 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -433,7 +433,6 @@ static struct regulator_init_data sdp4430_vana = { .constraints = { .min_uV = 2100000, .max_uV = 2100000, - .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE @@ -445,7 +444,6 @@ static struct regulator_init_data sdp4430_vcxio = { .constraints = { .min_uV = 1800000, .max_uV = 1800000, - .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE @@ -457,7 +455,6 @@ static struct regulator_init_data sdp4430_vdac = { .constraints = { .min_uV = 1800000, .max_uV = 1800000, - .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index fca5b9e80c1..220d3b85431 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -304,7 +304,6 @@ static struct regulator_init_data omap4_panda_vana = { .constraints = { .min_uV = 2100000, .max_uV = 2100000, - .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE @@ -316,7 +315,6 @@ static struct regulator_init_data omap4_panda_vcxio = { .constraints = { .min_uV = 1800000, .max_uV = 1800000, - .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE @@ -328,7 +326,6 @@ static struct regulator_init_data omap4_panda_vdac = { .constraints = { .min_uV = 1800000, .max_uV = 1800000, - .apply_uV = true, .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE -- cgit v1.2.3-70-g09d2 From d3f02fc3409824ff9b29bc23e60e76da768a1205 Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Mon, 7 Feb 2011 16:08:47 +0000 Subject: OMAP2: add regulator for MMC1 Signed-off-by: Balaji T K Tested-by: Kishore Kadiyala Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index ec74c0f2051..cc42d474c44 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -147,6 +148,25 @@ static void __init omap_2430sdp_init_early(void) omap2_init_common_devices(NULL, NULL); } +static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"), +}; + +/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +static struct regulator_init_data sdp2430_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies), + .consumer_supplies = &sdp2430_vmmc1_supplies[0], +}; + static struct twl4030_gpio_platform_data sdp2430_gpio_data = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, @@ -159,6 +179,7 @@ static struct twl4030_platform_data sdp2430_twldata = { /* platform_data for children goes here */ .gpio = &sdp2430_gpio_data, + .vmmc1 = &sdp2430_vmmc1, }; static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = { -- cgit v1.2.3-70-g09d2 From 66e171a3e8ed9179b2754831ae138e8fc251e4c7 Mon Sep 17 00:00:00 2001 From: Panduranga Mallireddy Date: Tue, 15 Feb 2011 03:40:32 -0500 Subject: omap: panda: wlan board muxing Add board muxing to support the wlan wl1271 chip that is hardwired to mmc5 (fifth mmc controller) on the PANDA. Based on the wlan board muxing for zoom3 by Ohad Ben-Cohen Signed-off-by: Panduranga Mallireddy Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 220d3b85431..9f4f86e73ce 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -387,6 +387,19 @@ static int __init omap4_panda_i2c_init(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 53 */ + OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), + /* WLAN POWER ENABLE - GPIO 43 */ + OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC5 CMD */ + OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC5 CLK */ + OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC5 DAT[0-3] */ + OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else -- cgit v1.2.3-70-g09d2 From cdc43482713d0af97d30d9b5d3c53b18fcec5d35 Mon Sep 17 00:00:00 2001 From: Panduranga Mallireddy Date: Tue, 15 Feb 2011 03:40:33 -0500 Subject: omap: select REGULATOR_FIXED_VOLTAGE by default for panda and sdp4430 Power to the wl12xx wlan device is controlled by a fixed regulator. Boards that have the wl12xx should select REGULATOR_FIXED_VOLTAGE. Signed-off-by: Panduranga Mallireddy Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 9b4e78fe3d1..b9d8a7b2a86 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -310,6 +310,7 @@ config MACH_OMAP_4430SDP depends on ARCH_OMAP4 select OMAP_PACKAGE_CBL select OMAP_PACKAGE_CBS + select REGULATOR_FIXED_VOLTAGE config MACH_OMAP4_PANDA bool "OMAP4 Panda Board" @@ -317,6 +318,7 @@ config MACH_OMAP4_PANDA depends on ARCH_OMAP4 select OMAP_PACKAGE_CBL select OMAP_PACKAGE_CBS + select REGULATOR_FIXED_VOLTAGE config OMAP3_EMU bool "OMAP3 debugging peripherals" -- cgit v1.2.3-70-g09d2 From edc840613c0fff590cad2deafdeffe6ea51405f7 Mon Sep 17 00:00:00 2001 From: Panduranga Mallireddy Date: Tue, 15 Feb 2011 03:40:34 -0500 Subject: omap: panda: add fixed regulator device for wlan Add a fixed regulator vmmc device to enable power control of the wl1271 wlan device. Based on the patch for zoom by Ohad Ben-Cohen Signed-off-by: Panduranga Mallireddy Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 9f4f86e73ce..d56bef15d3c 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -45,6 +46,7 @@ #define GPIO_HUB_POWER 1 #define GPIO_HUB_NRESET 62 +#define GPIO_WIFI_PMENA 43 static struct gpio_led gpio_leds[] = { { @@ -171,6 +173,37 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { }, }; +static struct regulator_consumer_supply omap4_panda_vmmc5_supply = { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.4", +}; + +static struct regulator_init_data panda_vmmc5 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap4_panda_vmmc5_supply, +}; + +static struct fixed_voltage_config panda_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.8V */ + .gpio = GPIO_WIFI_PMENA, + .startup_delay = 70000, /* 70msec */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &panda_vmmc5, +}; + +static struct platform_device omap_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &panda_vwlan, + }, +}; + static int omap4_twl6030_hsmmc_late_init(struct device *dev) { int ret = 0; @@ -416,6 +449,7 @@ static void __init omap4_panda_init(void) omap4_panda_i2c_init(); platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); + platform_device_register(&omap_vwlan_device); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); omap4_ehci_init(); -- cgit v1.2.3-70-g09d2 From b17e0979113b7b75bb3f73e2243d156f91698edb Mon Sep 17 00:00:00 2001 From: Panduranga Mallireddy Date: Tue, 15 Feb 2011 03:40:35 -0500 Subject: omap: panda: add mmc5/wl1271 device support Add MMC5 support on PANDA, which has the wl1271 device hardwired to. The wl1271 is a 4-wire, 1.8V, embedded SDIO WLAN device with an external IRQ line, and power-controlled by a GPIO-based fixed regulator. Based on the patch for mmc3/wl1271 device support for zoom by Ohad Ben-Cohen Signed-off-by: Panduranga Mallireddy Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index d56bef15d3c..3dd241b9515 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -47,6 +48,7 @@ #define GPIO_HUB_POWER 1 #define GPIO_HUB_NRESET 62 #define GPIO_WIFI_PMENA 43 +#define GPIO_WIFI_IRQ 53 static struct gpio_led gpio_leds[] = { { @@ -163,6 +165,15 @@ static struct omap2_hsmmc_info mmc[] = { .gpio_wp = -EINVAL, .gpio_cd = -EINVAL, }, + { + .name = "wl1271", + .mmc = 5, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .ocr_mask = MMC_VDD_165_195, + .nonremovable = true, + }, {} /* Terminator */ }; @@ -204,6 +215,12 @@ static struct platform_device omap_vwlan_device = { }, }; +struct wl12xx_platform_data omap_panda_wlan_data __initdata = { + .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ), + /* PANDA ref clock is 38.4 MHz */ + .board_ref_clock = 2, +}; + static int omap4_twl6030_hsmmc_late_init(struct device *dev) { int ret = 0; @@ -447,6 +464,9 @@ static void __init omap4_panda_init(void) package = OMAP_PACKAGE_CBL; omap4_mux_init(board_mux, package); + if (wl12xx_set_platform_data(&omap_panda_wlan_data)) + pr_err("error setting wl12xx data\n"); + omap4_panda_i2c_init(); platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); platform_device_register(&omap_vwlan_device); -- cgit v1.2.3-70-g09d2 From 7715db5aeca09d853be4f2eb0bc688a970220621 Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Tue, 15 Feb 2011 03:40:36 -0500 Subject: OMAP: hsmmc: Enable MMC4 and MMC5 on OMAP4 platforms OMAP4 supports up to 5 MMC controllers, but only 3 of these were initialized. MMC5 is used by wl12xx chip. So initialize MMC4 and MMC5. Signed-off-by: Kishore Kadiyala Signed-off-by: Panduranga Mallireddy Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/hsmmc.c | 5 +++++ drivers/mmc/host/omap_hsmmc.c | 24 ++++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 34272e4863f..5496bc7d40a 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -350,6 +350,11 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) mmc->slots[0].after_set_reg = NULL; } break; + case 4: + case 5: + mmc->slots[0].before_set_reg = NULL; + mmc->slots[0].after_set_reg = NULL; + break; default: pr_err("MMC%d configuration not supported!\n", c->mmc); kfree(mmc); diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 078fdf11af0..8c42573f42e 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -260,7 +260,7 @@ static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, return ret; } -static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, +static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, int vdd) { struct omap_hsmmc_host *host = @@ -316,6 +316,12 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, return ret; } +static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, + int vdd) +{ + return 0; +} + static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, int vdd, int cardsleep) { @@ -326,7 +332,7 @@ static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, return regulator_set_mode(host->vcc, mode); } -static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, +static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep, int vdd, int cardsleep) { struct omap_hsmmc_host *host = @@ -365,6 +371,12 @@ static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, return regulator_enable(host->vcc_aux); } +static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep, + int vdd, int cardsleep) +{ + return 0; +} + static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) { struct regulator *reg; @@ -379,10 +391,14 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) break; case OMAP_MMC2_DEVID: case OMAP_MMC3_DEVID: + case OMAP_MMC5_DEVID: /* Off-chip level shifting, or none */ - mmc_slot(host).set_power = omap_hsmmc_23_set_power; - mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; + mmc_slot(host).set_power = omap_hsmmc_235_set_power; + mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep; break; + case OMAP_MMC4_DEVID: + mmc_slot(host).set_power = omap_hsmmc_4_set_power; + mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep; default: pr_err("MMC%d configuration not supported!\n", host->id); return -EINVAL; -- cgit v1.2.3-70-g09d2 From 3b03b58dab847883e6b9a431558c7d8e43fa94c6 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 22 Feb 2011 10:36:27 +0100 Subject: OMAP4: hwmod data: Prevent timer1 to be reset and idle during init Since the timer1 is now started before the hwmod_init, we cannot reset it and idle it anymore. Add the appropriate flags to prevent the hwmod framework to do that. Signed-off-by: Benoit Cousson Cc: Kevin Hilman Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 182aa79d5e5..79a86017891 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -3989,6 +3989,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_timer1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), .main_clk = "timer1_fck", -- cgit v1.2.3-70-g09d2 From 996746ca127d722c279325552cdcc48b20079a61 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Tue, 22 Feb 2011 09:50:36 +0200 Subject: OMAP2420: hwmod data: add DSS DISPC RFBI VENC Hwmod needs database of all IPs in a system. This patch generates the hwmod database for OMAP2420 Display Sub System,. Since DSS is also considered as an IP as DISPC, RFBI, name it as dss_core. Acked-by: Benoit Cousson Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 310 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/l3_2xxx.h | 20 ++ arch/arm/plat-omap/include/plat/l4_2xxx.h | 24 +++ 3 files changed, 354 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/l3_2xxx.h create mode 100644 arch/arm/plat-omap/include/plat/l4_2xxx.h (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 7fffd340c76..f323c6bb22d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include "omap_hwmod_common_data.h" @@ -39,6 +41,10 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_iva_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_dss_core_hwmod; +static struct omap_hwmod omap2420_dss_dispc_hwmod; +static struct omap_hwmod omap2420_dss_rfbi_hwmod; +static struct omap_hwmod omap2420_dss_venc_hwmod; static struct omap_hwmod omap2420_wd_timer2_hwmod; static struct omap_hwmod omap2420_gpio1_hwmod; static struct omap_hwmod omap2420_gpio2_hwmod; @@ -67,6 +73,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { &omap2420_mpu__l3_main, }; +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap2420_dss__l3 = { + .master = &omap2420_dss_core_hwmod, + .slave = &omap2420_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Master interfaces on the L3 interconnect */ static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { &omap2420_l3_main__l4_core, @@ -509,6 +528,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_dss_hwmod_class = { + .name = "dss", + .sysc = &omap2420_dss_sysc, +}; + +/* dss */ +static struct omap_hwmod_irq_info omap2420_dss_irqs[] = { + { .irq = 25 }, +}; + +static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { + &omap2420_dss__l3, +}; + +static struct omap_hwmod_addr_space omap2420_dss_addrs[] = { + { + .pa_start = 0x48050000, + .pa_end = 0x480503FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2420_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { + &omap2420_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, +}; + +static struct omap_hwmod omap2420_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2420_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .mpu_irqs = omap2420_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs), + .sdma_reqs = omap2420_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap2420_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), + .masters = omap2420_dss_masters, + .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap2420_dispc_sysc, +}; + +static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { + { + .pa_start = 0x48050400, + .pa_end = 0x480507FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2420_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { + &omap2420_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap2420_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2420_dispc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .slaves = omap2420_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap2420_rfbi_sysc, +}; + +static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = { + { + .pa_start = 0x48050800, + .pa_end = 0x48050BFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2420_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { + &omap2420_l4_core__dss_rfbi, +}; + +static struct omap_hwmod omap2420_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2420_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2420_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap2420_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = { + { + .pa_start = 0x48050C00, + .pa_end = 0x48050FFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_venc_hwmod, + .clk = "dss_54m_fck", + .addr = omap2420_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { + &omap2420_l4_core__dss_venc, +}; + +static struct omap_hwmod omap2420_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2420_venc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2420_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + /* I2C common */ static struct omap_hwmod_class_sysconfig i2c_sysc = { .rev_offs = 0x00, @@ -1026,6 +1330,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_uart1_hwmod, &omap2420_uart2_hwmod, &omap2420_uart3_hwmod, + /* dss class */ + &omap2420_dss_core_hwmod, + &omap2420_dss_dispc_hwmod, + &omap2420_dss_rfbi_hwmod, + &omap2420_dss_venc_hwmod, + /* i2c class */ &omap2420_i2c1_hwmod, &omap2420_i2c2_hwmod, diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h new file mode 100644 index 00000000000..b8b5641379b --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l3_2xxx.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H + +/* L3 CONNIDs */ +/* Display Sub system (DSS) */ +#define OMAP2_L3_CORE_FW_CONNID_DSS 8 + +#endif diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h new file mode 100644 index 00000000000..3f39cf8a35c --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l4_2xxx.h @@ -0,0 +1,24 @@ +/* + * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H + +/* L4 CORE */ +/* Display Sub system (DSS) */ +#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28 +#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29 +#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30 +#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31 +#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32 + +#endif -- cgit v1.2.3-70-g09d2 From de56dbb6c1f8de1f54b09111eb50d8f9b8b073b2 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Tue, 22 Feb 2011 09:51:15 +0200 Subject: OMAP2430: hwmod data: add DSS DISPC RFBI VENC Hwmod needs database of all IPs in a system. This patch generates the hwmod database for OMAP2430 Display Sub System. Since DSS is also considered as an IP as DISPC, RFBI, name it as dss_core. Acked-by: Benoit Cousson Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 284 +++++++++++++++++++++++++++++ 1 file changed, 284 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 7ba688a1c84..de0015d3843 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -39,6 +40,10 @@ static struct omap_hwmod omap2430_mpu_hwmod; static struct omap_hwmod omap2430_iva_hwmod; static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; +static struct omap_hwmod omap2430_dss_core_hwmod; +static struct omap_hwmod omap2430_dss_dispc_hwmod; +static struct omap_hwmod omap2430_dss_rfbi_hwmod; +static struct omap_hwmod omap2430_dss_venc_hwmod; static struct omap_hwmod omap2430_wd_timer2_hwmod; static struct omap_hwmod omap2430_gpio1_hwmod; static struct omap_hwmod omap2430_gpio2_hwmod; @@ -69,6 +74,19 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { &omap2430_mpu__l3_main, }; +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap2430_dss__l3 = { + .master = &omap2430_dss_core_hwmod, + .slave = &omap2430_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Master interfaces on the L3 interconnect */ static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { &omap2430_l3_main__l4_core, @@ -566,6 +584,266 @@ static struct omap_hwmod omap2430_uart3_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_dss_hwmod_class = { + .name = "dss", + .sysc = &omap2430_dss_sysc, +}; + +/* dss */ +static struct omap_hwmod_irq_info omap2430_dss_irqs[] = { + { .irq = 25 }, +}; +static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { + &omap2430_dss__l3, +}; + +static struct omap_hwmod_addr_space omap2430_dss_addrs[] = { + { + .pa_start = 0x48050000, + .pa_end = 0x480503FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2430_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { + &omap2430_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, +}; + +static struct omap_hwmod omap2430_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2430_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .mpu_irqs = omap2430_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs), + .sdma_reqs = omap2430_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap2430_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), + .masters = omap2430_dss_masters, + .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap2430_dispc_sysc, +}; + +static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { + { + .pa_start = 0x48050400, + .pa_end = 0x480507FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2430_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { + &omap2430_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap2430_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2430_dispc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .slaves = omap2430_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap2430_rfbi_sysc, +}; + +static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = { + { + .pa_start = 0x48050800, + .pa_end = 0x48050BFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2430_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { + &omap2430_l4_core__dss_rfbi, +}; + +static struct omap_hwmod omap2430_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2430_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2430_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap2430_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = { + { + .pa_start = 0x48050C00, + .pa_end = 0x48050FFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_dss_venc_hwmod, + .clk = "dss_54m_fck", + .addr = omap2430_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { + &omap2430_l4_core__dss_venc, +}; + +static struct omap_hwmod omap2430_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2430_venc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2430_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, +}; + /* I2C common */ static struct omap_hwmod_class_sysconfig i2c_sysc = { .rev_offs = 0x00, @@ -1240,6 +1518,12 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_uart1_hwmod, &omap2430_uart2_hwmod, &omap2430_uart3_hwmod, + /* dss class */ + &omap2430_dss_core_hwmod, + &omap2430_dss_dispc_hwmod, + &omap2430_dss_rfbi_hwmod, + &omap2430_dss_venc_hwmod, + /* i2c class */ &omap2430_i2c1_hwmod, &omap2430_i2c2_hwmod, -- cgit v1.2.3-70-g09d2 From e04d9e1e4825cb3f6cfc238d7357ef084952eab1 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:21:51 +0000 Subject: OMAP3: hwmod data: add DSS DISPC RFBI DSI VENC Hwmod needs database of all IPs in a system. This patch generates the hwmod database for Display Sub System applicable for OMAP3430 and OMAP36xx. DSS is also considered as an IP as DISPC, RFBI and named as dss_core. For all the IP modules in DSS, same clock is needed for enabling. Hwmod sees DSS IPs as independent IPs, so same clock has to be repeated for .main_clk in each IP. This patch defines separate hwmod databases for OMAP3430ES1 and (OMAP3430ES2 and OMAP36xx) as OMAP3430ES1 does not have IDLEST bit to poll on for dss IP, and also the firewall regions are different between 3430es1 and later. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 433 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/l3_3xxx.h | 20 ++ arch/arm/plat-omap/include/plat/l4_3xxx.h | 10 + 3 files changed, 463 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/l3_3xxx.h (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 879f55f272e..e9d00122856 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +47,12 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; static struct omap_hwmod omap3xxx_wd_timer2_hwmod; +static struct omap_hwmod omap3430es1_dss_core_hwmod; +static struct omap_hwmod omap3xxx_dss_core_hwmod; +static struct omap_hwmod omap3xxx_dss_dispc_hwmod; +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; +static struct omap_hwmod omap3xxx_dss_venc_hwmod; static struct omap_hwmod omap3xxx_i2c1_hwmod; static struct omap_hwmod omap3xxx_i2c2_hwmod; static struct omap_hwmod omap3xxx_i2c3_hwmod; @@ -91,6 +98,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { &omap3xxx_mpu__l3_main, }; +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { + .master = &omap3xxx_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Master interfaces on the L3 interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { &omap3xxx_l3_main__l4_core, @@ -742,6 +762,410 @@ static struct omap_hwmod_class i2c_class = { .sysc = &i2c_sysc, }; +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { + .name = "dss", + .sysc = &omap3xxx_dss_sysc, +}; + +/* dss */ +static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = { + { .irq = 25 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, + { .name = "dsi1", .dma_req = 74 }, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { + &omap3xxx_dss__l3, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = { + { + .pa_start = 0x48050000, + .pa_end = 0x480503FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3430es1_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { + &omap3430es1_l4_core__dss, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { + &omap3xxx_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_tv_fck" }, + { .role = "dssclk", .clk = "dss_96m_fck" }, + { .role = "sys_clk", .clk = "dss2_alwon_fck" }, +}; + +static struct omap_hwmod omap3430es1_dss_core_hwmod = { + .name = "dss_core", + .class = &omap3xxx_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .mpu_irqs = omap3xxx_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), + .sdma_reqs = omap3xxx_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), + + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3430es1_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod omap3xxx_dss_core_hwmod = { + .name = "dss_core", + .class = &omap3xxx_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .mpu_irqs = omap3xxx_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), + .sdma_reqs = omap3xxx_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), + + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3xxx_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | + CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap3xxx_dispc_sysc, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { + { + .pa_start = 0x48050400, + .pa_end = 0x480507FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { + &omap3xxx_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap3xxx_dispc_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'dsi' class + * display serial interface controller + */ + +static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { + .name = "dsi", +}; + +/* dss_dsi1 */ +static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { + { + .pa_start = 0x4804FC00, + .pa_end = 0x4804FFFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dsi1_hwmod, + .addr = omap3xxx_dss_dsi1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dsi1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { + &omap3xxx_l4_core__dss_dsi1, +}; + +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { + .name = "dss_dsi1", + .class = &omap3xxx_dsi_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_dsi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap3xxx_rfbi_sysc, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48050800, + .pa_end = 0x48050BFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { + &omap3xxx_l4_core__dss_rfbi, +}; + +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap3xxx_rfbi_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap3xxx_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = { + { + .pa_start = 0x48050C00, + .pa_end = 0x48050FFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_venc_hwmod, + .clk = "dss_tv_fck", + .addr = omap3xxx_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { + &omap3xxx_l4_core__dss_venc, +}; + +static struct omap_hwmod omap3xxx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap3xxx_venc_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + /* I2C1 */ static struct omap_i2c_dev_attr i2c1_dev_attr = { @@ -1800,6 +2224,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, &omap3xxx_uart4_hwmod, + /* dss class */ + &omap3430es1_dss_core_hwmod, + &omap3xxx_dss_core_hwmod, + &omap3xxx_dss_dispc_hwmod, + &omap3xxx_dss_dsi1_hwmod, + &omap3xxx_dss_rfbi_hwmod, + &omap3xxx_dss_venc_hwmod, + + /* i2c class */ &omap3xxx_i2c1_hwmod, &omap3xxx_i2c2_hwmod, &omap3xxx_i2c3_hwmod, diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h new file mode 100644 index 00000000000..cde1938c5f8 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l3_3xxx.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H + +/* L3 Initiator IDs */ +/* Display Sub system (DSS) */ +#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29 + +#endif diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h index 5e194937542..881a858b1ff 100644 --- a/arch/arm/plat-omap/include/plat/l4_3xxx.h +++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h @@ -21,4 +21,14 @@ #define OMAP3_L4_CORE_FW_I2C3_REGION 73 #define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 +/* Display Sub system (DSS) */ +#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2 + +#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104 +#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3 +#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4 +#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4 +#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5 +#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6 +#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7 #endif -- cgit v1.2.3-70-g09d2 From 1dde9732d543f30d4297e8b74329c5ce797b5d16 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:21:53 +0000 Subject: OMAP2, 3: DSS2: Use Regulator init with driver name Use driver name in regulator inits needed for display instead of using device structure name. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-3430sdp.c | 11 +++-------- arch/arm/mach-omap2/board-cm-t35.c | 12 ++++-------- arch/arm/mach-omap2/board-igep0020.c | 6 ++---- arch/arm/mach-omap2/board-omap3evm.c | 6 ++---- arch/arm/mach-omap2/board-omap3stalker.c | 12 ++++-------- 5 files changed, 15 insertions(+), 32 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 31085883199..0f680cc4d9f 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -315,10 +315,8 @@ static struct platform_device sdp3430_dss_device = { }, }; -static struct regulator_consumer_supply sdp3430_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &sdp3430_dss_device.dev, -}; +static struct regulator_consumer_supply sdp3430_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); static struct platform_device *sdp3430_devices[] __initdata = { &sdp3430_dss_device, @@ -545,10 +543,7 @@ static struct regulator_init_data sdp3430_vdac = { /* VPLL2 for digital video outputs */ static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { - { - .supply = "vdds_dsi", - .dev = &sdp3430_dss_device.dev, - } + REGULATOR_SUPPLY("vdds_dsi", "omapdss"), }; static struct regulator_init_data sdp3430_vpll2 = { diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 9e4de92a579..d650b7f8078 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -495,15 +495,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = { .supply = "vmmc_aux", }; -static struct regulator_consumer_supply cm_t35_vdac_supply = { - .supply = "vdda_dac", - .dev = &cm_t35_dss_device.dev, -}; +static struct regulator_consumer_supply cm_t35_vdac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); -static struct regulator_consumer_supply cm_t35_vdvi_supply = { - .supply = "vdvi", - .dev = &cm_t35_dss_device.dev, -}; +static struct regulator_consumer_supply cm_t35_vdvi_supply = + REGULATOR_SUPPLY("vdvi", "omapdss"); /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data cm_t35_vmmc1 = { diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index dd0b1ac3b66..c235fa2a77a 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -493,10 +493,8 @@ static struct platform_device igep2_dss_device = { }, }; -static struct regulator_consumer_supply igep2_vpll2_supply = { - .supply = "vdds_dsi", - .dev = &igep2_dss_device.dev, -}; +static struct regulator_consumer_supply igep2_vpll2_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); static struct regulator_init_data igep2_vpll2 = { .constraints = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index c2a0fca4aa5..5e38da97dec 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -500,10 +500,8 @@ static struct twl4030_codec_data omap3evm_codec_data = { .audio = &omap3evm_audio_data, }; -static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &omap3_evm_dss_device.dev, -}; +static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); /* VDAC for DSS driving S-Video */ static struct regulator_init_data omap3_evm_vdac = { diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 5d1ccef6916..9c63c37b500 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -448,10 +448,8 @@ static struct twl4030_codec_data omap3stalker_codec_data = { .audio = &omap3stalker_audio_data, }; -static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &omap3_stalker_dss_device.dev, -}; +static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); /* VDAC for DSS driving S-Video */ static struct regulator_init_data omap3_stalker_vdac = { @@ -469,10 +467,8 @@ static struct regulator_init_data omap3_stalker_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_stalker_vpll2_supply = { - .supply = "vdds_dsi", - .dev = &omap3_stalker_lcd_device.dev, -}; +static struct regulator_consumer_supply omap3_stalker_vpll2_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); static struct regulator_init_data omap3_stalker_vpll2 = { .constraints = { -- cgit v1.2.3-70-g09d2 From b7ee79abcc1bd549eadf5a9852657058e6ecca47 Mon Sep 17 00:00:00 2001 From: Sumit Semwal Date: Mon, 24 Jan 2011 06:21:54 +0000 Subject: OMAP2, 3: DSS2: Create new file display.c for central dss driver registration. A new file display.c is introduced for display driver init, which adds a function omap_display_init to do the DSS driver registration. This is the first step in moving away registration of DSS from board files into a common place. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/Makefile | 3 +++ arch/arm/mach-omap2/display.c | 45 +++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/display.h | 11 ++++++++ 3 files changed, 59 insertions(+) create mode 100644 arch/arm/mach-omap2/display.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ee72a9787bf..1c3635d7f4c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -245,3 +245,6 @@ obj-y += $(smc91x-m) $(smc91x-y) smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o obj-y += $(smsc911x-m) $(smsc911x-y) obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o + +disp-$(CONFIG_OMAP2_DSS) := display.o +obj-y += $(disp-m) $(disp-y) diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c new file mode 100644 index 00000000000..b18db84b034 --- /dev/null +++ b/arch/arm/mach-omap2/display.c @@ -0,0 +1,45 @@ +/* + * OMAP2plus display device setup / initialization. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Senthilvadivu Guruswamy + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +static struct platform_device omap_display_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = NULL, + }, +}; + +int __init omap_display_init(struct omap_dss_board_info *board_data) +{ + int r = 0; + omap_display_device.dev.platform_data = board_data; + + r = platform_device_register(&omap_display_device); + if (r < 0) + printk(KERN_ERR "Unable to register OMAP-Display device\n"); + + return r; +} diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 537f4e449f5..0f140ecedb0 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -23,6 +23,7 @@ #include #include #include +#include #include #define DISPC_IRQ_FRAMEDONE (1 << 0) @@ -226,6 +227,16 @@ struct omap_dss_board_info { struct omap_dss_device *default_device; }; +#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS) +/* Init with the board info */ +extern int omap_display_init(struct omap_dss_board_info *board_data); +#else +static inline int omap_display_init(struct omap_dss_board_info *board_data) +{ + return 0; +} +#endif + struct omap_video_timings { /* Unit: pixels */ u16 x_res; -- cgit v1.2.3-70-g09d2 From d5e13227c32f12de3afb2e26a86bc9f3e5aaf7b6 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Tue, 22 Feb 2011 11:24:50 +0200 Subject: OMAP2, 3: DSS2: board files: replace platform_device_register with omap_display_init() This patch updated board files to replace platform_device_register or platform_add_devices of DSS with omap_display_init(). This moves away registration of DSS from board files into a common place. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/board-3430sdp.c | 14 +------------- arch/arm/mach-omap2/board-am3517evm.c | 16 +--------------- arch/arm/mach-omap2/board-cm-t35.c | 10 +--------- arch/arm/mach-omap2/board-devkit8000.c | 10 +--------- arch/arm/mach-omap2/board-igep0020.c | 10 +--------- arch/arm/mach-omap2/board-omap3beagle.c | 10 +--------- arch/arm/mach-omap2/board-omap3evm.c | 14 +------------- arch/arm/mach-omap2/board-omap3pandora.c | 10 +--------- arch/arm/mach-omap2/board-omap3stalker.c | 10 +--------- arch/arm/mach-omap2/board-rx51-video.c | 15 +-------------- arch/arm/mach-omap2/board-zoom-display.c | 15 +-------------- 11 files changed, 11 insertions(+), 123 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 0f680cc4d9f..df09e0d6f7d 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -307,21 +307,9 @@ static struct omap_dss_board_info sdp3430_dss_data = { .default_device = &sdp3430_lcd_device, }; -static struct platform_device sdp3430_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &sdp3430_dss_data, - }, -}; - static struct regulator_consumer_supply sdp3430_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); -static struct platform_device *sdp3430_devices[] __initdata = { - &sdp3430_dss_device, -}; - static struct omap_board_config_kernel sdp3430_config[] __initdata = { }; @@ -795,7 +783,7 @@ static void __init omap_3430sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3430_i2c_init(); - platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); + omap_display_init(&sdp3430_dss_data); if (omap_rev() > OMAP3430_REV_ES1_0) ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2; else diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 8532d6e0d53..634fe65b33c 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -378,24 +378,12 @@ static struct omap_dss_board_info am3517_evm_dss_data = { .default_device = &am3517_evm_lcd_device, }; -static struct platform_device am3517_evm_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &am3517_evm_dss_data, - }, -}; - /* * Board initialization */ static struct omap_board_config_kernel am3517_evm_config[] __initdata = { }; -static struct platform_device *am3517_evm_devices[] __initdata = { - &am3517_evm_dss_device, -}; - static void __init am3517_evm_init_early(void) { omap_board_config = am3517_evm_config; @@ -498,9 +486,7 @@ static void __init am3517_evm_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); am3517_evm_i2c_init(); - platform_add_devices(am3517_evm_devices, - ARRAY_SIZE(am3517_evm_devices)); - + omap_display_init(&am3517_evm_dss_data); omap_serial_init(); /* Configure GPIO for EHCI port */ diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index d650b7f8078..7311824be99 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -401,14 +401,6 @@ static struct omap_dss_board_info cm_t35_dss_data = { .default_device = &cm_t35_dvi_device, }; -static struct platform_device cm_t35_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &cm_t35_dss_data, - }, -}; - static struct omap2_mcspi_device_config tdo24m_mcspi_config = { .turbo_mode = 0, .single_channel = 1, /* 0: slave, 1: master */ @@ -468,7 +460,7 @@ static void __init cm_t35_init_display(void) msleep(50); gpio_set_value(lcd_en_gpio, 1); - err = platform_device_register(&cm_t35_dss_device); + err = omap_display_init(&cm_t35_dss_data); if (err) { pr_err("CM-T35: failed to register DSS device\n"); goto err_dev_reg; diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index af742887e83..54abdd06436 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -195,14 +195,6 @@ static struct omap_dss_board_info devkit8000_dss_data = { .default_device = &devkit8000_lcd_device, }; -static struct platform_device devkit8000_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &devkit8000_dss_data, - }, -}; - static struct regulator_consumer_supply devkit8000_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); @@ -579,7 +571,6 @@ static void __init omap_dm9000_init(void) } static struct platform_device *devkit8000_devices[] __initdata = { - &devkit8000_dss_device, &leds_gpio, &keys_gpio, &omap_dm9000_dev, @@ -801,6 +792,7 @@ static void __init devkit8000_init(void) platform_add_devices(devkit8000_devices, ARRAY_SIZE(devkit8000_devices)); + omap_display_init(&devkit8000_dss_data); spi_register_board_info(devkit8000_spi_board_info, ARRAY_SIZE(devkit8000_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index c235fa2a77a..54e6318f4a8 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -485,14 +485,6 @@ static struct omap_dss_board_info igep2_dss_data = { .default_device = &igep2_dvi_device, }; -static struct platform_device igep2_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &igep2_dss_data, - }, -}; - static struct regulator_consumer_supply igep2_vpll2_supply = REGULATOR_SUPPLY("vdds_dsi", "omapdss"); @@ -519,7 +511,6 @@ static void __init igep2_display_init(void) } static struct platform_device *igep2_devices[] __initdata = { - &igep2_dss_device, &igep2_vwlan_device, }; @@ -694,6 +685,7 @@ static void __init igep2_init(void) /* Register I2C busses and drivers */ igep2_i2c_init(); platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); + omap_display_init(&igep2_dss_data); omap_serial_init(); usb_musb_init(&musb_board_data); usb_ehci_init(&ehci_pdata); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 19bcd004d60..a1faea3b776 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -228,14 +228,6 @@ static struct omap_dss_board_info beagle_dss_data = { .default_device = &beagle_dvi_device, }; -static struct platform_device beagle_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &beagle_dss_data, - }, -}; - static struct regulator_consumer_supply beagle_vdac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); @@ -554,7 +546,6 @@ static void __init omap3_beagle_init_irq(void) static struct platform_device *omap3_beagle_devices[] __initdata = { &leds_gpio, &keys_gpio, - &beagle_dss_device, }; static void __init omap3beagle_flash_init(void) @@ -621,6 +612,7 @@ static void __init omap3_beagle_init(void) omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); + omap_display_init(&beagle_dss_data); omap_serial_init(); omap_mux_init_gpio(170, OMAP_PIN_INPUT); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 5e38da97dec..8afafddadfb 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -328,14 +328,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = { .default_device = &omap3_evm_lcd_device, }; -static struct platform_device omap3_evm_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &omap3_evm_dss_data, - }, -}; - static struct regulator_consumer_supply omap3evm_vmmc1_supply = { .supply = "vmmc", }; @@ -631,10 +623,6 @@ static void __init omap3_evm_init_early(void) omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); } -static struct platform_device *omap3_evm_devices[] __initdata = { - &omap3_evm_dss_device, -}; - static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, @@ -672,7 +660,7 @@ static void __init omap3_evm_init(void) omap3_evm_i2c_init(); - platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices)); + omap_display_init(&omap3_evm_dss_data); spi_register_board_info(omap3evm_spi_board_info, ARRAY_SIZE(omap3evm_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index b91f74ce3a9..17ef5479c7f 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -253,14 +253,6 @@ static struct omap_dss_board_info pandora_dss_data = { .default_device = &pandora_lcd_device, }; -static struct platform_device pandora_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &pandora_dss_data, - }, -}; - static void pandora_wl1251_init_card(struct mmc_card *card) { /* @@ -676,7 +668,6 @@ fail: static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_leds_gpio, &pandora_keys_gpio, - &pandora_dss_device, &pandora_vwlan_device, }; @@ -711,6 +702,7 @@ static void __init omap3pandora_init(void) pandora_wl1251_init(); platform_add_devices(omap3pandora_devices, ARRAY_SIZE(omap3pandora_devices)); + omap_display_init(&pandora_dss_data); omap_serial_init(); spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 9c63c37b500..07006c323fc 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -240,14 +240,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = { .default_device = &omap3_stalker_dvi_device, }; -static struct platform_device omap3_stalker_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &omap3_stalker_dss_data, - }, -}; - static struct regulator_consumer_supply omap3stalker_vmmc1_supply = { .supply = "vmmc", }; @@ -604,7 +596,6 @@ static void __init omap3_stalker_init_irq(void) } static struct platform_device *omap3_stalker_devices[] __initdata = { - &omap3_stalker_dss_device, &keys_gpio, }; @@ -644,6 +635,7 @@ static void __init omap3_stalker_init(void) platform_add_devices(omap3_stalker_devices, ARRAY_SIZE(omap3_stalker_devices)); + omap_display_init(&omap3_stalker_dss_data); spi_register_board_info(omap3stalker_spi_board_info, ARRAY_SIZE(omap3stalker_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index acd670054d9..89a66db8b77 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -66,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = { .default_device = &rx51_lcd_device, }; -struct platform_device rx51_display_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &rx51_dss_board_info, - }, -}; - -static struct platform_device *rx51_video_devices[] __initdata = { - &rx51_display_device, -}; - static int __init rx51_video_init(void) { if (!machine_is_nokia_rx51()) @@ -95,8 +83,7 @@ static int __init rx51_video_init(void) gpio_direction_output(RX51_LCD_RESET_GPIO, 1); - platform_add_devices(rx51_video_devices, - ARRAY_SIZE(rx51_video_devices)); + omap_display_init(&rx51_dss_board_info); return 0; } diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index 6bcd43657ae..37b84c2b850 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -130,14 +130,6 @@ static struct omap_dss_board_info zoom_dss_data = { .default_device = &zoom_lcd_device, }; -static struct platform_device zoom_dss_device = { - .name = "omapdss", - .id = -1, - .dev = { - .platform_data = &zoom_dss_data, - }, -}; - static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { .turbo_mode = 1, .single_channel = 1, /* 0: slave, 1: master */ @@ -153,14 +145,9 @@ static struct spi_board_info nec_8048_spi_board_info[] __initdata = { }, }; -static struct platform_device *zoom_display_devices[] __initdata = { - &zoom_dss_device, -}; - void __init zoom_display_init(void) { - platform_add_devices(zoom_display_devices, - ARRAY_SIZE(zoom_display_devices)); + omap_display_init(&zoom_dss_data); spi_register_board_info(nec_8048_spi_board_info, ARRAY_SIZE(nec_8048_spi_board_info)); zoom_lcd_panel_init(); -- cgit v1.2.3-70-g09d2 From fca1ab55f9a9f7e862a03a68c2b5577c15c344df Mon Sep 17 00:00:00 2001 From: Omar Ramirez Luna Date: Thu, 24 Feb 2011 12:51:32 -0800 Subject: OMAP2: hwmod data: add mailbox data Mailbox hwmod data for omap2430 and 2420. Signed-off-by: Omar Ramirez Luna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73 ++++++++++++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index f323c6bb22d..19ad9d053de 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1207,6 +1207,76 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors + * using a queued mailbox-interrupt mechanism. + */ + +static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap2420_mailbox_sysc, +}; + +/* mailbox */ +static struct omap_hwmod omap2420_mailbox_hwmod; +static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { + { .name = "dsp", .irq = 26 }, + { .name = "iva", .irq = 34 }, +}; + +static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = { + { + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, + }, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mailbox_hwmod, + .addr = omap2420_mailbox_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { + &omap2420_l4_core__mailbox, +}; + +static struct omap_hwmod omap2420_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2420_mailbox_hwmod_class, + .mpu_irqs = omap2420_mailbox_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs), + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, + }, + }, + .slaves = omap2420_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + /* * 'mcspi' class * multichannel serial port interface (mcspi) / master/slave synchronous serial @@ -1348,6 +1418,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { /* dma_system class*/ &omap2420_dma_system_hwmod, + /* mailbox class */ + &omap2420_mailbox_hwmod, + /* mcspi class */ &omap2420_mcspi1_hwmod, &omap2420_mcspi2_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index de0015d3843..91d2581c770 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1294,6 +1294,75 @@ static struct omap_hwmod omap2430_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors + * using a queued mailbox-interrupt mechanism. + */ + +static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap2430_mailbox_sysc, +}; + +/* mailbox */ +static struct omap_hwmod omap2430_mailbox_hwmod; +static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { + { .irq = 26 }, +}; + +static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = { + { + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, + }, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mailbox_hwmod, + .addr = omap2430_mailbox_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { + &omap2430_l4_core__mailbox, +}; + +static struct omap_hwmod omap2430_mailbox_hwmod = { + .name = "mailbox", + .class = &omap2430_mailbox_hwmod_class, + .mpu_irqs = omap2430_mailbox_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs), + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, + }, + }, + .slaves = omap2430_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + /* * 'mcspi' class * multichannel serial port interface (mcspi) / master/slave synchronous serial @@ -1537,6 +1606,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { /* dma_system class*/ &omap2430_dma_system_hwmod, + /* mailbox class */ + &omap2430_mailbox_hwmod, + /* mcspi class */ &omap2430_mcspi1_hwmod, &omap2430_mcspi2_hwmod, -- cgit v1.2.3-70-g09d2 From 0f9dfdd3d76d356250595cde200efe7c07dec0a1 Mon Sep 17 00:00:00 2001 From: Felipe Contreras Date: Thu, 24 Feb 2011 12:51:32 -0800 Subject: OMAP3: hwmod data: add mailbox data Mailbox hwmod data for omap3. Signed-off-by: Felipe Contreras Signed-off-by: Omar Ramirez Luna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71 ++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e9d00122856..510d5e11a4e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1858,6 +1858,74 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; +/* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors + * using a queued mailbox-interrupt mechanism. + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { + .rev_offs = 0x000, + .sysc_offs = 0x010, + .syss_offs = 0x014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap3xxx_mailbox_sysc, +}; + +static struct omap_hwmod omap3xxx_mailbox_hwmod; +static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { + { .irq = 26 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { + { + .pa_start = 0x48094000, + .pa_end = 0x480941ff, + .flags = ADDR_TYPE_RT, + }, +}; + +/* l4_core -> mailbox */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mailbox_hwmod, + .addr = omap3xxx_mailbox_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mailbox slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { + &omap3xxx_l4_core__mailbox, +}; + +static struct omap_hwmod omap3xxx_mailbox_hwmod = { + .name = "mailbox", + .class = &omap3xxx_mailbox_hwmod_class, + .mpu_irqs = omap3xxx_mailbox_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs), + .main_clk = "mailboxes_ick", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, + }, + }, + .slaves = omap3xxx_mailbox_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + /* l4 core -> mcspi1 interface */ static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { { @@ -2253,6 +2321,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { /* dma_system class*/ &omap3xxx_dma_system_hwmod, + /* mailbox class */ + &omap3xxx_mailbox_hwmod, + /* mcspi class */ &omap34xx_mcspi1, &omap34xx_mcspi2, -- cgit v1.2.3-70-g09d2 From 69dbf857c80e9697621ecb0d4323385999449663 Mon Sep 17 00:00:00 2001 From: Felipe Contreras Date: Thu, 24 Feb 2011 12:51:33 -0800 Subject: OMAP: mailbox: build device using omap_device/omap_hwmod Remove static platform_device and resource data within omap mailbox driver; use the one defined in the hwmod database along with omap_device framework for device build and registration. Add device latency functions to be used, so clock can be enabled and sysconfig is configured. Signed-off-by: Felipe Contreras Signed-off-by: Omar Ramirez Luna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 98 +++++++------------------------------------ arch/arm/mach-omap2/mailbox.c | 7 ++-- 2 files changed, 19 insertions(+), 86 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 9ee876fd367..d216976988d 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -184,95 +184,29 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data } #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) - -#define MBOX_REG_SIZE 0x120 - -#ifdef CONFIG_ARCH_OMAP2 -static struct resource omap2_mbox_resources[] = { - { - .start = OMAP24XX_MAILBOX_BASE, - .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_24XX_MAIL_U0_MPU, - .flags = IORESOURCE_IRQ, - .name = "dsp", - }, - { - .start = INT_24XX_MAIL_U3_MPU, - .flags = IORESOURCE_IRQ, - .name = "iva", - }, -}; -static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); -#else -#define omap2_mbox_resources NULL -#define omap2_mbox_resources_sz 0 -#endif - -#ifdef CONFIG_ARCH_OMAP3 -static struct resource omap3_mbox_resources[] = { - { - .start = OMAP34XX_MAILBOX_BASE, - .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_24XX_MAIL_U0_MPU, - .flags = IORESOURCE_IRQ, - .name = "dsp", - }, -}; -static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); -#else -#define omap3_mbox_resources NULL -#define omap3_mbox_resources_sz 0 -#endif - -#ifdef CONFIG_ARCH_OMAP4 - -#define OMAP4_MBOX_REG_SIZE 0x130 -static struct resource omap4_mbox_resources[] = { - { - .start = OMAP44XX_MAILBOX_BASE, - .end = OMAP44XX_MAILBOX_BASE + - OMAP4_MBOX_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP44XX_IRQ_MAIL_U0, - .flags = IORESOURCE_IRQ, - .name = "mbox", +static struct omap_device_pm_latency mbox_latencies[] = { + [0] = { + .activate_func = omap_device_enable_hwmods, + .deactivate_func = omap_device_idle_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, }; -static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); -#else -#define omap4_mbox_resources NULL -#define omap4_mbox_resources_sz 0 -#endif - -static struct platform_device mbox_device = { - .name = "omap-mailbox", - .id = -1, -}; static inline void omap_init_mbox(void) { - if (cpu_is_omap24xx()) { - mbox_device.resource = omap2_mbox_resources; - mbox_device.num_resources = omap2_mbox_resources_sz; - } else if (cpu_is_omap34xx()) { - mbox_device.resource = omap3_mbox_resources; - mbox_device.num_resources = omap3_mbox_resources_sz; - } else if (cpu_is_omap44xx()) { - mbox_device.resource = omap4_mbox_resources; - mbox_device.num_resources = omap4_mbox_resources_sz; - } else { - pr_err("%s: platform not supported\n", __func__); + struct omap_hwmod *oh; + struct omap_device *od; + + oh = omap_hwmod_lookup("mailbox"); + if (!oh) { + pr_err("%s: unable to find hwmod\n", __func__); return; } - platform_device_register(&mbox_device); + + od = omap_device_build("omap-mailbox", -1, oh, NULL, 0, + mbox_latencies, ARRAY_SIZE(mbox_latencies), 0); + WARN(IS_ERR(od), "%s: could not build device, err %ld\n", + __func__, PTR_ERR(od)); } #else static inline void omap_init_mbox(void) { } diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 29b9dc3917a..de352bdbcd0 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -398,14 +398,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) else if (cpu_is_omap34xx()) { list = omap3_mboxes; - list[0]->irq = platform_get_irq_byname(pdev, "dsp"); + list[0]->irq = platform_get_irq(pdev, 0); } #endif #if defined(CONFIG_ARCH_OMAP2) else if (cpu_is_omap2430()) { list = omap2_mboxes; - list[0]->irq = platform_get_irq_byname(pdev, "dsp"); + list[0]->irq = platform_get_irq(pdev, 0); } else if (cpu_is_omap2420()) { list = omap2_mboxes; @@ -417,8 +417,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) else if (cpu_is_omap44xx()) { list = omap4_mboxes; - list[0]->irq = list[1]->irq = - platform_get_irq_byname(pdev, "mbox"); + list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0); } #endif else { -- cgit v1.2.3-70-g09d2 From 82d2a5db5296834a4317e554f57b8883d7abb86d Mon Sep 17 00:00:00 2001 From: Omar Ramirez Luna Date: Thu, 24 Feb 2011 12:51:33 -0800 Subject: OMAP: mailbox: use runtime pm for clk and sysc handling Use runtime pm APIs to enable/disable mailbox clocks and to configure SYSC register. Based on the patch sent by Felipe Contreras: https://patchwork.kernel.org/patch/101662/ Signed-off-by: Omar Ramirez Luna Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mailbox.c | 65 ++++--------------------------------------- 1 file changed, 5 insertions(+), 60 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index de352bdbcd0..9a61e1f907a 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -14,12 +14,11 @@ #include #include #include +#include #include #include #define MAILBOX_REVISION 0x000 -#define MAILBOX_SYSCONFIG 0x010 -#define MAILBOX_SYSSTATUS 0x014 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) @@ -33,17 +32,6 @@ #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) -/* SYSCONFIG: register bit definition */ -#define AUTOIDLE (1 << 0) -#define SOFTRESET (1 << 1) -#define SMARTIDLE (2 << 3) -#define OMAP4_SOFTRESET (1 << 0) -#define OMAP4_NOIDLE (1 << 2) -#define OMAP4_SMARTIDLE (2 << 2) - -/* SYSSTATUS: register bit definition */ -#define RESETDONE (1 << 0) - #define MBOX_REG_SIZE 0x120 #define OMAP4_MBOX_REG_SIZE 0x130 @@ -70,8 +58,6 @@ struct omap_mbox2_priv { unsigned long irqdisable; }; -static struct clk *mbox_ick_handle; - static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq); @@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs) static int omap2_mbox_startup(struct omap_mbox *mbox) { u32 l; - unsigned long timeout; - mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); - if (IS_ERR(mbox_ick_handle)) { - printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", - PTR_ERR(mbox_ick_handle)); - return PTR_ERR(mbox_ick_handle); - } - clk_enable(mbox_ick_handle); - - if (cpu_is_omap44xx()) { - mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG); - timeout = jiffies + msecs_to_jiffies(20); - do { - l = mbox_read_reg(MAILBOX_SYSCONFIG); - if (!(l & OMAP4_SOFTRESET)) - break; - } while (!time_after(jiffies, timeout)); - - if (l & OMAP4_SOFTRESET) { - pr_err("Can't take mailbox out of reset\n"); - return -ENODEV; - } - } else { - mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG); - timeout = jiffies + msecs_to_jiffies(20); - do { - l = mbox_read_reg(MAILBOX_SYSSTATUS); - if (l & RESETDONE) - break; - } while (!time_after(jiffies, timeout)); - - if (!(l & RESETDONE)) { - pr_err("Can't take mailbox out of reset\n"); - return -ENODEV; - } - } + pm_runtime_enable(mbox->dev->parent); + pm_runtime_get_sync(mbox->dev->parent); l = mbox_read_reg(MAILBOX_REVISION); pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); - if (cpu_is_omap44xx()) - l = OMAP4_SMARTIDLE; - else - l = SMARTIDLE | AUTOIDLE; - mbox_write_reg(l, MAILBOX_SYSCONFIG); - omap2_mbox_enable_irq(mbox, IRQ_RX); return 0; @@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) static void omap2_mbox_shutdown(struct omap_mbox *mbox) { - clk_disable(mbox_ick_handle); - clk_put(mbox_ick_handle); - mbox_ick_handle = NULL; + pm_runtime_put_sync(mbox->dev->parent); + pm_runtime_disable(mbox->dev->parent); } /* Mailbox FIFO handle functions */ -- cgit v1.2.3-70-g09d2 From cd5038024d6c92fbe4bf67af91eea5c6fb24a192 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 12:51:45 -0800 Subject: OMAP: hwmod: allow hwmod to provide address space accessible from SDMA Adds support for resource API to get address space info other than just MPU. The drivers can now use platform_get_resource_byname() to get resource of type 'IORESOURCE_MEM' by name. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 1 + arch/arm/plat-omap/include/plat/omap_hwmod.h | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 9e89a58711b..c7762ab0dc8 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1883,6 +1883,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) os = oh->slaves[i]; for (j = 0; j < os->addr_cnt; j++) { + (res + r)->name = (os->addr + j)->name; (res + r)->start = (os->addr + j)->pa_start; (res + r)->end = (os->addr + j)->pa_end; (res + r)->flags = IORESOURCE_MEM; diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index fedd82971c9..04b1ea16a67 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -178,7 +178,8 @@ struct omap_hwmod_omap2_firewall { #define ADDR_TYPE_RT (1 << 1) /** - * struct omap_hwmod_addr_space - MPU address space handled by the hwmod + * struct omap_hwmod_addr_space - address space handled by the hwmod + * @name: name of the address space * @pa_start: starting physical address * @pa_end: ending physical address * @flags: (see omap_hwmod_addr_space.flags macros above) @@ -187,6 +188,7 @@ struct omap_hwmod_omap2_firewall { * structure. GPMC is one example. */ struct omap_hwmod_addr_space { + const char *name; u32 pa_start; u32 pa_end; u8 flags; -- cgit v1.2.3-70-g09d2 From 3cf32bba8ca0e0052ca41d74d455a5805b7fea85 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 12:51:45 -0800 Subject: OMAP: McBSP: Convert McBSP to platform device model Implement McBSP as platform device and add support for registering through platform device layer using resource structures. Later in this patch series, OMAP2+ McBSP driver would be modified to use hwmod framework after populating the omap2+ hwmod database. Signed-off-by: Kishon Vijay Abraham I Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mcbsp.c | 327 +++++++++++++---- arch/arm/mach-omap2/mcbsp.c | 613 ++++++++++++++++++++++++++------ arch/arm/plat-omap/devices.c | 10 +- arch/arm/plat-omap/include/plat/mcbsp.h | 14 +- arch/arm/plat-omap/mcbsp.c | 59 ++- 5 files changed, 818 insertions(+), 205 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 820973666f3..e68f6c012fd 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -10,6 +10,7 @@ * * Multichannel mode not supported. */ +#include #include #include #include @@ -78,100 +79,288 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = { }; #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) +struct resource omap7xx_mcbsp_res[][6] = { + { + { + .start = OMAP7XX_MCBSP1_BASE, + .end = OMAP7XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_7XX_McBSP1RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_7XX_McBSP1TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP7XX_MCBSP2_BASE, + .end = OMAP7XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_7XX_McBSP2RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_7XX_McBSP2TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { { - .phys_base = OMAP7XX_MCBSP1_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP_DMA_MCBSP1_TX, - .rx_irq = INT_7XX_McBSP1RX, - .tx_irq = INT_7XX_McBSP1TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP7XX_MCBSP2_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP_DMA_MCBSP3_TX, - .rx_irq = INT_7XX_McBSP2RX, - .tx_irq = INT_7XX_McBSP2TX, .ops = &omap1_mcbsp_ops, }, }; -#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) -#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) +#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1]) +#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res) #else +#define omap7xx_mcbsp_res NULL #define omap7xx_mcbsp_pdata NULL -#define OMAP7XX_MCBSP_PDATA_SZ 0 -#define OMAP7XX_MCBSP_REG_NUM 0 +#define OMAP7XX_MCBSP_RES_SZ 0 +#define OMAP7XX_MCBSP_COUNT 0 #endif #ifdef CONFIG_ARCH_OMAP15XX +struct resource omap15xx_mcbsp_res[][6] = { + { + { + .start = OMAP1510_MCBSP1_BASE, + .end = OMAP1510_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP1RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP1TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1510_MCBSP2_BASE, + .end = OMAP1510_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_1510_SPI_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_1510_SPI_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1510_MCBSP3_BASE, + .end = OMAP1510_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP3RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP3TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { { - .phys_base = OMAP1510_MCBSP1_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP_DMA_MCBSP1_TX, - .rx_irq = INT_McBSP1RX, - .tx_irq = INT_McBSP1TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1510_MCBSP2_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP_DMA_MCBSP2_TX, - .rx_irq = INT_1510_SPI_RX, - .tx_irq = INT_1510_SPI_TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1510_MCBSP3_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP_DMA_MCBSP3_TX, - .rx_irq = INT_McBSP3RX, - .tx_irq = INT_McBSP3TX, .ops = &omap1_mcbsp_ops, }, }; -#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) -#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) +#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1]) +#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res) #else +#define omap15xx_mcbsp_res NULL #define omap15xx_mcbsp_pdata NULL -#define OMAP15XX_MCBSP_PDATA_SZ 0 -#define OMAP15XX_MCBSP_REG_NUM 0 +#define OMAP15XX_MCBSP_RES_SZ 0 +#define OMAP15XX_MCBSP_COUNT 0 #endif #ifdef CONFIG_ARCH_OMAP16XX +struct resource omap16xx_mcbsp_res[][6] = { + { + { + .start = OMAP1610_MCBSP1_BASE, + .end = OMAP1610_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP1RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP1TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1610_MCBSP2_BASE, + .end = OMAP1610_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_1610_McBSP2_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_1610_McBSP2_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1610_MCBSP3_BASE, + .end = OMAP1610_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP3RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP3TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { { - .phys_base = OMAP1610_MCBSP1_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP_DMA_MCBSP1_TX, - .rx_irq = INT_McBSP1RX, - .tx_irq = INT_McBSP1TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1610_MCBSP2_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP_DMA_MCBSP2_TX, - .rx_irq = INT_1610_McBSP2_RX, - .tx_irq = INT_1610_McBSP2_TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1610_MCBSP3_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP_DMA_MCBSP3_TX, - .rx_irq = INT_McBSP3RX, - .tx_irq = INT_McBSP3TX, .ops = &omap1_mcbsp_ops, }, }; -#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) -#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) +#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1]) +#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res) #else +#define omap16xx_mcbsp_res NULL #define omap16xx_mcbsp_pdata NULL -#define OMAP16XX_MCBSP_PDATA_SZ 0 -#define OMAP16XX_MCBSP_REG_NUM 0 +#define OMAP16XX_MCBSP_RES_SZ 0 +#define OMAP16XX_MCBSP_COUNT 0 #endif static int __init omap1_mcbsp_init(void) @@ -179,16 +368,12 @@ static int __init omap1_mcbsp_init(void) if (!cpu_class_is_omap1()) return -ENODEV; - if (cpu_is_omap7xx()) { - omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); - } else if (cpu_is_omap15xx()) { - omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); - } else if (cpu_is_omap16xx()) { - omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16); - } + if (cpu_is_omap7xx()) + omap_mcbsp_count = OMAP7XX_MCBSP_COUNT; + else if (cpu_is_omap15xx()) + omap_mcbsp_count = OMAP15XX_MCBSP_COUNT; + else if (cpu_is_omap16xx()) + omap_mcbsp_count = OMAP16XX_MCBSP_COUNT; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); @@ -196,16 +381,22 @@ static int __init omap1_mcbsp_init(void) return -ENOMEM; if (cpu_is_omap7xx()) - omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, - OMAP7XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0], + OMAP7XX_MCBSP_RES_SZ, + omap7xx_mcbsp_pdata, + OMAP7XX_MCBSP_COUNT); if (cpu_is_omap15xx()) - omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, - OMAP15XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0], + OMAP15XX_MCBSP_RES_SZ, + omap15xx_mcbsp_pdata, + OMAP15XX_MCBSP_COUNT); if (cpu_is_omap16xx()) - omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, - OMAP16XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0], + OMAP16XX_MCBSP_RES_SZ, + omap16xx_mcbsp_pdata, + OMAP16XX_MCBSP_COUNT); return omap_mcbsp_init(); } diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 0526b758bdc..765ebe7da72 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -105,173 +105,542 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); /* Platform data */ #ifdef CONFIG_SOC_OMAP2420 -static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { +struct resource omap2420_mcbsp_res[][6] = { { - .phys_base = OMAP24XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + { + .start = OMAP24XX_MCBSP1_BASE, + .end = OMAP24XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP24XX_MCBSP2_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + { + .start = OMAP24XX_MCBSP2_BASE, + .end = OMAP24XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) -#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1]) +#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res) #else -#define omap2420_mcbsp_pdata NULL -#define OMAP2420_MCBSP_PDATA_SZ 0 -#define OMAP2420_MCBSP_REG_NUM 0 +#define omap2420_mcbsp_res NULL +#define OMAP2420_MCBSP_RES_SZ 0 +#define OMAP2420_MCBSP_COUNT 0 #endif +#define omap2420_mcbsp_pdata NULL + #ifdef CONFIG_SOC_OMAP2430 -static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { +struct resource omap2430_mcbsp_res[][6] = { { - .phys_base = OMAP24XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + { + .start = OMAP24XX_MCBSP1_BASE, + .end = OMAP24XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP24XX_MCBSP2_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + { + .start = OMAP24XX_MCBSP2_BASE, + .end = OMAP24XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP3_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + { + .start = OMAP2430_MCBSP3_BASE, + .end = OMAP2430_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP3_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP3_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP4_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + { + .start = OMAP2430_MCBSP4_BASE, + .end = OMAP2430_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP4_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP4_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP5_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, - .rx_irq = INT_24XX_MCBSP5_IRQ_RX, - .tx_irq = INT_24XX_MCBSP5_IRQ_TX, + { + .start = OMAP2430_MCBSP5_BASE, + .end = OMAP2430_MCBSP5_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP5_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP5_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP5_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP5_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) -#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1]) +#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res) #else -#define omap2430_mcbsp_pdata NULL -#define OMAP2430_MCBSP_PDATA_SZ 0 -#define OMAP2430_MCBSP_REG_NUM 0 +#define omap2430_mcbsp_res NULL +#define OMAP2430_MCBSP_RES_SZ 0 +#define OMAP2430_MCBSP_COUNT 0 #endif +#define omap2430_mcbsp_pdata NULL + #ifdef CONFIG_ARCH_OMAP3 +struct resource omap34xx_mcbsp_res[][7] = { + { + { + .start = OMAP34XX_MCBSP1_BASE, + .end = OMAP34XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP2_BASE, + .end = OMAP34XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "sidetone", + .start = OMAP34XX_MCBSP2_ST_BASE, + .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP3_BASE, + .end = OMAP34XX_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "sidetone", + .start = OMAP34XX_MCBSP3_ST_BASE, + .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP3_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP3_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP4_BASE, + .end = OMAP34XX_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP4_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP4_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP5_BASE, + .end = OMAP34XX_MCBSP5_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP5_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP5_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP5_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP5_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { { - .phys_base = OMAP34XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP2_BASE, - .phys_base_st = OMAP34XX_MCBSP2_ST_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { - .phys_base = OMAP34XX_MCBSP3_BASE, - .phys_base_st = OMAP34XX_MCBSP3_ST_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP4_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP5_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, - .rx_irq = INT_24XX_MCBSP5_IRQ_RX, - .tx_irq = INT_24XX_MCBSP5_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; -#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) -#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1]) +#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res) #else #define omap34xx_mcbsp_pdata NULL -#define OMAP34XX_MCBSP_PDATA_SZ 0 -#define OMAP34XX_MCBSP_REG_NUM 0 +#define omap34XX_mcbsp_res NULL +#define OMAP34XX_MCBSP_RES_SZ 0 +#define OMAP34XX_MCBSP_COUNT 0 #endif -static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { +struct resource omap44xx_mcbsp_res[][6] = { { - .phys_base = OMAP44XX_MCBSP1_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP1, + { + .name = "mpu", + .start = OMAP44XX_MCBSP1_BASE, + .end = OMAP44XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP1_DMA_BASE, + .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP2_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP2, + { + .name = "mpu", + .start = OMAP44XX_MCBSP2_BASE, + .end = OMAP44XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP2_DMA_BASE, + .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP2, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP3_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP3, + { + .name = "mpu", + .start = OMAP44XX_MCBSP3_BASE, + .end = OMAP44XX_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP3_DMA_BASE, + .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP3, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP4_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP4, + { + .start = OMAP44XX_MCBSP4_BASE, + .end = OMAP44XX_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP4, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) -#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define omap44xx_mcbsp_pdata NULL +#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1]) +#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res) static int __init omap2_mcbsp_init(void) { - if (cpu_is_omap2420()) { - omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); - } else if (cpu_is_omap2430()) { - omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); - } else if (cpu_is_omap34xx()) { - omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32); - } else if (cpu_is_omap44xx()) { - omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32); - } + if (cpu_is_omap2420()) + omap_mcbsp_count = OMAP2420_MCBSP_COUNT; + else if (cpu_is_omap2430()) + omap_mcbsp_count = OMAP2430_MCBSP_COUNT; + else if (cpu_is_omap34xx()) + omap_mcbsp_count = OMAP34XX_MCBSP_COUNT; + else if (cpu_is_omap44xx()) + omap_mcbsp_count = OMAP44XX_MCBSP_COUNT; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); @@ -279,17 +648,25 @@ static int __init omap2_mcbsp_init(void) return -ENOMEM; if (cpu_is_omap2420()) - omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, - OMAP2420_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0], + OMAP2420_MCBSP_RES_SZ, + omap2420_mcbsp_pdata, + OMAP2420_MCBSP_COUNT); if (cpu_is_omap2430()) - omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, - OMAP2430_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0], + OMAP2420_MCBSP_RES_SZ, + omap2430_mcbsp_pdata, + OMAP2430_MCBSP_COUNT); if (cpu_is_omap34xx()) - omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, - OMAP34XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0], + OMAP34XX_MCBSP_RES_SZ, + omap34xx_mcbsp_pdata, + OMAP34XX_MCBSP_COUNT); if (cpu_is_omap44xx()) - omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, - OMAP44XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0], + OMAP44XX_MCBSP_RES_SZ, + omap44xx_mcbsp_pdata, + OMAP44XX_MCBSP_COUNT); return omap_mcbsp_init(); } diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 10245b837c1..7d9f815cede 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -35,8 +35,8 @@ static struct platform_device **omap_mcbsp_devices; -void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, - int size) +void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, + struct omap_mcbsp_platform_data *config, int size) { int i; @@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); if (!new_mcbsp) continue; + platform_device_add_resources(new_mcbsp, &res[i * res_count], + res_count); new_mcbsp->dev.platform_data = &config[i]; ret = platform_device_add(new_mcbsp); if (ret) { @@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, } #else -void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, - int size) +void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, + struct omap_mcbsp_platform_data *config, int size) { } #endif diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 6ecf1051e5f..dc1a28299ae 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -63,9 +63,12 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP34XX_MCBSP4_BASE 0x49026000 #define OMAP34XX_MCBSP5_BASE 0x48096000 -#define OMAP44XX_MCBSP1_BASE 0x49022000 -#define OMAP44XX_MCBSP2_BASE 0x49024000 -#define OMAP44XX_MCBSP3_BASE 0x49026000 +#define OMAP44XX_MCBSP1_BASE 0x40122000 +#define OMAP44XX_MCBSP1_DMA_BASE 0x49022000 +#define OMAP44XX_MCBSP2_BASE 0x40124000 +#define OMAP44XX_MCBSP2_DMA_BASE 0x49024000 +#define OMAP44XX_MCBSP3_BASE 0x40126000 +#define OMAP44XX_MCBSP3_DMA_BASE 0x49026000 #define OMAP44XX_MCBSP4_BASE 0x48096000 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) @@ -431,6 +434,7 @@ struct omap_mcbsp_st_data { struct omap_mcbsp { struct device *dev; unsigned long phys_base; + unsigned long phys_dma_base; void __iomem *io_base; u8 id; u8 free; @@ -474,8 +478,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size; #define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; int omap_mcbsp_init(void); -void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, - int size); +void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, + struct omap_mcbsp_platform_data *config, int size); void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); #ifdef CONFIG_ARCH_OMAP3 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index b5a6e178a7f..5f25ae5f9c1 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1649,7 +1649,8 @@ static const struct attribute_group sidetone_attr_group = { static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) { - struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; + struct platform_device *pdev; + struct resource *res; struct omap_mcbsp_st_data *st_data; int err; @@ -1659,7 +1660,10 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) goto err1; } - st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); + pdev = container_of(mcbsp->dev, struct platform_device, dev); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); + st_data->io_base_st = ioremap(res->start, resource_size(res)); if (!st_data->io_base_st) { err = -ENOMEM; goto err2; @@ -1748,6 +1752,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; struct omap_mcbsp *mcbsp; int id = pdev->id - 1; + struct resource *res; int ret = 0; if (!pdata) { @@ -1777,25 +1782,59 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->dma_tx_lch = -1; mcbsp->dma_rx_lch = -1; - mcbsp->phys_base = pdata->phys_base; - mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); + if (!res) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory" + "resource\n", __func__, pdev->id); + ret = -ENOMEM; + goto exit; + } + } + mcbsp->phys_base = res->start; + omap_mcbsp_cache_size = resource_size(res); + mcbsp->io_base = ioremap(res->start, resource_size(res)); if (!mcbsp->io_base) { ret = -ENOMEM; goto err_ioremap; } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); + if (!res) + mcbsp->phys_dma_base = mcbsp->phys_base; + else + mcbsp->phys_dma_base = res->start; + /* Default I/O is IRQ based */ mcbsp->io_type = OMAP_MCBSP_IRQ_IO; - mcbsp->tx_irq = pdata->tx_irq; - mcbsp->rx_irq = pdata->rx_irq; - mcbsp->dma_rx_sync = pdata->dma_rx_sync; - mcbsp->dma_tx_sync = pdata->dma_tx_sync; + + mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); + mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); + + res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); + if (!res) { + dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n", + __func__, pdev->id); + ret = -ENODEV; + goto err_res; + } + mcbsp->dma_rx_sync = res->start; + + res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); + if (!res) { + dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n", + __func__, pdev->id); + ret = -ENODEV; + goto err_res; + } + mcbsp->dma_tx_sync = res->start; mcbsp->iclk = clk_get(&pdev->dev, "ick"); if (IS_ERR(mcbsp->iclk)) { ret = PTR_ERR(mcbsp->iclk); dev_err(&pdev->dev, "unable to get ick: %d\n", ret); - goto err_iclk; + goto err_res; } mcbsp->fclk = clk_get(&pdev->dev, "fck"); @@ -1817,7 +1856,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) err_fclk: clk_put(mcbsp->iclk); -err_iclk: +err_res: iounmap(mcbsp->io_base); err_ioremap: kfree(mcbsp); -- cgit v1.2.3-70-g09d2 From 3cb72fa4fed52437484a699ba78ad926ff4483c5 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 24 Feb 2011 12:51:46 -0800 Subject: OMAP2420: hwmod data: Add McBSP Add McBSP hwmod data for OMAP2420. Also add macros in prcm-common.h for idlest bit of OMAP24XX McBSP devices Signed-off-by: Charulatha V Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Shubhrajyoti D Cc: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 129 +++++++++++++++++++++++++++++ arch/arm/mach-omap2/prcm-common.h | 4 + 2 files changed, 133 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 19ad9d053de..e44ecb46551 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -109,6 +109,8 @@ static struct omap_hwmod omap2420_uart2_hwmod; static struct omap_hwmod omap2420_uart3_hwmod; static struct omap_hwmod omap2420_i2c1_hwmod; static struct omap_hwmod omap2420_i2c2_hwmod; +static struct omap_hwmod omap2420_mcbsp1_hwmod; +static struct omap_hwmod omap2420_mcbsp2_hwmod; /* l4 core -> mcspi1 interface */ static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { @@ -1390,6 +1392,129 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { + .name = "mcbsp", +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, +}; + +static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = { + { .name = "rx", .dma_req = 32 }, + { .name = "tx", .dma_req = 31 }, +}; + +static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2420_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { + &omap2420_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap2420_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), + .sdma_reqs = omap2420_mcbsp1_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap2420_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, +}; + +static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = { + { .name = "rx", .dma_req = 34 }, + { .name = "tx", .dma_req = 33 }, +}; + +static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48076000, + .pa_end = 0x480760ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap2420_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { + &omap2420_l4_core__mcbsp2, +}; + +static struct omap_hwmod omap2420_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2420_mcbsp_hwmod_class, + .mpu_irqs = omap2420_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), + .sdma_reqs = omap2420_mcbsp2_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap2420_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, @@ -1421,6 +1546,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { /* mailbox class */ &omap2420_mailbox_hwmod, + /* mcbsp class */ + &omap2420_mcbsp1_hwmod, + &omap2420_mcbsp2_hwmod, + /* mcspi class */ &omap2420_mcspi1_hwmod, &omap2420_mcspi2_hwmod, diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 87486f55978..d4af21d1b61 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -121,6 +121,10 @@ #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) #define OMAP24XX_ST_MCSPI1_SHIFT 17 #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) +#define OMAP24XX_ST_MCBSP2_SHIFT 16 +#define OMAP24XX_ST_MCBSP2_MASK (1 << 16) +#define OMAP24XX_ST_MCBSP1_SHIFT 15 +#define OMAP24XX_ST_MCBSP1_MASK (1 << 15) #define OMAP24XX_ST_GPT12_SHIFT 14 #define OMAP24XX_ST_GPT12_MASK (1 << 14) #define OMAP24XX_ST_GPT11_SHIFT 13 -- cgit v1.2.3-70-g09d2 From 37801b3df60a000cc1d65ea8b472e841dc93ea75 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 24 Feb 2011 12:51:46 -0800 Subject: OMAP2430: hwmod data: Add McBSP Add McBSP hwmod data for OMAP2430. Added a revision member inorder to facilitate the driver to differentiate between mcbsp in different omap. Signed-off-by: Charulatha V Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Shubhrajyoti D Cc: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 320 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 2 + 2 files changed, 322 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 91d2581c770..1e65a4f5117 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -51,6 +52,11 @@ static struct omap_hwmod omap2430_gpio3_hwmod; static struct omap_hwmod omap2430_gpio4_hwmod; static struct omap_hwmod omap2430_gpio5_hwmod; static struct omap_hwmod omap2430_dma_system_hwmod; +static struct omap_hwmod omap2430_mcbsp1_hwmod; +static struct omap_hwmod omap2430_mcbsp2_hwmod; +static struct omap_hwmod omap2430_mcbsp3_hwmod; +static struct omap_hwmod omap2430_mcbsp4_hwmod; +static struct omap_hwmod omap2430_mcbsp5_hwmod; static struct omap_hwmod omap2430_mcspi1_hwmod; static struct omap_hwmod omap2430_mcspi2_hwmod; static struct omap_hwmod omap2430_mcspi3_hwmod; @@ -1575,7 +1581,314 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { + .rev_offs = 0x007C, + .sysc_offs = 0x008C, + .sysc_flags = (SYSC_HAS_SOFTRESET), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap2430_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE2, +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .name = "ovr", .irq = 61 }, + { .name = "common", .irq = 64 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = { + { .name = "rx", .dma_req = 32 }, + { .name = "tx", .dma_req = 31 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2430_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { + &omap2430_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap2430_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), + .sdma_reqs = omap2430_mcbsp1_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap2430_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .name = "common", .irq = 16 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = { + { .name = "rx", .dma_req = 34 }, + { .name = "tx", .dma_req = 33 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48076000, + .pa_end = 0x480760ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap2430_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { + &omap2430_l4_core__mcbsp2, +}; + +static struct omap_hwmod omap2430_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs), + .sdma_reqs = omap2430_mcbsp2_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap2430_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, + { .name = "common", .irq = 17 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = { + { .name = "rx", .dma_req = 18 }, + { .name = "tx", .dma_req = 17 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808C000, + .pa_end = 0x4808C0ff, + .flags = ADDR_TYPE_RT + }, +}; +/* l4_core -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap2430_mcbsp3_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { + &omap2430_l4_core__mcbsp3, +}; + +static struct omap_hwmod omap2430_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs), + .sdma_reqs = omap2430_mcbsp3_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap2430_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, + { .name = "common", .irq = 18 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808E000, + .pa_end = 0x4808E0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap2430_mcbsp4_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { + &omap2430_l4_core__mcbsp4, +}; + +static struct omap_hwmod omap2430_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs), + .sdma_reqs = omap2430_mcbsp4_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs), + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, + }, + }, + .slaves = omap2430_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, + { .name = "common", .irq = 19 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap2430_mcbsp5_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp5 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { + &omap2430_l4_core__mcbsp5, +}; + +static struct omap_hwmod omap2430_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs), + .sdma_reqs = omap2430_mcbsp5_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs), + .main_clk = "mcbsp5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, + }, + }, + .slaves = omap2430_mcbsp5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, @@ -1606,6 +1919,13 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { /* dma_system class*/ &omap2430_dma_system_hwmod, + /* mcbsp class */ + &omap2430_mcbsp1_hwmod, + &omap2430_mcbsp2_hwmod, + &omap2430_mcbsp3_hwmod, + &omap2430_mcbsp4_hwmod, + &omap2430_mcbsp5_hwmod, + /* mailbox class */ &omap2430_mailbox_hwmod, diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index dc1a28299ae..64491a5385e 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -37,6 +37,8 @@ static struct platform_device omap_mcbsp##port_nr = { \ .id = OMAP_MCBSP##port_nr, \ } +#define MCBSP_CONFIG_TYPE2 0x2 + #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 -- cgit v1.2.3-70-g09d2 From dc48e5fc782f8d447aae2e82ba7453ddcf32c617 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 24 Feb 2011 15:16:49 +0530 Subject: OMAP3: hwmod data: Add McBSP Add McBSP hwmod data for OMAP3. Added a revision member inorder to facilitate the driver to differentiate between mcbsp in different omap. Signed-off-by: Charulatha V Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Shubhrajyoti D Cc: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 439 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 1 + 2 files changed, 440 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 510d5e11a4e..e1d89c0607e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "omap_hwmod_common_data.h" @@ -72,6 +73,14 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod; static struct omap_hwmod omap3xxx_dma_system_hwmod; +static struct omap_hwmod omap3xxx_mcbsp1_hwmod; +static struct omap_hwmod omap3xxx_mcbsp2_hwmod; +static struct omap_hwmod omap3xxx_mcbsp3_hwmod; +static struct omap_hwmod omap3xxx_mcbsp4_hwmod; +static struct omap_hwmod omap3xxx_mcbsp5_hwmod; +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; + /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { .master = &omap3xxx_l3_main_hwmod, @@ -1729,6 +1738,427 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, + .clockact = 0x2, +}; + +static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap3xxx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE3, +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { + { .name = "irq", .irq = 16 }, + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = { + { .name = "rx", .dma_req = 32 }, + { .name = "tx", .dma_req = 31 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap3xxx_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { + &omap3xxx_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), + .sdma_reqs = omap3xxx_mcbsp1_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { + { .name = "irq", .irq = 17 }, + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = { + { .name = "rx", .dma_req = 34 }, + { .name = "tx", .dma_req = 33 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { + &omap3xxx_l4_per__mcbsp2, +}; + +static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), + .sdma_reqs = omap3xxx_mcbsp2_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { + { .name = "irq", .irq = 22 }, + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = { + { .name = "rx", .dma_req = 18 }, + { .name = "tx", .dma_req = 17 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { + &omap3xxx_l4_per__mcbsp3, +}; + +static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), + .sdma_reqs = omap3xxx_mcbsp3_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { + { .name = "irq", .irq = 23 }, + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap3xxx_mcbsp4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { + &omap3xxx_l4_per__mcbsp4, +}; + +static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs), + .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs), + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { + { .name = "irq", .irq = 27 }, + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap3xxx_mcbsp5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp5 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { + &omap3xxx_l4_core__mcbsp5, +}; + +static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs), + .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs), + .main_clk = "mcbsp5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; +/* 'mcbsp sidetone' class */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_AUTOIDLE, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { + .name = "mcbsp_sidetone", + .sysc = &omap3xxx_mcbsp_sidetone_sysc, +}; + +/* mcbsp2_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { + { .name = "irq", .irq = 4 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x49028000, + .pa_end = 0x490280ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp2_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_sidetone_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_sidetone_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs), + .user = OCP_USER_MPU, +}; + +/* mcbsp2_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp2_sidetone, +}; + +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { + .name = "mcbsp2_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp2_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp3_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { + { .name = "irq", .irq = 5 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x4902A000, + .pa_end = 0x4902A0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp3_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_sidetone_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_sidetone_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs), + .user = OCP_USER_MPU, +}; + +/* mcbsp3_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp3_sidetone, +}; + +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { + .name = "mcbsp3_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp3_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + + /* SR common */ static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { .clkact_shift = 20, @@ -2321,6 +2751,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { /* dma_system class*/ &omap3xxx_dma_system_hwmod, + /* mcbsp class */ + &omap3xxx_mcbsp1_hwmod, + &omap3xxx_mcbsp2_hwmod, + &omap3xxx_mcbsp3_hwmod, + &omap3xxx_mcbsp4_hwmod, + &omap3xxx_mcbsp5_hwmod, + &omap3xxx_mcbsp2_sidetone_hwmod, + &omap3xxx_mcbsp3_sidetone_hwmod, + /* mailbox class */ &omap3xxx_mailbox_hwmod, diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 64491a5385e..f084b6acfbf 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -38,6 +38,7 @@ static struct platform_device omap_mcbsp##port_nr = { \ } #define MCBSP_CONFIG_TYPE2 0x2 +#define MCBSP_CONFIG_TYPE3 0x3 #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 -- cgit v1.2.3-70-g09d2 From cb7e9ded3240d717d1d24812d33b3ef2c98c084e Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:50 +0530 Subject: OMAP4: hwmod: Naming of address space Added a name to address space belonging to SDMA and MPU facilitating the driver to get the address space info by name. Added a revision member inorder to facilitate the driver to differentiate between mcbsp in different omap. Also added a platform_get_irq in probe to get irq number by index since from OMAP4, there will be a single irq line. Signed-off-by: Benoit Cousson Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 ++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 1 + arch/arm/plat-omap/mcbsp.c | 4 ++++ 3 files changed, 13 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 79a86017891..673b011403c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -2737,6 +2738,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap44xx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE4, }; /* mcbsp1 */ @@ -2752,6 +2754,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { { + .name = "mpu", .pa_start = 0x40122000, .pa_end = 0x401220ff, .flags = ADDR_TYPE_RT @@ -2770,6 +2773,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { { + .name = "dma", .pa_start = 0x49022000, .pa_end = 0x490220ff, .flags = ADDR_TYPE_RT @@ -2823,6 +2827,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { { + .name = "mpu", .pa_start = 0x40124000, .pa_end = 0x401240ff, .flags = ADDR_TYPE_RT @@ -2841,6 +2846,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { { + .name = "dma", .pa_start = 0x49024000, .pa_end = 0x490240ff, .flags = ADDR_TYPE_RT @@ -2894,6 +2900,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { { + .name = "mpu", .pa_start = 0x40126000, .pa_end = 0x401260ff, .flags = ADDR_TYPE_RT @@ -2912,6 +2919,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { { + .name = "dma", .pa_start = 0x49026000, .pa_end = 0x490260ff, .flags = ADDR_TYPE_RT diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index f084b6acfbf..afcbb7bb016 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -39,6 +39,7 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define MCBSP_CONFIG_TYPE2 0x2 #define MCBSP_CONFIG_TYPE3 0x3 +#define MCBSP_CONFIG_TYPE4 0x4 #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 5f25ae5f9c1..62bd073b0f8 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1812,6 +1812,10 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); + /* From OMAP4 there will be a single irq line */ + if (mcbsp->tx_irq == -ENXIO) + mcbsp->tx_irq = platform_get_irq(pdev, 0); + res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); if (!res) { dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n", -- cgit v1.2.3-70-g09d2 From 8b1906f12a60d377b11d8a3dd256ce0a0ef6c614 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:51 +0530 Subject: OMAP3: hwmod: add dev_attr for McBSP sidetone Since the sidetone block is tightly coupled to the mcbsp, sidetone information is directly added to mcbsp2 & 3 hwmod dev_attr. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 10 ++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 9 +++++++++ 2 files changed, 19 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e1d89c0607e..25226bf063e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1852,6 +1852,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { &omap3xxx_l4_per__mcbsp2, }; +static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { + .sidetone = "mcbsp2_sidetone", +}; + static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap3xxx_mcbsp_hwmod_class, @@ -1871,6 +1875,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { }, .slaves = omap3xxx_mcbsp2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), + .dev_attr = &omap34xx_mcbsp2_dev_attr, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -1910,6 +1915,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { &omap3xxx_l4_per__mcbsp3, }; +static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { + .sidetone = "mcbsp3_sidetone", +}; + static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap3xxx_mcbsp_hwmod_class, @@ -1929,6 +1938,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { }, .slaves = omap3xxx_mcbsp3_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), + .dev_attr = &omap34xx_mcbsp3_dev_attr, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index afcbb7bb016..1fe06372c9c 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -475,6 +475,15 @@ struct omap_mcbsp { #endif void *reg_cache; }; + +/** + * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod + * @sidetone: name of the sidetone device + */ +struct omap_mcbsp_dev_attr { + const char *sidetone; +}; + extern struct omap_mcbsp **mcbsp_ptr; extern int omap_mcbsp_count, omap_mcbsp_cache_size; -- cgit v1.2.3-70-g09d2 From 64bcbd33c7c70d0aea4e614212a2568321a0396b Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:52 +0530 Subject: OMAP2+: McBSP: hwmod adaptation for McBSP Modify OMAP2+ McBSP to use omap hwmod framework APIs Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Charulatha V Signed-off-by: Shubhrajyoti D Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 595 +++----------------------------- arch/arm/plat-omap/include/plat/mcbsp.h | 2 +- 2 files changed, 46 insertions(+), 551 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 765ebe7da72..275d6cfa0b2 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -22,10 +22,10 @@ #include #include #include +#include #include "control.h" - /* McBSP internal signal muxing functions */ void omap2_mcbsp1_mux_clkr_src(u8 mux) @@ -101,573 +101,68 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) } EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); - -/* Platform data */ - -#ifdef CONFIG_SOC_OMAP2420 -struct resource omap2420_mcbsp_res[][6] = { +struct omap_device_pm_latency omap2_mcbsp_latency[] = { { - { - .start = OMAP24XX_MCBSP1_BASE, - .end = OMAP24XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP1_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP1_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP24XX_MCBSP2_BASE, - .end = OMAP24XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP2_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP2_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, }; -#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1]) -#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res) -#else -#define omap2420_mcbsp_res NULL -#define OMAP2420_MCBSP_RES_SZ 0 -#define OMAP2420_MCBSP_COUNT 0 -#endif -#define omap2420_mcbsp_pdata NULL +static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) +{ + int id, count = 1; + char *name = "omap-mcbsp"; + struct omap_hwmod *oh_device[2]; + struct omap_mcbsp_platform_data *pdata = NULL; + struct omap_device *od; -#ifdef CONFIG_SOC_OMAP2430 -struct resource omap2430_mcbsp_res[][6] = { - { - { - .start = OMAP24XX_MCBSP1_BASE, - .end = OMAP24XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP1_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP1_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP24XX_MCBSP2_BASE, - .end = OMAP24XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP2_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP2_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP2430_MCBSP3_BASE, - .end = OMAP2430_MCBSP3_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP3_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP3_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP3_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP3_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP2430_MCBSP4_BASE, - .end = OMAP2430_MCBSP4_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP4_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP4_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP4_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP4_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP2430_MCBSP5_BASE, - .end = OMAP2430_MCBSP5_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP5_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP5_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP5_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP5_TX, - .flags = IORESOURCE_DMA, - }, - }, -}; -#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1]) -#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res) -#else -#define omap2430_mcbsp_res NULL -#define OMAP2430_MCBSP_RES_SZ 0 -#define OMAP2430_MCBSP_COUNT 0 -#endif + sscanf(oh->name, "mcbsp%d", &id); -#define omap2430_mcbsp_pdata NULL + pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL); + if (!pdata) { + pr_err("%s: No memory for mcbsp\n", __func__); + return -ENOMEM; + } -#ifdef CONFIG_ARCH_OMAP3 -struct resource omap34xx_mcbsp_res[][7] = { - { - { - .start = OMAP34XX_MCBSP1_BASE, - .end = OMAP34XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP1_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP1_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP2_BASE, - .end = OMAP34XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "sidetone", - .start = OMAP34XX_MCBSP2_ST_BASE, - .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP2_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP2_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP3_BASE, - .end = OMAP34XX_MCBSP3_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "sidetone", - .start = OMAP34XX_MCBSP3_ST_BASE, - .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP3_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP3_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP3_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP3_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP4_BASE, - .end = OMAP34XX_MCBSP4_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP4_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP4_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP4_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP4_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP5_BASE, - .end = OMAP34XX_MCBSP5_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP5_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP5_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP5_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP5_TX, - .flags = IORESOURCE_DMA, - }, - }, -}; + if (oh->class->rev == MCBSP_CONFIG_TYPE3) { + if (id == 2) + /* The FIFO has 1024 + 256 locations */ + pdata->buffer_size = 0x500; + else + /* The FIFO has 128 locations */ + pdata->buffer_size = 0x80; + } -static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, - { - .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ - }, - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, -}; -#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1]) -#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res) -#else -#define omap34xx_mcbsp_pdata NULL -#define omap34XX_mcbsp_res NULL -#define OMAP34XX_MCBSP_RES_SZ 0 -#define OMAP34XX_MCBSP_COUNT 0 -#endif + oh_device[0] = oh; -struct resource omap44xx_mcbsp_res[][6] = { - { - { - .name = "mpu", - .start = OMAP44XX_MCBSP1_BASE, - .end = OMAP44XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "dma", - .start = OMAP44XX_MCBSP1_DMA_BASE, - .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP1, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .name = "mpu", - .start = OMAP44XX_MCBSP2_BASE, - .end = OMAP44XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "dma", - .start = OMAP44XX_MCBSP2_DMA_BASE, - .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP2, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .name = "mpu", - .start = OMAP44XX_MCBSP3_BASE, - .end = OMAP44XX_MCBSP3_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "dma", - .start = OMAP44XX_MCBSP3_DMA_BASE, - .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP3, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP3_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP3_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP44XX_MCBSP4_BASE, - .end = OMAP44XX_MCBSP4_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP4, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP4_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP4_TX, - .flags = IORESOURCE_DMA, - }, - }, -}; -#define omap44xx_mcbsp_pdata NULL -#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1]) -#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res) + if (oh->dev_attr) { + oh_device[1] = omap_hwmod_lookup(( + (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); + count++; + } + od = omap_device_build_ss(name, id, oh_device, count, pdata, + sizeof(*pdata), omap2_mcbsp_latency, + ARRAY_SIZE(omap2_mcbsp_latency), false); + kfree(pdata); + if (IS_ERR(od)) { + pr_err("%s: Cant build omap_device for %s:%s.\n", __func__, + name, oh->name); + return PTR_ERR(od); + } + omap_mcbsp_count++; + return 0; +} static int __init omap2_mcbsp_init(void) { - if (cpu_is_omap2420()) - omap_mcbsp_count = OMAP2420_MCBSP_COUNT; - else if (cpu_is_omap2430()) - omap_mcbsp_count = OMAP2430_MCBSP_COUNT; - else if (cpu_is_omap34xx()) - omap_mcbsp_count = OMAP34XX_MCBSP_COUNT; - else if (cpu_is_omap44xx()) - omap_mcbsp_count = OMAP44XX_MCBSP_COUNT; + omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); if (!mcbsp_ptr) return -ENOMEM; - if (cpu_is_omap2420()) - omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0], - OMAP2420_MCBSP_RES_SZ, - omap2420_mcbsp_pdata, - OMAP2420_MCBSP_COUNT); - if (cpu_is_omap2430()) - omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0], - OMAP2420_MCBSP_RES_SZ, - omap2430_mcbsp_pdata, - OMAP2430_MCBSP_COUNT); - if (cpu_is_omap34xx()) - omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0], - OMAP34XX_MCBSP_RES_SZ, - omap34xx_mcbsp_pdata, - OMAP34XX_MCBSP_COUNT); - if (cpu_is_omap44xx()) - omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0], - OMAP44XX_MCBSP_RES_SZ, - omap44xx_mcbsp_pdata, - OMAP44XX_MCBSP_COUNT); - return omap_mcbsp_init(); } arch_initcall(omap2_mcbsp_init); diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 1fe06372c9c..c6cabfc77a1 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -421,8 +421,8 @@ struct omap_mcbsp_platform_data { #ifdef CONFIG_ARCH_OMAP3 /* Sidetone block for McBSP 2 and 3 */ unsigned long phys_base_st; - u16 buffer_size; #endif + u16 buffer_size; }; struct omap_mcbsp_st_data { -- cgit v1.2.3-70-g09d2 From e95496d4acadd0b72c4947be61e8d44700fdaae7 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:54 +0530 Subject: OMAP: McBSP: Add pm runtime support Add pm runtime support for McBSP driver. Reference to fclk is not removed because it is required when the functional clock is switched from one source to another. Signed-off-by: Kishon Vijay Abraham I Cc: Paul Walmsley Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 5 +++-- arch/arm/plat-omap/include/plat/mcbsp.h | 1 - arch/arm/plat-omap/mcbsp.c | 23 ++++++----------------- 3 files changed, 9 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 275d6cfa0b2..4ada6a9ca4a 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "control.h" @@ -83,7 +84,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) return -EINVAL; } - clk_disable(mcbsp->fclk); + pm_runtime_put_sync(mcbsp->dev); r = clk_set_parent(mcbsp->fclk, fck_src); if (IS_ERR_VALUE(r)) { @@ -93,7 +94,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) return -EINVAL; } - clk_enable(mcbsp->fclk); + pm_runtime_get_sync(mcbsp->dev); clk_put(fck_src); diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index c6cabfc77a1..964a940c475 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -465,7 +465,6 @@ struct omap_mcbsp { /* Protect the field .free, while checking if the mcbsp is in use */ spinlock_t lock; struct omap_mcbsp_platform_data *pdata; - struct clk *iclk; struct clk *fclk; #ifdef CONFIG_ARCH_OMAP3 struct omap_mcbsp_st_data *st_data; diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 67ec74ea253..6d230164b4f 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -28,6 +28,7 @@ #include #include #include +#include /* XXX These "sideways" includes are a sign that something is wrong */ #include "../mach-omap2/cm2xxx_3xxx.h" @@ -757,8 +758,7 @@ int omap_mcbsp_request(unsigned int id) if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) mcbsp->pdata->ops->request(id); - clk_enable(mcbsp->iclk); - clk_enable(mcbsp->fclk); + pm_runtime_get_sync(mcbsp->dev); /* Do procedure specific to omap34xx arch, if applicable */ omap34xx_mcbsp_request(mcbsp); @@ -806,8 +806,7 @@ err_clk_disable: /* Do procedure specific to omap34xx arch, if applicable */ omap34xx_mcbsp_free(mcbsp); - clk_disable(mcbsp->fclk); - clk_disable(mcbsp->iclk); + pm_runtime_put_sync(mcbsp->dev); spin_lock(&mcbsp->lock); mcbsp->free = true; @@ -837,8 +836,7 @@ void omap_mcbsp_free(unsigned int id) /* Do procedure specific to omap34xx arch, if applicable */ omap34xx_mcbsp_free(mcbsp); - clk_disable(mcbsp->fclk); - clk_disable(mcbsp->iclk); + pm_runtime_put_sync(mcbsp->dev); if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { /* Free IRQs */ @@ -1827,32 +1825,24 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) } mcbsp->dma_tx_sync = res->start; - mcbsp->iclk = clk_get(&pdev->dev, "ick"); - if (IS_ERR(mcbsp->iclk)) { - ret = PTR_ERR(mcbsp->iclk); - dev_err(&pdev->dev, "unable to get ick: %d\n", ret); - goto err_res; - } - mcbsp->fclk = clk_get(&pdev->dev, "fck"); if (IS_ERR(mcbsp->fclk)) { ret = PTR_ERR(mcbsp->fclk); dev_err(&pdev->dev, "unable to get fck: %d\n", ret); - goto err_fclk; + goto err_res; } mcbsp->pdata = pdata; mcbsp->dev = &pdev->dev; mcbsp_ptr[id] = mcbsp; platform_set_drvdata(pdev, mcbsp); + pm_runtime_enable(mcbsp->dev); /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ omap34xx_device_init(mcbsp); return 0; -err_fclk: - clk_put(mcbsp->iclk); err_res: iounmap(mcbsp->io_base); err_ioremap: @@ -1875,7 +1865,6 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) omap34xx_device_exit(mcbsp); clk_put(mcbsp->fclk); - clk_put(mcbsp->iclk); iounmap(mcbsp->io_base); kfree(mcbsp); -- cgit v1.2.3-70-g09d2 From 9504ba64f014cfd50a64106e49c8ba729522db5b Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:55 +0530 Subject: OMAP: McBSP: APIs to pass DMA params from McBSP driver to client drivers After McBSP driver is hwmod adapted, the information about the hw would be obtained from the hwmod database by the mcbsp driver. Since DMA programming is handled by the client driver, APIs are provided to pass the DMA channel number and base address of data register required by the client driver for DMA programming. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Charulatha V Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 2 ++ arch/arm/plat-omap/include/plat/mcbsp.h | 7 ++++ arch/arm/plat-omap/mcbsp.c | 64 +++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 4ada6a9ca4a..565b9064a32 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -126,6 +126,8 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) return -ENOMEM; } + pdata->mcbsp_config_type = oh->class->rev; + if (oh->class->rev == MCBSP_CONFIG_TYPE3) { if (id == 2) /* The FIFO has 1024 + 256 locations */ diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 964a940c475..21c9b104c61 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -81,6 +81,8 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP_MCBSP_REG_DRR1 0x02 #define OMAP_MCBSP_REG_DXR2 0x04 #define OMAP_MCBSP_REG_DXR1 0x06 +#define OMAP_MCBSP_REG_DRR 0x02 +#define OMAP_MCBSP_REG_DXR 0x06 #define OMAP_MCBSP_REG_SPCR2 0x08 #define OMAP_MCBSP_REG_SPCR1 0x0a #define OMAP_MCBSP_REG_RCR2 0x0c @@ -423,6 +425,7 @@ struct omap_mcbsp_platform_data { unsigned long phys_base_st; #endif u16 buffer_size; + unsigned int mcbsp_config_type; }; struct omap_mcbsp_st_data { @@ -473,6 +476,7 @@ struct omap_mcbsp { u16 max_rx_thres; #endif void *reg_cache; + unsigned int mcbsp_config_type; }; /** @@ -541,6 +545,9 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); void omap2_mcbsp1_mux_clkr_src(u8 mux); void omap2_mcbsp1_mux_fsr_src(u8 mux); +int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); +int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); + #ifdef CONFIG_ARCH_OMAP3 /* Sidetone specific API */ int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 6d230164b4f..d598d9fd65a 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -229,6 +229,69 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) } EXPORT_SYMBOL(omap_mcbsp_config); +/** + * omap_mcbsp_dma_params - returns the dma channel number + * @id - mcbsp id + * @stream - indicates the direction of data flow (rx or tx) + * + * Returns the dma channel number for the rx channel or tx channel + * based on the value of @stream for the requested mcbsp given by @id + */ +int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream) +{ + struct omap_mcbsp *mcbsp; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + if (stream) + return mcbsp->dma_rx_sync; + else + return mcbsp->dma_tx_sync; +} +EXPORT_SYMBOL(omap_mcbsp_dma_ch_params); + +/** + * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register + * @id - mcbsp id + * @stream - indicates the direction of data flow (rx or tx) + * + * Returns the address of mcbsp data transmit register or data receive register + * to be used by DMA for transferring/receiving data based on the value of + * @stream for the requested mcbsp given by @id + */ +int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream) +{ + struct omap_mcbsp *mcbsp; + int data_reg; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + data_reg = mcbsp->phys_dma_base; + + if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) { + if (stream) + data_reg += OMAP_MCBSP_REG_DRR1; + else + data_reg += OMAP_MCBSP_REG_DXR1; + } else { + if (stream) + data_reg += OMAP_MCBSP_REG_DRR; + else + data_reg += OMAP_MCBSP_REG_DXR; + } + + return data_reg; +} +EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); + #ifdef CONFIG_ARCH_OMAP3 static struct omap_device *find_omap_device_by_dev(struct device *dev) { @@ -1835,6 +1898,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->pdata = pdata; mcbsp->dev = &pdev->dev; mcbsp_ptr[id] = mcbsp; + mcbsp->mcbsp_config_type = pdata->mcbsp_config_type; platform_set_drvdata(pdev, mcbsp); pm_runtime_enable(mcbsp->dev); -- cgit v1.2.3-70-g09d2 From 92e753d7984db36f0a3c0bbf0f377da114768775 Mon Sep 17 00:00:00 2001 From: David Cohen Date: Wed, 16 Feb 2011 19:35:50 +0000 Subject: OMAP2+: IOMMU: don't print fault warning on specific layer IOMMU upper layer and user are responsible to handle a fault and to define whether it will end up as an error or not. OMAP2+ specific layer should not print anything in such case. Signed-off-by: David Cohen Acked-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/iommu2.c | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index 14ee686b649..49a1e5e841c 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -145,15 +145,7 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on) static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) { - int i; u32 stat, da; - const char *err_msg[] = { - "tlb miss", - "translation fault", - "emulation miss", - "table walk fault", - "multi hit fault", - }; stat = iommu_read_reg(obj, MMU_IRQSTATUS); stat &= MMU_IRQ_MASK; @@ -163,14 +155,6 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) da = iommu_read_reg(obj, MMU_FAULT_AD); *ra = da; - dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); - - for (i = 0; i < ARRAY_SIZE(err_msg); i++) { - if (stat & (1 << i)) - printk("%s ", err_msg[i]); - } - printk("\n"); - iommu_write_reg(obj, stat, MMU_IRQSTATUS); return stat; -- cgit v1.2.3-70-g09d2 From d594f1f31afe13edd8c02f3854a65cc58cfb3b74 Mon Sep 17 00:00:00 2001 From: David Cohen Date: Wed, 16 Feb 2011 19:35:51 +0000 Subject: omap: IOMMU: add support to callback during fault handling Add support to register an isr for IOMMU fault situations and adapt it to allow such (*isr)() to be used as fault callback. Drivers using IOMMU module might want to be informed when errors happen in order to debug it or react. Signed-off-by: David Cohen Acked-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/iommu2.c | 17 +++++++++-- arch/arm/plat-omap/include/plat/iommu.h | 14 ++++++++- arch/arm/plat-omap/iommu.c | 52 +++++++++++++++++++++++---------- 3 files changed, 65 insertions(+), 18 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index 49a1e5e841c..adb083e41ac 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -146,18 +146,31 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on) static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) { u32 stat, da; + u32 errs = 0; stat = iommu_read_reg(obj, MMU_IRQSTATUS); stat &= MMU_IRQ_MASK; - if (!stat) + if (!stat) { + *ra = 0; return 0; + } da = iommu_read_reg(obj, MMU_FAULT_AD); *ra = da; + if (stat & MMU_IRQ_TLBMISS) + errs |= OMAP_IOMMU_ERR_TLB_MISS; + if (stat & MMU_IRQ_TRANSLATIONFAULT) + errs |= OMAP_IOMMU_ERR_TRANS_FAULT; + if (stat & MMU_IRQ_EMUMISS) + errs |= OMAP_IOMMU_ERR_EMU_MISS; + if (stat & MMU_IRQ_TABLEWALKFAULT) + errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT; + if (stat & MMU_IRQ_MULTIHITFAULT) + errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT; iommu_write_reg(obj, stat, MMU_IRQSTATUS); - return stat; + return errs; } static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 19cbb5e9ece..174f1b9c8c0 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -31,6 +31,7 @@ struct iommu { struct clk *clk; void __iomem *regbase; struct device *dev; + void *isr_priv; unsigned int refcount; struct mutex iommu_lock; /* global for this whole object */ @@ -47,7 +48,7 @@ struct iommu { struct list_head mmap; struct mutex mmap_lock; /* protect mmap */ - int (*isr)(struct iommu *obj); + int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv); void *ctx; /* iommu context: registres saved area */ u32 da_start; @@ -109,6 +110,13 @@ struct iommu_platform_data { u32 da_end; }; +/* IOMMU errors */ +#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0) +#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1) +#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2) +#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3) +#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4) + #if defined(CONFIG_ARCH_OMAP1) #error "iommu for this processor not implemented yet" #else @@ -161,6 +169,10 @@ extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); extern struct iommu *iommu_get(const char *name); extern void iommu_put(struct iommu *obj); +extern int iommu_set_isr(const char *name, + int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, + void *priv), + void *isr_priv); extern void iommu_save_ctx(struct iommu *obj); extern void iommu_restore_ctx(struct iommu *obj); diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 4b3218eaf3e..e3eb0380090 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -783,25 +783,19 @@ static void iopgtable_clear_entry_all(struct iommu *obj) */ static irqreturn_t iommu_fault_handler(int irq, void *data) { - u32 stat, da; + u32 da, errs; u32 *iopgd, *iopte; - int err = -EIO; struct iommu *obj = data; if (!obj->refcount) return IRQ_NONE; - /* Dynamic loading TLB or PTE */ - if (obj->isr) - err = obj->isr(obj); - - if (!err) - return IRQ_HANDLED; - clk_enable(obj->clk); - stat = iommu_report_fault(obj, &da); + errs = iommu_report_fault(obj, &da); clk_disable(obj->clk); - if (!stat) + + /* Fault callback or TLB/PTE Dynamic loading */ + if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) return IRQ_HANDLED; iommu_disable(obj); @@ -809,15 +803,16 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) iopgd = iopgd_offset(obj, da); if (!iopgd_is_table(*iopgd)) { - dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", obj->name, - da, iopgd, *iopgd); + dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " + "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); return IRQ_NONE; } iopte = iopte_offset(iopgd, da); - dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", - obj->name, da, iopgd, *iopgd, iopte, *iopte); + dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " + "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, + iopte, *iopte); return IRQ_NONE; } @@ -920,6 +915,33 @@ void iommu_put(struct iommu *obj) } EXPORT_SYMBOL_GPL(iommu_put); +int iommu_set_isr(const char *name, + int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, + void *priv), + void *isr_priv) +{ + struct device *dev; + struct iommu *obj; + + dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, + device_match_by_alias); + if (!dev) + return -ENODEV; + + obj = to_iommu(dev); + mutex_lock(&obj->iommu_lock); + if (obj->refcount != 0) { + mutex_unlock(&obj->iommu_lock); + return -EBUSY; + } + obj->isr = isr; + obj->isr_priv = isr_priv; + mutex_unlock(&obj->iommu_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(iommu_set_isr); + /* * OMAP Device MMU(IOMMU) detection */ -- cgit v1.2.3-70-g09d2 From bd061715392ccd72a398577615e856175d2b7b2b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 25 Feb 2011 10:11:15 -0800 Subject: omap: Fix compile if MTD_NAND_OMAP2 is not selected Fix compile if MTD_NAND_OMAP2 is not selected Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index c32c06828f0..729892fdcf2 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -154,7 +154,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, } #else void -__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) +__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type) { } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ -- cgit v1.2.3-70-g09d2 From 589541c0bfb1426ad39c7b59c0372346bcf84229 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Mon, 21 Feb 2011 08:42:36 +0200 Subject: omap: rx51: Add SI4713 FM transmitter Add SI4713 FM transmitter supplies, platform data and setup to RX-51/N900. It is connected to line output signals of TLV320AIC34 codec A part. Driver can be either built-in or a module. It can be tuned with v4l2-ctl from ivtv-utils. Following examples illustrate the use of it: v4l2-ctl -d /dev/radio0 --set-ctrl=mute=0 (power up) v4l2-ctl -d /dev/radio0 -f 107900 (tune 107.9 MHz) v4l2-ctl -d /dev/radio0 --set-ctrl=mute=1 (power down) Signed-off-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-rx51-peripherals.c | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index e75e240cad6..d0998f81269 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -36,6 +36,8 @@ #include #include +#include +#include #include <../drivers/staging/iio/light/tsl2563.h> @@ -47,6 +49,8 @@ #define RX51_WL1251_POWER_GPIO 87 #define RX51_WL1251_IRQ_GPIO 42 +#define RX51_FMTX_RESET_GPIO 163 +#define RX51_FMTX_IRQ 53 /* list all spi devices here */ enum { @@ -357,10 +361,14 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = { REGULATOR_SUPPLY("DVDD", "2-0018"), REGULATOR_SUPPLY("IOVDD", "2-0019"), REGULATOR_SUPPLY("DVDD", "2-0019"), + /* Si4713 IO supply */ + REGULATOR_SUPPLY("vio", "2-0063"), }; static struct regulator_consumer_supply rx51_vaux1_consumers[] = { REGULATOR_SUPPLY("vdds_sdi", "omapdss"), + /* Si4713 supply */ + REGULATOR_SUPPLY("vdd", "2-0063"), }; static struct regulator_consumer_supply rx51_vdac_supply[] = { @@ -511,6 +519,41 @@ static struct regulator_init_data rx51_vio = { .consumer_supplies = rx51_vio_supplies, }; +static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = { + .gpio_reset = RX51_FMTX_RESET_GPIO, +}; + +static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = { + I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH), + .platform_data = &rx51_si4713_i2c_data, +}; + +static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = { + .i2c_bus = 2, + .subdev_board_info = &rx51_si4713_board_info, +}; + +static struct platform_device rx51_si4713_dev __initdata_or_module = { + .name = "radio-si4713", + .id = -1, + .dev = { + .platform_data = &rx51_si4713_data, + }, +}; + +static __init void rx51_init_si4713(void) +{ + int err; + + err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq"); + if (err) { + printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err); + return; + } + rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ); + platform_device_register(&rx51_si4713_dev); +} + static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) { /* FIXME this gpio setup is just a placeholder for now */ @@ -921,6 +964,7 @@ void __init rx51_peripherals_init(void) board_smc91x_init(); rx51_add_gpio_keys(); rx51_init_wl1251(); + rx51_init_si4713(); spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); -- cgit v1.2.3-70-g09d2 From e0530460f6bc268b446040f1973d427d21f042d9 Mon Sep 17 00:00:00 2001 From: "Radek PilaÅ™ (Mrkva)" Date: Thu, 24 Feb 2011 19:02:49 +0100 Subject: OMAP3 Touchbook: fix board initialization init_early hook runs too early for omap3_mux_init(), so the board won't boot. Moved to init_machine, then it works just fine. Signed-off-by: Radek Pilar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3touchbook.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 6a60f79dccc..a35afe2227d 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -417,7 +417,6 @@ static struct omap_board_mux board_mux[] __initdata = { static void __init omap3_touchbook_init_early(void) { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_board_config = omap3_touchbook_config; omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); omap2_init_common_infrastructure(); @@ -514,6 +513,7 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_touchbook_init(void) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); pm_power_off = omap3_touchbook_poweroff; omap3_touchbook_i2c_init(); -- cgit v1.2.3-70-g09d2 From e41cccfe794d188b0ae7f17f01692bcbc0e0dc87 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 24 Feb 2011 14:36:03 -0800 Subject: omap2+: Minimize board specific init_early calls We should only call init_common_infrastructure and init_common_devices from init_early. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 5 +++-- arch/arm/mach-omap2/board-3430sdp.c | 6 +++--- arch/arm/mach-omap2/board-3630sdp.c | 4 ++-- arch/arm/mach-omap2/board-4430sdp.c | 5 +++-- arch/arm/mach-omap2/board-am3517crane.c | 6 +++--- arch/arm/mach-omap2/board-am3517evm.c | 10 +++++----- arch/arm/mach-omap2/board-apollon.c | 4 ++-- arch/arm/mach-omap2/board-cm-t35.c | 11 +++++------ arch/arm/mach-omap2/board-cm-t3517.c | 5 ++--- arch/arm/mach-omap2/board-generic.c | 4 ++-- arch/arm/mach-omap2/board-h4.c | 5 +++-- arch/arm/mach-omap2/board-ldp.c | 4 ++-- arch/arm/mach-omap2/board-omap3evm.c | 5 +++-- arch/arm/mach-omap2/board-omap3stalker.c | 4 ++-- arch/arm/mach-omap2/board-omap3touchbook.c | 5 +++-- arch/arm/mach-omap2/board-overo.c | 4 ++-- arch/arm/mach-omap2/board-rx51.c | 6 +++--- arch/arm/mach-omap2/board-ti8168evm.c | 4 ++-- 18 files changed, 50 insertions(+), 47 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index cc42d474c44..59de1dc5d6b 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -142,8 +142,6 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = { static void __init omap_2430sdp_init_early(void) { - omap_board_config = sdp2430_config; - omap_board_config_size = ARRAY_SIZE(sdp2430_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -246,6 +244,9 @@ static void __init omap_2430sdp_init(void) omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); + omap_board_config = sdp2430_config; + omap_board_config_size = ARRAY_SIZE(sdp2430_config); + omap2430_i2c_init(); platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 8950ecc9b94..b12b62064e7 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -315,9 +315,6 @@ static struct omap_board_config_kernel sdp3430_config[] __initdata = { static void __init omap_3430sdp_init_early(void) { - omap_board_config = sdp3430_config; - omap_board_config_size = ARRAY_SIZE(sdp3430_config); - omap3_pm_init_cpuidle(omap3_cpuidle_params_table); omap2_init_common_infrastructure(); omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); } @@ -788,6 +785,9 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap_3430sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_board_config = sdp3430_config; + omap_board_config_size = ARRAY_SIZE(sdp3430_config); + omap3_pm_init_cpuidle(omap3_cpuidle_params_table); omap3430_i2c_init(); omap_display_init(&sdp3430_dss_data); if (omap_rev() > OMAP3430_REV_ES1_0) diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 8d1c4358ecf..c4e22b32e47 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -72,8 +72,6 @@ static struct omap_board_config_kernel sdp_config[] __initdata = { static void __init omap_sdp_init_early(void) { - omap_board_config = sdp_config; - omap_board_config_size = ARRAY_SIZE(sdp_config); omap2_init_common_infrastructure(); omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, h8mbx00u0mer0em_sdrc_params); @@ -206,6 +204,8 @@ static struct flash_partitions sdp_flash_partitions[] = { static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); + omap_board_config = sdp_config; + omap_board_config_size = ARRAY_SIZE(sdp_config); zoom_peripherals_init(); zoom_display_init(); board_smc91x_init(); diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 1a943be822c..81ef97961ed 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -325,8 +325,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = { static void __init omap_4430sdp_init_early(void) { - omap_board_config = sdp4430_config; - omap_board_config_size = ARRAY_SIZE(sdp4430_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); #ifdef CONFIG_OMAP_32K_TIMER @@ -640,6 +638,9 @@ static void __init omap_4430sdp_init(void) package = OMAP_PACKAGE_CBL; omap4_mux_init(board_mux, package); + omap_board_config = sdp4430_config; + omap_board_config_size = ARRAY_SIZE(sdp4430_config); + omap4_i2c_init(); omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index ae3a83d47da..f53bbb2c347 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -51,9 +51,6 @@ static struct omap_board_mux board_mux[] __initdata = { static void __init am3517_crane_init_early(void) { - omap_board_config = am3517_crane_config; - omap_board_config_size = ARRAY_SIZE(am3517_crane_config); - omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -76,6 +73,9 @@ static void __init am3517_crane_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); + omap_board_config = am3517_crane_config; + omap_board_config_size = ARRAY_SIZE(am3517_crane_config); + /* Configure GPIO for EHCI port */ if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 634fe65b33c..30ec4519326 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -381,13 +381,8 @@ static struct omap_dss_board_info am3517_evm_dss_data = { /* * Board initialization */ -static struct omap_board_config_kernel am3517_evm_config[] __initdata = { -}; - static void __init am3517_evm_init_early(void) { - omap_board_config = am3517_evm_config; - omap_board_config_size = ARRAY_SIZE(am3517_evm_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -481,8 +476,13 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata) platform_device_register(&am3517_hecc_device); } +static struct omap_board_config_kernel am3517_evm_config[] __initdata = { +}; + static void __init am3517_evm_init(void) { + omap_board_config = am3517_evm_config; + omap_board_config_size = ARRAY_SIZE(am3517_evm_config); omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); am3517_evm_i2c_init(); diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 4ef4aad4e71..f4f8374a029 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -276,8 +276,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = { static void __init omap_apollon_init_early(void) { - omap_board_config = apollon_config; - omap_board_config_size = ARRAY_SIZE(apollon_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -319,6 +317,8 @@ static void __init omap_apollon_init(void) u32 v; omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); + omap_board_config = apollon_config; + omap_board_config_size = ARRAY_SIZE(apollon_config); apollon_init_smc91x(); apollon_led_init(); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 7311824be99..27bea540ccb 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -668,14 +668,8 @@ static void __init cm_t35_init_i2c(void) ARRAY_SIZE(cm_t35_i2c_boardinfo)); } -static struct omap_board_config_kernel cm_t35_config[] __initdata = { -}; - static void __init cm_t35_init_early(void) { - omap_board_config = cm_t35_config; - omap_board_config_size = ARRAY_SIZE(cm_t35_config); - omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); @@ -785,8 +779,13 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; +static struct omap_board_config_kernel cm_t35_config[] __initdata = { +}; + static void __init cm_t35_init(void) { + omap_board_config = cm_t35_config; + omap_board_config_size = ARRAY_SIZE(cm_t35_config); omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); omap_serial_init(); cm_t35_init_i2c(); diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 38bef6d004c..9da6e8240e8 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -256,9 +256,6 @@ static struct omap_board_config_kernel cm_t3517_config[] __initdata = { static void __init cm_t3517_init_early(void) { - omap_board_config = cm_t3517_config; - omap_board_config_size = ARRAY_SIZE(cm_t3517_config); - omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -293,6 +290,8 @@ static void __init cm_t3517_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); + omap_board_config = cm_t3517_config; + omap_board_config_size = ARRAY_SIZE(cm_t3517_config); cm_t3517_init_leds(); cm_t3517_init_nand(); cm_t3517_init_rtc(); diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 682da9251db..73e3c31e850 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -35,8 +35,6 @@ static struct omap_board_config_kernel generic_config[] = { static void __init omap_generic_init_early(void) { - omap_board_config = generic_config; - omap_board_config_size = ARRAY_SIZE(generic_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -44,6 +42,8 @@ static void __init omap_generic_init_early(void) static void __init omap_generic_init(void) { omap_serial_init(); + omap_board_config = generic_config; + omap_board_config_size = ARRAY_SIZE(generic_config); } static void __init omap_generic_map_io(void) diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index f6a3872f72f..7e6bf4fa153 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -292,8 +292,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = { static void __init omap_h4_init_early(void) { - omap_board_config = h4_config; - omap_board_config_size = ARRAY_SIZE(h4_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -334,6 +332,9 @@ static void __init omap_h4_init(void) { omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); + omap_board_config = h4_config; + omap_board_config_size = ARRAY_SIZE(h4_config); + /* * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index a3fae5697a7..a69e59455ee 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -290,8 +290,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = { static void __init omap_ldp_init_early(void) { - omap_board_config = ldp_config; - omap_board_config_size = ARRAY_SIZE(ldp_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -422,6 +420,8 @@ static struct mtd_partition ldp_nand_partitions[] = { static void __init omap_ldp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_board_config = ldp_config; + omap_board_config_size = ARRAY_SIZE(ldp_config); ldp_init_smsc911x(); omap_i2c_init(); platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 5364147892c..3d9b58a53c9 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -732,8 +732,6 @@ static struct omap_board_config_kernel omap3_evm_config[] __initdata = { static void __init omap3_evm_init_early(void) { - omap_board_config = omap3_evm_config; - omap_board_config_size = ARRAY_SIZE(omap3_evm_config); omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); } @@ -824,6 +822,9 @@ static void __init omap3_evm_init(void) else omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB); + omap_board_config = omap3_evm_config; + omap_board_config_size = ARRAY_SIZE(omap3_evm_config); + omap3_evm_i2c_init(); omap_display_init(&omap3_evm_dss_data); diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 07006c323fc..fd8b7649b14 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -581,8 +581,6 @@ static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { static void __init omap3_stalker_init_early(void) { - omap_board_config = omap3_stalker_config; - omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); } @@ -629,6 +627,8 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_stalker_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); + omap_board_config = omap3_stalker_config; + omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); omap3_stalker_i2c_init(); diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index a35afe2227d..8e2a7ba4153 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -417,8 +417,6 @@ static struct omap_board_mux board_mux[] __initdata = { static void __init omap3_touchbook_init_early(void) { - omap_board_config = omap3_touchbook_config; - omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); @@ -514,6 +512,9 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_touchbook_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_board_config = omap3_touchbook_config; + omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); + pm_power_off = omap3_touchbook_poweroff; omap3_touchbook_i2c_init(); diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index a33ec0edec1..d480ddb3952 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -411,8 +411,6 @@ static struct omap_board_config_kernel overo_config[] __initdata = { static void __init overo_init_early(void) { - omap_board_config = overo_config; - omap_board_config_size = ARRAY_SIZE(overo_config); omap2_init_common_infrastructure(); omap2_init_common_devices(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); @@ -448,6 +446,8 @@ static struct omap_musb_board_data musb_board_data = { static void __init overo_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_board_config = overo_config; + omap_board_config_size = ARRAY_SIZE(overo_config); overo_i2c_init(); platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); omap_serial_init(); diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 3cf72fe6d75..e964895b80e 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -102,9 +102,6 @@ static void __init rx51_init_early(void) { struct omap_sdrc_params *sdrc_params; - omap_board_config = rx51_config; - omap_board_config_size = ARRAY_SIZE(rx51_config); - omap3_pm_init_cpuidle(rx51_cpuidle_params); omap2_init_common_infrastructure(); sdrc_params = nokia_get_sdram_timings(); omap2_init_common_devices(sdrc_params, sdrc_params); @@ -127,6 +124,9 @@ static struct omap_musb_board_data musb_board_data = { static void __init rx51_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_board_config = rx51_config; + omap_board_config_size = ARRAY_SIZE(rx51_config); + omap3_pm_init_cpuidle(rx51_cpuidle_params); omap_serial_init(); usb_musb_init(&musb_board_data); rx51_peripherals_init(); diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index f2b097190e0..09fa7bfff8d 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -29,8 +29,6 @@ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = { static void __init ti8168_init_early(void) { - omap_board_config = ti8168_evm_config; - omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); omap2_init_common_infrastructure(); omap2_init_common_devices(NULL, NULL); } @@ -43,6 +41,8 @@ static void __init ti8168_evm_init_irq(void) static void __init ti8168_evm_init(void) { omap_serial_init(); + omap_board_config = ti8168_evm_config; + omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); } static void __init ti8168_evm_map_io(void) -- cgit v1.2.3-70-g09d2 From 3673d1ef5dc94d8b942c33fe1895a0ff52efbc3c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 16:06:46 -0700 Subject: OMAP: powerdomain: remove unused func declaration Trivial fix to remove the unused function declaration from the powerdomain header. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/powerdomain.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index c66431edfeb..0b7a357cb38 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -165,7 +165,6 @@ struct pwrdm_ops { int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); }; -void pwrdm_fw_init(void); void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); struct powerdomain *pwrdm_lookup(const char *name); -- cgit v1.2.3-70-g09d2 From 32d4034eea9c5c2b2edc365e1a0787c8f5b84c3c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 16:06:47 -0700 Subject: OMAP: clockdomain: Infrastructure to put arch specific code Put infrastructure in place, so arch specific func pointers can be hooked up to the platform-independent part of the framework. This is in preparation of splitting the clockdomain framework into platform-independent part (for all omaps) and platform-specific parts. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clockdomain.c | 10 ++++++- arch/arm/mach-omap2/clockdomain.h | 37 +++++++++++++++++++++++- arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 2 +- arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +- 4 files changed, 47 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 58e42f76603..f70b06ae866 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -44,6 +44,7 @@ static LIST_HEAD(clkdm_list); /* array of clockdomain deps to be added/removed when clkdm in hwsup mode */ static struct clkdm_autodep *autodeps; +static struct clkdm_ops *arch_clkdm; /* Private functions */ @@ -292,6 +293,7 @@ static void _disable_hwsup(struct clockdomain *clkdm) * clkdm_init - set up the clockdomain layer * @clkdms: optional pointer to an array of clockdomains to register * @init_autodeps: optional pointer to an array of autodeps to register + * @custom_funcs: func pointers for arch specfic implementations * * Set up internal state. If a pointer to an array of clockdomains * @clkdms was supplied, loop through the list of clockdomains, @@ -300,12 +302,18 @@ static void _disable_hwsup(struct clockdomain *clkdm) * @init_autodeps was provided, register those. No return value. */ void clkdm_init(struct clockdomain **clkdms, - struct clkdm_autodep *init_autodeps) + struct clkdm_autodep *init_autodeps, + struct clkdm_ops *custom_funcs) { struct clockdomain **c = NULL; struct clockdomain *clkdm; struct clkdm_autodep *autodep = NULL; + if (!custom_funcs) + WARN(1, "No custom clkdm functions registered\n"); + else + arch_clkdm = custom_funcs; + if (clkdms) for (c = clkdms; *c; c++) _clkdm_register(*c); diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 9b459c26fb8..71ad265cf13 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -116,7 +116,42 @@ struct clockdomain { struct list_head node; }; -void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); +/** + * struct clkdm_ops - Arch specfic function implementations + * @clkdm_add_wkdep: Add a wakeup dependency between clk domains + * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains + * @clkdm_read_wkdep: Read wakeup dependency state between clk domains + * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain + * @clkdm_add_sleepdep: Add a sleep dependency between clk domains + * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains + * @clkdm_read_sleepdep: Read sleep dependency state between clk domains + * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain + * @clkdm_sleep: Force a clockdomain to sleep + * @clkdm_wakeup: Force a clockdomain to wakeup + * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain + * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain + * @clkdm_clk_enable: Put the clkdm in right state for a clock enable + * @clkdm_clk_disable: Put the clkdm in right state for a clock disable + */ +struct clkdm_ops { + int (*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2); + int (*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2); + int (*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2); + int (*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm); + int (*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2); + int (*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2); + int (*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2); + int (*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm); + int (*clkdm_sleep)(struct clockdomain *clkdm); + int (*clkdm_wakeup)(struct clockdomain *clkdm); + void (*clkdm_allow_idle)(struct clockdomain *clkdm); + void (*clkdm_deny_idle)(struct clockdomain *clkdm); + int (*clkdm_clk_enable)(struct clockdomain *clkdm); + int (*clkdm_clk_disable)(struct clockdomain *clkdm); +}; + +void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps, + struct clkdm_ops *custom_funcs); struct clockdomain *clkdm_lookup(const char *name); int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index e6f0d18d5e8..e2a959eab31 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -856,5 +856,5 @@ static struct clockdomain *clockdomains_omap2[] __initdata = { void __init omap2_clockdomains_init(void) { - clkdm_init(clockdomains_omap2, clkdm_autodeps); + clkdm_init(clockdomains_omap2, clkdm_autodeps, NULL); } diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 10622c914ab..a5000d473d4 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -305,5 +305,5 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { void __init omap44xx_clockdomains_init(void) { - clkdm_init(clockdomains_omap44xx, NULL); + clkdm_init(clockdomains_omap44xx, NULL, NULL); } -- cgit v1.2.3-70-g09d2 From 4aef7a2a5aad52b60ac1a2f3cee055b8271b70d5 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 16:06:47 -0700 Subject: OMAP: clockdomain: Arch specific funcs to handle deps Define the following architecture specific funtions for omap2/3 .clkdm_add_wkdep .clkdm_del_wkdep .clkdm_read_wkdep .clkdm_clear_all_wkdeps .clkdm_add_sleepdep .clkdm_del_sleepdep .clkdm_read_sleepdep .clkdm_clear_all_sleepdeps Convert the platform-independent framework to call these functions. With this also move the clkdm lookups for all wkdep_srcs and sleepdep_srcs at clkdm_init. Signed-off-by: Rajendra Nayak [paul@pwsan.com: fixed loop termination conditions in omap*_clkdm_clear_all_*(); thanks to Kevin Hilman for finding and helping fix those bugs; also avoid re-resolving clockdomains during init; abstracted out clkdm_dep walk] Cc: Kevin Hilman Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/clockdomain.c | 177 +++++++++++++---------- arch/arm/mach-omap2/clockdomain.h | 6 +- arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 130 +++++++++++++++++ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 9 +- arch/arm/mach-omap2/io.c | 6 +- 6 files changed, 246 insertions(+), 84 deletions(-) create mode 100644 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ee72a9787bf..759d9ebd79c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -102,8 +102,10 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \ # PRCM clockdomain control obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ + clockdomain2xxx_3xxx.o \ clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ + clockdomain2xxx_3xxx.o \ clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ clockdomains44xx_data.o diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index f70b06ae866..895c153c18e 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -287,6 +287,32 @@ static void _disable_hwsup(struct clockdomain *clkdm) BUG(); } +/** + * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms + * @clkdm: clockdomain that we are resolving dependencies for + * @clkdm_deps: ptr to array of struct clkdm_deps to resolve + * + * Iterates through @clkdm_deps, looking up the struct clockdomain named by + * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep. + * No return value. + */ +static void _resolve_clkdm_deps(struct clockdomain *clkdm, + struct clkdm_dep *clkdm_deps) +{ + struct clkdm_dep *cd; + + for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + if (cd->clkdm) + continue; + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + + WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen", + clkdm->name, cd->clkdm_name); + } +} + /* Public functions */ /** @@ -333,7 +359,10 @@ void clkdm_init(struct clockdomain **clkdms, else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO) omap2_clkdm_deny_idle(clkdm); + _resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs); clkdm_clear_all_wkdeps(clkdm); + + _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs); clkdm_clear_all_sleepdeps(clkdm); } } @@ -430,6 +459,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; + int ret = 0; if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { pr_err("clockdomain: %s/%s: %s: not yet implemented\n", @@ -441,21 +471,26 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) return -EINVAL; cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); - if (IS_ERR(cd)) { + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep) + ret = -EINVAL; + + if (ret) { pr_debug("clockdomain: hardware cannot set/clear wake up of " "%s when %s wakes up\n", clkdm1->name, clkdm2->name); - return PTR_ERR(cd); + return ret; } if (atomic_inc_return(&cd->wkdep_usecount) == 1) { pr_debug("clockdomain: hardware will wake up %s when %s wakes " "up\n", clkdm1->name, clkdm2->name); - omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2); } - return 0; + return ret; } /** @@ -471,6 +506,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; + int ret = 0; if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { pr_err("clockdomain: %s/%s: %s: not yet implemented\n", @@ -482,21 +518,26 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) return -EINVAL; cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); - if (IS_ERR(cd)) { + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep) + ret = -EINVAL; + + if (ret) { pr_debug("clockdomain: hardware cannot set/clear wake up of " "%s when %s wakes up\n", clkdm1->name, clkdm2->name); - return PTR_ERR(cd); + return ret; } if (atomic_dec_return(&cd->wkdep_usecount) == 0) { pr_debug("clockdomain: hardware will no longer wake up %s " "after %s wakes up\n", clkdm1->name, clkdm2->name); - omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2); } - return 0; + return ret; } /** @@ -516,6 +557,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; + int ret = 0; if (!clkdm1 || !clkdm2) return -EINVAL; @@ -527,15 +569,20 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) } cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); - if (IS_ERR(cd)) { + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep) + ret = -EINVAL; + + if (ret) { pr_debug("clockdomain: hardware cannot set/clear wake up of " "%s when %s wakes up\n", clkdm1->name, clkdm2->name); - return PTR_ERR(cd); + return ret; } /* XXX It's faster to return the atomic wkdep_usecount */ - return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, - (1 << clkdm2->dep_bit)); + return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2); } /** @@ -550,9 +597,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) */ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) { - struct clkdm_dep *cd; - u32 mask = 0; - if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { pr_err("clockdomain: %s: %s: not yet implemented\n", clkdm->name, __func__); @@ -562,21 +606,10 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) if (!clkdm) return -EINVAL; - for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; - - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - - /* PRM accesses are slow, so minimize them */ - mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->wkdep_usecount, 0); - } - - omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); + if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps) + return -EINVAL; - return 0; + return arch_clkdm->clkdm_clear_all_wkdeps(clkdm); } /** @@ -594,31 +627,33 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; - - if (!cpu_is_omap34xx()) - return -EINVAL; + int ret = 0; if (!clkdm1 || !clkdm2) return -EINVAL; cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); - if (IS_ERR(cd)) { + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep) + ret = -EINVAL; + + if (ret) { pr_debug("clockdomain: hardware cannot set/clear sleep " "dependency affecting %s from %s\n", clkdm1->name, clkdm2->name); - return PTR_ERR(cd); + return ret; } if (atomic_inc_return(&cd->sleepdep_usecount) == 1) { pr_debug("clockdomain: will prevent %s from sleeping if %s " "is active\n", clkdm1->name, clkdm2->name); - omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP); + ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2); } - return 0; + return ret; } /** @@ -636,19 +671,23 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; - - if (!cpu_is_omap34xx()) - return -EINVAL; + int ret = 0; if (!clkdm1 || !clkdm2) return -EINVAL; cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); - if (IS_ERR(cd)) { + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep) + ret = -EINVAL; + + if (ret) { pr_debug("clockdomain: hardware cannot set/clear sleep " "dependency affecting %s from %s\n", clkdm1->name, clkdm2->name); - return PTR_ERR(cd); + return ret; } if (atomic_dec_return(&cd->sleepdep_usecount) == 0) { @@ -656,12 +695,10 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) "sleeping if %s is active\n", clkdm1->name, clkdm2->name); - omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP); + ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2); } - return 0; + return ret; } /** @@ -683,25 +720,27 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) { struct clkdm_dep *cd; - - if (!cpu_is_omap34xx()) - return -EINVAL; + int ret = 0; if (!clkdm1 || !clkdm2) return -EINVAL; cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); - if (IS_ERR(cd)) { + if (IS_ERR(cd)) + ret = PTR_ERR(cd); + + if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep) + ret = -EINVAL; + + if (ret) { pr_debug("clockdomain: hardware cannot set/clear sleep " "dependency affecting %s from %s\n", clkdm1->name, clkdm2->name); - return PTR_ERR(cd); + return ret; } /* XXX It's faster to return the atomic sleepdep_usecount */ - return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP, - (1 << clkdm2->dep_bit)); + return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2); } /** @@ -716,31 +755,13 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) */ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) { - struct clkdm_dep *cd; - u32 mask = 0; - - if (!cpu_is_omap34xx()) - return -EINVAL; - if (!clkdm) return -EINVAL; - for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; - - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - - /* PRM accesses are slow, so minimize them */ - mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->sleepdep_usecount, 0); - } - - omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP); + if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps) + return -EINVAL; - return 0; + return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm); } /** diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 71ad265cf13..90b6d6a5086 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -176,7 +176,11 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm); int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); -extern void __init omap2_clockdomains_init(void); +extern void __init omap2xxx_clockdomains_init(void); +extern void __init omap3xxx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); +extern struct clkdm_ops omap2_clkdm_operations; +extern struct clkdm_ops omap3_clkdm_operations; + #endif diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c new file mode 100644 index 00000000000..a1fd6fd5a46 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -0,0 +1,130 @@ +/* + * OMAP2 and OMAP3 clockdomain control + * + * Copyright (C) 2008-2010 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Derived from mach-omap2/clockdomain.c written by Paul Walmsley + * Rajendra Nayak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include "prm.h" +#include "prm2xxx_3xxx.h" +#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" +#include "cm-regbits-34xx.h" +#include "clockdomain.h" + +static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + return 0; +} + +static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + return 0; +} + +static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + PM_WKDEP, (1 << clkdm2->dep_bit)); +} + +static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) +{ + struct clkdm_dep *cd; + u32 mask = 0; + + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + if (!cd->clkdm) + continue; /* only happens if data is erroneous */ + + /* PRM accesses are slow, so minimize them */ + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->wkdep_usecount, 0); + } + + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + PM_WKDEP); + return 0; +} + +static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + return 0; +} + +static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + return 0; +} + +static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit)); +} + +static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) +{ + struct clkdm_dep *cd; + u32 mask = 0; + + for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + if (!cd->clkdm) + continue; /* only happens if data is erroneous */ + + /* PRM accesses are slow, so minimize them */ + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->sleepdep_usecount, 0); + } + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + return 0; +} + +struct clkdm_ops omap2_clkdm_operations = { + .clkdm_add_wkdep = omap2_clkdm_add_wkdep, + .clkdm_del_wkdep = omap2_clkdm_del_wkdep, + .clkdm_read_wkdep = omap2_clkdm_read_wkdep, + .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, +}; + +struct clkdm_ops omap3_clkdm_operations = { + .clkdm_add_wkdep = omap2_clkdm_add_wkdep, + .clkdm_del_wkdep = omap2_clkdm_del_wkdep, + .clkdm_read_wkdep = omap2_clkdm_read_wkdep, + .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, + .clkdm_add_sleepdep = omap3_clkdm_add_sleepdep, + .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep, + .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep, + .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps, +}; diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index e2a959eab31..ffdfe54f326 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -854,7 +854,12 @@ static struct clockdomain *clockdomains_omap2[] __initdata = { NULL, }; -void __init omap2_clockdomains_init(void) +void __init omap2xxx_clockdomains_init(void) { - clkdm_init(clockdomains_omap2, clkdm_autodeps, NULL); + clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations); +} + +void __init omap3xxx_clockdomains_init(void) +{ + clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations); } diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b8b49e4ae92..03f71ec3cd8 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -357,15 +357,15 @@ void __init omap2_init_common_infrastructure(void) if (cpu_is_omap242x()) { omap2xxx_powerdomains_init(); - omap2_clockdomains_init(); + omap2xxx_clockdomains_init(); omap2420_hwmod_init(); } else if (cpu_is_omap243x()) { omap2xxx_powerdomains_init(); - omap2_clockdomains_init(); + omap2xxx_clockdomains_init(); omap2430_hwmod_init(); } else if (cpu_is_omap34xx()) { omap3xxx_powerdomains_init(); - omap2_clockdomains_init(); + omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); } else if (cpu_is_omap44xx()) { omap44xx_powerdomains_init(); -- cgit v1.2.3-70-g09d2 From 68b921ad7f35e0323ce0d9fe94e5701a112f257c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 16:06:47 -0700 Subject: OMAP: clockdomain: Arch specific funcs for sleep/wakeup of clkdm Define the following architecture specific funtions for omap2/3/4 .clkdm_sleep .clkdm_wakeup Convert the platform-independent framework to call these functions. Also rename the api's by removing the omap2_ preamble. Hence call omap2_clkdm_wakeup as clkdm_wakeup and omap2_clkdm_sleep as clkdm_sleep. Signed-off-by: Rajendra Nayak [paul@pwsan.com: fixed omap3_clkdm_clear_all_sleepdeps() and omap2_clkdm_clear_all_wkdeps() to test against the correct loop termination condition; thanks to Kevin Hilman for finding and helping fix] Cc: Kevin Hilman Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/clockdomain.c | 64 +++++++---------------------- arch/arm/mach-omap2/clockdomain.h | 5 ++- arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 35 ++++++++++++++++ arch/arm/mach-omap2/clockdomain44xx.c | 35 ++++++++++++++++ arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +- arch/arm/mach-omap2/pm.c | 4 +- arch/arm/mach-omap2/pm24xx.c | 6 +-- arch/arm/mach-omap2/pm34xx.c | 2 +- 9 files changed, 96 insertions(+), 58 deletions(-) create mode 100644 arch/arm/mach-omap2/clockdomain44xx.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 759d9ebd79c..10c3c8f16ea 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -108,6 +108,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ clockdomain2xxx_3xxx.o \ clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ + clockdomain44xx.o \ clockdomains44xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 895c153c18e..3035eb9eec3 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -355,7 +355,7 @@ void clkdm_init(struct clockdomain **clkdms, */ list_for_each_entry(clkdm, &clkdm_list, node) { if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - omap2_clkdm_wakeup(clkdm); + clkdm_wakeup(clkdm); else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO) omap2_clkdm_deny_idle(clkdm); @@ -765,7 +765,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) } /** - * omap2_clkdm_sleep - force clockdomain sleep transition + * clkdm_sleep - force clockdomain sleep transition * @clkdm: struct clockdomain * * * Instruct the CM to force a sleep transition on the specified @@ -773,7 +773,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) * clockdomain does not support software-initiated sleep; 0 upon * success. */ -int omap2_clkdm_sleep(struct clockdomain *clkdm) +int clkdm_sleep(struct clockdomain *clkdm) { if (!clkdm) return -EINVAL; @@ -784,33 +784,16 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) return -EINVAL; } - pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name); - - if (cpu_is_omap24xx()) { - - omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, - clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); - - } else if (cpu_is_omap34xx()) { - - omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - } else if (cpu_is_omap44xx()) { - - omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, - clkdm->cm_inst, - clkdm->clkdm_offs); + if (!arch_clkdm || !arch_clkdm->clkdm_sleep) + return -EINVAL; - } else { - BUG(); - }; + pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name); - return 0; + return arch_clkdm->clkdm_sleep(clkdm); } /** - * omap2_clkdm_wakeup - force clockdomain wakeup transition + * clkdm_wakeup - force clockdomain wakeup transition * @clkdm: struct clockdomain * * * Instruct the CM to force a wakeup transition on the specified @@ -818,7 +801,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) * clockdomain does not support software-controlled wakeup; 0 upon * success. */ -int omap2_clkdm_wakeup(struct clockdomain *clkdm) +int clkdm_wakeup(struct clockdomain *clkdm) { if (!clkdm) return -EINVAL; @@ -829,29 +812,12 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) return -EINVAL; } - pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name); - - if (cpu_is_omap24xx()) { - - omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, - clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); - - } else if (cpu_is_omap34xx()) { - - omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - } else if (cpu_is_omap44xx()) { - - omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, - clkdm->cm_inst, - clkdm->clkdm_offs); + if (!arch_clkdm || !arch_clkdm->clkdm_wakeup) + return -EINVAL; - } else { - BUG(); - }; + pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name); - return 0; + return arch_clkdm->clkdm_wakeup(clkdm); } /** @@ -990,7 +956,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) _clkdm_add_autodeps(clkdm); _enable_hwsup(clkdm); } else { - omap2_clkdm_wakeup(clkdm); + clkdm_wakeup(clkdm); } pwrdm_wait_transition(clkdm->pwrdm.ptr); @@ -1062,7 +1028,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) _clkdm_del_autodeps(clkdm); _enable_hwsup(clkdm); } else { - omap2_clkdm_sleep(clkdm); + clkdm_sleep(clkdm); } pwrdm_clkdm_state_switch(clkdm); diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 90b6d6a5086..7a5cb5cf994 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -170,8 +170,8 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); void omap2_clkdm_allow_idle(struct clockdomain *clkdm); void omap2_clkdm_deny_idle(struct clockdomain *clkdm); -int omap2_clkdm_wakeup(struct clockdomain *clkdm); -int omap2_clkdm_sleep(struct clockdomain *clkdm); +int clkdm_wakeup(struct clockdomain *clkdm); +int clkdm_sleep(struct clockdomain *clkdm); int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); @@ -182,5 +182,6 @@ extern void __init omap44xx_clockdomains_init(void); extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; +extern struct clkdm_ops omap4_clkdm_operations; #endif diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index a1fd6fd5a46..08c87fe3da1 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -20,6 +20,7 @@ #include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" +#include "prm-regbits-24xx.h" #include "clockdomain.h" static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, @@ -111,11 +112,43 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) return 0; } +static int omap2_clkdm_sleep(struct clockdomain *clkdm) +{ + omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + clkdm->pwrdm.ptr->prcm_offs, + OMAP2_PM_PWSTCTRL); + return 0; +} + +static int omap2_clkdm_wakeup(struct clockdomain *clkdm) +{ + omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + clkdm->pwrdm.ptr->prcm_offs, + OMAP2_PM_PWSTCTRL); + return 0; +} + +static int omap3_clkdm_sleep(struct clockdomain *clkdm) +{ + omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; +} + +static int omap3_clkdm_wakeup(struct clockdomain *clkdm) +{ + omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; +} + struct clkdm_ops omap2_clkdm_operations = { .clkdm_add_wkdep = omap2_clkdm_add_wkdep, .clkdm_del_wkdep = omap2_clkdm_del_wkdep, .clkdm_read_wkdep = omap2_clkdm_read_wkdep, .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, + .clkdm_sleep = omap2_clkdm_sleep, + .clkdm_wakeup = omap2_clkdm_wakeup, }; struct clkdm_ops omap3_clkdm_operations = { @@ -127,4 +160,6 @@ struct clkdm_ops omap3_clkdm_operations = { .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep, .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep, .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps, + .clkdm_sleep = omap3_clkdm_sleep, + .clkdm_wakeup = omap3_clkdm_wakeup, }; diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c new file mode 100644 index 00000000000..9ccb406cf54 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -0,0 +1,35 @@ +/* + * OMAP4 clockdomain control + * + * Copyright (C) 2008-2010 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Derived from mach-omap2/clockdomain.c written by Paul Walmsley + * Rajendra Nayak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "clockdomain.h" +#include "cminst44xx.h" + +static int omap4_clkdm_sleep(struct clockdomain *clkdm) +{ + omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static int omap4_clkdm_wakeup(struct clockdomain *clkdm) +{ + omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +struct clkdm_ops omap4_clkdm_operations = { + .clkdm_sleep = omap4_clkdm_sleep, + .clkdm_wakeup = omap4_clkdm_wakeup, +}; diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index a5000d473d4..eea6f8e4028 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -305,5 +305,5 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { void __init omap44xx_clockdomains_init(void) { - clkdm_init(clockdomains_omap44xx, NULL, NULL); + clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations); } diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index d5a102c7198..74c31008079 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -124,7 +124,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { sleep_switch = LOWPOWERSTATE_SWITCH; } else { - omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); + clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); pwrdm_wait_transition(pwrdm); sleep_switch = FORCEWAKEUP_SWITCH; } @@ -142,7 +142,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO) omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); else - omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[0]); + clkdm_sleep(pwrdm->pwrdm_clkdms[0]); break; case LOWPOWERSTATE_SWITCH: pwrdm_set_lowpwrstchange(pwrdm); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 97feb3ab6a6..4125621bf59 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -370,7 +370,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) omap2_clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && atomic_read(&clkdm->usecount) == 0) - omap2_clkdm_sleep(clkdm); + clkdm_sleep(clkdm); return 0; } @@ -405,11 +405,11 @@ static void __init prcm_setup_regs(void) pwrdm = clkdm_get_pwrdm(dsp_clkdm); pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - omap2_clkdm_sleep(dsp_clkdm); + clkdm_sleep(dsp_clkdm); pwrdm = clkdm_get_pwrdm(gfx_clkdm); pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); - omap2_clkdm_sleep(gfx_clkdm); + clkdm_sleep(gfx_clkdm); /* * Clear clockdomain wakeup dependencies and enable diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 2f864e4b085..81df2b169a5 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -993,7 +993,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) omap2_clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && atomic_read(&clkdm->usecount) == 0) - omap2_clkdm_sleep(clkdm); + clkdm_sleep(clkdm); return 0; } -- cgit v1.2.3-70-g09d2 From 5cd1937b6d5990fe5d5287d925f05afd38e9fb02 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 16:06:48 -0700 Subject: OMAP: clockdomain: Arch specific funcs for hwsup control of clkdm Define the following architecture specific funtions for omap2/3/4 .clkdm_allow_idle .clkdm_deny_idle Convert the platform-independent framework to call these functions. Also rename the api's by removing the omap2_ preamble. Hence call omap2_clkdm_allow_idle as clkdm_allow_idle and omap2_clkdm_deny_idle as clkdm_deny_idle. Make the _clkdm_add_autodeps and _clkdm_del_autodeps as non-static so they can be accessed from OMAP2/3 platform specific code. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clockdomain.c | 47 ++++++++++-------------------- arch/arm/mach-omap2/clockdomain.h | 6 ++-- arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 40 +++++++++++++++++++++++++ arch/arm/mach-omap2/clockdomain44xx.c | 14 +++++++++ arch/arm/mach-omap2/cpuidle34xx.c | 4 +-- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/mach-omap2/pm24xx.c | 2 +- arch/arm/mach-omap2/pm34xx.c | 4 +-- 8 files changed, 79 insertions(+), 40 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 3035eb9eec3..44664e7cc2a 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -178,7 +178,7 @@ static void _autodep_lookup(struct clkdm_autodep *autodep) * XXX autodeps are deprecated and should be removed at the earliest * opportunity */ -static void _clkdm_add_autodeps(struct clockdomain *clkdm) +void _clkdm_add_autodeps(struct clockdomain *clkdm) { struct clkdm_autodep *autodep; @@ -212,7 +212,7 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) * XXX autodeps are deprecated and should be removed at the earliest * opportunity */ -static void _clkdm_del_autodeps(struct clockdomain *clkdm) +void _clkdm_del_autodeps(struct clockdomain *clkdm) { struct clkdm_autodep *autodep; @@ -357,7 +357,7 @@ void clkdm_init(struct clockdomain **clkdms, if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) clkdm_wakeup(clkdm); else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO) - omap2_clkdm_deny_idle(clkdm); + clkdm_deny_idle(clkdm); _resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs); clkdm_clear_all_wkdeps(clkdm); @@ -821,7 +821,7 @@ int clkdm_wakeup(struct clockdomain *clkdm) } /** - * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm + * clkdm_allow_idle - enable hwsup idle transitions for clkdm * @clkdm: struct clockdomain * * * Allow the hardware to automatically switch the clockdomain @clkdm into @@ -830,7 +830,7 @@ int clkdm_wakeup(struct clockdomain *clkdm) * framework, wkdep/sleepdep autodependencies are added; this is so * device drivers can read and write to the device. No return value. */ -void omap2_clkdm_allow_idle(struct clockdomain *clkdm) +void clkdm_allow_idle(struct clockdomain *clkdm) { if (!clkdm) return; @@ -841,27 +841,18 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) return; } + if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle) + return; + pr_debug("clockdomain: enabling automatic idle transitions for %s\n", clkdm->name); - /* - * XXX This should be removed once TI adds wakeup/sleep - * dependency code and data for OMAP4. - */ - if (cpu_is_omap44xx()) { - pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name); - } else { - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_add_autodeps(clkdm); - } - - _enable_hwsup(clkdm); - + arch_clkdm->clkdm_allow_idle(clkdm); pwrdm_clkdm_state_switch(clkdm); } /** - * omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm + * clkdm_deny_idle - disable hwsup idle transitions for clkdm * @clkdm: struct clockdomain * * * Prevent the hardware from automatically switching the clockdomain @@ -869,7 +860,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) * downstream clocks enabled in the clock framework, wkdep/sleepdep * autodependencies are removed. No return value. */ -void omap2_clkdm_deny_idle(struct clockdomain *clkdm) +void clkdm_deny_idle(struct clockdomain *clkdm) { if (!clkdm) return; @@ -880,21 +871,13 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) return; } + if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle) + return; + pr_debug("clockdomain: disabling automatic idle transitions for %s\n", clkdm->name); - _disable_hwsup(clkdm); - - /* - * XXX This should be removed once TI adds wakeup/sleep - * dependency code and data for OMAP4. - */ - if (cpu_is_omap44xx()) { - pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name); - } else { - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_del_autodeps(clkdm); - } + arch_clkdm->clkdm_deny_idle(clkdm); } diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 7a5cb5cf994..7126658d9ae 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -167,8 +167,8 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); -void omap2_clkdm_allow_idle(struct clockdomain *clkdm); -void omap2_clkdm_deny_idle(struct clockdomain *clkdm); +void clkdm_allow_idle(struct clockdomain *clkdm); +void clkdm_deny_idle(struct clockdomain *clkdm); int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); @@ -179,6 +179,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); extern void __init omap2xxx_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); +extern void _clkdm_add_autodeps(struct clockdomain *clkdm); +extern void _clkdm_del_autodeps(struct clockdomain *clkdm); extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index 08c87fe3da1..25c27a5c722 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -128,6 +128,24 @@ static int omap2_clkdm_wakeup(struct clockdomain *clkdm) return 0; } +static void omap2_clkdm_allow_idle(struct clockdomain *clkdm) +{ + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_add_autodeps(clkdm); + + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); +} + +static void omap2_clkdm_deny_idle(struct clockdomain *clkdm) +{ + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_del_autodeps(clkdm); +} + static int omap3_clkdm_sleep(struct clockdomain *clkdm) { omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, @@ -142,6 +160,24 @@ static int omap3_clkdm_wakeup(struct clockdomain *clkdm) return 0; } +static void omap3_clkdm_allow_idle(struct clockdomain *clkdm) +{ + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_add_autodeps(clkdm); + + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); +} + +static void omap3_clkdm_deny_idle(struct clockdomain *clkdm) +{ + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_del_autodeps(clkdm); +} + struct clkdm_ops omap2_clkdm_operations = { .clkdm_add_wkdep = omap2_clkdm_add_wkdep, .clkdm_del_wkdep = omap2_clkdm_del_wkdep, @@ -149,6 +185,8 @@ struct clkdm_ops omap2_clkdm_operations = { .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, .clkdm_sleep = omap2_clkdm_sleep, .clkdm_wakeup = omap2_clkdm_wakeup, + .clkdm_allow_idle = omap2_clkdm_allow_idle, + .clkdm_deny_idle = omap2_clkdm_deny_idle, }; struct clkdm_ops omap3_clkdm_operations = { @@ -162,4 +200,6 @@ struct clkdm_ops omap3_clkdm_operations = { .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps, .clkdm_sleep = omap3_clkdm_sleep, .clkdm_wakeup = omap3_clkdm_wakeup, + .clkdm_allow_idle = omap3_clkdm_allow_idle, + .clkdm_deny_idle = omap3_clkdm_deny_idle, }; diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c index 9ccb406cf54..a46125f1545 100644 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -29,7 +29,21 @@ static int omap4_clkdm_wakeup(struct clockdomain *clkdm) return 0; } +static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) +{ + omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); +} + +static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) +{ + omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); +} + struct clkdm_ops omap4_clkdm_operations = { .clkdm_sleep = omap4_clkdm_sleep, .clkdm_wakeup = omap4_clkdm_wakeup, + .clkdm_allow_idle = omap4_clkdm_allow_idle, + .clkdm_deny_idle = omap4_clkdm_deny_idle, }; diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index f7b22a16f38..7cc80715ef1 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -99,14 +99,14 @@ static int omap3_idle_bm_check(void) static int _cpuidle_allow_idle(struct powerdomain *pwrdm, struct clockdomain *clkdm) { - omap2_clkdm_allow_idle(clkdm); + clkdm_allow_idle(clkdm); return 0; } static int _cpuidle_deny_idle(struct powerdomain *pwrdm, struct clockdomain *clkdm) { - omap2_clkdm_deny_idle(clkdm); + clkdm_deny_idle(clkdm); return 0; } diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 74c31008079..7bb64d8121a 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -140,7 +140,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) switch (sleep_switch) { case FORCEWAKEUP_SWITCH: if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO) - omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); + clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); else clkdm_sleep(pwrdm->pwrdm_clkdms[0]); break; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 4125621bf59..e983c8301f5 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -367,7 +367,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) clkdm_clear_all_sleepdeps(clkdm); if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) - omap2_clkdm_allow_idle(clkdm); + clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && atomic_read(&clkdm->usecount) == 0) clkdm_sleep(clkdm); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 81df2b169a5..eda9a4e99a8 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -496,7 +496,7 @@ console_still_active: pwrdm_post_transition(); - omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); + clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); } int omap3_can_sleep(void) @@ -990,7 +990,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) { if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) - omap2_clkdm_allow_idle(clkdm); + clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && atomic_read(&clkdm->usecount) == 0) clkdm_sleep(clkdm); -- cgit v1.2.3-70-g09d2 From 4da71ae607fc657075286abd2774041ff4d00fe5 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 16:06:48 -0700 Subject: OMAP: clockdomain: Arch specific funcs for clkdm_clk_enable/disable Define the following architecture specific funtions for omap2/3/4 .clkdm_clk_enable .clkdm_clk_disable Convert the platform-independent framework to call these functions. Also rename the api's by removing the omap2_ preamble. Hence call omap2_clkdm_k_enable as clkdm_clk_enable and omap2_clkdm_clk_disable as clkdm_clk_disable.a Remove unused functions (_enable/_disable_hwsup) and unsed headers from clockdomain.c file. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 6 +- arch/arm/mach-omap2/clockdomain.c | 131 +++-------------------------- arch/arm/mach-omap2/clockdomain.h | 4 +- arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 69 +++++++++++++++ arch/arm/mach-omap2/clockdomain44xx.c | 28 ++++++ 5 files changed, 114 insertions(+), 124 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 2a2f15213ad..e9625fcf639 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -264,7 +264,7 @@ void omap2_clk_disable(struct clk *clk) clk->ops->disable(clk); if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); + clkdm_clk_disable(clk->clkdm, clk); if (clk->parent) omap2_clk_disable(clk->parent); @@ -304,7 +304,7 @@ int omap2_clk_enable(struct clk *clk) } if (clk->clkdm) { - ret = omap2_clkdm_clk_enable(clk->clkdm, clk); + ret = clkdm_clk_enable(clk->clkdm, clk); if (ret) { WARN(1, "clock: %s: could not enable clockdomain %s: " "%d\n", clk->name, clk->clkdm->name, ret); @@ -322,7 +322,7 @@ int omap2_clk_enable(struct clk *clk) oce_err3: if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); + clkdm_clk_disable(clk->clkdm, clk); oce_err2: if (clk->parent) omap2_clk_disable(clk->parent); diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 44664e7cc2a..70d242007e0 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -26,17 +26,8 @@ #include -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-24xx.h" -#include "cminst44xx.h" -#include "prcm44xx.h" - #include -#include "powerdomain.h" #include "clockdomain.h" -#include /* clkdm_list contains all registered struct clockdomains */ static LIST_HEAD(clkdm_list); @@ -235,58 +226,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm) } } -/** - * _enable_hwsup - place a clockdomain into hardware-supervised idle - * @clkdm: struct clockdomain * - * - * Place the clockdomain into hardware-supervised idle mode. No return - * value. - * - * XXX Should this return an error if the clockdomain does not support - * hardware-supervised idle mode? - */ -static void _enable_hwsup(struct clockdomain *clkdm) -{ - if (cpu_is_omap24xx()) - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - else if (cpu_is_omap34xx()) - omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - else if (cpu_is_omap44xx()) - return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, - clkdm->clkdm_offs); - else - BUG(); -} - -/** - * _disable_hwsup - place a clockdomain into software-supervised idle - * @clkdm: struct clockdomain * - * - * Place the clockdomain @clkdm into software-supervised idle mode. - * No return value. - * - * XXX Should this return an error if the clockdomain does not support - * software-supervised idle mode? - */ -static void _disable_hwsup(struct clockdomain *clkdm) -{ - if (cpu_is_omap24xx()) - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - else if (cpu_is_omap34xx()) - omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - else if (cpu_is_omap44xx()) - return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, - clkdm->clkdm_offs); - else - BUG(); -} - /** * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms * @clkdm: clockdomain that we are resolving dependencies for @@ -884,7 +823,7 @@ void clkdm_deny_idle(struct clockdomain *clkdm) /* Clockdomain-to-clock framework interface code */ /** - * omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm + * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * * @clk: struct clk * of the enabled downstream clock * @@ -897,10 +836,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm) * by on-chip processors. Returns -EINVAL if passed null pointers; * returns 0 upon success or if the clockdomain is in hwsup idle mode. */ -int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) { - bool hwsup = false; - /* * XXX Rewrite this code to maintain a list of enabled * downstream clocks for debugging purposes? @@ -909,6 +846,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) if (!clkdm || !clk) return -EINVAL; + if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable) + return -EINVAL; + if (atomic_inc_return(&clkdm->usecount) > 1) return 0; @@ -917,31 +857,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, clk->name); - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - - if (!clkdm->clktrctrl_mask) - return 0; - - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - } else if (cpu_is_omap44xx()) { - - hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, - clkdm->clkdm_offs); - - } - - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - _disable_hwsup(clkdm); - _clkdm_add_autodeps(clkdm); - _enable_hwsup(clkdm); - } else { - clkdm_wakeup(clkdm); - } - + arch_clkdm->clkdm_clk_enable(clkdm); pwrdm_wait_transition(clkdm->pwrdm.ptr); pwrdm_clkdm_state_switch(clkdm); @@ -949,7 +865,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) } /** - * omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm + * clkdm_clk_disable - remove an enabled downstream clock from this clkdm * @clkdm: struct clockdomain * * @clk: struct clk * of the disabled downstream clock * @@ -962,10 +878,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) * is enabled; or returns 0 upon success or if the clockdomain is in * hwsup idle mode. */ -int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) { - bool hwsup = false; - /* * XXX Rewrite this code to maintain a list of enabled * downstream clocks for debugging purposes? @@ -974,6 +888,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) if (!clkdm || !clk) return -EINVAL; + if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable) + return -EINVAL; + #ifdef DEBUG if (atomic_read(&clkdm->usecount) == 0) { WARN_ON(1); /* underflow */ @@ -989,31 +906,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, clk->name); - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - - if (!clkdm->clktrctrl_mask) - return 0; - - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - } else if (cpu_is_omap44xx()) { - - hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, - clkdm->clkdm_offs); - - } - - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - _disable_hwsup(clkdm); - _clkdm_del_autodeps(clkdm); - _enable_hwsup(clkdm); - } else { - clkdm_sleep(clkdm); - } - + arch_clkdm->clkdm_clk_disable(clkdm); pwrdm_clkdm_state_switch(clkdm); return 0; diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 7126658d9ae..de52f059f9e 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -173,8 +173,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm); int clkdm_wakeup(struct clockdomain *clkdm); int clkdm_sleep(struct clockdomain *clkdm); -int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); +int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); +int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); extern void __init omap2xxx_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c index 25c27a5c722..48d0db7e606 100644 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c @@ -146,6 +146,71 @@ static void omap2_clkdm_deny_idle(struct clockdomain *clkdm) _clkdm_del_autodeps(clkdm); } +static void _enable_hwsup(struct clockdomain *clkdm) +{ + if (cpu_is_omap24xx()) + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + else if (cpu_is_omap34xx()) + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); +} + +static void _disable_hwsup(struct clockdomain *clkdm) +{ + if (cpu_is_omap24xx()) + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + else if (cpu_is_omap34xx()) + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); +} + + +static int omap2_clkdm_clk_enable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + if (!clkdm->clktrctrl_mask) + return 0; + + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + _disable_hwsup(clkdm); + _clkdm_add_autodeps(clkdm); + _enable_hwsup(clkdm); + } else { + clkdm_wakeup(clkdm); + } + + return 0; +} + +static int omap2_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + if (!clkdm->clktrctrl_mask) + return 0; + + hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + _disable_hwsup(clkdm); + _clkdm_del_autodeps(clkdm); + _enable_hwsup(clkdm); + } else { + clkdm_sleep(clkdm); + } + + return 0; +} + static int omap3_clkdm_sleep(struct clockdomain *clkdm) { omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, @@ -187,6 +252,8 @@ struct clkdm_ops omap2_clkdm_operations = { .clkdm_wakeup = omap2_clkdm_wakeup, .clkdm_allow_idle = omap2_clkdm_allow_idle, .clkdm_deny_idle = omap2_clkdm_deny_idle, + .clkdm_clk_enable = omap2_clkdm_clk_enable, + .clkdm_clk_disable = omap2_clkdm_clk_disable, }; struct clkdm_ops omap3_clkdm_operations = { @@ -202,4 +269,6 @@ struct clkdm_ops omap3_clkdm_operations = { .clkdm_wakeup = omap3_clkdm_wakeup, .clkdm_allow_idle = omap3_clkdm_allow_idle, .clkdm_deny_idle = omap3_clkdm_deny_idle, + .clkdm_clk_enable = omap2_clkdm_clk_enable, + .clkdm_clk_disable = omap2_clkdm_clk_disable, }; diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c index a46125f1545..c0ccc470164 100644 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -41,9 +41,37 @@ static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) clkdm->cm_inst, clkdm->clkdm_offs); } +static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); + + if (!hwsup) + clkdm_wakeup(clkdm); + + return 0; +} + +static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); + + if (!hwsup) + clkdm_sleep(clkdm); + + return 0; +} + struct clkdm_ops omap4_clkdm_operations = { .clkdm_sleep = omap4_clkdm_sleep, .clkdm_wakeup = omap4_clkdm_wakeup, .clkdm_allow_idle = omap4_clkdm_allow_idle, .clkdm_deny_idle = omap4_clkdm_deny_idle, + .clkdm_clk_enable = omap4_clkdm_clk_enable, + .clkdm_clk_disable = omap4_clkdm_clk_disable, }; -- cgit v1.2.3-70-g09d2 From 514c5948b2b5a3f9f9ebc344fc03073f3bd481b4 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:48:13 -0700 Subject: OMAP4: clockdomain: Add clkdm static dependency srcs OMAP4 supports static dependencies and dynamic dependencies between clock domains. Static dependencies imply both wakeup as well as sleep dependencies. Generate all clockdomain static dependency sources. (Dynamic dependency sources are hardwired and cannot to controlled from software). The autogen scripts are updated to generate the contents of this patch. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clockdomains44xx_data.c | 390 +++++++++++++++++++++++++++- 1 file changed, 385 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index eea6f8e4028..f53258acd1d 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -18,11 +18,6 @@ * published by the Free Software Foundation. */ -/* - * To-Do List - * -> Populate the Sleep/Wakeup dependencies for the domains - */ - #include #include @@ -35,6 +30,355 @@ #include "prcm44xx.h" #include "prcm_mpu44xx.h" +/* Static Dependencies for OMAP4 Clock Domains */ + +static struct clkdm_dep ducati_wkup_sleep_deps[] = { + { + .clkdm_name = "abe_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_dss_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_gfx_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_init_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_cfg_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_secure_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "tesla_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep iss_wkup_sleep_deps[] = { + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep ivahd_wkup_sleep_deps[] = { + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = { + { + .clkdm_name = "abe_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_init_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_cfg_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep l3_dma_wkup_sleep_deps[] = { + { + .clkdm_name = "abe_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ducati_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_dss_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_init_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_cfg_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_secure_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep l3_dss_wkup_sleep_deps[] = { + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = { + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep l3_init_wkup_sleep_deps[] = { + { + .clkdm_name = "abe_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_cfg_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_secure_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep mpuss_wkup_sleep_deps[] = { + { + .clkdm_name = "abe_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ducati_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_dss_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_gfx_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_init_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_cfg_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_secure_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "tesla_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; + +static struct clkdm_dep tesla_wkup_sleep_deps[] = { + { + .clkdm_name = "abe_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "ivahd_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_1_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_2_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_emif_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l3_init_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_cfg_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_per_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { + .clkdm_name = "l4_wkup_clkdm", + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) + }, + { NULL }, +}; static struct clockdomain l4_cefuse_44xx_clkdm = { .name = "l4_cefuse_clkdm", @@ -52,6 +396,7 @@ static struct clockdomain l4_cfg_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, + .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -62,6 +407,9 @@ static struct clockdomain tesla_44xx_clkdm = { .prcm_partition = OMAP4430_CM1_PARTITION, .cm_inst = OMAP4430_CM1_TESLA_INST, .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, + .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT, + .wkdep_srcs = tesla_wkup_sleep_deps, + .sleepdep_srcs = tesla_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -72,6 +420,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_GFX_INST, .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, + .dep_bit = OMAP4430_GFX_STATDEP_SHIFT, + .wkdep_srcs = l3_gfx_wkup_sleep_deps, + .sleepdep_srcs = l3_gfx_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -82,6 +433,9 @@ static struct clockdomain ivahd_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_IVAHD_INST, .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, + .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT, + .wkdep_srcs = ivahd_wkup_sleep_deps, + .sleepdep_srcs = ivahd_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -92,6 +446,9 @@ static struct clockdomain l4_secure_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_L4PER_INST, .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, + .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT, + .wkdep_srcs = l4_secure_wkup_sleep_deps, + .sleepdep_srcs = l4_secure_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -102,6 +459,7 @@ static struct clockdomain l4_per_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_L4PER_INST, .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, + .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -112,6 +470,7 @@ static struct clockdomain abe_44xx_clkdm = { .prcm_partition = OMAP4430_CM1_PARTITION, .cm_inst = OMAP4430_CM1_ABE_INST, .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, + .dep_bit = OMAP4430_ABE_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -131,6 +490,9 @@ static struct clockdomain l3_init_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_L3INIT_INST, .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, + .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT, + .wkdep_srcs = l3_init_wkup_sleep_deps, + .sleepdep_srcs = l3_init_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -141,6 +503,8 @@ static struct clockdomain mpuss_44xx_clkdm = { .prcm_partition = OMAP4430_CM1_PARTITION, .cm_inst = OMAP4430_CM1_MPU_INST, .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, + .wkdep_srcs = mpuss_wkup_sleep_deps, + .sleepdep_srcs = mpuss_wkup_sleep_deps, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -171,6 +535,7 @@ static struct clockdomain l3_emif_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, + .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -191,6 +556,9 @@ static struct clockdomain ducati_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, + .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT, + .wkdep_srcs = ducati_wkup_sleep_deps, + .sleepdep_srcs = ducati_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -201,6 +569,7 @@ static struct clockdomain l3_2_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, + .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -211,6 +580,7 @@ static struct clockdomain l3_1_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, + .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -221,6 +591,8 @@ static struct clockdomain l3_d2d_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, + .wkdep_srcs = l3_d2d_wkup_sleep_deps, + .sleepdep_srcs = l3_d2d_wkup_sleep_deps, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -231,6 +603,8 @@ static struct clockdomain iss_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CAM_INST, .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, + .wkdep_srcs = iss_wkup_sleep_deps, + .sleepdep_srcs = iss_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -241,6 +615,9 @@ static struct clockdomain l3_dss_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_DSS_INST, .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, + .dep_bit = OMAP4430_DSS_STATDEP_SHIFT, + .wkdep_srcs = l3_dss_wkup_sleep_deps, + .sleepdep_srcs = l3_dss_wkup_sleep_deps, .flags = CLKDM_CAN_HWSUP_SWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -251,6 +628,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = { .prcm_partition = OMAP4430_PRM_PARTITION, .cm_inst = OMAP4430_PRM_WKUP_CM_INST, .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, + .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, .flags = CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; @@ -271,6 +649,8 @@ static struct clockdomain l3_dma_44xx_clkdm = { .prcm_partition = OMAP4430_CM2_PARTITION, .cm_inst = OMAP4430_CM2_CORE_INST, .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, + .wkdep_srcs = l3_dma_wkup_sleep_deps, + .sleepdep_srcs = l3_dma_wkup_sleep_deps, .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; -- cgit v1.2.3-70-g09d2 From 04eb7773d803bd0a8249c5bba37f81c496253ea1 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:48:14 -0700 Subject: OMAP4: CM: Add CM accesor api for bitwise control Add new OMAP4 CM accesor apis to set/clear and read bitfields (based on mask) from CM registers. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/cminst44xx.c | 21 +++++++++++++++++++++ arch/arm/mach-omap2/cminst44xx.h | 6 ++++++ 2 files changed, 27 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index c04bbbea17a..a482bfa0a95 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -73,6 +73,27 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, return v; } +u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) +{ + return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx); +} + +u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx) +{ + return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx); +} + +u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) +{ + u32 v; + + v = omap4_cminst_read_inst_reg(part, inst, idx); + v &= mask; + v >>= __ffs(mask); + + return v; +} + /* * */ diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h index a6abd0a8cb8..2b32c181a2e 100644 --- a/arch/arm/mach-omap2/cminst44xx.h +++ b/arch/arm/mach-omap2/cminst44xx.h @@ -25,6 +25,12 @@ extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx); extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, s16 idx); +extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, + s16 idx); +extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, + s16 idx); +extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, + u32 mask); extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); -- cgit v1.2.3-70-g09d2 From 15b08d930f0b1a65a20e042046bd99ed7f75556b Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:48:14 -0700 Subject: OMAP4: clockdomain: Add wkup/sleep dependency support Add OMAP4 platform specific implementation to support clkdm wkup and sleep dependencies a.k.a static dependencies. Signed-off-by: Rajendra Nayak [paul@pwsan.com: removed comment about PRM; zero-prefixed STATICDEP register offset; fixed loop termination condition in omap4_clkdm_clear_all_wkup_sleep_deps(); thanks to Kevin Hilman for finding and helping fix this bug] Cc: Kevin Hilman Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clockdomain44xx.c | 60 +++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/cm44xx.h | 1 + 2 files changed, 61 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c index c0ccc470164..a1a4ecd2654 100644 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ b/arch/arm/mach-omap2/clockdomain44xx.c @@ -12,8 +12,60 @@ * published by the Free Software Foundation. */ +#include #include "clockdomain.h" #include "cminst44xx.h" +#include "cm44xx.h" + +static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), + clkdm1->prcm_partition, + clkdm1->cm_inst, clkdm1->clkdm_offs + + OMAP4_CM_STATICDEP); + return 0; +} + +static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), + clkdm1->prcm_partition, + clkdm1->cm_inst, clkdm1->clkdm_offs + + OMAP4_CM_STATICDEP); + return 0; +} + +static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, + clkdm1->cm_inst, clkdm1->clkdm_offs + + OMAP4_CM_STATICDEP, + (1 << clkdm2->dep_bit)); +} + +static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) +{ + struct clkdm_dep *cd; + u32 mask = 0; + + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { + if (!omap_chip_is(cd->omap_chip)) + continue; + if (!cd->clkdm) + continue; /* only happens if data is erroneous */ + + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->wkdep_usecount, 0); + } + + omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs + + OMAP4_CM_STATICDEP); + return 0; +} static int omap4_clkdm_sleep(struct clockdomain *clkdm) { @@ -68,6 +120,14 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) } struct clkdm_ops omap4_clkdm_operations = { + .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, + .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, + .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, + .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, + .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, + .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, + .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, + .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, .clkdm_sleep = omap4_clkdm_sleep, .clkdm_wakeup = omap4_clkdm_wakeup, .clkdm_allow_idle = omap4_clkdm_allow_idle, diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index 48fc3f426fb..0b87ec82b41 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h @@ -21,6 +21,7 @@ #include "cm.h" #define OMAP4_CM_CLKSTCTRL 0x0000 +#define OMAP4_CM_STATICDEP 0x0004 /* Function prototypes */ # ifndef __ASSEMBLER__ -- cgit v1.2.3-70-g09d2 From 5f8662ba3da6e410eb771b5d8751a1e02d87513f Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:48:14 -0700 Subject: OMAP4: clockdomain: Remove pr_errs' stating unsupported wkdep Now that wkup and sleep dependencies are supported (in the form of static deps) for OMAP4, remove all instances of pr_errs' stating dependencies are still unsupported on OMAP4. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clockdomain.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 70d242007e0..a0341dee1c3 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -400,12 +400,6 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) struct clkdm_dep *cd; int ret = 0; - if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { - pr_err("clockdomain: %s/%s: %s: not yet implemented\n", - clkdm1->name, clkdm2->name, __func__); - return -EINVAL; - } - if (!clkdm1 || !clkdm2) return -EINVAL; @@ -447,12 +441,6 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) struct clkdm_dep *cd; int ret = 0; - if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { - pr_err("clockdomain: %s/%s: %s: not yet implemented\n", - clkdm1->name, clkdm2->name, __func__); - return -EINVAL; - } - if (!clkdm1 || !clkdm2) return -EINVAL; @@ -501,12 +489,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) if (!clkdm1 || !clkdm2) return -EINVAL; - if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { - pr_err("clockdomain: %s/%s: %s: not yet implemented\n", - clkdm1->name, clkdm2->name, __func__); - return -EINVAL; - } - cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); if (IS_ERR(cd)) ret = PTR_ERR(cd); @@ -536,12 +518,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) */ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) { - if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) { - pr_err("clockdomain: %s: %s: not yet implemented\n", - clkdm->name, __func__); - return -EINVAL; - } - if (!clkdm) return -EINVAL; -- cgit v1.2.3-70-g09d2 From 6c52f32dcf1d76a95bda3a12d6be9a3102a2693c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:48:36 -0700 Subject: omap: clock: Check for enable/disable ops support Check if enable/disable operations are supported for a given clock node before attempting to call them. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e9625fcf639..b1875965bb5 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -261,7 +261,8 @@ void omap2_clk_disable(struct clk *clk) pr_debug("clock: %s: disabling in hardware\n", clk->name); - clk->ops->disable(clk); + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); if (clk->clkdm) clkdm_clk_disable(clk->clkdm, clk); @@ -312,10 +313,13 @@ int omap2_clk_enable(struct clk *clk) } } - ret = clk->ops->enable(clk); - if (ret) { - WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret); - goto oce_err3; + if (clk->ops && clk->ops->enable) { + ret = clk->ops->enable(clk); + if (ret) { + WARN(1, "clock: %s: could not enable: %d\n", + clk->name, ret); + goto oce_err3; + } } return 0; -- cgit v1.2.3-70-g09d2 From 5a2926b8805bc697d47a243dbf2f20de68abe14c Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:48:37 -0700 Subject: omap3: dpll: Populate clkops for dpll1_ck DPLL1 on omap3 is very similar to the rest of the non-core dpll's. Hence populate clkops_omap3_noncore_dpll_ops as the clkops for it, instead of the currently populated clkops_null. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock3xxx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index f14d986f0b5..0cdb8343d65 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -296,7 +296,7 @@ static struct dpll_data dpll1_dd = { static struct clk dpll1_ck = { .name = "dpll1_ck", - .ops = &clkops_null, + .ops = &clkops_omap3_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll1_dd, .round_rate = &omap2_dpll_round_rate, -- cgit v1.2.3-70-g09d2 From 6c6f5a7437955cec637c00ab1d09b8f70fc0ab3a Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:49:00 -0700 Subject: OMAP3/4: DPLL: Add allow_idle/deny_idle support for all DPLL's All OMAP3/4 dpll's support hardware level autogating. Populate allow_idle/deny_idle function pointers for all DPLL's in clkops. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 8 +++++++- arch/arm/mach-omap2/clock.h | 1 + arch/arm/mach-omap2/clock3xxx_data.c | 2 +- arch/arm/mach-omap2/clock44xx_data.c | 2 +- 4 files changed, 10 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index b1875965bb5..46d03ccc280 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -377,10 +377,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) const struct clkops clkops_omap3_noncore_dpll_ops = { .enable = omap3_noncore_dpll_enable, .disable = omap3_noncore_dpll_disable, + .allow_idle = omap3_dpll_allow_idle, + .deny_idle = omap3_dpll_deny_idle, }; -#endif +const struct clkops clkops_omap3_core_dpll_ops = { + .allow_idle = omap3_dpll_allow_idle, + .deny_idle = omap3_dpll_deny_idle, +}; +#endif /* * OMAP2+ clock reset and init functions diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 896584e3c4a..2a939e5ec6a 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -146,5 +146,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) #endif extern const struct clkops clkops_omap3_noncore_dpll_ops; +extern const struct clkops clkops_omap3_core_dpll_ops; #endif diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 0cdb8343d65..78ea7997686 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -429,7 +429,7 @@ static struct dpll_data dpll3_dd = { static struct clk dpll3_ck = { .name = "dpll3_ck", - .ops = &clkops_null, + .ops = &clkops_omap3_core_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll3_dd, .round_rate = &omap2_dpll_round_rate, diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index de9ec8ddd2a..b843b6e5976 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -443,7 +443,7 @@ static struct clk dpll_core_ck = { .parent = &sys_clkin_ck, .dpll_data = &dpll_core_dd, .init = &omap2_init_dpll_parent, - .ops = &clkops_null, + .ops = &clkops_omap3_core_dpll_ops, .recalc = &omap3_dpll_recalc, }; -- cgit v1.2.3-70-g09d2 From b80b956dc56c6a3cb77b97e2abff48fb7ebc2119 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:49:01 -0700 Subject: OMAP2+: clock: autoidle as many clocks as possible if CONFIG_OMAP_RESET_CLOCKS Attempt to enable autoidle for as many clocks as possible in the OMAP2+-common CONFIG_OMAP_RESET_CLOCKS code. Currently, this only enables DPLL autoidle for OMAP3/4 DPLLs; but future patches will enable autoidle for other clocks and the OMAP2 DPLL/APLLs. In the long run, we should probably get rid of CONFIG_OMAP_RESET_CLOCKS, and unconditionally run the code that it selects. Otherwise, the state of the clock tree won't match the hardware state - this could result in clocks being enabled or disabled unpredictably. Based on a patch by Rajendra Nayak that did this in the pm34xx.c/pm44xx.c code. Signed-off-by: Paul Walmsley Cc: Rajendra Nayak --- arch/arm/mach-omap2/pm34xx.c | 17 ----------------- arch/arm/plat-omap/clock.c | 1 + 2 files changed, 1 insertion(+), 17 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index eda9a4e99a8..a99f296bdbf 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -813,23 +813,6 @@ static void __init prcm_setup_regs(void) omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); - /* - * Set all plls to autoidle. This is needed until autoidle is - * enabled by clockfw - */ - omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, - OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, - MPU_MOD, - CM_AUTOIDLE2); - omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | - (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), - PLL_MOD, - CM_AUTOIDLE); - omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, - PLL_MOD, - CM_AUTOIDLE2); - /* * Enable control of expternal oscillator through * sys_clkreq. In the long run clock framework should diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 0ae0eae01fd..2770dddd72c 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -446,6 +446,7 @@ static int __init clk_disable_unused(void) return 0; } late_initcall(clk_disable_unused); +late_initcall(omap_clk_enable_autoidle_all); #endif int __init clk_init(struct clk_functions * custom_clocks) -- cgit v1.2.3-70-g09d2 From 97f678989afe5dd1584a0877dfd8b0d2e124b73a Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:49:01 -0700 Subject: OMAP4: DPLL: Add dpll api to control GATE_CTRL On OMAP4, the dpll post divider outputs (MX outputs) along with clockout_x2 output provide a way to allow/deny hardware level autogating. Allowing autoidle would mean that the hw would autogate this clock when there is no dependency for it. Denying idle would mean that this clock output will be forced to stay enabled. Add dpll api's to read/allow/deny idle control for these dpll mx postdividers. NOTE: The gatectrl bit set to 0 allows gatectrl, and the bit set to 1 denies gatectrl. Signed-off-by: Rajendra Nayak [paul@pwsan.com: moved OMAP4-specific DPLL control code to mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clock.h | 3 ++ arch/arm/mach-omap2/dpll44xx.c | 78 +++++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/clock.h | 14 +++++- 4 files changed, 95 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/dpll44xx.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 10c3c8f16ea..89274a9f035 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -123,7 +123,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ clock3517.o clock36xx.o \ dpll3xxx.o clock3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ - dpll3xxx.o + dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 2a939e5ec6a..c450d69a0dc 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk); int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); int omap3_noncore_dpll_enable(struct clk *clk); void omap3_noncore_dpll_disable(struct clk *clk); +int omap4_dpllmx_gatectrl_read(struct clk *clk); +void omap4_dpllmx_allow_gatectrl(struct clk *clk); +void omap4_dpllmx_deny_gatectrl(struct clk *clk); #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c new file mode 100644 index 00000000000..94a3592cd54 --- /dev/null +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -0,0 +1,78 @@ +/* + * OMAP4-specific DPLL control functions + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Rajendra Nayak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "clock.h" +#include "cm-regbits-44xx.h" + +/* Supported only on OMAP4 */ +int omap4_dpllmx_gatectrl_read(struct clk *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + return -EINVAL; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = __raw_readl(clk->clksel_reg); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +void omap4_dpllmx_allow_gatectrl(struct clk *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + return; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = __raw_readl(clk->clksel_reg); + /* Clear the bit to allow gatectrl */ + v &= ~mask; + __raw_writel(v, clk->clksel_reg); +} + +void omap4_dpllmx_deny_gatectrl(struct clk *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + return; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = __raw_readl(clk->clksel_reg); + /* Set the bit to deny gatectrl */ + v |= mask; + __raw_writel(v, clk->clksel_reg); +} diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index be69f5cac32..dcd7bb81420 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -176,12 +176,24 @@ struct dpll_data { #endif -/* struct clk.flags possibilities */ +/* + * struct clk.flags possibilities + * + * XXX document the rest of the clock flags here + * + * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL + * bits share the same register. This flag allows the + * omap4_dpllmx*() code to determine which GATE_CTRL bit field + * should be used. This is a temporary solution - a better approach + * would be to associate clock type-specific data with the clock, + * similar to the struct dpll_data approach. + */ #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ #define CLOCK_IDLE_CONTROL (1 << 1) #define CLOCK_NO_IDLE_PARENT (1 << 2) #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ +#define CLOCK_CLKOUTX2 (1 << 5) /** * struct clk - OMAP struct clk -- cgit v1.2.3-70-g09d2 From 70db8a6273692fdf5226c007c9882a10b3203963 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:49:02 -0700 Subject: omap4: dpll: Enable auto gate control for all MX postdividers Enable hardware gate control for all dpll MX and X2 postdividers. This requires the allow_idle/deny_idle functions to be populated for all clock nodes (mx/x2 post dividers) in clkops. Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.h | 1 + arch/arm/mach-omap2/clock44xx_data.c | 52 +++++++++++++++++++++--------------- arch/arm/mach-omap2/dpll44xx.c | 6 +++++ 3 files changed, 37 insertions(+), 22 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index c450d69a0dc..0725a6ad8b4 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -150,5 +150,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) extern const struct clkops clkops_omap3_noncore_dpll_ops; extern const struct clkops clkops_omap3_core_dpll_ops; +extern const struct clkops clkops_omap4_dpllmx_ops; #endif diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index b843b6e5976..dcbe10571a0 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = { static struct clk dpll_abe_x2_ck = { .name = "dpll_abe_x2_ck", .parent = &dpll_abe_ck, - .ops = &clkops_null, + .flags = CLOCK_CLKOUTX2, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap3_clkoutx2_recalc, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, }; static const struct clksel_rate div31_1to31_rates[] = { @@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = { .clksel = dpll_abe_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = { .clksel = dpll_abe_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -450,6 +452,7 @@ static struct clk dpll_core_ck = { static struct clk dpll_core_x2_ck = { .name = "dpll_core_x2_ck", .parent = &dpll_core_ck, + .flags = CLOCK_CLKOUTX2, .ops = &clkops_null, .recalc = &omap3_clkoutx2_recalc, }; @@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = { .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = { .clksel = dpll_core_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = { .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = { .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = { .clksel = dpll_abe_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = { .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = { static struct clk dpll_iva_x2_ck = { .name = "dpll_iva_x2_ck", .parent = &dpll_iva_ck, + .flags = CLOCK_CLKOUTX2, .ops = &clkops_null, .recalc = &omap3_clkoutx2_recalc, }; @@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = { .clksel = dpll_iva_m4x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = { .clksel = dpll_iva_m4x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = { .clksel = dpll_mpu_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = { .clksel = dpll_per_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = { static struct clk dpll_per_x2_ck = { .name = "dpll_per_x2_ck", .parent = &dpll_per_ck, - .ops = &clkops_null, + .flags = CLOCK_CLKOUTX2, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap3_clkoutx2_recalc, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, }; static const struct clksel dpll_per_m2x2_div[] = { @@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = { .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = { .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = { .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = { .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = { .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = { static struct clk dpll_unipro_x2_ck = { .name = "dpll_unipro_x2_ck", .parent = &dpll_unipro_ck, + .flags = CLOCK_CLKOUTX2, .ops = &clkops_null, .recalc = &omap3_clkoutx2_recalc, }; @@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = { .clksel = dpll_unipro_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = { static struct clk dpll_usb_clkdcoldo_ck = { .name = "dpll_usb_clkdcoldo_ck", .parent = &dpll_usb_ck, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, + .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, .recalc = &followparent_recalc, }; @@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = { .clksel = dpll_usb_m2_div, .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, - .ops = &clkops_null, + .ops = &clkops_omap4_dpllmx_ops, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 94a3592cd54..4e4da6160d0 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -76,3 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) v |= mask; __raw_writel(v, clk->clksel_reg); } + +const struct clkops clkops_omap4_dpllmx_ops = { + .allow_idle = omap4_dpllmx_allow_gatectrl, + .deny_idle = omap4_dpllmx_deny_gatectrl, +}; + -- cgit v1.2.3-70-g09d2 From c6461f5c5970833cf28c5096cdfc7a095eb3bbb5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:49:53 -0700 Subject: OMAP2+: clock: disable autoidle on all clocks during clock init Disable autoidle on all clocks during clock framework initialization. (If CONFIG_PM is set, autoidle is re-enabled for all clocks later in the boot process.) The principle behind this patch, and some similar patches, is that the kernel should start with all power management features disabled. Later in the boot process, the PM code, if compiled in with CONFIG_PM, enables or re-enables power management features. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clock2420_data.c | 3 +++ arch/arm/mach-omap2/clock2430_data.c | 3 +++ arch/arm/mach-omap2/clock3xxx.c | 3 --- arch/arm/mach-omap2/clock3xxx_data.c | 6 +++++- arch/arm/mach-omap2/clock44xx_data.c | 3 +++ 5 files changed, 14 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 0a992bc8d0d..ee73e14ac3c 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1913,6 +1913,9 @@ int __init omap2420_clk_init(void) omap2_init_clk_clkdm(c->lk.clk); } + /* Disable autoidle on all clocks; let the PM code enable it later */ + omap_clk_disable_autoidle_all(); + /* Check the MPU rate set by bootloader */ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); for (prcm = rate_table; prcm->mpu_speed; prcm++) { diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index c047dcd007e..a1298e55d91 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -2028,6 +2028,9 @@ int __init omap2430_clk_init(void) omap2_init_clk_clkdm(c->lk.clk); } + /* Disable autoidle on all clocks; let the PM code enable it later */ + omap_clk_disable_autoidle_all(); + /* Check the MPU rate set by bootloader */ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); for (prcm = rate_table; prcm->mpu_speed; prcm++) { diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index e9f66b6dec1..952c3e01c9e 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void) clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); clk_enable(dpll5_clk); - /* Enable autoidle to allow it to enter low power bypass */ - omap3_dpll_allow_idle(dpll5_clk); - /* Program dpll5_m2_clk divider for no division */ dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); clk_enable(dpll5_m2_clk); diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 78ea7997686..65b79e6afb5 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3538,6 +3538,9 @@ int __init omap3xxx_clk_init(void) omap2_init_clk_clkdm(c->lk.clk); } + /* Disable autoidle on all clocks; let the PM code enable it later */ + omap_clk_disable_autoidle_all(); + recalculate_root_clocks(); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", @@ -3551,7 +3554,8 @@ int __init omap3xxx_clk_init(void) clk_enable_init_clocks(); /* - * Lock DPLL5 and put it in autoidle. + * Lock DPLL5 -- here only until other device init code can + * handle this */ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) omap3_clk_lock_dpll5(); diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index dcbe10571a0..279534240fc 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3309,6 +3309,9 @@ int __init omap4xxx_clk_init(void) omap2_init_clk_clkdm(c->lk.clk); } + /* Disable autoidle on all clocks; let the PM code enable it later */ + omap_clk_disable_autoidle_all(); + recalculate_root_clocks(); /* -- cgit v1.2.3-70-g09d2 From eddb12624d9a8087f1f8f1a2812f840c5e8191ac Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 23 Feb 2011 00:14:04 -0700 Subject: OMAP2420: hwmod data: add dmtimer Add dmtimer data. Signed-off-by: Thara Gopinath Signed-off-by: Tarun Kanti DebBarma Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 634 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/dmtimer.h | 11 + 2 files changed, 645 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index f323c6bb22d..c2f84aa114b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -337,6 +338,625 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_timer_hwmod_class = { + .name = "timer", + .sysc = &omap2420_timer_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, +}; + +/* timer1 */ +static struct omap_hwmod omap2420_timer1_hwmod; +static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { + { .irq = 37, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { + { + .pa_start = 0x48028000, + .pa_end = 0x48028000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2420_timer1_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { + &omap2420_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap2420_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2420_timer1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs), + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, + }, + }, + .slaves = omap2420_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer2 */ +static struct omap_hwmod omap2420_timer2_hwmod; +static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { + { .irq = 38, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = { + { + .pa_start = 0x4802a000, + .pa_end = 0x4802a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2420_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { + &omap2420_l4_core__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap2420_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2420_timer2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs), + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, + }, + }, + .slaves = omap2420_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer3 */ +static struct omap_hwmod omap2420_timer3_hwmod; +static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { + { .irq = 39, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = { + { + .pa_start = 0x48078000, + .pa_end = 0x48078000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2420_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { + &omap2420_l4_core__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap2420_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2420_timer3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs), + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + }, + }, + .slaves = omap2420_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer4 */ +static struct omap_hwmod omap2420_timer4_hwmod; +static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { + { .irq = 40, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = { + { + .pa_start = 0x4807a000, + .pa_end = 0x4807a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2420_timer4_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { + &omap2420_l4_core__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap2420_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2420_timer4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs), + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, + }, + }, + .slaves = omap2420_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer5 */ +static struct omap_hwmod omap2420_timer5_hwmod; +static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { + { .irq = 41, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = { + { + .pa_start = 0x4807c000, + .pa_end = 0x4807c000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2420_timer5_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { + &omap2420_l4_core__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap2420_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2420_timer5_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs), + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + }, + }, + .slaves = omap2420_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + + +/* timer6 */ +static struct omap_hwmod omap2420_timer6_hwmod; +static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { + { .irq = 42, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = { + { + .pa_start = 0x4807e000, + .pa_end = 0x4807e000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2420_timer6_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { + &omap2420_l4_core__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap2420_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2420_timer6_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs), + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, + }, + }, + .slaves = omap2420_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer7 */ +static struct omap_hwmod omap2420_timer7_hwmod; +static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { + { .irq = 43, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = { + { + .pa_start = 0x48080000, + .pa_end = 0x48080000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2420_timer7_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { + &omap2420_l4_core__timer7, +}; + +/* timer7 hwmod */ +static struct omap_hwmod omap2420_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2420_timer7_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs), + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + }, + }, + .slaves = omap2420_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer8 */ +static struct omap_hwmod omap2420_timer8_hwmod; +static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { + { .irq = 44, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = { + { + .pa_start = 0x48082000, + .pa_end = 0x48082000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2420_timer8_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { + &omap2420_l4_core__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap2420_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2420_timer8_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs), + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, + }, + }, + .slaves = omap2420_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer9 */ +static struct omap_hwmod omap2420_timer9_hwmod; +static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { + { .irq = 45, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = { + { + .pa_start = 0x48084000, + .pa_end = 0x48084000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2420_timer9_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { + &omap2420_l4_core__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap2420_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2420_timer9_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs), + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + }, + }, + .slaves = omap2420_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer10 */ +static struct omap_hwmod omap2420_timer10_hwmod; +static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { + { .irq = 46, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x48086000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2420_timer10_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { + &omap2420_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap2420_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2420_timer10_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs), + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, + }, + }, + .slaves = omap2420_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer11 */ +static struct omap_hwmod omap2420_timer11_hwmod; +static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { + { .irq = 47, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x48088000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2420_timer11_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { + &omap2420_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap2420_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2420_timer11_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs), + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, + }, + }, + .slaves = omap2420_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer12 */ +static struct omap_hwmod omap2420_timer12_hwmod; +static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { + { .irq = 48, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = { + { + .pa_start = 0x4808a000, + .pa_end = 0x4808a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2420_timer12_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { + &omap2420_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap2420_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2420_timer12_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs), + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, + }, + }, + .slaves = omap2420_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { { @@ -1326,6 +1946,20 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, + + &omap2420_timer1_hwmod, + &omap2420_timer2_hwmod, + &omap2420_timer3_hwmod, + &omap2420_timer4_hwmod, + &omap2420_timer5_hwmod, + &omap2420_timer6_hwmod, + &omap2420_timer7_hwmod, + &omap2420_timer8_hwmod, + &omap2420_timer9_hwmod, + &omap2420_timer10_hwmod, + &omap2420_timer11_hwmod, + &omap2420_timer12_hwmod, + &omap2420_wd_timer2_hwmod, &omap2420_uart1_hwmod, &omap2420_uart2_hwmod, diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index dfa3aff9761..d6c70d2f403 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -3,6 +3,12 @@ * * OMAP Dual-Mode Timers * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Tarun Kanti DebBarma + * Thara Gopinath + * + * Platform device conversion and hwmod support. + * * Copyright (C) 2005 Nokia Corporation * Author: Lauri Leukkunen * PWM and clock framwork support by Timo Teras. @@ -44,6 +50,11 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 +/* + * IP revision identifier so that Highlander IP + * in OMAP4 can be distinguished. + */ +#define OMAP_TIMER_IP_VERSION_1 0x1 struct omap_dm_timer; extern struct omap_dm_timer *gptimer_wakeup; extern struct sys_timer omap_timer; -- cgit v1.2.3-70-g09d2 From b6b582291fbe8cca987c8823c87ee4a62b24f105 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 23 Feb 2011 00:14:05 -0700 Subject: OMAP2430: hwmod data: add dmtimer Add dmtimer data. Signed-off-by: Thara Gopinath Signed-off-by: Tarun Kanti DebBarma Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 633 +++++++++++++++++++++++++++++ 1 file changed, 633 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index de0015d3843..c03699653b0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "omap_hwmod_common_data.h" @@ -393,6 +394,624 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_timer_hwmod_class = { + .name = "timer", + .sysc = &omap2430_timer_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, +}; + +/* timer1 */ +static struct omap_hwmod omap2430_timer1_hwmod; +static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = { + { .irq = 37, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { + { + .pa_start = 0x49018000, + .pa_end = 0x49018000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2430_timer1_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { + &omap2430_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap2430_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2430_timer1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs), + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, + }, + }, + .slaves = omap2430_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer2 */ +static struct omap_hwmod omap2430_timer2_hwmod; +static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = { + { .irq = 38, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = { + { + .pa_start = 0x4802a000, + .pa_end = 0x4802a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2430_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { + &omap2430_l4_core__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap2430_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2430_timer2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs), + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, + }, + }, + .slaves = omap2430_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer3 */ +static struct omap_hwmod omap2430_timer3_hwmod; +static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = { + { .irq = 39, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = { + { + .pa_start = 0x48078000, + .pa_end = 0x48078000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2430_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { + &omap2430_l4_core__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap2430_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2430_timer3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs), + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + }, + }, + .slaves = omap2430_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer4 */ +static struct omap_hwmod omap2430_timer4_hwmod; +static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = { + { .irq = 40, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = { + { + .pa_start = 0x4807a000, + .pa_end = 0x4807a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2430_timer4_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { + &omap2430_l4_core__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap2430_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2430_timer4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs), + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, + }, + }, + .slaves = omap2430_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer5 */ +static struct omap_hwmod omap2430_timer5_hwmod; +static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = { + { .irq = 41, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = { + { + .pa_start = 0x4807c000, + .pa_end = 0x4807c000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2430_timer5_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { + &omap2430_l4_core__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap2430_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2430_timer5_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs), + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + }, + }, + .slaves = omap2430_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer6 */ +static struct omap_hwmod omap2430_timer6_hwmod; +static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = { + { .irq = 42, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = { + { + .pa_start = 0x4807e000, + .pa_end = 0x4807e000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2430_timer6_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { + &omap2430_l4_core__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap2430_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2430_timer6_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs), + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, + }, + }, + .slaves = omap2430_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer7 */ +static struct omap_hwmod omap2430_timer7_hwmod; +static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = { + { .irq = 43, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = { + { + .pa_start = 0x48080000, + .pa_end = 0x48080000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2430_timer7_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { + &omap2430_l4_core__timer7, +}; + +/* timer7 hwmod */ +static struct omap_hwmod omap2430_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2430_timer7_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs), + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + }, + }, + .slaves = omap2430_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer8 */ +static struct omap_hwmod omap2430_timer8_hwmod; +static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = { + { .irq = 44, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = { + { + .pa_start = 0x48082000, + .pa_end = 0x48082000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2430_timer8_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { + &omap2430_l4_core__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap2430_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2430_timer8_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs), + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, + }, + }, + .slaves = omap2430_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer9 */ +static struct omap_hwmod omap2430_timer9_hwmod; +static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = { + { .irq = 45, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = { + { + .pa_start = 0x48084000, + .pa_end = 0x48084000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2430_timer9_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { + &omap2430_l4_core__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap2430_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2430_timer9_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs), + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + }, + }, + .slaves = omap2430_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer10 */ +static struct omap_hwmod omap2430_timer10_hwmod; +static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = { + { .irq = 46, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x48086000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2430_timer10_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { + &omap2430_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap2430_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2430_timer10_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs), + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, + }, + }, + .slaves = omap2430_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer11 */ +static struct omap_hwmod omap2430_timer11_hwmod; +static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = { + { .irq = 47, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x48088000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2430_timer11_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { + &omap2430_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap2430_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2430_timer11_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs), + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, + }, + }, + .slaves = omap2430_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + +/* timer12 */ +static struct omap_hwmod omap2430_timer12_hwmod; +static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = { + { .irq = 48, }, +}; + +static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = { + { + .pa_start = 0x4808a000, + .pa_end = 0x4808a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2430_timer12_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { + &omap2430_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap2430_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2430_timer12_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs), + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, + }, + }, + .slaves = omap2430_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { { @@ -1514,6 +2133,20 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, &omap2430_iva_hwmod, + + &omap2430_timer1_hwmod, + &omap2430_timer2_hwmod, + &omap2430_timer3_hwmod, + &omap2430_timer4_hwmod, + &omap2430_timer5_hwmod, + &omap2430_timer6_hwmod, + &omap2430_timer7_hwmod, + &omap2430_timer8_hwmod, + &omap2430_timer9_hwmod, + &omap2430_timer10_hwmod, + &omap2430_timer11_hwmod, + &omap2430_timer12_hwmod, + &omap2430_wd_timer2_hwmod, &omap2430_uart1_hwmod, &omap2430_uart2_hwmod, -- cgit v1.2.3-70-g09d2 From ce722d269ff85ab11aa680784bcc6eff06e3e3ea Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 23 Feb 2011 00:14:05 -0700 Subject: OMAP3: hwmod data: add dmtimer Add dmtimer data. Signed-off-by: Thara Gopinath Signed-off-by: Tarun Kanti DebBarma Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 649 +++++++++++++++++++++++++++++ 1 file changed, 649 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e9d00122856..b8776ee241f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -515,6 +516,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* timer class */ +static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { + .name = "timer", + .sysc = &omap3xxx_timer_1ms_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { + .name = "timer", + .sysc = &omap3xxx_timer_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, +}; + +/* timer1 */ +static struct omap_hwmod omap3xxx_timer1_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = { + { .irq = 37, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { + { + .pa_start = 0x48318000, + .pa_end = 0x48318000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap3xxx_timer1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { + &omap3xxx_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap3xxx_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap3xxx_timer1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs), + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, + }, + }, + .slaves = omap3xxx_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer2 */ +static struct omap_hwmod omap3xxx_timer2_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = { + { .irq = 38, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { + { + .pa_start = 0x49032000, + .pa_end = 0x49032000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap3xxx_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { + &omap3xxx_l4_per__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap3xxx_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap3xxx_timer2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs), + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, + }, + }, + .slaves = omap3xxx_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer3 */ +static struct omap_hwmod omap3xxx_timer3_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = { + { .irq = 39, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { + { + .pa_start = 0x49034000, + .pa_end = 0x49034000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap3xxx_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { + &omap3xxx_l4_per__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap3xxx_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap3xxx_timer3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs), + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, + }, + }, + .slaves = omap3xxx_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer4 */ +static struct omap_hwmod omap3xxx_timer4_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = { + { .irq = 40, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { + { + .pa_start = 0x49036000, + .pa_end = 0x49036000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap3xxx_timer4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { + &omap3xxx_l4_per__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap3xxx_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap3xxx_timer4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs), + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, + }, + }, + .slaves = omap3xxx_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer5 */ +static struct omap_hwmod omap3xxx_timer5_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = { + { .irq = 41, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { + { + .pa_start = 0x49038000, + .pa_end = 0x49038000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap3xxx_timer5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { + &omap3xxx_l4_per__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap3xxx_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap3xxx_timer5_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs), + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT5_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, + }, + }, + .slaves = omap3xxx_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer6 */ +static struct omap_hwmod omap3xxx_timer6_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = { + { .irq = 42, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { + { + .pa_start = 0x4903A000, + .pa_end = 0x4903A000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer6 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap3xxx_timer6_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { + &omap3xxx_l4_per__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap3xxx_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap3xxx_timer6_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs), + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT6_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, + }, + }, + .slaves = omap3xxx_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer7 */ +static struct omap_hwmod omap3xxx_timer7_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = { + { .irq = 43, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { + { + .pa_start = 0x4903C000, + .pa_end = 0x4903C000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer7 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap3xxx_timer7_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { + &omap3xxx_l4_per__timer7, +}; + +/* timer7 hwmod */ +static struct omap_hwmod omap3xxx_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap3xxx_timer7_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs), + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT7_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, + }, + }, + .slaves = omap3xxx_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer8 */ +static struct omap_hwmod omap3xxx_timer8_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = { + { .irq = 44, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { + { + .pa_start = 0x4903E000, + .pa_end = 0x4903E000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer8 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap3xxx_timer8_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { + &omap3xxx_l4_per__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap3xxx_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap3xxx_timer8_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs), + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT8_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, + }, + }, + .slaves = omap3xxx_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer9 */ +static struct omap_hwmod omap3xxx_timer9_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = { + { .irq = 45, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { + { + .pa_start = 0x49040000, + .pa_end = 0x49040000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap3xxx_timer9_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { + &omap3xxx_l4_per__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap3xxx_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap3xxx_timer9_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs), + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT9_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, + }, + }, + .slaves = omap3xxx_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer10 */ +static struct omap_hwmod omap3xxx_timer10_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = { + { .irq = 46, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x48086000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap3xxx_timer10_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { + &omap3xxx_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap3xxx_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap3xxx_timer10_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs), + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, + }, + }, + .slaves = omap3xxx_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer11 */ +static struct omap_hwmod omap3xxx_timer11_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = { + { .irq = 47, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x48088000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap3xxx_timer11_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { + &omap3xxx_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap3xxx_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap3xxx_timer11_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs), + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, + }, + }, + .slaves = omap3xxx_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + +/* timer12*/ +static struct omap_hwmod omap3xxx_timer12_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { + { .irq = 95, }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { + { + .pa_start = 0x48304000, + .pa_end = 0x48304000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap3xxx_timer12_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { + &omap3xxx_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap3xxx_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap3xxx_timer12_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs), + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_GPT12_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, + }, + }, + .slaves = omap3xxx_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { { @@ -2219,6 +2854,20 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + + &omap3xxx_timer1_hwmod, + &omap3xxx_timer2_hwmod, + &omap3xxx_timer3_hwmod, + &omap3xxx_timer4_hwmod, + &omap3xxx_timer5_hwmod, + &omap3xxx_timer6_hwmod, + &omap3xxx_timer7_hwmod, + &omap3xxx_timer8_hwmod, + &omap3xxx_timer9_hwmod, + &omap3xxx_timer10_hwmod, + &omap3xxx_timer11_hwmod, + &omap3xxx_timer12_hwmod, + &omap3xxx_wd_timer2_hwmod, &omap3xxx_uart1_hwmod, &omap3xxx_uart2_hwmod, -- cgit v1.2.3-70-g09d2 From bac1a0f0bbf0b11b23fe714826f29fc9aeb35855 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 23 Feb 2011 00:14:06 -0700 Subject: OMAP2+: hwmod: allow multiple calls to omap_hwmod_init() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no longer any reason why we should prevent multiple calls to omap_hwmod_init(). It is now simply used to register an array of hwmods. This should allow a subset of hwmods (e.g., hwmods handling the system clocksource and clockevents) to be registered earlier than the remaining mass of hwmods. Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 9e89a58711b..2a7ab6adee8 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list); /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; -/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ -static u8 inited; - /* Private functions */ @@ -1595,26 +1592,20 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), */ int __init omap_hwmod_init(struct omap_hwmod **ohs) { - struct omap_hwmod *oh; - int r; - - if (inited) - return -EINVAL; - - inited = 1; + int r, i; if (!ohs) return 0; - oh = *ohs; - while (oh) { - if (omap_chip_is(oh->omap_chip)) { - r = _register(oh); - WARN(r, "omap_hwmod: %s: _register returned " - "%d\n", oh->name, r); - } - oh = *++ohs; - } + i = 0; + do { + if (!omap_chip_is(ohs[i]->omap_chip)) + continue; + + r = _register(ohs[i]); + WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, + r); + } while (ohs[++i]); return 0; } -- cgit v1.2.3-70-g09d2 From 550c8092c55c22db8f843bad070fd1731292a75e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Mon, 28 Feb 2011 11:58:14 -0700 Subject: OMAP2+: hwmod: rename some init functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename omap_hwmod_init() to omap_hwmod_register(). Rename omap_hwmod_late_init() to omap_hwmod_setup_all(). Also change all of the callers to reflect the new names. While here, update some copyrights. Suggested by Tony Lindgren . N.B. The comment in mach-omap2/serial.c may no longer be correct, given recent changes in init order. Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Kevin Hilman Cc: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 33 +++++++++++++--------------- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 2 +- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +- arch/arm/mach-omap2/serial.c | 2 +- arch/arm/plat-omap/include/plat/omap_hwmod.h | 6 +++-- 7 files changed, 24 insertions(+), 25 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2a7ab6adee8..557d9eb609a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1,7 +1,7 @@ /* * omap_hwmod implementation for OMAP2/3/4 * - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009-2011 Nokia Corporation * * Paul Walmsley, Benoît Cousson, Kevin Hilman * @@ -901,7 +901,7 @@ static struct omap_hwmod *_lookup(const char *name) * @oh: struct omap_hwmod * * @data: not used; pass NULL * - * Called by omap_hwmod_late_init() (after omap2_clk_init()). + * Called by omap_hwmod_setup_all() (after omap2_clk_init()). * Resolves all clock names embedded in the hwmod. Returns -EINVAL if * the omap_hwmod has not yet been registered or if the clocks have * already been initialized, 0 on success, or a non-zero error on @@ -1580,17 +1580,15 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), return ret; } - /** - * omap_hwmod_init - init omap_hwmod code and register hwmods + * omap_hwmod_register - register an array of hwmods * @ohs: pointer to an array of omap_hwmods to register * * Intended to be called early in boot before the clock framework is * initialized. If @ohs is not null, will register all omap_hwmods - * listed in @ohs that are valid for this chip. Returns -EINVAL if - * omap_hwmod_init() has already been called or 0 otherwise. + * listed in @ohs that are valid for this chip. Returns 0. */ -int __init omap_hwmod_init(struct omap_hwmod **ohs) +int __init omap_hwmod_register(struct omap_hwmod **ohs) { int r, i; @@ -1613,9 +1611,8 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs) /* * _populate_mpu_rt_base - populate the virtual address for a hwmod * - * Must be called only from omap_hwmod_late_init so ioremap works properly. + * Must be called only from omap_hwmod_setup_all() so ioremap works properly. * Assumes the caller takes care of locking if needed. - * */ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) { @@ -1631,13 +1628,13 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) } /** - * omap_hwmod_late_init - do some post-clock framework initialization + * omap_hwmod_setup - do some post-clock framework initialization * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls * _setup() on each hwmod. Returns 0. */ -static int __init omap_hwmod_late_init(void) +static int __init omap_hwmod_setup_all(void) { int r; @@ -1645,7 +1642,7 @@ static int __init omap_hwmod_late_init(void) /* XXX check return value */ r = omap_hwmod_for_each(_init_clocks, NULL); - WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); + WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__); mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", @@ -1655,7 +1652,7 @@ static int __init omap_hwmod_late_init(void) return 0; } -core_initcall(omap_hwmod_late_init); +core_initcall(omap_hwmod_setup_all); /** * omap_hwmod_enable - enable an omap_hwmod @@ -2174,11 +2171,11 @@ int omap_hwmod_for_each_by_class(const char *classname, * @oh: struct omap_hwmod * * @state: state that _setup() should leave the hwmod in * - * Sets the hwmod state that @oh will enter at the end of _setup() (called by - * omap_hwmod_late_init()). Only valid to call between calls to - * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or - * -EINVAL if there is a problem with the arguments or if the hwmod is - * in the wrong state. + * Sets the hwmod state that @oh will enter at the end of _setup() + * (called by omap_hwmod_setup_all()). Only valid to call between + * calling omap_hwmod_register() and omap_hwmod_setup_all(). Returns + * 0 upon success or -EINVAL if there is a problem with the arguments + * or if the hwmod is in the wrong state. */ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) { diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index c2f84aa114b..e58621aa9b3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1990,5 +1990,5 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { int __init omap2420_hwmod_init(void) { - return omap_hwmod_init(omap2420_hwmods); + return omap_hwmod_register(omap2420_hwmods); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c03699653b0..b46a54ce1a4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -2183,5 +2183,5 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { int __init omap2430_hwmod_init(void) { - return omap_hwmod_init(omap2430_hwmods); + return omap_hwmod_register(omap2430_hwmods); } diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index b8776ee241f..fc1b2b963bb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2919,5 +2919,5 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { int __init omap3xxx_hwmod_init(void) { - return omap_hwmod_init(omap3xxx_hwmods); + return omap_hwmod_register(omap3xxx_hwmods); } diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 79a86017891..2c5882792e0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -5125,6 +5125,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { int __init omap44xx_hwmod_init(void) { - return omap_hwmod_init(omap44xx_hwmods); + return omap_hwmod_register(omap44xx_hwmods); } diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 47eef48b883..1ac361b7b8c 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -680,7 +680,7 @@ static int __init omap_serial_early_init(void) num_uarts++; /* - * NOTE: omap_hwmod_init() has not yet been called, + * NOTE: omap_hwmod_setup*() has not yet been called, * so no hwmod functions will work yet. */ diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index fedd82971c9..afdf1971c51 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -1,7 +1,7 @@ /* * omap_hwmod macros, structures * - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009-2011 Nokia Corporation * Paul Walmsley * * Created in collaboration with (alphabetical order): Benoît Cousson, @@ -370,8 +370,10 @@ struct omap_hwmod_omap4_prcm { * of standby, rather than relying on module smart-standby * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for * SDRAM controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_RESET * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM * controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_IDLE * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) * when module is enabled, rather than the default, which is to * enable autoidle @@ -535,7 +537,7 @@ struct omap_hwmod { const struct omap_chip_id omap_chip; }; -int omap_hwmod_init(struct omap_hwmod **ohs); +int omap_hwmod_register(struct omap_hwmod **ohs); struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); -- cgit v1.2.3-70-g09d2 From 569edd705cc4e81a9129b5557f1fb259e21418a9 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 23 Feb 2011 00:14:06 -0700 Subject: OMAP2+: hwmod: find MPU initiator hwmod during in _register() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the code that looks for the MPU initiator hwmod to run during the individual hwmod _register() function. (Previously, it ran after all hwmods were registered in the omap_hwmod_late_init() function.) This is done so code can late-initialize a few individual hwmods -- for example, for the system timer -- before the entire set of hwmods is initialized later in boot via omap_hwmod_late_init(). Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 557d9eb609a..e4c934bd25b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1452,7 +1452,7 @@ static int _setup(struct omap_hwmod *oh, void *data) */ static int __init _register(struct omap_hwmod *oh) { - int ret, ms_id; + int ms_id; if (!oh || !oh->name || !oh->class || !oh->class->name || (oh->_state != _HWMOD_STATE_UNKNOWN)) @@ -1475,9 +1475,14 @@ static int __init _register(struct omap_hwmod *oh) oh->_state = _HWMOD_STATE_REGISTERED; - ret = 0; + /* + * XXX Rather than doing a strcmp(), this should test a flag + * set in the hwmod data, inserted by the autogenerator code. + */ + if (!strcmp(oh->name, MPU_INITIATOR_NAME)) + mpu_oh = oh; - return ret; + return 0; } @@ -1632,22 +1637,24 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls - * _setup() on each hwmod. Returns 0. + * _setup() on each hwmod. Returns 0 upon success or -EINVAL upon error. */ static int __init omap_hwmod_setup_all(void) { int r; + if (!mpu_oh) { + pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", + __func__, MPU_INITIATOR_NAME); + return -EINVAL; + } + r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); /* XXX check return value */ r = omap_hwmod_for_each(_init_clocks, NULL); WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__); - mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); - WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", - MPU_INITIATOR_NAME); - omap_hwmod_for_each(_setup, NULL); return 0; -- cgit v1.2.3-70-g09d2 From 48d54f3fd20b435311f295b3bca3570096a2ac83 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 23 Feb 2011 00:14:07 -0700 Subject: OMAP2+: hwmod: ignore attempts to re-setup a hwmod MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously, if a hwmod had already been set up, and the code attempted to set up the hwmod again, an error would be returned. This is not really useful behavior if we wish to allow the OMAP core code to setup the hwmods needed for the Linux clocksources and clockevents before the rest of the hwmods are setup. So, instead of generating errors, just ignore the attempt to re-setup the hwmod. Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e4c934bd25b..43aa894174f 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -902,17 +902,15 @@ static struct omap_hwmod *_lookup(const char *name) * @data: not used; pass NULL * * Called by omap_hwmod_setup_all() (after omap2_clk_init()). - * Resolves all clock names embedded in the hwmod. Returns -EINVAL if - * the omap_hwmod has not yet been registered or if the clocks have - * already been initialized, 0 on success, or a non-zero error on - * failure. + * Resolves all clock names embedded in the hwmod. Returns 0 on + * success, or a negative error code on failure. */ static int _init_clocks(struct omap_hwmod *oh, void *data) { int ret = 0; - if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) - return -EINVAL; + if (oh->_state != _HWMOD_STATE_REGISTERED) + return 0; pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); @@ -1351,14 +1349,16 @@ static int _shutdown(struct omap_hwmod *oh) * @oh: struct omap_hwmod * * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the - * wrong state or returns 0. + * OCP_SYSCONFIG register. Returns 0. */ static int _setup(struct omap_hwmod *oh, void *data) { int i, r; u8 postsetup_state; + if (oh->_state != _HWMOD_STATE_CLKS_INITED) + return 0; + /* Set iclk autoidle mode */ if (oh->slaves_cnt > 0) { for (i = 0; i < oh->slaves_cnt; i++) { @@ -1621,6 +1621,9 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs) */ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) { + if (oh->_state != _HWMOD_STATE_REGISTERED) + return 0; + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) return 0; -- cgit v1.2.3-70-g09d2 From a2debdbd1ad896a410019c9cf30785cad15930fc Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 23 Feb 2011 00:14:07 -0700 Subject: OMAP2+: hwmod: add ability to setup individual hwmods MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add omap_hwmod_setup_one(), which is intended for use early in boot to selectively setup the hwmods needed for system clocksources and clockevents, and any other hwmod that is needed in early boot. omap_hwmod_setup_all() can then be called later in the boot process. The point is to minimize the amount of code that needs to be run early. Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Kevin Hilman Cc: Santosh Shilimkar Cc: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 62 ++++++++++++++++++++++++---- arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 ++ 2 files changed, 58 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 43aa894174f..f76f133780c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -901,7 +901,7 @@ static struct omap_hwmod *_lookup(const char *name) * @oh: struct omap_hwmod * * @data: not used; pass NULL * - * Called by omap_hwmod_setup_all() (after omap2_clk_init()). + * Called by omap_hwmod_setup_*() (after omap2_clk_init()). * Resolves all clock names embedded in the hwmod. Returns 0 on * success, or a negative error code on failure. */ @@ -1616,7 +1616,7 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs) /* * _populate_mpu_rt_base - populate the virtual address for a hwmod * - * Must be called only from omap_hwmod_setup_all() so ioremap works properly. + * Must be called only from omap_hwmod_setup_*() so ioremap works properly. * Assumes the caller takes care of locking if needed. */ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) @@ -1635,12 +1635,60 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) return 0; } +/** + * omap_hwmod_setup_one - set up a single hwmod + * @oh_name: const char * name of the already-registered hwmod to set up + * + * Must be called after omap2_clk_init(). Resolves the struct clk + * names to struct clk pointers for each registered omap_hwmod. Also + * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon + * success. + */ +int __init omap_hwmod_setup_one(const char *oh_name) +{ + struct omap_hwmod *oh; + int r; + + pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); + + if (!mpu_oh) { + pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", + oh_name, MPU_INITIATOR_NAME); + return -EINVAL; + } + + oh = _lookup(oh_name); + if (!oh) { + WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); + return -EINVAL; + } + + if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) + omap_hwmod_setup_one(MPU_INITIATOR_NAME); + + r = _populate_mpu_rt_base(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); + return -EINVAL; + } + + r = _init_clocks(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); + return -EINVAL; + } + + _setup(oh, NULL); + + return 0; +} + /** * omap_hwmod_setup - do some post-clock framework initialization * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls - * _setup() on each hwmod. Returns 0 upon success or -EINVAL upon error. + * _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) { @@ -1654,9 +1702,9 @@ static int __init omap_hwmod_setup_all(void) r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); - /* XXX check return value */ r = omap_hwmod_for_each(_init_clocks, NULL); - WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__); + WARN(IS_ERR_VALUE(r), + "omap_hwmod: %s: _init_clocks failed\n", __func__); omap_hwmod_for_each(_setup, NULL); @@ -2182,8 +2230,8 @@ int omap_hwmod_for_each_by_class(const char *classname, * @state: state that _setup() should leave the hwmod in * * Sets the hwmod state that @oh will enter at the end of _setup() - * (called by omap_hwmod_setup_all()). Only valid to call between - * calling omap_hwmod_register() and omap_hwmod_setup_all(). Returns + * (called by omap_hwmod_setup_*()). Only valid to call between + * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns * 0 upon success or -EINVAL if there is a problem with the arguments * or if the hwmod is in the wrong state. */ diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index afdf1971c51..f96e72ed4db 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -30,6 +30,7 @@ #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H #include +#include #include #include #include @@ -542,6 +543,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); +int __init omap_hwmod_setup_one(const char *name); + int omap_hwmod_enable(struct omap_hwmod *oh); int _omap_hwmod_enable(struct omap_hwmod *oh); int omap_hwmod_idle(struct omap_hwmod *oh); -- cgit v1.2.3-70-g09d2 From 38698bef545403a334cf92153874bd06dc22cc66 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 23 Feb 2011 00:14:08 -0700 Subject: OMAP2+: clockevent: set up GPTIMER clockevent hwmod right before timer init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set up the GPTIMER hwmod used for the clockevent source immediately before it is used. This avoids the need to set up all of the hwmods until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.) This second version fixes a bug pointed out by Santosh Shilimkar , that would cause the kernel to use an incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 - thanks Santosh. Also, Tarun Kanti DebBarma pointed out that the original patch did not apply cleanly; this has now been fixed. Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Tony Lindgren Cc: Kevin Hilman Cc: Santosh Shilimkar Acked-by: Santosh Shilimkar Cc: Tarun Kanti DebBarma --- arch/arm/mach-omap2/timer-gp.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 7b7c2683ae7..fb8d656e4d0 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -39,10 +39,11 @@ #include #include #include +#include +#include #include "timer-gp.h" -#include /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 @@ -132,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; int src; + char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */ inited = 1; + sprintf(clockevent_hwmod_name, "timer%d", gptimer_id); + omap_hwmod_setup_one(clockevent_hwmod_name); + gptimer = omap_dm_timer_request_specific(gptimer_id); BUG_ON(gptimer == NULL); gptimer_wakeup = gptimer; -- cgit v1.2.3-70-g09d2 From aca6ad073ea820776bf5bdb87cf82eace35042c8 Mon Sep 17 00:00:00 2001 From: Eyal Reizer Date: Sun, 27 Feb 2011 10:45:18 +0000 Subject: omap: omap3evm: add support for the WL12xx WLAN module to the omap3evm This patch is again current omap-for-linus branch Adds platform initialization for working with the WLAN module attached to the omap3evm. The patch includes MMC2 initialization, SDIO and control pins muxing and platform device registration. Signed-off-by: Eyal Reizer Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3evm.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 5364147892c..7341f966bf1 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -411,7 +411,7 @@ static struct omap2_hsmmc_info mmc[] = { #ifdef CONFIG_WL12XX_PLATFORM_DATA { .name = "wl1271", - .mmc = 2, + .mmc = 2, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, .gpio_wp = -EINVAL, .gpio_cd = -EINVAL, @@ -603,10 +603,8 @@ static struct regulator_init_data omap3evm_vio = { #define OMAP3EVM_WLAN_PMENA_GPIO (150) #define OMAP3EVM_WLAN_IRQ_GPIO (149) -static struct regulator_consumer_supply omap3evm_vmmc2_supply = { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", -}; +static struct regulator_consumer_supply omap3evm_vmmc2_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); /* VMMC2 for driving the WL12xx module */ static struct regulator_init_data omap3evm_vmmc2 = { @@ -627,7 +625,7 @@ static struct fixed_voltage_config omap3evm_vwlan = { .init_data = &omap3evm_vmmc2, }; -static struct platform_device omap3evm_vwlan_device = { +static struct platform_device omap3evm_wlan_regulator = { .name = "reg-fixed-voltage", .id = 1, .dev = { @@ -637,8 +635,7 @@ static struct platform_device omap3evm_vwlan_device = { struct wl12xx_platform_data omap3evm_wlan_data __initdata = { .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO), - /* ref clock is 38.4 MHz */ - .board_ref_clock = 2, + .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ }; #endif @@ -765,7 +762,7 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = { OMAP_PIN_OFF_NONE), #ifdef CONFIG_WL12XX_PLATFORM_DATA /* WLAN IRQ - GPIO 149 */ - OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), /* WLAN POWER ENABLE - GPIO 150 */ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), @@ -801,6 +798,21 @@ static struct omap_board_mux omap36x_board_mux[] __initdata = { OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), +#ifdef CONFIG_WL12XX_PLATFORM_DATA + /* WLAN IRQ - GPIO 149 */ + OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + + /* WLAN POWER ENABLE - GPIO 150 */ + OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + /* MMC2 SDIO pin muxes for WL12xx */ + OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), +#endif { .reg_offset = OMAP_MUX_TERMINATOR }, }; @@ -871,7 +883,7 @@ static void __init omap3_evm_init(void) /* WL12xx WLAN Init */ if (wl12xx_set_platform_data(&omap3evm_wlan_data)) pr_err("error setting wl12xx data\n"); - platform_device_register(&omap3evm_vwlan_device); + platform_device_register(&omap3evm_wlan_regulator); #endif } -- cgit v1.2.3-70-g09d2 From e08016d0f4fcfe038a402071ada3073c6ca8d62d Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Tue, 1 Mar 2011 13:12:55 -0800 Subject: omap: mmc: split out init for 2420 The MMC controller on the OMAP2420 is different from those on the OMAP2430, OMAP3 and OMAP4 families - all of the latter are identical. The one on the OMAP2420 is closer to that on OMAP1 chips. Currently, the n8x0 is the only OMAP2420 platform supported in mainline which registers the MMC controller. Upcoming changes to register the controllers using hwmod data are potentially invasive. To reduce the risk, separate out the 2420 controller registration from the common init function and update its only user. Also seperating out mux settings for OMAP2420. Signed-off-by: Anand Gadiyar Signed-off-by: Kishore Kadiyala Cc: Tony Lindgren Cc: Madhusudhan Chikkature Cc: Chris Ball Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 2 +- arch/arm/mach-omap2/devices.c | 88 ++++++++++++++++++++++------------- arch/arm/plat-omap/include/plat/mmc.h | 4 ++ 3 files changed, 61 insertions(+), 33 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index b36cbd21e2d..e710cd9e079 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -536,7 +536,7 @@ static void __init n8x0_mmc_init(void) } mmc_data[0] = &mmc1_data; - omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC); + omap242x_init_mmc(mmc_data); } #else diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 9ee876fd367..100bb425e9c 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -650,11 +650,10 @@ err1: static inline void omap_hsmmc_reset(void) {} #endif -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ - defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, - int controller_nr) +static inline void omap242x_mmc_mux(struct omap_mmc_platform_data + *mmc_controller) { if ((mmc_controller->slots[0].switch_pin > 0) && \ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) @@ -665,33 +664,61 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, OMAP_PIN_INPUT_PULLUP); - if (cpu_is_omap2420() && controller_nr == 0) { - omap_mux_init_signal("sdmmc_cmd", 0); - omap_mux_init_signal("sdmmc_clki", 0); - omap_mux_init_signal("sdmmc_clko", 0); - omap_mux_init_signal("sdmmc_dat0", 0); - omap_mux_init_signal("sdmmc_dat_dir0", 0); - omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { - omap_mux_init_signal("sdmmc_dat1", 0); - omap_mux_init_signal("sdmmc_dat2", 0); - omap_mux_init_signal("sdmmc_dat3", 0); - omap_mux_init_signal("sdmmc_dat_dir1", 0); - omap_mux_init_signal("sdmmc_dat_dir2", 0); - omap_mux_init_signal("sdmmc_dat_dir3", 0); - } + omap_mux_init_signal("sdmmc_cmd", 0); + omap_mux_init_signal("sdmmc_clki", 0); + omap_mux_init_signal("sdmmc_clko", 0); + omap_mux_init_signal("sdmmc_dat0", 0); + omap_mux_init_signal("sdmmc_dat_dir0", 0); + omap_mux_init_signal("sdmmc_cmd_dir", 0); + if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { + omap_mux_init_signal("sdmmc_dat1", 0); + omap_mux_init_signal("sdmmc_dat2", 0); + omap_mux_init_signal("sdmmc_dat3", 0); + omap_mux_init_signal("sdmmc_dat_dir1", 0); + omap_mux_init_signal("sdmmc_dat_dir2", 0); + omap_mux_init_signal("sdmmc_dat_dir3", 0); + } - /* - * Use internal loop-back in MMC/SDIO Module Input Clock - * selection - */ - if (mmc_controller->slots[0].internal_clock) { - u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - v |= (1 << 24); - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); - } + /* + * Use internal loop-back in MMC/SDIO Module Input Clock + * selection + */ + if (mmc_controller->slots[0].internal_clock) { + u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + v |= (1 << 24); + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + } +} + +void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) +{ + char *name = "mmci-omap"; + + if (!mmc_data[0]) { + pr_err("%s fails: Incomplete platform data\n", __func__); + return; } + omap242x_mmc_mux(mmc_data[0]); + omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, + INT_24XX_MMC_IRQ, mmc_data[0]); +} + +#endif + +#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) + +static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, + int controller_nr) +{ + if ((mmc_controller->slots[0].switch_pin > 0) && \ + (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, + OMAP_PIN_INPUT_PULLUP); + if ((mmc_controller->slots[0].gpio_wp > 0) && \ + (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, + OMAP_PIN_INPUT_PULLUP); if (cpu_is_omap34xx()) { if (controller_nr == 0) { omap_mux_init_signal("sdmmc1_clk", @@ -808,10 +835,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, continue; } - if (cpu_is_omap2420()) { - size = OMAP2420_MMC_SIZE; - name = "mmci-omap"; - } else if (cpu_is_omap44xx()) { + if (cpu_is_omap44xx()) { if (i < 3) irq += OMAP44XX_IRQ_GIC_START; size = OMAP4_HSMMC_SIZE; diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index f57f36abb07..e5de5d452b3 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -159,6 +159,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot, defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers); +void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers); int omap_mmc_add(const char *name, int id, unsigned long base, @@ -169,6 +170,9 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers) { } +static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) +{ +} static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers) { -- cgit v1.2.3-70-g09d2 From bce06f375644f8b28fbc1d261699fdfe459733ad Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 1 Mar 2011 13:12:55 -0800 Subject: OMAP2430: hwmod data: Add HSMMC Update the omap2430 hwmod data with the HSMMC info. Signed-off-by: Paul Walmsley Signed-off-by: Kevin Hilman Signed-off-by: Rajendra Nayak Cc: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 148 +++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index b46a54ce1a4..0d239e3a980 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -55,6 +55,8 @@ static struct omap_hwmod omap2430_dma_system_hwmod; static struct omap_hwmod omap2430_mcspi1_hwmod; static struct omap_hwmod omap2430_mcspi2_hwmod; static struct omap_hwmod omap2430_mcspi3_hwmod; +static struct omap_hwmod omap2430_mmc1_hwmod; +static struct omap_hwmod omap2430_mmc2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -251,6 +253,42 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { &omap2430_l4_core__usbhsotg, }; +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c1ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap2430_mmc1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b41ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mmc2_hwmod, + .addr = omap2430_mmc2_addr_space, + .clk = "mmchs2_ick", + .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { &omap2430_l3_main__l4_core, @@ -259,6 +297,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { &omap2430_l4_core__l4_wkup, + &omap2430_l4_core__mmc1, + &omap2430_l4_core__mmc2, }; /* L4 CORE */ @@ -2127,6 +2167,112 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { +/* MMC/SD/SDIO common */ + +static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mmc_class = { + .name = "mmc", + .sysc = &omap2430_mmc_sysc, +}; + +/* MMC/SD/SDIO1 */ + +static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { + { .irq = 83 }, +}; + +static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { + { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ + { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ +}; + +static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb1_fck" }, +}; + +static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { + &omap2430_l4_core__mmc1, +}; + +static struct omap_hwmod omap2430_mmc1_hwmod = { + .name = "mmc1", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2430_mmc1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs), + .sdma_reqs = omap2430_mmc1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs), + .opt_clks = omap2430_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS1_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, + }, + }, + .slaves = omap2430_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), + .class = &omap2430_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* MMC/SD/SDIO2 */ + +static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { + { .irq = 86 }, +}; + +static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { + { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ + { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ +}; + +static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { + { .role = "dbck", .clk = "mmchsdb2_fck" }, +}; + +static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { + &omap2430_l4_core__mmc2, +}; + +static struct omap_hwmod omap2430_mmc2_hwmod = { + .name = "mmc2", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .mpu_irqs = omap2430_mmc2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs), + .sdma_reqs = omap2430_mmc2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs), + .opt_clks = omap2430_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP2430_EN_MMCHS2_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, + }, + }, + .slaves = omap2430_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), + .class = &omap2430_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, @@ -2159,6 +2305,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { /* i2c class */ &omap2430_i2c1_hwmod, &omap2430_i2c2_hwmod, + &omap2430_mmc1_hwmod, + &omap2430_mmc2_hwmod, /* gpio class */ &omap2430_gpio1_hwmod, -- cgit v1.2.3-70-g09d2 From b163605e3f2051e0cbd378d46a91cab2563b7ebf Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 1 Mar 2011 13:12:56 -0800 Subject: OMAP3: hwmod data: Add HSMMC Update the omap3 hwmod data with the HSMMC info. Signed-off-by: Paul Walmsley Signed-off-by: Kevin Hilman Signed-off-by: Rajendra Nayak Signed-off-by: Kishore Kadiyala Cc: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 209 +++++++++++++++++++++++++++++ arch/arm/mach-omap2/prcm-common.h | 4 + 2 files changed, 213 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index fc1b2b963bb..207ccfbac2e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -69,6 +69,9 @@ static struct omap_hwmod omap34xx_mcspi1; static struct omap_hwmod omap34xx_mcspi2; static struct omap_hwmod omap34xx_mcspi3; static struct omap_hwmod omap34xx_mcspi4; +static struct omap_hwmod omap3xxx_mmc1_hwmod; +static struct omap_hwmod omap3xxx_mmc2_hwmod; +static struct omap_hwmod omap3xxx_mmc3_hwmod; static struct omap_hwmod am35xx_usbhsotg_hwmod; static struct omap_hwmod omap3xxx_dma_system_hwmod; @@ -159,6 +162,63 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> MMC1 interface */ +static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = { + { + .pa_start = 0x4809c000, + .pa_end = 0x4809c1ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc1_hwmod, + .clk = "mmchs1_ick", + .addr = omap3xxx_mmc1_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> MMC2 interface */ +static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = { + { + .pa_start = 0x480b4000, + .pa_end = 0x480b41ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc2_hwmod, + .clk = "mmchs2_ick", + .addr = omap3xxx_mmc2_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + +/* L4 CORE -> MMC3 interface */ +static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { + { + .pa_start = 0x480ad000, + .pa_end = 0x480ad1ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mmc3_hwmod, + .clk = "mmchs3_ick", + .addr = omap3xxx_mmc3_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 +}; + /* L4 CORE -> UART1 interface */ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { { @@ -2847,11 +2907,160 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) }; +/* MMC/SD/SDIO common */ + +static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { + .rev_offs = 0x1fc, + .sysc_offs = 0x10, + .syss_offs = 0x14, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap34xx_mmc_class = { + .name = "mmc", + .sysc = &omap34xx_mmc_sysc, +}; + +/* MMC/SD/SDIO1 */ + +static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { + { .irq = 83, }, +}; + +static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { + { .name = "tx", .dma_req = 61, }, + { .name = "rx", .dma_req = 62, }, +}; + +static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { + &omap3xxx_l4_core__mmc1, +}; + +static struct omap_hwmod omap3xxx_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs), + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs), + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + }, + }, + .slaves = omap3xxx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), + .class = &omap34xx_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* MMC/SD/SDIO2 */ + +static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { + { .irq = INT_24XX_MMC2_IRQ, }, +}; + +static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { + { .name = "tx", .dma_req = 47, }, + { .name = "rx", .dma_req = 48, }, +}; + +static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { + &omap3xxx_l4_core__mmc2, +}; + +static struct omap_hwmod omap3xxx_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs), + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs), + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, + }, + .slaves = omap3xxx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), + .class = &omap34xx_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* MMC/SD/SDIO3 */ + +static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { + { .irq = 94, }, +}; + +static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { + { .name = "tx", .dma_req = 77, }, + { .name = "rx", .dma_req = 78, }, +}; + +static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { + { .role = "dbck", .clk = "omap_32k_fck", }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { + &omap3xxx_l4_core__mmc3, +}; + +static struct omap_hwmod omap3xxx_mmc3_hwmod = { + .name = "mmc3", + .mpu_irqs = omap34xx_mmc3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs), + .sdma_reqs = omap34xx_mmc3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs), + .opt_clks = omap34xx_mmc3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), + .main_clk = "mmchs3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, + }, + }, + .slaves = omap3xxx_mmc3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), + .class = &omap34xx_mmc_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, &omap3xxx_l4_per_hwmod, &omap3xxx_l4_wkup_hwmod, + &omap3xxx_mmc1_hwmod, + &omap3xxx_mmc2_hwmod, + &omap3xxx_mmc3_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 87486f55978..098e65943a0 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -191,6 +191,8 @@ #define OMAP3430_AUTOIDLE_MASK (1 << 0) /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ +#define OMAP3430_EN_MMC3_MASK (1 << 30) +#define OMAP3430_EN_MMC3_SHIFT 30 #define OMAP3430_EN_MMC2_MASK (1 << 25) #define OMAP3430_EN_MMC2_SHIFT 25 #define OMAP3430_EN_MMC1_MASK (1 << 24) @@ -231,6 +233,8 @@ #define OMAP3430_EN_HSOTGUSB_SHIFT 4 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ +#define OMAP3430_ST_MMC3_SHIFT 30 +#define OMAP3430_ST_MMC3_MASK (1 << 30) #define OMAP3430_ST_MMC2_SHIFT 25 #define OMAP3430_ST_MMC2_MASK (1 << 25) #define OMAP3430_ST_MMC1_SHIFT 24 -- cgit v1.2.3-70-g09d2 From 17203bdaf2fd0cda6ac941a7b3fb8416c57303c7 Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Tue, 1 Mar 2011 13:12:56 -0800 Subject: OMAP4: hwmod data: enable HSMMC Enabling hsmmc hwmod for OMAP4 Signed-off-by: Anand Gadiyar Signed-off-by: Kishore Kadiyala Acked-by: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 2c5882792e0..12fcd0a0820 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -5077,11 +5077,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_mcspi4_hwmod, /* mmc class */ -/* &omap44xx_mmc1_hwmod, */ -/* &omap44xx_mmc2_hwmod, */ -/* &omap44xx_mmc3_hwmod, */ -/* &omap44xx_mmc4_hwmod, */ -/* &omap44xx_mmc5_hwmod, */ + &omap44xx_mmc1_hwmod, + &omap44xx_mmc2_hwmod, + &omap44xx_mmc3_hwmod, + &omap44xx_mmc4_hwmod, + &omap44xx_mmc5_hwmod, /* mpu class */ &omap44xx_mpu_hwmod, -- cgit v1.2.3-70-g09d2 From 6ab8946f672497a55625d2106250d2923125fdfb Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Tue, 1 Mar 2011 13:12:56 -0800 Subject: OMAP: hwmod data: Add dev_attr and use in the host driver Add a device attribute to hwmod data of omap2430, omap3, omap4. Currently the device attribute holds information regarding dual volt MMC card support by the controller which will be later passed to the host driver via platform data. Signed-off-by: Kevin Hilman Signed-off-by: Kishore Kadiyala Acked-by: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 6 ++++++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 6 ++++++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 ++++++++ arch/arm/plat-omap/include/plat/mmc.h | 9 +++++++++ 4 files changed, 29 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 0d239e3a980..ca25fa2af78 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include "omap_hwmod_common_data.h" @@ -2204,6 +2205,10 @@ static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { &omap2430_l4_core__mmc1, }; +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + static struct omap_hwmod omap2430_mmc1_hwmod = { .name = "mmc1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2223,6 +2228,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, }, }, + .dev_attr = &mmc1_dev_attr, .slaves = omap2430_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), .class = &omap2430_mmc_class, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 207ccfbac2e..5fdcc1e9d4a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -2944,6 +2945,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { &omap3xxx_l4_core__mmc1, }; +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + static struct omap_hwmod omap3xxx_mmc1_hwmod = { .name = "mmc1", .mpu_irqs = omap34xx_mmc1_mpu_irqs, @@ -2962,6 +2967,7 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = { .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, }, }, + .dev_attr = &mmc1_dev_attr, .slaves = omap3xxx_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), .class = &omap34xx_mmc_class, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 12fcd0a0820..9398c2db725 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -3383,6 +3384,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { }; /* mmc1 */ + static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { { .irq = 83 + OMAP44XX_IRQ_GIC_START }, }; @@ -3420,6 +3422,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { &omap44xx_l4_per__mmc1, }; +/* mmc1 dev_attr */ +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + static struct omap_hwmod omap44xx_mmc1_hwmod = { .name = "mmc1", .class = &omap44xx_mmc_hwmod_class, @@ -3433,6 +3440,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, }, }, + .dev_attr = &mmc1_dev_attr, .slaves = omap44xx_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), .masters = omap44xx_mmc1_masters, diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index e5de5d452b3..a7afab09571 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -43,6 +43,12 @@ #define OMAP_MMC_MAX_SLOTS 2 +#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1) + +struct omap_mmc_dev_attr { + u8 flags; +}; + struct omap_mmc_platform_data { /* back-link to device */ struct device *dev; @@ -71,6 +77,9 @@ struct omap_mmc_platform_data { u64 dma_mask; + /* Integrating attributes from the omap_hwmod layer */ + u8 controller_flags; + /* Register offset deviation */ u16 reg_offset; -- cgit v1.2.3-70-g09d2 From d8d0a61c658e252de3077f6076f13423642caf67 Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Mon, 28 Feb 2011 20:48:03 +0530 Subject: OMAP: hsmmc: Move mux configuration to hsmmc.c Moving the definition of mux setting API from devices.c to hsmmc.c and renaming it from "omap2_mmc_mux" to "omap_hsmmc_mux". Also calling "omap_hsmmc_mux" from omap2_hsmmc_init. Signed-off-by: Kishore Kadiyala Cc: Chris Ball --- arch/arm/mach-omap2/devices.c | 83 ------------------------------------------ arch/arm/mach-omap2/hsmmc.c | 84 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+), 83 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 100bb425e9c..2f4a598ba67 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -708,87 +708,6 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) -static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, - int controller_nr) -{ - if ((mmc_controller->slots[0].switch_pin > 0) && \ - (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, - OMAP_PIN_INPUT_PULLUP); - if ((mmc_controller->slots[0].gpio_wp > 0) && \ - (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) - omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, - OMAP_PIN_INPUT_PULLUP); - if (cpu_is_omap34xx()) { - if (controller_nr == 0) { - omap_mux_init_signal("sdmmc1_clk", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_cmd", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat0", - OMAP_PIN_INPUT_PULLUP); - if (mmc_controller->slots[0].caps & - (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { - omap_mux_init_signal("sdmmc1_dat1", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat2", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat3", - OMAP_PIN_INPUT_PULLUP); - } - if (mmc_controller->slots[0].caps & - MMC_CAP_8_BIT_DATA) { - omap_mux_init_signal("sdmmc1_dat4", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat5", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat6", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc1_dat7", - OMAP_PIN_INPUT_PULLUP); - } - } - if (controller_nr == 1) { - /* MMC2 */ - omap_mux_init_signal("sdmmc2_clk", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_cmd", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat0", - OMAP_PIN_INPUT_PULLUP); - - /* - * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed - * in the board-*.c files - */ - if (mmc_controller->slots[0].caps & - (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { - omap_mux_init_signal("sdmmc2_dat1", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat2", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat3", - OMAP_PIN_INPUT_PULLUP); - } - if (mmc_controller->slots[0].caps & - MMC_CAP_8_BIT_DATA) { - omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", - OMAP_PIN_INPUT_PULLUP); - omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", - OMAP_PIN_INPUT_PULLUP); - } - } - - /* - * For MMC3 the pins need to be muxed in the board-*.c files - */ - } -} - void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers) { @@ -802,8 +721,6 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, if (!mmc_data[i]) continue; - omap2_mmc_mux(mmc_data[i], i); - switch (i) { case 0: base = OMAP2_MMC1_BASE; diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 5496bc7d40a..1348ac3d60e 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -16,7 +16,9 @@ #include #include #include +#include +#include "mux.h" #include "hsmmc.h" #include "control.h" @@ -204,6 +206,87 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on, return 0; } +static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, + int controller_nr) +{ + if ((mmc_controller->slots[0].switch_pin > 0) && \ + (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, + OMAP_PIN_INPUT_PULLUP); + if ((mmc_controller->slots[0].gpio_wp > 0) && \ + (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, + OMAP_PIN_INPUT_PULLUP); + if (cpu_is_omap34xx()) { + if (controller_nr == 0) { + omap_mux_init_signal("sdmmc1_clk", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc1_cmd", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc1_dat0", + OMAP_PIN_INPUT_PULLUP); + if (mmc_controller->slots[0].caps & + (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { + omap_mux_init_signal("sdmmc1_dat1", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc1_dat2", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc1_dat3", + OMAP_PIN_INPUT_PULLUP); + } + if (mmc_controller->slots[0].caps & + MMC_CAP_8_BIT_DATA) { + omap_mux_init_signal("sdmmc1_dat4", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc1_dat5", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc1_dat6", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc1_dat7", + OMAP_PIN_INPUT_PULLUP); + } + } + if (controller_nr == 1) { + /* MMC2 */ + omap_mux_init_signal("sdmmc2_clk", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc2_cmd", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc2_dat0", + OMAP_PIN_INPUT_PULLUP); + + /* + * For 8 wire configurations, Lines DAT4, 5, 6 and 7 + * need to be muxed in the board-*.c files + */ + if (mmc_controller->slots[0].caps & + (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { + omap_mux_init_signal("sdmmc2_dat1", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc2_dat2", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc2_dat3", + OMAP_PIN_INPUT_PULLUP); + } + if (mmc_controller->slots[0].caps & + MMC_CAP_8_BIT_DATA) { + omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", + OMAP_PIN_INPUT_PULLUP); + omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", + OMAP_PIN_INPUT_PULLUP); + } + } + + /* + * For MMC3 the pins need to be muxed in the board-*.c files + */ + } +} + static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) @@ -361,6 +444,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) continue; } hsmmc_data[c->mmc - 1] = mmc; + omap_hsmmc_mux(hsmmc_data[c->mmc - 1], (c->mmc - 1)); } omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); -- cgit v1.2.3-70-g09d2 From 4621d5f8cb435b1ba74efe6e0a7125febb40186b Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Mon, 28 Feb 2011 20:48:04 +0530 Subject: OMAP: adapt hsmmc to hwmod framework OMAP2420 platform consists of mmc block as in omap1 and not the hsmmc block as present in omap2430, omap3, omap4 platforms. Removing all base address macro defines except keeping one for OMAP2420 and adapting only hsmmc device registration and driver to hwmod framework. Changes involves: 1) Remove controller reset in devices.c which is taken care of by hwmod framework. 2) Using omap-device layer to register device and utilizing data from hwmod data file for base address, dma channel number, Irq_number, device attribute. 3) Update the driver to use dev_attr to find whether controller supports dual volt cards Signed-off-by: Paul Walmsley Signed-off-by: Kishore Kadiyala Reviewed-by: Balaji T K Cc: Benoit Cousson CC: Kevin Hilman Cc: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 168 ----------------- arch/arm/mach-omap2/hsmmc.c | 346 +++++++++++++++++++--------------- arch/arm/plat-omap/include/plat/mmc.h | 20 +- drivers/mmc/host/omap_hsmmc.c | 4 +- 4 files changed, 200 insertions(+), 338 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2f4a598ba67..31632ac1ca7 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -544,112 +544,6 @@ static inline void omap_init_aes(void) { } /*-------------------------------------------------------------------------*/ -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - -#define MMCHS_SYSCONFIG 0x0010 -#define MMCHS_SYSCONFIG_SWRESET (1 << 1) -#define MMCHS_SYSSTATUS 0x0014 -#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) - -static struct platform_device dummy_pdev = { - .dev = { - .bus = &platform_bus_type, - }, -}; - -/** - * omap_hsmmc_reset() - Full reset of each HS-MMC controller - * - * Ensure that each MMC controller is fully reset. Controllers - * left in an unknown state (by bootloader) may prevent retention - * or OFF-mode. This is especially important in cases where the - * MMC driver is not enabled, _or_ built as a module. - * - * In order for reset to work, interface, functional and debounce - * clocks must be enabled. The debounce clock comes from func_32k_clk - * and is not under SW control, so we only enable i- and f-clocks. - **/ -static void __init omap_hsmmc_reset(void) -{ - u32 i, nr_controllers; - struct clk *iclk, *fclk; - - if (cpu_is_omap242x()) - return; - - nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : - (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); - - for (i = 0; i < nr_controllers; i++) { - u32 v, base = 0; - struct device *dev = &dummy_pdev.dev; - - switch (i) { - case 0: - base = OMAP2_MMC1_BASE; - break; - case 1: - base = OMAP2_MMC2_BASE; - break; - case 2: - base = OMAP3_MMC3_BASE; - break; - case 3: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC4_BASE; - break; - case 4: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC5_BASE; - break; - } - - if (cpu_is_omap44xx()) - base += OMAP4_MMC_REG_OFFSET; - - dummy_pdev.id = i; - dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); - iclk = clk_get(dev, "ick"); - if (IS_ERR(iclk)) - goto err1; - if (clk_enable(iclk)) - goto err2; - - fclk = clk_get(dev, "fck"); - if (IS_ERR(fclk)) - goto err3; - if (clk_enable(fclk)) - goto err4; - - omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); - v = omap_readl(base + MMCHS_SYSSTATUS); - while (!(omap_readl(base + MMCHS_SYSSTATUS) & - MMCHS_SYSSTATUS_RESETDONE)) - cpu_relax(); - - clk_disable(fclk); - clk_put(fclk); - clk_disable(iclk); - clk_put(iclk); - } - return; - -err4: - clk_put(fclk); -err3: - clk_disable(iclk); -err2: - clk_put(iclk); -err1: - printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " - "cannot reset.\n", __func__, i); -} -#else -static inline void omap_hsmmc_reset(void) {} -#endif - #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) static inline void omap242x_mmc_mux(struct omap_mmc_platform_data @@ -706,67 +600,6 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) #endif -#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) - -void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers) -{ - int i; - char *name; - - for (i = 0; i < nr_controllers; i++) { - unsigned long base, size; - unsigned int irq = 0; - - if (!mmc_data[i]) - continue; - - switch (i) { - case 0: - base = OMAP2_MMC1_BASE; - irq = INT_24XX_MMC_IRQ; - break; - case 1: - base = OMAP2_MMC2_BASE; - irq = INT_24XX_MMC2_IRQ; - break; - case 2: - if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) - return; - base = OMAP3_MMC3_BASE; - irq = INT_34XX_MMC3_IRQ; - break; - case 3: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC4_BASE; - irq = OMAP44XX_IRQ_MMC4; - break; - case 4: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC5_BASE; - irq = OMAP44XX_IRQ_MMC5; - break; - default: - continue; - } - - if (cpu_is_omap44xx()) { - if (i < 3) - irq += OMAP44XX_IRQ_GIC_START; - size = OMAP4_HSMMC_SIZE; - name = "mmci-omap-hs"; - } else { - size = OMAP3_HSMMC_SIZE; - name = "mmci-omap-hs"; - } - omap_mmc_add(name, i, base, size, irq, mmc_data[i]); - }; -} - -#endif - /*-------------------------------------------------------------------------*/ #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) @@ -836,7 +669,6 @@ static int __init omap2_init_devices(void) * please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - omap_hsmmc_reset(); omap_init_audio(); omap_init_camera(); omap_init_mbox(); diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 1348ac3d60e..d492bc4d342 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -30,10 +31,6 @@ static u16 control_mmc1; #define HSMMC_NAME_LEN 9 -static struct hsmmc_controller { - char name[HSMMC_NAME_LEN + 1]; -} hsmmc[OMAP34XX_NR_MMC]; - #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) static int hsmmc_get_context_loss(struct device *dev) @@ -287,13 +284,203 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, } } -static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; +static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, + struct omap_mmc_platform_data *mmc) +{ + char *hc_name; + + hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); + if (!hc_name) { + pr_err("Cannot allocate memory for controller slot name\n"); + kfree(hc_name); + return -ENOMEM; + } + + if (c->name) + strncpy(hc_name, c->name, HSMMC_NAME_LEN); + else + snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", + c->mmc, 1); + mmc->slots[0].name = hc_name; + mmc->nr_slots = 1; + mmc->slots[0].caps = c->caps; + mmc->slots[0].internal_clock = !c->ext_clock; + mmc->dma_mask = 0xffffffff; + if (cpu_is_omap44xx()) + mmc->reg_offset = OMAP4_MMC_REG_OFFSET; + else + mmc->reg_offset = 0; + + mmc->get_context_loss_count = hsmmc_get_context_loss; + + mmc->slots[0].switch_pin = c->gpio_cd; + mmc->slots[0].gpio_wp = c->gpio_wp; + + mmc->slots[0].remux = c->remux; + mmc->slots[0].init_card = c->init_card; + + if (c->cover_only) + mmc->slots[0].cover = 1; + + if (c->nonremovable) + mmc->slots[0].nonremovable = 1; + + if (c->power_saving) + mmc->slots[0].power_saving = 1; + + if (c->no_off) + mmc->slots[0].no_off = 1; + + if (c->vcc_aux_disable_is_sleep) + mmc->slots[0].vcc_aux_disable_is_sleep = 1; + + /* + * NOTE: MMC slots should have a Vcc regulator set up. + * This may be from a TWL4030-family chip, another + * controllable regulator, or a fixed supply. + * + * temporary HACK: ocr_mask instead of fixed supply + */ + mmc->slots[0].ocr_mask = c->ocr_mask; + + if (cpu_is_omap3517() || cpu_is_omap3505()) + mmc->slots[0].set_power = nop_mmc_set_power; + else + mmc->slots[0].features |= HSMMC_HAS_PBIAS; + + if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) + mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; + + switch (c->mmc) { + case 1: + if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { + /* on-chip level shifting via PBIAS0/PBIAS1 */ + if (cpu_is_omap44xx()) { + mmc->slots[0].before_set_reg = + omap4_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap4_hsmmc1_after_set_reg; + } else { + mmc->slots[0].before_set_reg = + omap_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap_hsmmc1_after_set_reg; + } + } + + /* OMAP3630 HSMMC1 supports only 4-bit */ + if (cpu_is_omap3630() && + (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + mmc->slots[0].caps = c->caps; + } + break; + case 2: + if (c->ext_clock) + c->transceiver = 1; + if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + } + /* FALLTHROUGH */ + case 3: + if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { + /* off-chip level shifting, or none */ + mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; + mmc->slots[0].after_set_reg = NULL; + } + break; + case 4: + case 5: + mmc->slots[0].before_set_reg = NULL; + mmc->slots[0].after_set_reg = NULL; + break; + default: + pr_err("MMC%d configuration not supported!\n", c->mmc); + kfree(hc_name); + return -ENODEV; + } + return 0; +} + +static struct omap_device_pm_latency omap_hsmmc_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, + /* + * XXX There should also be an entry here to power off/on the + * MMC regulators/PBIAS cells, etc. + */ +}; + +#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 + +void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) +{ + struct omap_hwmod *oh; + struct omap_device *od; + struct omap_device_pm_latency *ohl; + char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; + struct omap_mmc_platform_data *mmc_data; + struct omap_mmc_dev_attr *mmc_dev_attr; + char *name; + int l; + int ohl_cnt = 0; + + mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); + if (!mmc_data) { + pr_err("Cannot allocate memory for mmc device!\n"); + goto done; + } + + if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) { + pr_err("%s fails!\n", __func__); + goto done; + } + omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); + + name = "mmci-omap-hs"; + ohl = omap_hsmmc_latency; + ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency); + + l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, + "mmc%d", ctrl_nr); + WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN, + "String buffer overflow in MMC%d device setup\n", ctrl_nr); + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + kfree(mmc_data->slots[0].name); + goto done; + } + + if (oh->dev_attr != NULL) { + mmc_dev_attr = oh->dev_attr; + mmc_data->controller_flags = mmc_dev_attr->flags; + } + + od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, + sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); + if (IS_ERR(od)) { + WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name); + kfree(mmc_data->slots[0].name); + goto done; + } + /* + * return device handle to board setup code + * required to populate for regulator framework structure + */ + hsmmcinfo->dev = &od->pdev.dev; + +done: + kfree(mmc_data); +} void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { - struct omap2_hsmmc_info *c; - int nr_hsmmc = ARRAY_SIZE(hsmmc_data); - int i; u32 reg; if (!cpu_is_omap44xx()) { @@ -319,148 +506,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) omap4_ctrl_pad_writel(reg, control_mmc1); } - for (c = controllers; c->mmc; c++) { - struct hsmmc_controller *hc = hsmmc + c->mmc - 1; - struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; - - if (!c->mmc || c->mmc > nr_hsmmc) { - pr_debug("MMC%d: no such controller\n", c->mmc); - continue; - } - if (mmc) { - pr_debug("MMC%d: already configured\n", c->mmc); - continue; - } - - mmc = kzalloc(sizeof(struct omap_mmc_platform_data), - GFP_KERNEL); - if (!mmc) { - pr_err("Cannot allocate memory for mmc device!\n"); - goto done; - } - - if (c->name) - strncpy(hc->name, c->name, HSMMC_NAME_LEN); - else - snprintf(hc->name, ARRAY_SIZE(hc->name), - "mmc%islot%i", c->mmc, 1); - mmc->slots[0].name = hc->name; - mmc->nr_slots = 1; - mmc->slots[0].caps = c->caps; - mmc->slots[0].internal_clock = !c->ext_clock; - mmc->dma_mask = 0xffffffff; - if (cpu_is_omap44xx()) - mmc->reg_offset = OMAP4_MMC_REG_OFFSET; - else - mmc->reg_offset = 0; - - mmc->get_context_loss_count = hsmmc_get_context_loss; - - mmc->slots[0].switch_pin = c->gpio_cd; - mmc->slots[0].gpio_wp = c->gpio_wp; - - mmc->slots[0].remux = c->remux; - mmc->slots[0].init_card = c->init_card; - - if (c->cover_only) - mmc->slots[0].cover = 1; - - if (c->nonremovable) - mmc->slots[0].nonremovable = 1; - - if (c->power_saving) - mmc->slots[0].power_saving = 1; - - if (c->no_off) - mmc->slots[0].no_off = 1; - - if (c->vcc_aux_disable_is_sleep) - mmc->slots[0].vcc_aux_disable_is_sleep = 1; - - /* NOTE: MMC slots should have a Vcc regulator set up. - * This may be from a TWL4030-family chip, another - * controllable regulator, or a fixed supply. - * - * temporary HACK: ocr_mask instead of fixed supply - */ - mmc->slots[0].ocr_mask = c->ocr_mask; - - if (cpu_is_omap3517() || cpu_is_omap3505()) - mmc->slots[0].set_power = nop_mmc_set_power; - else - mmc->slots[0].features |= HSMMC_HAS_PBIAS; - - if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) - mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; - - switch (c->mmc) { - case 1: - if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { - /* on-chip level shifting via PBIAS0/PBIAS1 */ - if (cpu_is_omap44xx()) { - mmc->slots[0].before_set_reg = - omap4_hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = - omap4_hsmmc1_after_set_reg; - } else { - mmc->slots[0].before_set_reg = - omap_hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = - omap_hsmmc1_after_set_reg; - } - } - - /* Omap3630 HSMMC1 supports only 4-bit */ - if (cpu_is_omap3630() && - (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - mmc->slots[0].caps = c->caps; - } - break; - case 2: - if (c->ext_clock) - c->transceiver = 1; - if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - } - /* FALLTHROUGH */ - case 3: - if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { - /* off-chip level shifting, or none */ - mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; - mmc->slots[0].after_set_reg = NULL; - } - break; - case 4: - case 5: - mmc->slots[0].before_set_reg = NULL; - mmc->slots[0].after_set_reg = NULL; - break; - default: - pr_err("MMC%d configuration not supported!\n", c->mmc); - kfree(mmc); - continue; - } - hsmmc_data[c->mmc - 1] = mmc; - omap_hsmmc_mux(hsmmc_data[c->mmc - 1], (c->mmc - 1)); - } - - omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); - - /* pass the device nodes back to board setup code */ - for (c = controllers; c->mmc; c++) { - struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; + for (; controllers->mmc; controllers++) + omap_init_hsmmc(controllers, controllers->mmc); - if (!c->mmc || c->mmc > nr_hsmmc) - continue; - c->dev = mmc->dev; - } - -done: - for (i = 0; i < nr_hsmmc; i++) - kfree(hsmmc_data[i]); } #endif diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index a7afab09571..f38fef9f131 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -24,22 +24,10 @@ #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ #define OMAP24XX_NR_MMC 2 -#define OMAP34XX_NR_MMC 3 -#define OMAP44XX_NR_MMC 5 #define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE -#define OMAP3_HSMMC_SIZE 0x200 -#define OMAP4_HSMMC_SIZE 0x1000 #define OMAP2_MMC1_BASE 0x4809c000 -#define OMAP2_MMC2_BASE 0x480b4000 -#define OMAP3_MMC3_BASE 0x480ad000 -#define OMAP4_MMC4_BASE 0x480d1000 -#define OMAP4_MMC5_BASE 0x480d5000 + #define OMAP4_MMC_REG_OFFSET 0x100 -#define HSMMC5 (1 << 4) -#define HSMMC4 (1 << 3) -#define HSMMC3 (1 << 2) -#define HSMMC2 (1 << 1) -#define HSMMC1 (1 << 0) #define OMAP_MMC_MAX_SLOTS 2 @@ -169,8 +157,6 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot, void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers); void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); -void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers); int omap_mmc_add(const char *name, int id, unsigned long base, unsigned long size, unsigned int irq, struct omap_mmc_platform_data *data); @@ -182,10 +168,6 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) { } -static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers) -{ -} static inline int omap_mmc_add(const char *name, int id, unsigned long base, unsigned long size, unsigned int irq, struct omap_mmc_platform_data *data) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 8c42573f42e..d0bd2b43393 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -1571,7 +1571,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; } - if (host->id == OMAP_MMC1_DEVID) { + if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { /* Only MMC1 can interface at 3V without some flavor * of external transceiver; but they all handle 1.8V. */ @@ -1663,7 +1663,7 @@ static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) u32 hctl, capa, value; /* Only MMC1 supports 3.0V */ - if (host->id == OMAP_MMC1_DEVID) { + if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { hctl = SDVS30; capa = VS30 | VS18; } else { -- cgit v1.2.3-70-g09d2 From 0005ae73cfe44ee42d0be12a12cc82bf982f518e Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Mon, 28 Feb 2011 20:48:05 +0530 Subject: OMAP: hsmmc: Rename the device and driver Modifying the device & driver name from "mmci-omap-hs" to "omap_hsmmc". Signed-off-by: Kishore Kadiyala Acked-by: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 2 +- arch/arm/mach-omap2/board-3430sdp.c | 6 +++--- arch/arm/mach-omap2/board-4430sdp.c | 14 +++++++------- arch/arm/mach-omap2/board-devkit8000.c | 2 +- arch/arm/mach-omap2/board-igep0020.c | 6 +++--- arch/arm/mach-omap2/board-igep0030.c | 6 +++--- arch/arm/mach-omap2/board-omap3evm.c | 2 +- arch/arm/mach-omap2/board-omap3pandora.c | 6 +++--- arch/arm/mach-omap2/board-omap4panda.c | 4 ++-- arch/arm/mach-omap2/board-rm680.c | 2 +- arch/arm/mach-omap2/board-rx51-peripherals.c | 8 ++++---- arch/arm/mach-omap2/board-zoom-peripherals.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 12 ++++++------ arch/arm/mach-omap2/clock3xxx_data.c | 12 ++++++------ arch/arm/mach-omap2/clock44xx_data.c | 20 ++++++++++---------- arch/arm/mach-omap2/hsmmc.c | 2 +- drivers/mmc/host/omap_hsmmc.c | 2 +- 17 files changed, 54 insertions(+), 54 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index cc42d474c44..ab0880ba3c4 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -149,7 +149,7 @@ static void __init omap_2430sdp_init_early(void) } static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"), + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), }; /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 8950ecc9b94..40b0174a4ef 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -410,15 +410,15 @@ static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { }; static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"), + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), }; static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { - REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.0"), + REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), }; static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), }; /* diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 1a943be822c..f914099b225 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -348,11 +348,6 @@ static struct twl4030_usb_data omap4_usbphy_data = { }; static struct omap2_hsmmc_info mmc[] = { - { - .mmc = 1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - .gpio_wp = -EINVAL, - }, { .mmc = 2, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, @@ -361,19 +356,24 @@ static struct omap2_hsmmc_info mmc[] = { .nonremovable = true, .ocr_mask = MMC_VDD_29_30, }, + { + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .gpio_wp = -EINVAL, + }, {} /* Terminator */ }; static struct regulator_consumer_supply sdp4430_vaux_supply[] = { { .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", + .dev_name = "omap_hsmmc.1", }, }; static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { { .supply = "vmmc", - .dev_name = "mmci-omap-hs.0", + .dev_name = "omap_hsmmc.0", }, }; diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 54abdd06436..c9170f4d5d4 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -140,7 +140,7 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) } static struct regulator_consumer_supply devkit8000_vmmc1_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); /* ads7846 on SPI */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 54e6318f4a8..1877c28961e 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -250,7 +250,7 @@ static inline void __init igep2_init_smsc911x(void) { } #endif static struct regulator_consumer_supply igep2_vmmc1_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data igep2_vmmc1 = { @@ -268,7 +268,7 @@ static struct regulator_init_data igep2_vmmc1 = { }; static struct regulator_consumer_supply igep2_vio_supply = - REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); static struct regulator_init_data igep2_vio = { .constraints = { @@ -286,7 +286,7 @@ static struct regulator_init_data igep2_vio = { }; static struct regulator_consumer_supply igep2_vmmc2_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); static struct regulator_init_data igep2_vmmc2 = { .constraints = { diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index d75028e48f5..4273d0672ef 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -142,7 +142,7 @@ static void __init igep3_flash_init(void) {} #endif static struct regulator_consumer_supply igep3_vmmc1_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data igep3_vmmc1 = { @@ -160,7 +160,7 @@ static struct regulator_init_data igep3_vmmc1 = { }; static struct regulator_consumer_supply igep3_vio_supply = - REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); static struct regulator_init_data igep3_vio = { .constraints = { @@ -178,7 +178,7 @@ static struct regulator_init_data igep3_vio = { }; static struct regulator_consumer_supply igep3_vmmc2_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); static struct regulator_init_data igep3_vmmc2 = { .constraints = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 7341f966bf1..f2a3a883cca 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -604,7 +604,7 @@ static struct regulator_init_data omap3evm_vio = { #define OMAP3EVM_WLAN_IRQ_GPIO (149) static struct regulator_consumer_supply omap3evm_vmmc2_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); /* VMMC2 for driving the WL12xx module */ static struct regulator_init_data omap3evm_vmmc2 = { diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 17ef5479c7f..ed138694ccb 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -333,13 +333,13 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { }; static struct regulator_consumer_supply pandora_vmmc1_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); static struct regulator_consumer_supply pandora_vmmc2_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); static struct regulator_consumer_supply pandora_vmmc3_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"); static struct regulator_consumer_supply pandora_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 3dd241b9515..12bf09a7c5e 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -180,13 +180,13 @@ static struct omap2_hsmmc_info mmc[] = { static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { { .supply = "vmmc", - .dev_name = "mmci-omap-hs.0", + .dev_name = "omap_hsmmc.0", }, }; static struct regulator_consumer_supply omap4_panda_vmmc5_supply = { .supply = "vmmc", - .dev_name = "mmci-omap-hs.4", + .dev_name = "omap_hsmmc.4", }; static struct regulator_init_data panda_vmmc5 = { diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index bdebcb7328e..2af8b05e786 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -33,7 +33,7 @@ #include "sdram-nokia.h" static struct regulator_consumer_supply rm680_vemmc_consumers[] = { - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), }; /* Fixed regulator for internal eMMC */ diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index e75e240cad6..b74357ffe61 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -331,13 +331,13 @@ static struct omap2_hsmmc_info mmc[] __initdata = { }; static struct regulator_consumer_supply rx51_vmmc1_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); static struct regulator_consumer_supply rx51_vaux3_supply = - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); static struct regulator_consumer_supply rx51_vsim_supply = - REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); + REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { /* tlv320aic3x analog supplies */ @@ -348,7 +348,7 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { /* tpa6130a2 */ REGULATOR_SUPPLY("Vdd", "2-0060"), /* Keep vmmc as last item. It is not iterated for newer boards */ - REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), + REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), }; static struct regulator_consumer_supply rx51_vio_supplies[] = { diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index e0e040f34c6..7a098a4cdfe 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -118,7 +118,7 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = { static struct regulator_consumer_supply zoom_vmmc3_supply = { .supply = "vmmc", - .dev_name = "mmci-omap-hs.2", + .dev_name = "omap_hsmmc.2", }; /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index c047dcd007e..5c647ce05b0 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1984,15 +1984,15 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), - CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), - CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), - CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), - CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), + CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), + CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), - CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), - CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), }; /* diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index f14d986f0b5..052ac329282 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3290,10 +3290,10 @@ static struct omap_clk omap3xxx_clks[] = { CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), - CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), + CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX), CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), - CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), + CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX), CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), @@ -3323,13 +3323,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), - CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), - CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index de9ec8ddd2a..fdbc0426b6f 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3158,11 +3158,11 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), - CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), - CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), - CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), - CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), - CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), + CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), + CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), + CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), + CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), + CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), @@ -3245,11 +3245,11 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index d492bc4d342..137e1a5f3d8 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -442,7 +442,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) } omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); - name = "mmci-omap-hs"; + name = "omap_hsmmc"; ohl = omap_hsmmc_latency; ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency); diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index d0bd2b43393..191332b845c 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -118,7 +118,7 @@ #define MMC_TIMEOUT_MS 20 #define OMAP_MMC_MASTER_CLOCK 96000000 -#define DRIVER_NAME "mmci-omap-hs" +#define DRIVER_NAME "omap_hsmmc" /* Timeouts for entering power saving states on inactivity, msec */ #define OMAP_MMC_DISABLED_TIMEOUT 100 -- cgit v1.2.3-70-g09d2 From f463effebefb26f1dffb92d10725e938f4497bef Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 24 Feb 2011 12:56:42 +0000 Subject: ldp: Fix regulator mapping for ads7846 TS controller On the OMAP3430LDP board, the ads7846 touchscreen controller is powered by VAUX1 regulator (supplying 3.0v). Fix this mapping in the board file, and hence prevent the ads7846 driver init to fail with the below error.. ads7846 spi1.0: unable to get regulator: -19 Signed-off-by: Rajendra Nayak Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-ldp.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index a69e59455ee..e2ba77957a8 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -327,6 +327,26 @@ static struct regulator_init_data ldp_vmmc1 = { .consumer_supplies = &ldp_vmmc1_supply, }; +/* ads7846 on SPI */ +static struct regulator_consumer_supply ldp_vaux1_supplies[] = { + REGULATOR_SUPPLY("vcc", "spi1.0"), +}; + +/* VAUX1 */ +static struct regulator_init_data ldp_vaux1 = { + .constraints = { + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies), + .consumer_supplies = ldp_vaux1_supplies, +}; + static struct twl4030_platform_data ldp_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -335,6 +355,7 @@ static struct twl4030_platform_data ldp_twldata = { .madc = &ldp_madc_data, .usb = &ldp_usb_data, .vmmc1 = &ldp_vmmc1, + .vaux1 = &ldp_vaux1, .gpio = &ldp_gpio_data, .keypad = &ldp_kp_twl4030_data, }; -- cgit v1.2.3-70-g09d2 From ec179ea5361cdd34bf4e6d6bdfe02d6f4d6901b2 Mon Sep 17 00:00:00 2001 From: Guy Eilam Date: Fri, 25 Feb 2011 06:52:35 +0000 Subject: omap: panda: Add TI-ST driver support Added the KIM (Kernel initialization module for the Shared Transport driver) device entry in the board file Only the Blutooth enable GPIO is set for now Signed-off-by: Guy Eilam Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 3dd241b9515..4ff9877f316 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -50,6 +50,16 @@ #define GPIO_WIFI_PMENA 43 #define GPIO_WIFI_IRQ 53 +/* wl127x BT, FM, GPS connectivity chip */ +static int wl1271_gpios[] = {46, -1, -1}; +static struct platform_device wl1271_device = { + .name = "kim", + .id = -1, + .dev = { + .platform_data = &wl1271_gpios, + }, +}; + static struct gpio_led gpio_leds[] = { { .name = "pandaboard::status1", @@ -78,6 +88,7 @@ static struct platform_device leds_gpio = { static struct platform_device *panda_devices[] __initdata = { &leds_gpio, + &wl1271_device, }; static void __init omap4_panda_init_early(void) -- cgit v1.2.3-70-g09d2 From b7a834cc7d08276bf080077b3499d88f73e303ba Mon Sep 17 00:00:00 2001 From: Ilkka Koskinen Date: Fri, 25 Feb 2011 08:46:23 +0000 Subject: omap: rx51: Add support for vibra Add support for vibra Signed-off-by: Ilkka Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-rx51-peripherals.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index d0998f81269..7839e9493c7 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -742,6 +742,14 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = { .resource_config = twl4030_rconfig, }; +struct twl4030_codec_vibra_data rx51_vibra_data __initdata = { + .coexist = 0, +}; + +struct twl4030_codec_data rx51_codec_data __initdata = { + .audio_mclk = 26000000, + .vibra = &rx51_vibra_data, +}; static struct twl4030_platform_data rx51_twldata __initdata = { .irq_base = TWL4030_IRQ_BASE, @@ -753,6 +761,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .madc = &rx51_madc_data, .usb = &rx51_usb_data, .power = &rx51_t2scripts_data, + .codec = &rx51_codec_data, .vaux1 = &rx51_vaux1, .vaux2 = &rx51_vaux2, -- cgit v1.2.3-70-g09d2 From 6a58baf8f222f60cded29770ff9a0f6f6c100b64 Mon Sep 17 00:00:00 2001 From: Ilkka Koskinen Date: Wed, 2 Mar 2011 13:24:05 +0000 Subject: omap: Remove unnecessary twl4030_codec_audio settings from board files twl4030_codec_audio and twl4030_codec_vibra_data has unused field. In order to remove it, corresponding settings needs to be removed from board files. Signed-off-by: Ilkka Koskinen Acked-by: Peter Ujfalusi Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-3430sdp.c | 4 +--- arch/arm/mach-omap2/board-devkit8000.c | 4 +--- arch/arm/mach-omap2/board-igep0020.c | 4 +--- arch/arm/mach-omap2/board-omap3beagle.c | 4 +--- arch/arm/mach-omap2/board-omap3evm.c | 4 +--- arch/arm/mach-omap2/board-omap3pandora.c | 4 +--- arch/arm/mach-omap2/board-omap3stalker.c | 4 +--- arch/arm/mach-omap2/board-omap3touchbook.c | 4 +--- arch/arm/mach-omap2/board-overo.c | 4 +--- arch/arm/mach-omap2/board-zoom-peripherals.c | 4 +--- 10 files changed, 10 insertions(+), 30 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index b12b62064e7..95b1a9c19ba 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -552,9 +552,7 @@ static struct regulator_init_data sdp3430_vpll2 = { .consumer_supplies = sdp3430_vpll2_supplies, }; -static struct twl4030_codec_audio_data sdp3430_audio = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data sdp3430_audio; static struct twl4030_codec_data sdp3430_codec = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 54abdd06436..ddf5f04f22d 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -342,9 +342,7 @@ static struct twl4030_usb_data devkit8000_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static struct twl4030_codec_audio_data devkit8000_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data devkit8000_audio_data; static struct twl4030_codec_data devkit8000_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 54e6318f4a8..a0d6f2ff9a9 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -521,9 +521,7 @@ static void __init igep2_init_early(void) m65kxxxxam_sdrc_params); } -static struct twl4030_codec_audio_data igep2_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data igep2_audio_data; static struct twl4030_codec_data igep2_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index a1faea3b776..b6752ac5b97 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -427,9 +427,7 @@ static struct twl4030_usb_data beagle_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static struct twl4030_codec_audio_data beagle_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data beagle_audio_data; static struct twl4030_codec_data beagle_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 3d9b58a53c9..a8b1fefc63d 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -534,9 +534,7 @@ static struct twl4030_madc_platform_data omap3evm_madc_data = { .irq_line = 1, }; -static struct twl4030_codec_audio_data omap3evm_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data omap3evm_audio_data; static struct twl4030_codec_data omap3evm_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 17ef5479c7f..137f89dd5e4 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -516,9 +516,7 @@ static struct twl4030_usb_data omap3pandora_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static struct twl4030_codec_audio_data omap3pandora_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data omap3pandora_audio_data; static struct twl4030_codec_data omap3pandora_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index fd8b7649b14..15ede8b4981 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -431,9 +431,7 @@ static struct twl4030_madc_platform_data omap3stalker_madc_data = { .irq_line = 1, }; -static struct twl4030_codec_audio_data omap3stalker_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data omap3stalker_audio_data; static struct twl4030_codec_data omap3stalker_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 8e2a7ba4153..5554f5814aa 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -252,9 +252,7 @@ static struct twl4030_usb_data touchbook_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static struct twl4030_codec_audio_data touchbook_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data touchbook_audio_data; static struct twl4030_codec_data touchbook_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index d480ddb3952..60f8db31763 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -358,9 +358,7 @@ static struct regulator_init_data overo_vmmc1 = { .consumer_supplies = &overo_vmmc1_supply, }; -static struct twl4030_codec_audio_data overo_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data overo_audio_data; static struct twl4030_codec_data overo_codec_data = { .audio_mclk = 26000000, diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index e0e040f34c6..1ac9d353b7a 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -322,9 +322,7 @@ static struct twl4030_madc_platform_data zoom_madc_data = { .irq_line = 1, }; -static struct twl4030_codec_audio_data zoom_audio_data = { - .audio_mclk = 26000000, -}; +static struct twl4030_codec_audio_data zoom_audio_data; static struct twl4030_codec_data zoom_codec_data = { .audio_mclk = 26000000, -- cgit v1.2.3-70-g09d2 From cd97bb003276a66b2174e5dc589748e5c4bc357e Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Fri, 4 Mar 2011 16:01:43 +0100 Subject: Revert "OMAP4: hwmod data: Prevent timer1 to be reset and idle during init" The following commit: 38698be: OMAP2+: clockevent: set up GPTIMER clockevent hwmod right before timer init Fixed properly the issue with early init for the timer1 So reverts commit 3b03b58dab847883e6b9a431558c7d8e43fa94c6 that is now generated a warning at boot time. Signed-off-by: Benoit Cousson Reviewed-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7dbcdf751c0..7b72316781d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -4005,7 +4005,6 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { static struct omap_hwmod omap44xx_timer1_hwmod = { .name = "timer1", .class = &omap44xx_timer_1ms_hwmod_class, - .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, .mpu_irqs = omap44xx_timer1_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), .main_clk = "timer1_fck", -- cgit v1.2.3-70-g09d2 From 0fd0c21be71293d8a54d9075b18b5a25a1868057 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:49:53 -0700 Subject: OMAP2: clock: add DPLL autoidle support Add the necessary code and data to allow the clock framework to enable and disable the OMAP2 DPLL autoidle state. This is so the direct register access can be moved out of the mach-omap2/pm24xx.c code, and other code that needs to control this (e.g., CPUIdle) can do so via an API. As part of this patch, remove the pm24xx.c code that formerly wrote directly to the autoidle bits. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/clkt2xxx_dpll.c | 63 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 1 + arch/arm/mach-omap2/clock2420_data.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 2 +- arch/arm/mach-omap2/cm2xxx_3xxx.c | 27 ++++++++++++++++ arch/arm/mach-omap2/cm2xxx_3xxx.h | 3 ++ arch/arm/mach-omap2/pm24xx.c | 12 ++++--- 8 files changed, 105 insertions(+), 8 deletions(-) create mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 89274a9f035..ae44645551c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -115,7 +115,8 @@ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ clkt2xxx_sys.o \ clkt2xxx_dpllcore.o \ clkt2xxx_virt_prcm_set.o \ - clkt2xxx_apll.o clkt2xxx_osc.o + clkt2xxx_apll.o clkt2xxx_osc.o \ + clkt2xxx_dpll.o obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c new file mode 100644 index 00000000000..1502a7bc20b --- /dev/null +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -0,0 +1,63 @@ +/* + * OMAP2-specific DPLL control functions + * + * Copyright (C) 2011 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include + +#include "clock.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" + +/* Private functions */ + +/** + * _allow_idle - enable DPLL autoidle bits + * @clk: struct clk * of the DPLL to operate on + * + * Enable DPLL automatic idle control. The DPLL will enter low-power + * stop when its downstream clocks are gated. No return value. + * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 + * instead. Add some mechanism to optionally enter this mode. + */ +static void _allow_idle(struct clk *clk) +{ + if (!clk || !clk->dpll_data) + return; + + omap2xxx_cm_set_dpll_auto_low_power_stop(); +} + +/** + * _deny_idle - prevent DPLL from automatically idling + * @clk: struct clk * of the DPLL to operate on + * + * Disable DPLL automatic idle control. No return value. + */ +static void _deny_idle(struct clk *clk) +{ + if (!clk || !clk->dpll_data) + return; + + omap2xxx_cm_set_dpll_disable_autoidle(); +} + + +/* Public data */ + +const struct clkops clkops_omap2xxx_dpll_ops = { + .allow_idle = _allow_idle, + .deny_idle = _deny_idle, +}; + diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 0725a6ad8b4..9972d892a4a 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -148,6 +148,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) #define omap2_clk_exit_cpufreq_table 0 #endif +extern const struct clkops clkops_omap2xxx_dpll_ops; extern const struct clkops clkops_omap3_noncore_dpll_ops; extern const struct clkops clkops_omap3_core_dpll_ops; extern const struct clkops clkops_omap4_dpllmx_ops; diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index ee73e14ac3c..30fbcbd0ed8 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = { */ static struct clk dpll_ck = { .name = "dpll_ck", - .ops = &clkops_null, + .ops = &clkops_omap2xxx_dpll_ops, .parent = &sys_ck, /* Can be func_32k also */ .dpll_data = &dpll_dd, .clkdm_name = "wkup_clkdm", diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index a1298e55d91..1ff150a0f30 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = { */ static struct clk dpll_ck = { .name = "dpll_ck", - .ops = &clkops_null, + .ops = &clkops_omap2xxx_dpll_ops, .parent = &sys_ck, /* Can be func_32k also */ .dpll_data = &dpll_dd, .clkdm_name = "wkup_clkdm", diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 96954aa4867..6b0c7c85ef5 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -25,6 +25,10 @@ #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" +/* CM_AUTOIDLE_PLL.AUTO_* bit values */ +#define DPLL_AUTOIDLE_DISABLE 0x0 +#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 + static const u8 cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 }; @@ -125,6 +129,29 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); } +/* + * DPLL autoidle control + */ + +static void _omap2xxx_set_dpll_autoidle(u8 m) +{ + u32 v; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); + v &= ~OMAP24XX_AUTO_DPLL_MASK; + v |= m << OMAP24XX_AUTO_DPLL_SHIFT; + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); +} + +void omap2xxx_cm_set_dpll_disable_autoidle(void) +{ + _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP); +} + +void omap2xxx_cm_set_dpll_auto_low_power_stop(void) +{ + _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); +} /* * diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 5e9ea5bd60b..5f4df1ceafa 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -122,6 +122,9 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask); extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); +extern void omap2xxx_cm_set_dpll_disable_autoidle(void); +extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); + #endif /* CM register bits shared between 24XX and 3430 */ diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index e983c8301f5..297bb21061b 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -378,6 +378,7 @@ static void __init prcm_setup_regs(void) { int i, num_mem_banks; struct powerdomain *pwrdm; + u32 v; /* Enable autoidle */ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, @@ -468,11 +469,12 @@ static void __init prcm_setup_regs(void) omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, CM_AUTOIDLE); - /* Put DPLL and both APLLs into autoidle mode */ - omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | - (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT), - PLL_MOD, CM_AUTOIDLE); + /* Put both APLLs into autoidle mode */ + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); + v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT); + v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) | + (0x03 << OMAP24XX_AUTO_54M_SHIFT); + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | OMAP24XX_AUTO_WDT1_MASK | -- cgit v1.2.3-70-g09d2 From 92618ff8b025419960e2e845983f0f49b0cb57a9 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:27 -0700 Subject: OMAP2xxx: clock: add clockfw autoidle support for APLLs OMAP2xxx devices have two on-chip APLLs. These APLLs can automatically enter idle when not in use. Connect the APLL autoidle code to the clock code, so that the clock framework can handle this process. As part of this patch, remove the code in mach-omap2/pm24xx.c that previously handled APLL autoidle control. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clkt2xxx_apll.c | 24 ++++++++++++++++++++ arch/arm/mach-omap2/cm2xxx_3xxx.c | 44 ++++++++++++++++++++++++++++++++++++- arch/arm/mach-omap2/cm2xxx_3xxx.h | 5 +++++ arch/arm/mach-omap2/pm24xx.c | 8 ------- 4 files changed, 72 insertions(+), 9 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index f51cffd1fc5..b19a1f7234a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -78,6 +78,26 @@ static int omap2_clk_apll54_enable(struct clk *clk) return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK); } +static void _apll96_allow_idle(struct clk *clk) +{ + omap2xxx_cm_set_apll96_auto_low_power_stop(); +} + +static void _apll96_deny_idle(struct clk *clk) +{ + omap2xxx_cm_set_apll96_disable_autoidle(); +} + +static void _apll54_allow_idle(struct clk *clk) +{ + omap2xxx_cm_set_apll54_auto_low_power_stop(); +} + +static void _apll54_deny_idle(struct clk *clk) +{ + omap2xxx_cm_set_apll54_disable_autoidle(); +} + /* Stop APLL */ static void omap2_clk_apll_disable(struct clk *clk) { @@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk) const struct clkops clkops_apll96 = { .enable = omap2_clk_apll96_enable, .disable = omap2_clk_apll_disable, + .allow_idle = _apll96_allow_idle, + .deny_idle = _apll96_deny_idle, }; const struct clkops clkops_apll54 = { .enable = omap2_clk_apll54_enable, .disable = omap2_clk_apll_disable, + .allow_idle = _apll54_allow_idle, + .deny_idle = _apll54_deny_idle, }; /* Public functions */ diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 6b0c7c85ef5..9d0dec806e9 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -25,10 +25,14 @@ #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" -/* CM_AUTOIDLE_PLL.AUTO_* bit values */ +/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */ #define DPLL_AUTOIDLE_DISABLE 0x0 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 +/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */ +#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0 +#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 + static const u8 cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 }; @@ -153,6 +157,44 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void) _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); } +/* + * APLL autoidle control + */ + +static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) +{ + u32 v; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); + v &= ~mask; + v |= m << __ffs(mask); + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); +} + +void omap2xxx_cm_set_apll54_disable_autoidle(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, + OMAP24XX_AUTO_54M_MASK); +} + +void omap2xxx_cm_set_apll54_auto_low_power_stop(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, + OMAP24XX_AUTO_54M_MASK); +} + +void omap2xxx_cm_set_apll96_disable_autoidle(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, + OMAP24XX_AUTO_96M_MASK); +} + +void omap2xxx_cm_set_apll96_auto_low_power_stop(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, + OMAP24XX_AUTO_96M_MASK); +} + /* * */ diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 5f4df1ceafa..088bbad73db 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -125,6 +125,11 @@ extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); extern void omap2xxx_cm_set_dpll_disable_autoidle(void); extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); +extern void omap2xxx_cm_set_apll54_disable_autoidle(void); +extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void); +extern void omap2xxx_cm_set_apll96_disable_autoidle(void); +extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); + #endif /* CM register bits shared between 24XX and 3430 */ diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 297bb21061b..abe08f49b2e 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -378,7 +378,6 @@ static void __init prcm_setup_regs(void) { int i, num_mem_banks; struct powerdomain *pwrdm; - u32 v; /* Enable autoidle */ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, @@ -469,13 +468,6 @@ static void __init prcm_setup_regs(void) omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, CM_AUTOIDLE); - /* Put both APLLs into autoidle mode */ - v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); - v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT); - v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT); - omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); - omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | OMAP24XX_AUTO_WDT1_MASK | OMAP24XX_AUTO_MPU_WDT_MASK | -- cgit v1.2.3-70-g09d2 From cc1d230cfbc1622be4bf16568f468054be8c5d2e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:27 -0700 Subject: OMAP2+: clock: comment that osc_ck/osc_sys_ck should use clockfw autoidle control Place some comments in the OMAP oscillator clock control code to note that its autoidle mode should eventually be controlled via the new OMAP clockfw autoidle control interface. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clkt2xxx_osc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index df7b8050648..c3460928b5e 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -30,6 +30,13 @@ #include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" +/* + * XXX This does not actually enable the osc_ck, since the osc_ck must + * be running for this function to be called. Instead, this function + * is used to disable an autoidle mode on the osc_ck. The existing + * clk_enable/clk_disable()-based usecounting for osc_ck should be + * replaced with autoidle-based usecounting. + */ static int omap2_enable_osc_ck(struct clk *clk) { u32 pcc; @@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk) return 0; } +/* + * XXX This does not actually disable the osc_ck, since doing so would + * immediately halt the system. Instead, this function is used to + * enable an autoidle mode on the osc_ck. The existing + * clk_enable/clk_disable()-based usecounting for osc_ck should be + * replaced with autoidle-based usecounting. + */ static void omap2_disable_osc_ck(struct clk *clk) { u32 pcc; -- cgit v1.2.3-70-g09d2 From 530e544fdadb934470c5c2b0e8d60c3d5386c161 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:28 -0700 Subject: OMAP2+: clock: add interface clock type code with autoidle support Add interface clock type code with autoidle enable/disable support. The clkops structures created in this file will be used for all OMAP2/3 interface clocks with autoidle support. They will enable the clock framework to control interface clock autoidle directly. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/Makefile | 6 ++-- arch/arm/mach-omap2/clkt_iclk.c | 73 +++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 9 ++++- 3 files changed, 85 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-omap2/clkt_iclk.c (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ae44645551c..c5b1be9b732 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -110,19 +110,21 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ clockdomain44xx.o \ clockdomains44xx_data.o + # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ clkt2xxx_sys.o \ clkt2xxx_dpllcore.o \ clkt2xxx_virt_prcm_set.o \ clkt2xxx_apll.o clkt2xxx_osc.o \ - clkt2xxx_dpll.o + clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ clock34xx.o clkt34xx_dpll3m2.o \ clock3517.o clock36xx.o \ - dpll3xxx.o clock3xxx_data.o + dpll3xxx.o clock3xxx_data.o \ + clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ dpll3xxx.o dpll44xx.o diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c new file mode 100644 index 00000000000..dd8a6d3dc01 --- /dev/null +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -0,0 +1,73 @@ +/* + * OMAP2/3 interface clock control + * + * Copyright (C) 2011 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#undef DEBUG + +#include +#include +#include + +#include +#include + +#include "clock.h" +#include "clock2xxx.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" + +/* Private functions */ + +/* XXX */ +void omap2_clkt_iclk_allow_idle(struct clk *clk) +{ + u32 v, r; + + r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + + v = __raw_readl((__force void __iomem *)r); + v |= (1 << clk->enable_bit); + __raw_writel(v, (__force void __iomem *)r); +} + +/* XXX */ +void omap2_clkt_iclk_deny_idle(struct clk *clk) +{ + u32 v, r; + + r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + + v = __raw_readl((__force void __iomem *)r); + v &= ~(1 << clk->enable_bit); + __raw_writel(v, (__force void __iomem *)r); +} + +/* Public data */ + +const struct clkops clkops_omap2_iclk_dflt_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_companion = omap2_clk_dflt_find_companion, + .find_idlest = omap2_clk_dflt_find_idlest, + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + +const struct clkops clkops_omap2_iclk_dflt = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + +const struct clkops clkops_omap2_iclk_idle_only = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 9972d892a4a..5008f14448e 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -2,7 +2,7 @@ * linux/arch/arm/mach-omap2/clock.h * * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2009 Nokia Corporation + * Copyright (C) 2004-2011 Nokia Corporation * * Contacts: * Richard Woodruff @@ -86,6 +86,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); +/* clkt_iclk.c public functions */ +extern void omap2_clkt_iclk_allow_idle(struct clk *clk); +extern void omap2_clkt_iclk_deny_idle(struct clk *clk); + u32 omap2_get_dpll_rate(struct clk *clk); void omap2_init_dpll_parent(struct clk *clk); @@ -148,6 +152,9 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) #define omap2_clk_exit_cpufreq_table 0 #endif +extern const struct clkops clkops_omap2_iclk_dflt_wait; +extern const struct clkops clkops_omap2_iclk_dflt; +extern const struct clkops clkops_omap2_iclk_idle_only; extern const struct clkops clkops_omap2xxx_dpll_ops; extern const struct clkops clkops_omap3_noncore_dpll_ops; extern const struct clkops clkops_omap3_core_dpll_ops; -- cgit v1.2.3-70-g09d2 From a56d9ea865e42a6bf6393fc3d3a143553dbf68c5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:29 -0700 Subject: OMAP2420: clock: add sdrc_ick Add sdrc_ick to the OMAP2420 clock data so the clock code can control the CM_AUTOIDLE bit associated with this clock. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clock2420_data.c | 16 ++++++++++++++++ arch/arm/mach-omap2/cm-regbits-24xx.h | 1 + 2 files changed, 17 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 30fbcbd0ed8..63ed4816b92 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1608,6 +1608,21 @@ static struct clk sdma_ick = { .recalc = &followparent_recalc, }; +/* + * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE + * accesses derived from this data. + */ +static struct clk sdrc_ick = { + .name = "sdrc_ick", + .ops = &clkops_omap2_iclk_idle_only, + .parent = &core_l3_ck, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, + .recalc = &followparent_recalc, +}; + static struct clk vlynq_ick = { .name = "vlynq_ick", .ops = &clkops_omap2_dflt_wait, @@ -1869,6 +1884,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), CLK(NULL, "des_ick", &des_ick, CK_242X), diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index d70660e82fe..409c813eb2e 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -210,6 +210,7 @@ #define OMAP24XX_AUTO_USB_MASK (1 << 0) /* CM_AUTOIDLE3_CORE */ +#define OMAP24XX_AUTO_SDRC_SHIFT 2 #define OMAP24XX_AUTO_SDRC_MASK (1 << 2) #define OMAP24XX_AUTO_GPMC_MASK (1 << 1) #define OMAP24XX_AUTO_SDMA_MASK (1 << 0) -- cgit v1.2.3-70-g09d2 From 6ae690da1b6315f34ab7312bd2a02d49a606ccf7 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:29 -0700 Subject: OMAP2420: clock: use autoidle clkops for all autoidle-controllable interface clocks Mark each interface clock with a corresponding CM_AUTOIDLE bit with a clkops that has the allow_idle/deny_idle function pointers populated. This allows the OMAP clock framework to enable and disable autoidle for these clocks. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clock2420_data.c | 109 +++++++++++++++++++--------------- arch/arm/mach-omap2/cm-regbits-24xx.h | 2 + 2 files changed, 63 insertions(+), 48 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 63ed4816b92..68c03691e56 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -2,7 +2,7 @@ * linux/arch/arm/mach-omap2/clock2420_data.c * * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation + * Copyright (C) 2004-2011 Nokia Corporation * * Contacts: * Richard Woodruff @@ -481,7 +481,7 @@ static struct clk dsp_irate_ick = { /* 2420 only */ static struct clk dsp_ick = { .name = "dsp_ick", /* apparently ipi and isp */ - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &dsp_irate_ick, .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ @@ -579,7 +579,7 @@ static const struct clksel usb_l4_ick_clksel[] = { /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ static struct clk usb_l4_ick = { /* FS-USB interface clock */ .name = "usb_l4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l3_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -661,7 +661,7 @@ static struct clk ssi_ssr_sst_fck = { */ static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -716,6 +716,7 @@ static struct clk gfx_2d_fck = { .recalc = &omap2_clksel_recalc, }; +/* This interface clock does not have a CM_AUTOIDLE bit */ static struct clk gfx_ick = { .name = "gfx_ick", /* From l3 */ .ops = &clkops_omap2_dflt_wait, @@ -763,7 +764,7 @@ static const struct clksel dss1_fck_clksel[] = { static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &l4_ck, /* really both l3 and l4 */ .clkdm_name = "dss_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -845,7 +846,7 @@ static const struct clksel omap24xx_gpt_clksel[] = { static struct clk gpt1_ick = { .name = "gpt1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -871,7 +872,7 @@ static struct clk gpt1_fck = { static struct clk gpt2_ick = { .name = "gpt2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -895,7 +896,7 @@ static struct clk gpt2_fck = { static struct clk gpt3_ick = { .name = "gpt3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -919,7 +920,7 @@ static struct clk gpt3_fck = { static struct clk gpt4_ick = { .name = "gpt4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -943,7 +944,7 @@ static struct clk gpt4_fck = { static struct clk gpt5_ick = { .name = "gpt5_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -967,7 +968,7 @@ static struct clk gpt5_fck = { static struct clk gpt6_ick = { .name = "gpt6_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -991,7 +992,7 @@ static struct clk gpt6_fck = { static struct clk gpt7_ick = { .name = "gpt7_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, @@ -1014,7 +1015,7 @@ static struct clk gpt7_fck = { static struct clk gpt8_ick = { .name = "gpt8_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1038,7 +1039,7 @@ static struct clk gpt8_fck = { static struct clk gpt9_ick = { .name = "gpt9_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1062,7 +1063,7 @@ static struct clk gpt9_fck = { static struct clk gpt10_ick = { .name = "gpt10_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1086,7 +1087,7 @@ static struct clk gpt10_fck = { static struct clk gpt11_ick = { .name = "gpt11_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1110,7 +1111,7 @@ static struct clk gpt11_fck = { static struct clk gpt12_ick = { .name = "gpt12_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1134,7 +1135,7 @@ static struct clk gpt12_fck = { static struct clk mcbsp1_ick = { .name = "mcbsp1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1174,7 +1175,7 @@ static struct clk mcbsp1_fck = { static struct clk mcbsp2_ick = { .name = "mcbsp2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1198,7 +1199,7 @@ static struct clk mcbsp2_fck = { static struct clk mcspi1_ick = { .name = "mcspi1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1218,7 +1219,7 @@ static struct clk mcspi1_fck = { static struct clk mcspi2_ick = { .name = "mcspi2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1238,7 +1239,7 @@ static struct clk mcspi2_fck = { static struct clk uart1_ick = { .name = "uart1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1258,7 +1259,7 @@ static struct clk uart1_fck = { static struct clk uart2_ick = { .name = "uart2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1278,7 +1279,7 @@ static struct clk uart2_fck = { static struct clk uart3_ick = { .name = "uart3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1298,7 +1299,7 @@ static struct clk uart3_fck = { static struct clk gpios_ick = { .name = "gpios_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -1318,7 +1319,7 @@ static struct clk gpios_fck = { static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -1338,7 +1339,7 @@ static struct clk mpu_wdt_fck = { static struct clk sync_32k_ick = { .name = "sync_32k_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", @@ -1349,7 +1350,7 @@ static struct clk sync_32k_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -1359,7 +1360,7 @@ static struct clk wdt1_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", @@ -1370,7 +1371,7 @@ static struct clk omapctrl_ick = { static struct clk cam_ick = { .name = "cam_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1395,7 +1396,7 @@ static struct clk cam_fck = { static struct clk mailboxes_ick = { .name = "mailboxes_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1405,7 +1406,7 @@ static struct clk mailboxes_ick = { static struct clk wdt4_ick = { .name = "wdt4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1425,7 +1426,7 @@ static struct clk wdt4_fck = { static struct clk wdt3_ick = { .name = "wdt3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1445,7 +1446,7 @@ static struct clk wdt3_fck = { static struct clk mspro_ick = { .name = "mspro_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1465,7 +1466,7 @@ static struct clk mspro_fck = { static struct clk mmc_ick = { .name = "mmc_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1485,7 +1486,7 @@ static struct clk mmc_fck = { static struct clk fac_ick = { .name = "fac_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1505,7 +1506,7 @@ static struct clk fac_fck = { static struct clk eac_ick = { .name = "eac_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1525,7 +1526,7 @@ static struct clk eac_fck = { static struct clk hdq_ick = { .name = "hdq_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1545,7 +1546,7 @@ static struct clk hdq_fck = { static struct clk i2c2_ick = { .name = "i2c2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1565,7 +1566,7 @@ static struct clk i2c2_fck = { static struct clk i2c1_ick = { .name = "i2c1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1583,12 +1584,18 @@ static struct clk i2c1_fck = { .recalc = &followparent_recalc, }; +/* + * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE + * accesses derived from this data. + */ static struct clk gpmc_fck = { .name = "gpmc_fck", - .ops = &clkops_null, /* RMK: missing? */ + .ops = &clkops_omap2_iclk_idle_only, .parent = &core_l3_ck, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, .recalc = &followparent_recalc, }; @@ -1600,11 +1607,17 @@ static struct clk sdma_fck = { .recalc = &followparent_recalc, }; +/* + * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE + * accesses derived from this data. + */ static struct clk sdma_ick = { .name = "sdma_ick", - .ops = &clkops_null, /* RMK: missing? */ + .ops = &clkops_omap2_iclk_idle_only, .parent = &l4_ck, .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, .recalc = &followparent_recalc, }; @@ -1625,7 +1638,7 @@ static struct clk sdrc_ick = { static struct clk vlynq_ick = { .name = "vlynq_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l3_ck, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1674,7 +1687,7 @@ static struct clk vlynq_fck = { static struct clk des_ick = { .name = "des_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1684,7 +1697,7 @@ static struct clk des_ick = { static struct clk sha_ick = { .name = "sha_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1694,7 +1707,7 @@ static struct clk sha_ick = { static struct clk rng_ick = { .name = "rng_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1704,7 +1717,7 @@ static struct clk rng_ick = { static struct clk aes_ick = { .name = "aes_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1714,7 +1727,7 @@ static struct clk aes_ick = { static struct clk pka_ick = { .name = "pka_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 409c813eb2e..68629043756 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -212,7 +212,9 @@ /* CM_AUTOIDLE3_CORE */ #define OMAP24XX_AUTO_SDRC_SHIFT 2 #define OMAP24XX_AUTO_SDRC_MASK (1 << 2) +#define OMAP24XX_AUTO_GPMC_SHIFT 1 #define OMAP24XX_AUTO_GPMC_MASK (1 << 1) +#define OMAP24XX_AUTO_SDMA_SHIFT 0 #define OMAP24XX_AUTO_SDMA_MASK (1 << 0) /* CM_AUTOIDLE4_CORE */ -- cgit v1.2.3-70-g09d2 From e892b2528b8dc9eef8ca3f9af7b5b650b4e90bea Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:29 -0700 Subject: OMAP2430/3xxx: clock: add modem clock autoidle support OMAP2430 and OMAP3xxx have modem autoidle bits that are actually attached to clocks with CM_FCLKEN bits; add the code and data to handle these. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clkt_iclk.c | 9 +++++++++ arch/arm/mach-omap2/clock.h | 1 + 2 files changed, 10 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index dd8a6d3dc01..3d43fba2542 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -71,3 +71,12 @@ const struct clkops clkops_omap2_iclk_idle_only = { .deny_idle = omap2_clkt_iclk_deny_idle, }; +const struct clkops clkops_omap2_mdmclk_dflt_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_companion = omap2_clk_dflt_find_companion, + .find_idlest = omap2_clk_dflt_find_idlest, + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 5008f14448e..70f8b073e69 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -155,6 +155,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table) extern const struct clkops clkops_omap2_iclk_dflt_wait; extern const struct clkops clkops_omap2_iclk_dflt; extern const struct clkops clkops_omap2_iclk_idle_only; +extern const struct clkops clkops_omap2_mdmclk_dflt_wait; extern const struct clkops clkops_omap2xxx_dpll_ops; extern const struct clkops clkops_omap3_noncore_dpll_ops; extern const struct clkops clkops_omap3_core_dpll_ops; -- cgit v1.2.3-70-g09d2 From a1d5562315a1e911c8448b7fac33c966f9cb6294 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:30 -0700 Subject: OMAP2430: clock: use autoidle clkops for all autoidle-controllable interface clocks Mark each interface clock with a corresponding CM_AUTOIDLE bit with a clkops that has the allow_idle/deny_idle function pointers populated. This allows the OMAP clock framework to enable and disable autoidle for these clocks. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clock2430_data.c | 125 +++++++++++++++++++---------------- 1 file changed, 69 insertions(+), 56 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 1ff150a0f30..34daed9cd56 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -2,7 +2,7 @@ * linux/arch/arm/mach-omap2/clock2430_data.c * * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2010 Nokia Corporation + * Copyright (C) 2004-2011 Nokia Corporation * * Contacts: * Richard Woodruff @@ -525,7 +525,7 @@ static const struct clksel usb_l4_ick_clksel[] = { /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ static struct clk usb_l4_ick = { /* FS-USB interface clock */ .name = "usb_l4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l3_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -606,7 +606,7 @@ static struct clk ssi_ssr_sst_fck = { */ static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -661,6 +661,7 @@ static struct clk gfx_2d_fck = { .recalc = &omap2_clksel_recalc, }; +/* This interface clock does not have a CM_AUTOIDLE bit */ static struct clk gfx_ick = { .name = "gfx_ick", /* From l3 */ .ops = &clkops_omap2_dflt_wait, @@ -693,7 +694,7 @@ static const struct clksel mdm_ick_clksel[] = { static struct clk mdm_ick = { /* used both as a ick and fck */ .name = "mdm_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_ck, .clkdm_name = "mdm_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), @@ -706,7 +707,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ static struct clk mdm_osc_ck = { .name = "mdm_osc_ck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_mdmclk_dflt_wait, .parent = &osc_ck, .clkdm_name = "mdm_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), @@ -751,7 +752,7 @@ static const struct clksel dss1_fck_clksel[] = { static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &l4_ck, /* really both l3 and l4 */ .clkdm_name = "dss_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -833,7 +834,7 @@ static const struct clksel omap24xx_gpt_clksel[] = { static struct clk gpt1_ick = { .name = "gpt1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -859,7 +860,7 @@ static struct clk gpt1_fck = { static struct clk gpt2_ick = { .name = "gpt2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -883,7 +884,7 @@ static struct clk gpt2_fck = { static struct clk gpt3_ick = { .name = "gpt3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -907,7 +908,7 @@ static struct clk gpt3_fck = { static struct clk gpt4_ick = { .name = "gpt4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -931,7 +932,7 @@ static struct clk gpt4_fck = { static struct clk gpt5_ick = { .name = "gpt5_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -955,7 +956,7 @@ static struct clk gpt5_fck = { static struct clk gpt6_ick = { .name = "gpt6_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -979,7 +980,7 @@ static struct clk gpt6_fck = { static struct clk gpt7_ick = { .name = "gpt7_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, @@ -1002,7 +1003,7 @@ static struct clk gpt7_fck = { static struct clk gpt8_ick = { .name = "gpt8_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1026,7 +1027,7 @@ static struct clk gpt8_fck = { static struct clk gpt9_ick = { .name = "gpt9_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1050,7 +1051,7 @@ static struct clk gpt9_fck = { static struct clk gpt10_ick = { .name = "gpt10_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1074,7 +1075,7 @@ static struct clk gpt10_fck = { static struct clk gpt11_ick = { .name = "gpt11_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1098,7 +1099,7 @@ static struct clk gpt11_fck = { static struct clk gpt12_ick = { .name = "gpt12_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1122,7 +1123,7 @@ static struct clk gpt12_fck = { static struct clk mcbsp1_ick = { .name = "mcbsp1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1162,7 +1163,7 @@ static struct clk mcbsp1_fck = { static struct clk mcbsp2_ick = { .name = "mcbsp2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1186,7 +1187,7 @@ static struct clk mcbsp2_fck = { static struct clk mcbsp3_ick = { .name = "mcbsp3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1210,7 +1211,7 @@ static struct clk mcbsp3_fck = { static struct clk mcbsp4_ick = { .name = "mcbsp4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1234,7 +1235,7 @@ static struct clk mcbsp4_fck = { static struct clk mcbsp5_ick = { .name = "mcbsp5_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1258,7 +1259,7 @@ static struct clk mcbsp5_fck = { static struct clk mcspi1_ick = { .name = "mcspi1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1278,7 +1279,7 @@ static struct clk mcspi1_fck = { static struct clk mcspi2_ick = { .name = "mcspi2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1298,7 +1299,7 @@ static struct clk mcspi2_fck = { static struct clk mcspi3_ick = { .name = "mcspi3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1318,7 +1319,7 @@ static struct clk mcspi3_fck = { static struct clk uart1_ick = { .name = "uart1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1338,7 +1339,7 @@ static struct clk uart1_fck = { static struct clk uart2_ick = { .name = "uart2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1358,7 +1359,7 @@ static struct clk uart2_fck = { static struct clk uart3_ick = { .name = "uart3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1378,7 +1379,7 @@ static struct clk uart3_fck = { static struct clk gpios_ick = { .name = "gpios_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -1398,7 +1399,7 @@ static struct clk gpios_fck = { static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -1418,7 +1419,7 @@ static struct clk mpu_wdt_fck = { static struct clk sync_32k_ick = { .name = "sync_32k_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", @@ -1429,7 +1430,7 @@ static struct clk sync_32k_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -1439,7 +1440,7 @@ static struct clk wdt1_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", @@ -1450,7 +1451,7 @@ static struct clk omapctrl_ick = { static struct clk icr_ick = { .name = "icr_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), @@ -1460,7 +1461,7 @@ static struct clk icr_ick = { static struct clk cam_ick = { .name = "cam_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1485,7 +1486,7 @@ static struct clk cam_fck = { static struct clk mailboxes_ick = { .name = "mailboxes_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1495,7 +1496,7 @@ static struct clk mailboxes_ick = { static struct clk wdt4_ick = { .name = "wdt4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1515,7 +1516,7 @@ static struct clk wdt4_fck = { static struct clk mspro_ick = { .name = "mspro_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1535,7 +1536,7 @@ static struct clk mspro_fck = { static struct clk fac_ick = { .name = "fac_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1555,7 +1556,7 @@ static struct clk fac_fck = { static struct clk hdq_ick = { .name = "hdq_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1579,7 +1580,7 @@ static struct clk hdq_fck = { */ static struct clk i2c2_ick = { .name = "i2c2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1603,7 +1604,7 @@ static struct clk i2chs2_fck = { */ static struct clk i2c1_ick = { .name = "i2c1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1621,12 +1622,18 @@ static struct clk i2chs1_fck = { .recalc = &followparent_recalc, }; +/* + * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE + * accesses derived from this data. + */ static struct clk gpmc_fck = { .name = "gpmc_fck", - .ops = &clkops_null, /* RMK: missing? */ + .ops = &clkops_omap2_iclk_idle_only, .parent = &core_l3_ck, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, .recalc = &followparent_recalc, }; @@ -1638,17 +1645,23 @@ static struct clk sdma_fck = { .recalc = &followparent_recalc, }; +/* + * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE + * accesses derived from this data. + */ static struct clk sdma_ick = { .name = "sdma_ick", - .ops = &clkops_null, /* RMK: missing? */ + .ops = &clkops_omap2_iclk_idle_only, .parent = &l4_ck, .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, .recalc = &followparent_recalc, }; static struct clk sdrc_ick = { .name = "sdrc_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_idle_only, .parent = &l4_ck, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", @@ -1659,7 +1672,7 @@ static struct clk sdrc_ick = { static struct clk des_ick = { .name = "des_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1669,7 +1682,7 @@ static struct clk des_ick = { static struct clk sha_ick = { .name = "sha_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1679,7 +1692,7 @@ static struct clk sha_ick = { static struct clk rng_ick = { .name = "rng_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1689,7 +1702,7 @@ static struct clk rng_ick = { static struct clk aes_ick = { .name = "aes_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1699,7 +1712,7 @@ static struct clk aes_ick = { static struct clk pka_ick = { .name = "pka_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), @@ -1719,7 +1732,7 @@ static struct clk usb_fck = { static struct clk usbhs_ick = { .name = "usbhs_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l3_ck, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1729,7 +1742,7 @@ static struct clk usbhs_ick = { static struct clk mmchs1_ick = { .name = "mmchs1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1749,7 +1762,7 @@ static struct clk mmchs1_fck = { static struct clk mmchs2_ick = { .name = "mmchs2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1768,7 +1781,7 @@ static struct clk mmchs2_fck = { static struct clk gpio5_ick = { .name = "gpio5_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), @@ -1788,7 +1801,7 @@ static struct clk gpio5_fck = { static struct clk mdm_intc_ick = { .name = "mdm_intc_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), -- cgit v1.2.3-70-g09d2 From ec538e30f7eded2c4af8d9184619a3de65bc378e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:30 -0700 Subject: OMAP3: clock: use autoidle clkops for all autoidle-controllable interface clocks Mark each interface clock with a corresponding CM_AUTOIDLE bit with a clkops that has the allow_idle/deny_idle function pointers populated. This allows the OMAP clock framework to enable and disable autoidle for these clocks. Signed-off-by: Paul Walmsley Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/clock34xx.c | 29 ++++++- arch/arm/mach-omap2/clock34xx.h | 5 +- arch/arm/mach-omap2/clock3517.c | 4 +- arch/arm/mach-omap2/clock3xxx_data.c | 149 ++++++++++++++++++----------------- 4 files changed, 112 insertions(+), 75 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 287abc48092..1fc96b9ee33 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -2,7 +2,7 @@ * OMAP3-specific clock framework functions * * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation + * Copyright (C) 2007-2011 Nokia Corporation * * Paul Walmsley * Jouni Högander @@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = { .find_companion = omap2_clk_dflt_find_companion, }; +const struct clkops clkops_omap3430es2_iclk_ssi_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap3430es2_clk_ssi_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + /** * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST * @clk: struct clk * being enabled @@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = { .find_companion = omap2_clk_dflt_find_companion, }; +const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; + /** * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB * @clk: struct clk * being enabled @@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = { .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; + +const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, +}; diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 628e8de5768..084ba71b2b3 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -2,14 +2,17 @@ * OMAP34xx clock function prototypes and macros * * Copyright (C) 2007-2010 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation + * Copyright (C) 2007-2011 Nokia Corporation */ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H extern const struct clkops clkops_omap3430es2_ssi_wait; +extern const struct clkops clkops_omap3430es2_iclk_ssi_wait; extern const struct clkops clkops_omap3430es2_hsotgusb_wait; +extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait; extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; +extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait; #endif diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c index 74116a3cf09..2e97d08f0e5 100644 --- a/arch/arm/mach-omap2/clock3517.c +++ b/arch/arm/mach-omap2/clock3517.c @@ -2,7 +2,7 @@ * OMAP3517/3505-specific clock framework functions * * Copyright (C) 2010 Texas Instruments, Inc. - * Copyright (C) 2010 Nokia Corporation + * Copyright (C) 2011 Nokia Corporation * * Ranjith Lohithakshan * Paul Walmsley @@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = { .disable = omap2_dflt_clk_disable, .find_idlest = am35xx_clk_ipss_find_idlest, .find_companion = omap2_clk_dflt_find_companion, + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, }; diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 65b79e6afb5..305b5f75c44 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -2,7 +2,7 @@ * OMAP3 clock data * * Copyright (C) 2007-2010 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation + * Copyright (C) 2007-2011 Nokia Corporation * * Written by Paul Walmsley * With many device clock fixes by Kevin Hilman and Jouni Högander @@ -1205,7 +1205,10 @@ static const struct clksel gfx_l3_clksel[] = { { .parent = NULL } }; -/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ +/* + * Virtual parent clock for gfx_l3_ick and gfx_l3_fck + * This interface clock does not have a CM_AUTOIDLE bit + */ static struct clk gfx_l3_ck = { .name = "gfx_l3_ck", .ops = &clkops_omap2_dflt_wait, @@ -1304,6 +1307,7 @@ static struct clk sgx_fck = { .round_rate = &omap2_clksel_round_rate }; +/* This interface clock does not have a CM_AUTOIDLE bit */ static struct clk sgx_ick = { .name = "sgx_ick", .ops = &clkops_omap2_dflt_wait, @@ -1328,7 +1332,7 @@ static struct clk d2d_26m_fck = { static struct clk modem_fck = { .name = "modem_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_mdmclk_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MODEM_SHIFT, @@ -1338,7 +1342,7 @@ static struct clk modem_fck = { static struct clk sad2d_ick = { .name = "sad2d_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SAD2D_SHIFT, @@ -1348,7 +1352,7 @@ static struct clk sad2d_ick = { static struct clk mad2d_ick = { .name = "mad2d_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430_EN_MAD2D_SHIFT, @@ -1718,7 +1722,7 @@ static struct clk core_l3_ick = { static struct clk hsotgusb_ick_3430es1 = { .name = "hsotgusb_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, @@ -1728,7 +1732,7 @@ static struct clk hsotgusb_ick_3430es1 = { static struct clk hsotgusb_ick_3430es2 = { .name = "hsotgusb_ick", - .ops = &clkops_omap3430es2_hsotgusb_wait, + .ops = &clkops_omap3430es2_iclk_hsotgusb_wait, .parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, @@ -1736,6 +1740,7 @@ static struct clk hsotgusb_ick_3430es2 = { .recalc = &followparent_recalc, }; +/* This interface clock does not have a CM_AUTOIDLE bit */ static struct clk sdrc_ick = { .name = "sdrc_ick", .ops = &clkops_omap2_dflt_wait, @@ -1767,7 +1772,7 @@ static struct clk security_l3_ick = { static struct clk pka_ick = { .name = "pka_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &security_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_PKA_SHIFT, @@ -1786,7 +1791,7 @@ static struct clk core_l4_ick = { static struct clk usbtll_ick = { .name = "usbtll_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, @@ -1796,7 +1801,7 @@ static struct clk usbtll_ick = { static struct clk mmchs3_ick = { .name = "mmchs3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, @@ -1807,7 +1812,7 @@ static struct clk mmchs3_ick = { /* Intersystem Communication Registers - chassis mode only */ static struct clk icr_ick = { .name = "icr_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_ICR_SHIFT, @@ -1817,7 +1822,7 @@ static struct clk icr_ick = { static struct clk aes2_ick = { .name = "aes2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_AES2_SHIFT, @@ -1827,7 +1832,7 @@ static struct clk aes2_ick = { static struct clk sha12_ick = { .name = "sha12_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SHA12_SHIFT, @@ -1837,7 +1842,7 @@ static struct clk sha12_ick = { static struct clk des2_ick = { .name = "des2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_DES2_SHIFT, @@ -1847,7 +1852,7 @@ static struct clk des2_ick = { static struct clk mmchs2_ick = { .name = "mmchs2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, @@ -1857,7 +1862,7 @@ static struct clk mmchs2_ick = { static struct clk mmchs1_ick = { .name = "mmchs1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, @@ -1867,7 +1872,7 @@ static struct clk mmchs1_ick = { static struct clk mspro_ick = { .name = "mspro_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, @@ -1877,7 +1882,7 @@ static struct clk mspro_ick = { static struct clk hdq_ick = { .name = "hdq_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, @@ -1887,7 +1892,7 @@ static struct clk hdq_ick = { static struct clk mcspi4_ick = { .name = "mcspi4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, @@ -1897,7 +1902,7 @@ static struct clk mcspi4_ick = { static struct clk mcspi3_ick = { .name = "mcspi3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, @@ -1907,7 +1912,7 @@ static struct clk mcspi3_ick = { static struct clk mcspi2_ick = { .name = "mcspi2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, @@ -1917,7 +1922,7 @@ static struct clk mcspi2_ick = { static struct clk mcspi1_ick = { .name = "mcspi1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, @@ -1927,7 +1932,7 @@ static struct clk mcspi1_ick = { static struct clk i2c3_ick = { .name = "i2c3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, @@ -1937,7 +1942,7 @@ static struct clk i2c3_ick = { static struct clk i2c2_ick = { .name = "i2c2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, @@ -1947,7 +1952,7 @@ static struct clk i2c2_ick = { static struct clk i2c1_ick = { .name = "i2c1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, @@ -1957,7 +1962,7 @@ static struct clk i2c1_ick = { static struct clk uart2_ick = { .name = "uart2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, @@ -1967,7 +1972,7 @@ static struct clk uart2_ick = { static struct clk uart1_ick = { .name = "uart1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, @@ -1977,7 +1982,7 @@ static struct clk uart1_ick = { static struct clk gpt11_ick = { .name = "gpt11_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, @@ -1987,7 +1992,7 @@ static struct clk gpt11_ick = { static struct clk gpt10_ick = { .name = "gpt10_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, @@ -1997,7 +2002,7 @@ static struct clk gpt10_ick = { static struct clk mcbsp5_ick = { .name = "mcbsp5_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, @@ -2007,7 +2012,7 @@ static struct clk mcbsp5_ick = { static struct clk mcbsp1_ick = { .name = "mcbsp1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, @@ -2017,7 +2022,7 @@ static struct clk mcbsp1_ick = { static struct clk fac_ick = { .name = "fac_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, @@ -2027,7 +2032,7 @@ static struct clk fac_ick = { static struct clk mailboxes_ick = { .name = "mailboxes_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, @@ -2037,7 +2042,7 @@ static struct clk mailboxes_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, @@ -2057,7 +2062,7 @@ static struct clk ssi_l4_ick = { static struct clk ssi_ick_3430es1 = { .name = "ssi_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &ssi_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, @@ -2067,7 +2072,7 @@ static struct clk ssi_ick_3430es1 = { static struct clk ssi_ick_3430es2 = { .name = "ssi_ick", - .ops = &clkops_omap3430es2_ssi_wait, + .ops = &clkops_omap3430es2_iclk_ssi_wait, .parent = &ssi_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, @@ -2085,7 +2090,7 @@ static const struct clksel usb_l4_clksel[] = { static struct clk usb_l4_ick = { .name = "usb_l4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ick, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -2107,7 +2112,7 @@ static struct clk security_l4_ick2 = { static struct clk aes1_ick = { .name = "aes1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_AES1_SHIFT, @@ -2116,7 +2121,7 @@ static struct clk aes1_ick = { static struct clk rng_ick = { .name = "rng_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_RNG_SHIFT, @@ -2125,7 +2130,7 @@ static struct clk rng_ick = { static struct clk sha11_ick = { .name = "sha11_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_SHA11_SHIFT, @@ -2134,7 +2139,7 @@ static struct clk sha11_ick = { static struct clk des1_ick = { .name = "des1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_DES1_SHIFT, @@ -2195,7 +2200,7 @@ static struct clk dss2_alwon_fck = { static struct clk dss_ick_3430es1 = { /* Handles both L3 and L4 clocks */ .name = "dss_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, @@ -2206,7 +2211,7 @@ static struct clk dss_ick_3430es1 = { static struct clk dss_ick_3430es2 = { /* Handles both L3 and L4 clocks */ .name = "dss_ick", - .ops = &clkops_omap3430es2_dss_usbhost_wait, + .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, .parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, @@ -2229,7 +2234,7 @@ static struct clk cam_mclk = { static struct clk cam_ick = { /* Handles both L3 and L4 clocks */ .name = "cam_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_iclk_dflt, .parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, @@ -2272,7 +2277,7 @@ static struct clk usbhost_48m_fck = { static struct clk usbhost_ick = { /* Handles both L3 and L4 clocks */ .name = "usbhost_ick", - .ops = &clkops_omap3430es2_dss_usbhost_wait, + .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, .parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, @@ -2372,7 +2377,7 @@ static struct clk wkup_l4_ick = { /* Never specifically named in the TRM, so we have to infer a likely name */ static struct clk usim_ick = { .name = "usim_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, @@ -2382,7 +2387,7 @@ static struct clk usim_ick = { static struct clk wdt2_ick = { .name = "wdt2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, @@ -2392,7 +2397,7 @@ static struct clk wdt2_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT1_SHIFT, @@ -2402,7 +2407,7 @@ static struct clk wdt1_ick = { static struct clk gpio1_ick = { .name = "gpio1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, @@ -2412,7 +2417,7 @@ static struct clk gpio1_ick = { static struct clk omap_32ksync_ick = { .name = "omap_32ksync_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, @@ -2423,7 +2428,7 @@ static struct clk omap_32ksync_ick = { /* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_ick = { .name = "gpt12_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT12_SHIFT, @@ -2433,7 +2438,7 @@ static struct clk gpt12_ick = { static struct clk gpt1_ick = { .name = "gpt1_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, @@ -2663,7 +2668,7 @@ static struct clk per_l4_ick = { static struct clk gpio6_ick = { .name = "gpio6_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, @@ -2673,7 +2678,7 @@ static struct clk gpio6_ick = { static struct clk gpio5_ick = { .name = "gpio5_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, @@ -2683,7 +2688,7 @@ static struct clk gpio5_ick = { static struct clk gpio4_ick = { .name = "gpio4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, @@ -2693,7 +2698,7 @@ static struct clk gpio4_ick = { static struct clk gpio3_ick = { .name = "gpio3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, @@ -2703,7 +2708,7 @@ static struct clk gpio3_ick = { static struct clk gpio2_ick = { .name = "gpio2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, @@ -2713,7 +2718,7 @@ static struct clk gpio2_ick = { static struct clk wdt3_ick = { .name = "wdt3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, @@ -2723,7 +2728,7 @@ static struct clk wdt3_ick = { static struct clk uart3_ick = { .name = "uart3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, @@ -2733,7 +2738,7 @@ static struct clk uart3_ick = { static struct clk uart4_ick = { .name = "uart4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3630_EN_UART4_SHIFT, @@ -2743,7 +2748,7 @@ static struct clk uart4_ick = { static struct clk gpt9_ick = { .name = "gpt9_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, @@ -2753,7 +2758,7 @@ static struct clk gpt9_ick = { static struct clk gpt8_ick = { .name = "gpt8_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, @@ -2763,7 +2768,7 @@ static struct clk gpt8_ick = { static struct clk gpt7_ick = { .name = "gpt7_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, @@ -2773,7 +2778,7 @@ static struct clk gpt7_ick = { static struct clk gpt6_ick = { .name = "gpt6_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, @@ -2783,7 +2788,7 @@ static struct clk gpt6_ick = { static struct clk gpt5_ick = { .name = "gpt5_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, @@ -2793,7 +2798,7 @@ static struct clk gpt5_ick = { static struct clk gpt4_ick = { .name = "gpt4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, @@ -2803,7 +2808,7 @@ static struct clk gpt4_ick = { static struct clk gpt3_ick = { .name = "gpt3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, @@ -2813,7 +2818,7 @@ static struct clk gpt3_ick = { static struct clk gpt2_ick = { .name = "gpt2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, @@ -2823,7 +2828,7 @@ static struct clk gpt2_ick = { static struct clk mcbsp2_ick = { .name = "mcbsp2_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, @@ -2833,7 +2838,7 @@ static struct clk mcbsp2_ick = { static struct clk mcbsp3_ick = { .name = "mcbsp3_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, @@ -2843,7 +2848,7 @@ static struct clk mcbsp3_ick = { static struct clk mcbsp4_ick = { .name = "mcbsp4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, @@ -3186,7 +3191,7 @@ static struct clk vpfe_fck = { */ static struct clk uart4_ick_am35xx = { .name = "uart4_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_iclk_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = AM35XX_EN_UART4_SHIFT, -- cgit v1.2.3-70-g09d2 From 4ef70c0694bf428d9f1d4722edaffa1dc5fa39e1 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:39:30 -0700 Subject: OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in mach-omap2/pm*xx.c These CM_AUTOIDLE bits are now set by the clock code via the common PM code in mach-omap2/pm.c. N.B.: The pm24xx.c code that this patch removes didn't ensure that the CM_AUTOIDLE bits were set for several 2430-only modules, such as GPIO5, MDM_INTC, MMCHS1/2, the modem oscillator clock, and USBHS. Similarly, the pm34xx.c code that this patch removes didn't ensure that the CM_AUTOIDLE bits were set for USIM and the AM3517 UART4. Those cases should now be handled. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Tested-by: Rajendra Nayak Reviewed-by: Kevin Hilman --- arch/arm/mach-omap2/pm24xx.c | 63 ++------------------------ arch/arm/mach-omap2/pm34xx.c | 105 +------------------------------------------ 2 files changed, 5 insertions(+), 163 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index abe08f49b2e..96907da1910 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -379,7 +379,10 @@ static void __init prcm_setup_regs(void) int i, num_mem_banks; struct powerdomain *pwrdm; - /* Enable autoidle */ + /* + * Enable autoidle + * XXX This should be handled by hwmod code or PRCM init code + */ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, OMAP2_PRCM_SYSCONFIG_OFFSET); @@ -418,64 +421,6 @@ static void __init prcm_setup_regs(void) clkdm_for_each(clkdms_setup, NULL); clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); - /* Enable clock autoidle for all domains */ - omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | - OMAP24XX_AUTO_MAILBOXES_MASK | - OMAP24XX_AUTO_WDT4_MASK | - OMAP2420_AUTO_WDT3_MASK | - OMAP24XX_AUTO_MSPRO_MASK | - OMAP2420_AUTO_MMC_MASK | - OMAP24XX_AUTO_FAC_MASK | - OMAP2420_AUTO_EAC_MASK | - OMAP24XX_AUTO_HDQ_MASK | - OMAP24XX_AUTO_UART2_MASK | - OMAP24XX_AUTO_UART1_MASK | - OMAP24XX_AUTO_I2C2_MASK | - OMAP24XX_AUTO_I2C1_MASK | - OMAP24XX_AUTO_MCSPI2_MASK | - OMAP24XX_AUTO_MCSPI1_MASK | - OMAP24XX_AUTO_MCBSP2_MASK | - OMAP24XX_AUTO_MCBSP1_MASK | - OMAP24XX_AUTO_GPT12_MASK | - OMAP24XX_AUTO_GPT11_MASK | - OMAP24XX_AUTO_GPT10_MASK | - OMAP24XX_AUTO_GPT9_MASK | - OMAP24XX_AUTO_GPT8_MASK | - OMAP24XX_AUTO_GPT7_MASK | - OMAP24XX_AUTO_GPT6_MASK | - OMAP24XX_AUTO_GPT5_MASK | - OMAP24XX_AUTO_GPT4_MASK | - OMAP24XX_AUTO_GPT3_MASK | - OMAP24XX_AUTO_GPT2_MASK | - OMAP2420_AUTO_VLYNQ_MASK | - OMAP24XX_AUTO_DSS_MASK, - CORE_MOD, CM_AUTOIDLE1); - omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | - OMAP24XX_AUTO_SSI_MASK | - OMAP24XX_AUTO_USB_MASK, - CORE_MOD, CM_AUTOIDLE2); - omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | - OMAP24XX_AUTO_GPMC_MASK | - OMAP24XX_AUTO_SDMA_MASK, - CORE_MOD, CM_AUTOIDLE3); - omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | - OMAP24XX_AUTO_AES_MASK | - OMAP24XX_AUTO_RNG_MASK | - OMAP24XX_AUTO_SHA_MASK | - OMAP24XX_AUTO_DES_MASK, - CORE_MOD, OMAP24XX_CM_AUTOIDLE4); - - omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, - CM_AUTOIDLE); - - omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | - OMAP24XX_AUTO_WDT1_MASK | - OMAP24XX_AUTO_MPU_WDT_MASK | - OMAP24XX_AUTO_GPIOS_MASK | - OMAP24XX_AUTO_32KSYNC_MASK | - OMAP24XX_AUTO_GPT1_MASK, - WKUP_MOD, CM_AUTOIDLE); - /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk * stabilisation */ omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index a99f296bdbf..3d6a00e07a5 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -688,14 +688,11 @@ static void __init omap3_d2d_idle(void) static void __init prcm_setup_regs(void) { - u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? - OMAP3630_AUTO_UART4_MASK : 0; u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? OMAP3630_EN_UART4_MASK : 0; u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? OMAP3630_GRPSEL_UART4_MASK : 0; - /* XXX Reset all wkdeps. This should be done when initializing * powerdomains */ omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); @@ -710,107 +707,7 @@ static void __init prcm_setup_regs(void) } else omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); - /* - * Enable interface clock autoidle for all modules. - * Note that in the long run this should be done by clockfw - */ - omap2_cm_write_mod_reg( - OMAP3430_AUTO_MODEM_MASK | - OMAP3430ES2_AUTO_MMC3_MASK | - OMAP3430ES2_AUTO_ICR_MASK | - OMAP3430_AUTO_AES2_MASK | - OMAP3430_AUTO_SHA12_MASK | - OMAP3430_AUTO_DES2_MASK | - OMAP3430_AUTO_MMC2_MASK | - OMAP3430_AUTO_MMC1_MASK | - OMAP3430_AUTO_MSPRO_MASK | - OMAP3430_AUTO_HDQ_MASK | - OMAP3430_AUTO_MCSPI4_MASK | - OMAP3430_AUTO_MCSPI3_MASK | - OMAP3430_AUTO_MCSPI2_MASK | - OMAP3430_AUTO_MCSPI1_MASK | - OMAP3430_AUTO_I2C3_MASK | - OMAP3430_AUTO_I2C2_MASK | - OMAP3430_AUTO_I2C1_MASK | - OMAP3430_AUTO_UART2_MASK | - OMAP3430_AUTO_UART1_MASK | - OMAP3430_AUTO_GPT11_MASK | - OMAP3430_AUTO_GPT10_MASK | - OMAP3430_AUTO_MCBSP5_MASK | - OMAP3430_AUTO_MCBSP1_MASK | - OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ - OMAP3430_AUTO_MAILBOXES_MASK | - OMAP3430_AUTO_OMAPCTRL_MASK | - OMAP3430ES1_AUTO_FSHOSTUSB_MASK | - OMAP3430_AUTO_HSOTGUSB_MASK | - OMAP3430_AUTO_SAD2D_MASK | - OMAP3430_AUTO_SSI_MASK, - CORE_MOD, CM_AUTOIDLE1); - - omap2_cm_write_mod_reg( - OMAP3430_AUTO_PKA_MASK | - OMAP3430_AUTO_AES1_MASK | - OMAP3430_AUTO_RNG_MASK | - OMAP3430_AUTO_SHA11_MASK | - OMAP3430_AUTO_DES1_MASK, - CORE_MOD, CM_AUTOIDLE2); - - if (omap_rev() > OMAP3430_REV_ES1_0) { - omap2_cm_write_mod_reg( - OMAP3430_AUTO_MAD2D_MASK | - OMAP3430ES2_AUTO_USBTLL_MASK, - CORE_MOD, CM_AUTOIDLE3); - } - - omap2_cm_write_mod_reg( - OMAP3430_AUTO_WDT2_MASK | - OMAP3430_AUTO_WDT1_MASK | - OMAP3430_AUTO_GPIO1_MASK | - OMAP3430_AUTO_32KSYNC_MASK | - OMAP3430_AUTO_GPT12_MASK | - OMAP3430_AUTO_GPT1_MASK, - WKUP_MOD, CM_AUTOIDLE); - - omap2_cm_write_mod_reg( - OMAP3430_AUTO_DSS_MASK, - OMAP3430_DSS_MOD, - CM_AUTOIDLE); - - omap2_cm_write_mod_reg( - OMAP3430_AUTO_CAM_MASK, - OMAP3430_CAM_MOD, - CM_AUTOIDLE); - - omap2_cm_write_mod_reg( - omap3630_auto_uart4_mask | - OMAP3430_AUTO_GPIO6_MASK | - OMAP3430_AUTO_GPIO5_MASK | - OMAP3430_AUTO_GPIO4_MASK | - OMAP3430_AUTO_GPIO3_MASK | - OMAP3430_AUTO_GPIO2_MASK | - OMAP3430_AUTO_WDT3_MASK | - OMAP3430_AUTO_UART3_MASK | - OMAP3430_AUTO_GPT9_MASK | - OMAP3430_AUTO_GPT8_MASK | - OMAP3430_AUTO_GPT7_MASK | - OMAP3430_AUTO_GPT6_MASK | - OMAP3430_AUTO_GPT5_MASK | - OMAP3430_AUTO_GPT4_MASK | - OMAP3430_AUTO_GPT3_MASK | - OMAP3430_AUTO_GPT2_MASK | - OMAP3430_AUTO_MCBSP4_MASK | - OMAP3430_AUTO_MCBSP3_MASK | - OMAP3430_AUTO_MCBSP2_MASK, - OMAP3430_PER_MOD, - CM_AUTOIDLE); - - if (omap_rev() > OMAP3430_REV_ES1_0) { - omap2_cm_write_mod_reg( - OMAP3430ES2_AUTO_USBHOST_MASK, - OMAP3430ES2_USBHOST_MOD, - CM_AUTOIDLE); - } - + /* XXX This should be handled by hwmod code or SCM init code */ omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); /* -- cgit v1.2.3-70-g09d2 From a1fed577ddc0ca0ec7cf5e5ee033fe3df4192ebd Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:51:02 -0700 Subject: OMAP2xxx: clock: fix parents for L3-derived clocks Several clocks are listed as having the core L4 clock as their parent, when they are actually derived from the L3 clock. Fix these. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2420_data.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 68c03691e56..693a0a84c33 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1614,7 +1614,7 @@ static struct clk sdma_fck = { static struct clk sdma_ick = { .name = "sdma_ick", .ops = &clkops_omap2_iclk_idle_only, - .parent = &l4_ck, + .parent = &core_l3_ck, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 34daed9cd56..f00f52ebfea 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1652,7 +1652,7 @@ static struct clk sdma_fck = { static struct clk sdma_ick = { .name = "sdma_ick", .ops = &clkops_omap2_iclk_idle_only, - .parent = &l4_ck, + .parent = &core_l3_ck, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, @@ -1662,9 +1662,9 @@ static struct clk sdma_ick = { static struct clk sdrc_ick = { .name = "sdrc_ick", .ops = &clkops_omap2_iclk_idle_only, - .parent = &l4_ck, + .parent = &core_l3_ck, .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", + .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP2430_EN_SDRC_SHIFT, .recalc = &followparent_recalc, -- cgit v1.2.3-70-g09d2 From 3f9cfd3a47a07c93ff00a1a4ca067ada87e4076a Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 16 Feb 2011 15:38:38 -0700 Subject: OMAP2xxx: clock: fix low-frequency oscillator clock rate The OMAP2420/2430 external 32-kHz low-frequency oscillator is a 32768 Hz oscillator, not a 32,000 Hz oscillator[1][2]. Fix this in the clock tree. Signed-off-by: Paul Walmsley 1. OMAP2420/22 Multimedia Processor Data Manual, Version P [SWPS019P], section 5.1.4 "External 32-kHz CMOS Clock" (note that it refers to a "32.768-kHz" clock; this presumably should be "32.768-KHz") 2. OMAP2430 Multimedia Processor ES2.1 Data Manual, Version V [SWPS023V], section 5.1.4 "External 32-kHz CMOS Clock" (note that it refers to a "32.768-kHz" clock; this presumably should be "32.768-KHz") --- arch/arm/mach-omap2/clock2420_data.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 693a0a84c33..fd5ba90188b 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -55,7 +55,7 @@ static struct clk func_32k_ck = { .name = "func_32k_ck", .ops = &clkops_null, - .rate = 32000, + .rate = 32768, .clkdm_name = "wkup_clkdm", }; diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index f00f52ebfea..0d069ef49e2 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -55,7 +55,7 @@ static struct clk func_32k_ck = { .name = "func_32k_ck", .ops = &clkops_null, - .rate = 32000, + .rate = 32768, .clkdm_name = "wkup_clkdm", }; -- cgit v1.2.3-70-g09d2 From 19c1c0ce9ddc45fe8f84b6cf12ba9dbecd7b1aa1 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 16 Feb 2011 15:38:38 -0700 Subject: OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain The parent of the interface clocks for GPTIMER1, MPU_WDT, SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as being l4_ck. This isn't accurate; these modules exist inside the WKUP domain, and the interface clock to these modules runs at the SYS_CLK rate rather than the CORE L4 rate. So, create a new clock "wu_l4_ick", similar to the OMAP3 "wkup_l4_ick", that serves as the parent for these clocks. Also, these clocks were listed as existing inside core_l4_clkdm; wkup_clkdm is probably more accurate. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2420_data.c | 33 ++++++++++++++++++++------------ arch/arm/mach-omap2/clock2430_data.c | 37 ++++++++++++++++++++++-------------- 2 files changed, 44 insertions(+), 26 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index fd5ba90188b..6e9d20dc864 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -826,6 +826,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ .recalc = &followparent_recalc, }; +static struct clk wu_l4_ick = { + .name = "wu_l4_ick", + .ops = &clkops_null, + .parent = &sys_ck, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + /* * CORE power domain ICLK & FCLK defines. * Many of the these can have more than one possible parent. Entries @@ -847,8 +855,8 @@ static const struct clksel omap24xx_gpt_clksel[] = { static struct clk gpt1_ick = { .name = "gpt1_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .recalc = &followparent_recalc, @@ -1300,8 +1308,8 @@ static struct clk uart3_fck = { static struct clk gpios_ick = { .name = "gpios_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .recalc = &followparent_recalc, @@ -1320,8 +1328,8 @@ static struct clk gpios_fck = { static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .recalc = &followparent_recalc, @@ -1340,9 +1348,9 @@ static struct clk mpu_wdt_fck = { static struct clk sync_32k_ick = { .name = "sync_32k_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, .recalc = &followparent_recalc, @@ -1351,8 +1359,8 @@ static struct clk sync_32k_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_WDT1_SHIFT, .recalc = &followparent_recalc, @@ -1361,9 +1369,9 @@ static struct clk wdt1_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, .recalc = &followparent_recalc, @@ -1825,6 +1833,7 @@ static struct omap_clk omap2420_clks[] = { /* L4 domain clocks */ CLK(NULL, "l4_ck", &l4_ck, CK_242X), CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), /* virtual meta-group clock */ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), /* general l4 interface ck, multi-parent functional clk */ diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 0d069ef49e2..3378dbf8bac 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -814,6 +814,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ .recalc = &followparent_recalc, }; +static struct clk wu_l4_ick = { + .name = "wu_l4_ick", + .ops = &clkops_null, + .parent = &sys_ck, + .clkdm_name = "wkup_clkdm", + .recalc = &followparent_recalc, +}; + /* * CORE power domain ICLK & FCLK defines. * Many of the these can have more than one possible parent. Entries @@ -835,8 +843,8 @@ static const struct clksel omap24xx_gpt_clksel[] = { static struct clk gpt1_ick = { .name = "gpt1_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPT1_SHIFT, .recalc = &followparent_recalc, @@ -1380,8 +1388,8 @@ static struct clk uart3_fck = { static struct clk gpios_ick = { .name = "gpios_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, .recalc = &followparent_recalc, @@ -1400,8 +1408,8 @@ static struct clk gpios_fck = { static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, .recalc = &followparent_recalc, @@ -1420,9 +1428,9 @@ static struct clk mpu_wdt_fck = { static struct clk sync_32k_ick = { .name = "sync_32k_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, .recalc = &followparent_recalc, @@ -1431,8 +1439,8 @@ static struct clk sync_32k_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_WDT1_SHIFT, .recalc = &followparent_recalc, @@ -1441,9 +1449,9 @@ static struct clk wdt1_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, .recalc = &followparent_recalc, @@ -1452,8 +1460,8 @@ static struct clk omapctrl_ick = { static struct clk icr_ick = { .name = "icr_ick", .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", + .parent = &wu_l4_ick, + .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP2430_EN_ICR_SHIFT, .recalc = &followparent_recalc, @@ -1914,6 +1922,7 @@ static struct omap_clk omap2430_clks[] = { /* L4 domain clocks */ CLK(NULL, "l4_ck", &l4_ck, CK_243X), CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), /* virtual meta-group clock */ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), /* general l4 interface ck, multi-parent functional clk */ -- cgit v1.2.3-70-g09d2 From 241d3a8dca239610d3d991bf58d4fe38c2d86fd5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 16 Feb 2011 15:38:39 -0700 Subject: OMAP2+: clock: remove the DPLL rate tolerance code Remove the DPLL rate tolerance code that is called during rate rounding. As far as I know, this code is never used, since it's been more important for callers of the DPLL round_rate()/set_rate() functions to obtain an exact rate than it is to save a relatively small amount of power. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_dpll.c | 91 +++++++++------------------------ arch/arm/mach-omap2/clock.h | 4 -- arch/arm/mach-omap2/clock2420_data.c | 1 - arch/arm/mach-omap2/clock2430_data.c | 1 - arch/arm/mach-omap2/clock3xxx_data.c | 6 --- arch/arm/plat-omap/include/plat/clock.h | 7 +-- 6 files changed, 24 insertions(+), 86 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 337392c3f54..17735e7f47b 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk) if (!dd) return; - /* Return bypass rate if DPLL is bypassed */ v = __raw_readl(dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - /* Reparent in case the dpll is in bypass */ + /* Reparent the struct clk in case the dpll is in bypass */ if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) @@ -259,51 +258,23 @@ u32 omap2_get_dpll_rate(struct clk *clk) /* DPLL rate rounding code */ -/** - * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding - * @clk: struct clk * of the DPLL - * @tolerance: maximum rate error tolerance - * - * Set the maximum DPLL rate error tolerance for the rate rounding - * algorithm. The rate tolerance is an attempt to balance DPLL power - * saving (the least divider value "n") vs. rate fidelity (the least - * difference between the desired DPLL target rate and the rounded - * rate out of the algorithm). So, increasing the tolerance is likely - * to decrease DPLL power consumption and increase DPLL rate error. - * Returns -EINVAL if provided a null clock ptr or a clk that is not a - * DPLL; or 0 upon success. - */ -int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) -{ - if (!clk || !clk->dpll_data) - return -EINVAL; - - clk->dpll_data->rate_tolerance = tolerance; - - return 0; -} - /** * omap2_dpll_round_rate - round a target rate for an OMAP DPLL * @clk: struct clk * for a DPLL * @target_rate: desired DPLL clock rate * - * Given a DPLL, a desired target rate, and a rate tolerance, round - * the target rate to a possible, programmable rate for this DPLL. - * Rate tolerance is assumed to be set by the caller before this - * function is called. Attempts to select the minimum possible n - * within the tolerance to reduce power consumption. Stores the - * computed (m, n) in the DPLL's dpll_data structure so set_rate() - * will not need to call this (expensive) function again. Returns ~0 - * if the target rate cannot be rounded, either because the rate is - * too low or because the rate tolerance is set too tightly; or the - * rounded rate upon success. + * Given a DPLL and a desired target rate, round the target rate to a + * possible, programmable rate for this DPLL. Attempts to select the + * minimum possible n. Stores the computed (m, n) in the DPLL's + * dpll_data structure so set_rate() will not need to call this + * (expensive) function again. Returns ~0 if the target rate cannot + * be rounded, or the rounded rate upon success. */ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) { - int m, n, r, e, scaled_max_m; - unsigned long scaled_rt_rp, new_rate; - int min_e = -1, min_e_m = -1, min_e_n = -1; + int m, n, r, scaled_max_m; + unsigned long scaled_rt_rp; + unsigned long new_rate = 0; struct dpll_data *dd; if (!clk || !clk->dpll_data) @@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; - pr_debug("clock: starting DPLL round_rate for clock %s, target rate " - "%ld\n", clk->name, target_rate); + pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", + clk->name, target_rate); scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; @@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) if (r == DPLL_MULT_UNDERFLOW) continue; - e = target_rate - new_rate; - pr_debug("clock: n = %d: m = %d: rate error is %d " - "(new_rate = %ld)\n", n, m, e, new_rate); - - if (min_e == -1 || - min_e >= (int)(abs(e) - dd->rate_tolerance)) { - min_e = e; - min_e_m = m; - min_e_n = n; - - pr_debug("clock: found new least error %d\n", min_e); + pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", + clk->name, m, n, new_rate); - /* We found good settings -- bail out now */ - if (min_e <= dd->rate_tolerance) - break; + if (target_rate == new_rate) { + dd->last_rounded_m = m; + dd->last_rounded_n = n; + dd->last_rounded_rate = target_rate; + break; } } - if (min_e < 0) { - pr_debug("clock: error: target rate or tolerance too low\n"); + if (target_rate != new_rate) { + pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, + target_rate); return ~0; } - dd->last_rounded_m = min_e_m; - dd->last_rounded_n = min_e_n; - dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, - min_e_m, min_e_n); - - pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", - min_e, min_e_m, min_e_n); - pr_debug("clock: final rate: %ld (target rate: %ld)\n", - dd->last_rounded_rate, target_rate); - - return dd->last_rounded_rate; + return target_rate; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 70f8b073e69..62cfd6cc746 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -18,9 +18,6 @@ #include -/* The maximum error between a target DPLL rate and the rounded rate in Hz */ -#define DEFAULT_DPLL_RATE_TOLERANCE 50000 - /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 @@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap3_dpll_recalc(struct clk *clk); unsigned long omap3_clkoutx2_recalc(struct clk *clk); diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 6e9d20dc864..22eeafc89b9 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = { .max_multiplier = 1023, .min_divider = 1, .max_divider = 16, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; /* diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 3378dbf8bac..df4cac5fef0 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = { .max_multiplier = 1023, .min_divider = 1, .max_divider = 16, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; /* diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 305b5f75c44..3dbeb3a5813 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -291,7 +291,6 @@ static struct dpll_data dpll1_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll1_ck = { @@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll2_ck = { @@ -424,7 +422,6 @@ static struct dpll_data dpll3_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll3_ck = { @@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct dpll_data dpll4_dd_3630 __initdata = { @@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = { .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE, .flags = DPLL_J_TYPE }; @@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll5_ck = { diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index dcd7bb81420..006e599c661 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -109,7 +109,6 @@ struct clksel { * @clk_ref: struct clk pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg - * @rate_tolerance: maximum variance allowed from target rate (in Hz) * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() * @max_multiplier: maximum valid non-bypass multiplier value (actual) @@ -135,12 +134,9 @@ struct clksel { * XXX Some DPLLs have multiple bypass inputs, so it's not technically * correct to only have one @clk_bypass pointer. * - * XXX @rate_tolerance should probably be deprecated - currently there - * don't seem to be any usecases for DPLL rounding that is not exact. - * * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, * @last_rounded_n) should be separated from the runtime-fixed fields - * and placed into a differenct structure, so that the runtime-fixed data + * and placed into a different structure, so that the runtime-fixed data * can be placed into read-only space. */ struct dpll_data { @@ -151,7 +147,6 @@ struct dpll_data { struct clk *clk_ref; void __iomem *control_reg; u32 enable_mask; - unsigned int rate_tolerance; unsigned long last_rounded_rate; u16 last_rounded_m; u16 max_multiplier; -- cgit v1.2.3-70-g09d2 From 224113969dc9cc7a55f69da4dde5dc3fd1bbeb76 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:52:04 -0700 Subject: OMAP2xxx: clock: remove dsp_irate_ick After commit 81b34fbecbfbf24ed95c2d80d5cb14149652408f ("OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files"), it's possible to remove dsp_irate_ick from the OMAP2420 and OMAP2430 clock files. It was originally only needed due to a 2420/2430 clock tree difference, and now that the data is in separate files, it's superfluous. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.h | 1 + arch/arm/mach-omap2/clock2420_data.c | 31 ++++++++----------------------- arch/arm/mach-omap2/clock2430_data.c | 31 ++++++++----------------------- arch/arm/mach-omap2/clock_common_data.c | 6 ++++++ 4 files changed, 23 insertions(+), 46 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 62cfd6cc746..e10ff2b5484 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -139,6 +139,7 @@ extern struct clk *vclk, *sclk; extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; +extern const struct clksel_rate dsp_ick_rates[]; #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 22eeafc89b9..53bd999c63a 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -454,36 +454,22 @@ static struct clk dsp_fck = { .recalc = &omap2_clksel_recalc, }; -/* DSP interface clock */ -static const struct clksel_rate dsp_irate_ick_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel dsp_irate_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, { .parent = NULL } }; -/* This clock does not exist as such in the TRM. */ -static struct clk dsp_irate_ick = { - .name = "dsp_irate_ick", - .ops = &clkops_null, - .parent = &dsp_fck, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, - .clksel = dsp_irate_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* 2420 only */ static struct clk dsp_ick = { .name = "dsp_ick", /* apparently ipi and isp */ .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &dsp_irate_ick, + .parent = &dsp_fck, + .clkdm_name = "dsp_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ + .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, + .clksel = dsp_ick_clksel, + .recalc = &omap2_clksel_recalc, }; /* @@ -1812,7 +1798,6 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), /* dsp domain clocks */ CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), - CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X), CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index df4cac5fef0..36dde2635ac 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -433,37 +433,23 @@ static struct clk dsp_fck = { .recalc = &omap2_clksel_recalc, }; -/* DSP interface clock */ -static const struct clksel_rate dsp_irate_ick_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_243X }, - { .div = 0 }, -}; - -static const struct clksel dsp_irate_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_irate_ick_rates }, +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, { .parent = NULL } }; -/* This clock does not exist as such in the TRM. */ -static struct clk dsp_irate_ick = { - .name = "dsp_irate_ick", - .ops = &clkops_null, - .parent = &dsp_fck, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, - .clksel = dsp_irate_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ static struct clk iva2_1_ick = { .name = "iva2_1_ick", .ops = &clkops_omap2_dflt_wait, - .parent = &dsp_irate_ick, + .parent = &dsp_fck, + .clkdm_name = "dsp_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, + .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, + .clksel = dsp_ick_clksel, + .recalc = &omap2_clksel_recalc, }; /* @@ -1900,7 +1886,6 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), /* dsp domain clocks */ CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), - CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X), CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), /* GFX domain clocks */ CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index 1cf8131205f..6424d46be14 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -37,3 +37,9 @@ const struct clksel_rate gfx_l3_rates[] = { { .div = 0 } }; +const struct clksel_rate dsp_ick_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_243X }, + { .div = 0 }, +}; -- cgit v1.2.3-70-g09d2 From 691abf525d3d215f2e4eab7a015ef2b6375c58a5 Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Fri, 11 Feb 2011 09:05:00 +0000 Subject: omap2/3: clockdomains: fix compile-time warnings This patch fixes these warnings when building kernel for OMAP3EVM only. CC arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.o arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c:95: warning: 'dsp_24xx_wkdeps' defined but not used arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c:119: warning: 'mpu_24xx_wkdeps' defined but not used arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c:147: warning: 'core_24xx_wkdeps' defined but not used The problem should be noticed when building for other OMAP3 platforms (only) as well. Signed-off-by: Sanjeev Premi Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index ffdfe54f326..13bde95b679 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -89,6 +89,8 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = { /* 24XX-specific possible dependencies */ +#ifdef CONFIG_ARCH_OMAP2 + /* Wakeup dependency source arrays */ /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ @@ -168,6 +170,7 @@ static struct clkdm_dep core_24xx_wkdeps[] = { { NULL }, }; +#endif /* CONFIG_ARCH_OMAP2 */ /* 2430-specific possible wakeup dependencies */ -- cgit v1.2.3-70-g09d2 From a4fc92748e969b1312f283b0d1baf657329f2907 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 14:53:40 -0700 Subject: OMAP2xxx: clock: fix clockdomains on gpt7_ick, 2430 mmchs2_fck clocks Add a clockdomain to the GPTIMER7 interface and 2430 HSMMC2 functional clocks - both were previously missing them. Also, the 2430 mmchs1_fck is in core_l3_clkdm, but should be in core_l4_clkdm; fix this. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2420_data.c | 1 + arch/arm/mach-omap2/clock2430_data.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 53bd999c63a..5e80d3dc274 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -987,6 +987,7 @@ static struct clk gpt7_ick = { .name = "gpt7_ick", .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, + .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, .recalc = &followparent_recalc, diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 36dde2635ac..8957fc6f64e 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -975,6 +975,7 @@ static struct clk gpt7_ick = { .name = "gpt7_ick", .ops = &clkops_omap2_iclk_dflt_wait, .parent = &l4_ck, + .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP24XX_EN_GPT7_SHIFT, .recalc = &followparent_recalc, @@ -1747,7 +1748,7 @@ static struct clk mmchs1_fck = { .name = "mmchs1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, - .clkdm_name = "core_l3_clkdm", + .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, .recalc = &followparent_recalc, @@ -1767,6 +1768,7 @@ static struct clk mmchs2_fck = { .name = "mmchs2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, .recalc = &followparent_recalc, -- cgit v1.2.3-70-g09d2 From 8c810e7e14457d97706d4c6de4bb4847e3715d1b Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 13:56:40 -0700 Subject: OMAP2xxx: clock data: clean up some comments Minor cleanup of some clock data comments. No functional changes. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2420_data.c | 23 ++++++++++------------- arch/arm/mach-omap2/clock2430_data.c | 23 ++++++++++------------- 2 files changed, 20 insertions(+), 26 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 5e80d3dc274..b6f65d4ac97 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1,12 +1,12 @@ /* - * linux/arch/arm/mach-omap2/clock2420_data.c + * OMAP2420 clock data * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation + * Copyright (C) 2005-2009 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation * - * Contacts: - * Richard Woodruff - * Paul Walmsley + * Contacts: + * Richard Woodruff + * Paul Walmsley * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -34,18 +34,15 @@ /* * 2420 clock tree. * - * NOTE:In many cases here we are assigning a 'default' parent. In many - * cases the parent is selectable. The get/set parent calls will also - * switch sources. - * - * Many some clocks say always_enabled, but they can be auto idled for - * power savings. They will always be available upon clock request. + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. * * Several sources are given initial rates which may be wrong, this will * be fixed up in the init func. * * Things are broadly separated below by clock domains. It is - * noteworthy that most periferals have dependencies on multiple clock + * noteworthy that most peripherals have dependencies on multiple clock * domains. Many get their interface clocks from the L4 domain, but get * functional clocks from fixed sources or other core domain derived * clocks. diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 8957fc6f64e..5c2a075fd82 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1,12 +1,12 @@ /* - * linux/arch/arm/mach-omap2/clock2430_data.c + * OMAP2430 clock data * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation + * Copyright (C) 2005-2009 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation * - * Contacts: - * Richard Woodruff - * Paul Walmsley + * Contacts: + * Richard Woodruff + * Paul Walmsley * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -34,18 +34,15 @@ /* * 2430 clock tree. * - * NOTE:In many cases here we are assigning a 'default' parent. In many - * cases the parent is selectable. The get/set parent calls will also - * switch sources. - * - * Many some clocks say always_enabled, but they can be auto idled for - * power savings. They will always be available upon clock request. + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. * * Several sources are given initial rates which may be wrong, this will * be fixed up in the init func. * * Things are broadly separated below by clock domains. It is - * noteworthy that most periferals have dependencies on multiple clock + * noteworthy that most peripherals have dependencies on multiple clock * domains. Many get their interface clocks from the L4 domain, but get * functional clocks from fixed sources or other core domain derived * clocks. -- cgit v1.2.3-70-g09d2 From 0640b436e410290193f554dcfd777bcdeee59697 Mon Sep 17 00:00:00 2001 From: Abhilash Vadakkepat Koyamangalath Date: Tue, 8 Mar 2011 15:13:24 +0000 Subject: audio : AM3517 : Adding i2c info for AIC23 codec The i2c_board_info entry supporting AIC23 codec was added into the i2c2 bus. Signed-off-by: Abhilash K V Acked-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-am3517evm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 30ec4519326..77541cf59bd 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -199,6 +199,9 @@ static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = { .gpio_base = OMAP_MAX_GPIO_LINES, }; static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = { + { + I2C_BOARD_INFO("tlv320aic23", 0x1A), + }, { I2C_BOARD_INFO("tca6416", 0x21), .platform_data = &am3517evm_gpio_expander_info_0, -- cgit v1.2.3-70-g09d2 From 4bb194dc9471c79caa1952ecdb31148074ac1abf Mon Sep 17 00:00:00 2001 From: sricharan Date: Tue, 8 Feb 2011 22:13:37 +0530 Subject: OMAP3: hwmod_data: Add address space and irq in L3 hwmod. Add the address spaces, irqs of the l3 interconnect to the hwmod data. The hwmod changes are aligned with Benoit Cousson. Signed-off-by: sricharan Signed-off-by: Santosh Shilimkar Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 22 ++++++++++++++++++++-- arch/arm/plat-omap/include/plat/irqs.h | 2 ++ 2 files changed, 22 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e2792cf9c54..2539e469c1e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -100,10 +100,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L3 taret configuration and error log registers */ +static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { + { .irq = INT_34XX_L3_DBG_IRQ }, + { .irq = INT_34XX_L3_APP_IRQ }, +}; + +static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { + { + .pa_start = 0x68000000, + .pa_end = 0x6800ffff, + .flags = ADDR_TYPE_RT, + }, +}; + /* MPU -> L3 interface */ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { - .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_main_hwmod, + .master = &omap3xxx_mpu_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .addr = omap3xxx_l3_main_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs), .user = OCP_USER_MPU, }; @@ -135,6 +151,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { static struct omap_hwmod omap3xxx_l3_main_hwmod = { .name = "l3_main", .class = &l3_hwmod_class, + .mpu_irqs = omap3xxx_l3_main_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs), .masters = omap3xxx_l3_main_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), .slaves = omap3xxx_l3_main_slaves, diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 1b911681e91..d7792837046 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -315,6 +315,8 @@ #define INT_34XX_SSM_ABORT_IRQ 6 #define INT_34XX_SYS_NIRQ 7 #define INT_34XX_D2D_FW_IRQ 8 +#define INT_34XX_L3_DBG_IRQ 9 +#define INT_34XX_L3_APP_IRQ 10 #define INT_34XX_PRCM_MPU_IRQ 11 #define INT_34XX_MCBSP1_IRQ 16 #define INT_34XX_MCBSP2_IRQ 17 -- cgit v1.2.3-70-g09d2 From 0abcf6185eb87b9e00a821513802e56200378a6a Mon Sep 17 00:00:00 2001 From: sricharan Date: Tue, 8 Feb 2011 14:10:45 +0530 Subject: OMAP3: devices: Initialise the l3 device with the hwmod data. The l3 interconnect device is build with all the data required to handle the error logging. The data is extracted from the hwmod database. Signed-off-by: sricharan Signed-off-by: Santosh Shilimkar Acked-by: Benoit Cousson --- arch/arm/mach-omap2/devices.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2cb720b5b12..6a320b61631 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -36,6 +36,38 @@ #include "mux.h" #include "control.h" +#define L3_MODULES_MAX_LEN 12 + +static int __init omap3_l3_init(void) +{ + int l; + struct omap_hwmod *oh; + struct omap_device *od; + char oh_name[L3_MODULES_MAX_LEN]; + + /* + * To avoid code running on other OMAPs in + * multi-omap builds + */ + if (!(cpu_is_omap34xx())) + return -ENODEV; + + l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); + + oh = omap_hwmod_lookup(oh_name); + + if (!oh) + pr_err("could not look up %s\n", oh_name); + + od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, + NULL, 0, 0); + + WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); + + return PTR_ERR(od); +} +postcore_initcall(omap3_l3_init); + #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) static struct resource cam_resources[] = { -- cgit v1.2.3-70-g09d2 From e2fa61d409195550b3b05b213d7715bc67b0e855 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 7 Mar 2011 19:35:20 +0530 Subject: OMAP3: l3: Introduce l3-interconnect error handling driver The driver provides the information regarding the ocp errors that gets logged in the interconnect.The error info provides the details regarding the master or the target that generated the error, type of error and the corresponding address. The stack dump is also provided. Signed-off-by: sricharan [r.sricharan@ti.com: Enhacements, major cleanup and made it functional] Signed-off-by: Santosh Shilimkar [santosh.shilimkar@ti.com: Driver design changes as per OMAP4 version] Signed-off-by: Felipe Balbi [balbi@ti.com: Initial version of the driver] Acked-by: Benoit Cousson --- arch/arm/mach-omap2/Makefile | 3 + arch/arm/mach-omap2/omap_l3_smx.c | 314 +++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/omap_l3_smx.h | 338 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 655 insertions(+) create mode 100644 arch/arm/mach-omap2/omap_l3_smx.c create mode 100644 arch/arm/mach-omap2/omap_l3_smx.h (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1c3635d7f4c..e4c9bb3ad89 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -135,6 +135,9 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o +# L3 interconnect +obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o + obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c new file mode 100644 index 00000000000..265bff3acb9 --- /dev/null +++ b/arch/arm/mach-omap2/omap_l3_smx.c @@ -0,0 +1,314 @@ + /* + * OMAP3XXX L3 Interconnect Driver + * + * Copyright (C) 2011 Texas Corporation + * Felipe Balbi + * Santosh Shilimkar + * Sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ + +#include +#include +#include +#include +#include +#include "omap_l3_smx.h" + +static inline u64 omap3_l3_readll(void __iomem *base, u16 reg) +{ + return __raw_readll(base + reg); +} + +static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value) +{ + __raw_writell(value, base + reg); +} + +static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error) +{ + return (error & 0x0f000000) >> L3_ERROR_LOG_CODE; +} + +static inline u32 omap3_l3_decode_addr(u64 error_addr) +{ + return error_addr & 0xffffffff; +} + +static inline unsigned omap3_l3_decode_cmd(u64 error) +{ + return (error & 0x07) >> L3_ERROR_LOG_CMD; +} + +static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error) +{ + return (error & 0xff00) >> L3_ERROR_LOG_INITID; +} + +static inline unsigned omap3_l3_decode_req_info(u64 error) +{ + return (error >> 32) & 0xffff; +} + +static char *omap3_l3_code_string(u8 code) +{ + switch (code) { + case OMAP_L3_CODE_NOERROR: + return "No Error"; + case OMAP_L3_CODE_UNSUP_CMD: + return "Unsupported Command"; + case OMAP_L3_CODE_ADDR_HOLE: + return "Address Hole"; + case OMAP_L3_CODE_PROTECT_VIOLATION: + return "Protection Violation"; + case OMAP_L3_CODE_IN_BAND_ERR: + return "In-band Error"; + case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT: + return "Request Timeout Not Accepted"; + case OMAP_L3_CODE_REQ_TOUT_NO_RESP: + return "Request Timeout, no response"; + default: + return "UNKNOWN error"; + } +} + +static char *omap3_l3_initiator_string(u8 initid) +{ + switch (initid) { + case OMAP_L3_LCD: + return "LCD"; + case OMAP_L3_SAD2D: + return "SAD2D"; + case OMAP_L3_IA_MPU_SS_1: + case OMAP_L3_IA_MPU_SS_2: + case OMAP_L3_IA_MPU_SS_3: + case OMAP_L3_IA_MPU_SS_4: + case OMAP_L3_IA_MPU_SS_5: + return "MPU"; + case OMAP_L3_IA_IVA_SS_1: + case OMAP_L3_IA_IVA_SS_2: + case OMAP_L3_IA_IVA_SS_3: + return "IVA_SS"; + case OMAP_L3_IA_IVA_SS_DMA_1: + case OMAP_L3_IA_IVA_SS_DMA_2: + case OMAP_L3_IA_IVA_SS_DMA_3: + case OMAP_L3_IA_IVA_SS_DMA_4: + case OMAP_L3_IA_IVA_SS_DMA_5: + case OMAP_L3_IA_IVA_SS_DMA_6: + return "IVA_SS_DMA"; + case OMAP_L3_IA_SGX: + return "SGX"; + case OMAP_L3_IA_CAM_1: + case OMAP_L3_IA_CAM_2: + case OMAP_L3_IA_CAM_3: + return "CAM"; + case OMAP_L3_IA_DAP: + return "DAP"; + case OMAP_L3_SDMA_WR_1: + case OMAP_L3_SDMA_WR_2: + return "SDMA_WR"; + case OMAP_L3_SDMA_RD_1: + case OMAP_L3_SDMA_RD_2: + case OMAP_L3_SDMA_RD_3: + case OMAP_L3_SDMA_RD_4: + return "SDMA_RD"; + case OMAP_L3_USBOTG: + return "USB_OTG"; + case OMAP_L3_USBHOST: + return "USB_HOST"; + default: + return "UNKNOWN Initiator"; + } +} + +/** + * omap3_l3_block_irq - handles a register block's irq + * @l3: struct omap3_l3 * + * @base: register block base address + * @error: L3_ERROR_LOG register of our block + * + * Called in hard-irq context. Caller should take care of locking + * + * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error + * Analysis Sequence, we are following that sequence here, please + * refer to that Figure for more information on the subject. + */ +static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, + u64 error, int error_addr) +{ + u8 code = omap3_l3_decode_error_code(error); + u8 initid = omap3_l3_decode_initid(error); + u8 multi = error & L3_ERROR_LOG_MULTI; + u32 address = omap3_l3_decode_addr(error_addr); + + WARN(true, "%s Error seen by %s %s at address %x\n", + omap3_l3_code_string(code), + omap3_l3_initiator_string(initid), + multi ? "Multiple Errors" : "", + address); + + return IRQ_HANDLED; +} + +static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) +{ + struct omap3_l3 *l3 = _l3; + + u64 status, clear; + u64 error; + u64 error_addr; + u64 err_source = 0; + void __iomem *base; + int int_type; + + irqreturn_t ret = IRQ_NONE; + + if (irq == l3->app_irq) + int_type = L3_APPLICATION_ERROR; + else + int_type = L3_DEBUG_ERROR; + + if (!int_type) { + status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); + /* + * if we have a timeout error, there's nothing we can + * do besides rebooting the board. So let's BUG on any + * of such errors and handle the others. timeout error + * is severe and not expected to occur. + */ + BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK); + } else { + status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1); + /* No timeout error for debug sources */ + } + + base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source))); + + /* identify the error source */ + for (err_source = 0; !(status & (1 << err_source)); err_source++) + ; + error = omap3_l3_readll(base, L3_ERROR_LOG); + + if (error) { + error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); + + ret |= omap3_l3_block_irq(l3, error, error_addr); + } + + /* Clear the status register */ + clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) | + (L3_AGENT_STATUS_CLEAR_TA)); + + omap3_l3_writell(base, L3_AGENT_STATUS, clear); + + /* clear the error log register */ + omap3_l3_writell(base, L3_ERROR_LOG, error); + + return ret; +} + +static int __init omap3_l3_probe(struct platform_device *pdev) +{ + struct omap3_l3 *l3; + struct resource *res; + int ret; + int irq; + + l3 = kzalloc(sizeof(*l3), GFP_KERNEL); + if (!l3) { + ret = -ENOMEM; + goto err0; + } + + platform_set_drvdata(pdev, l3); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource\n"); + ret = -ENODEV; + goto err1; + } + l3->rt = ioremap(res->start, resource_size(res)); + if (!(l3->rt)) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err2; + } + + irq = platform_get_irq(pdev, 0); + ret = request_irq(irq, omap3_l3_app_irq, + IRQF_DISABLED | IRQF_TRIGGER_RISING, + "l3-debug-irq", l3); + if (ret) { + dev_err(&pdev->dev, "couldn't request debug irq\n"); + goto err3; + } + l3->debug_irq = irq; + + irq = platform_get_irq(pdev, 1); + ret = request_irq(irq, omap3_l3_app_irq, + IRQF_DISABLED | IRQF_TRIGGER_RISING, + "l3-app-irq", l3); + + if (ret) { + dev_err(&pdev->dev, "couldn't request app irq\n"); + goto err4; + } + + l3->app_irq = irq; + goto err0; + +err4: +err3: + iounmap(l3->rt); +err2: +err1: + kfree(l3); +err0: + return ret; +} + +static int __exit omap3_l3_remove(struct platform_device *pdev) +{ + struct omap3_l3 *l3 = platform_get_drvdata(pdev); + + free_irq(l3->app_irq, l3); + free_irq(l3->debug_irq, l3); + iounmap(l3->rt); + kfree(l3); + + return 0; +} + +static struct platform_driver omap3_l3_driver = { + .remove = __exit_p(omap3_l3_remove), + .driver = { + .name = "omap_l3_smx", + }, +}; + +static int __init omap3_l3_init(void) +{ + return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe); +} +postcore_initcall_sync(omap3_l3_init); + +static void __exit omap3_l3_exit(void) +{ + platform_driver_unregister(&omap3_l3_driver); +} +module_exit(omap3_l3_exit); diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h new file mode 100644 index 00000000000..ba2ed9a850c --- /dev/null +++ b/arch/arm/mach-omap2/omap_l3_smx.h @@ -0,0 +1,338 @@ + /* + * OMAP3XXX L3 Interconnect Driver header + * + * Copyright (C) 2011 Texas Corporation + * Felipe Balbi + * Santosh Shilimkar + * sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H +#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H + +/* Register definitions. All 64-bit wide */ +#define L3_COMPONENT 0x000 +#define L3_CORE 0x018 +#define L3_AGENT_CONTROL 0x020 +#define L3_AGENT_STATUS 0x028 +#define L3_ERROR_LOG 0x058 + +#define L3_ERROR_LOG_MULTI (1 << 31) +#define L3_ERROR_LOG_SECONDARY (1 << 30) + +#define L3_ERROR_LOG_ADDR 0x060 + +/* Register definitions for Sideband Interconnect */ +#define L3_SI_CONTROL 0x020 +#define L3_SI_FLAG_STATUS_0 0x510 + +const u64 shift = 1; + +#define L3_STATUS_0_MPUIA_BRST (shift << 0) +#define L3_STATUS_0_MPUIA_RSP (shift << 1) +#define L3_STATUS_0_MPUIA_INBAND (shift << 2) +#define L3_STATUS_0_IVAIA_BRST (shift << 6) +#define L3_STATUS_0_IVAIA_RSP (shift << 7) +#define L3_STATUS_0_IVAIA_INBAND (shift << 8) +#define L3_STATUS_0_SGXIA_BRST (shift << 9) +#define L3_STATUS_0_SGXIA_RSP (shift << 10) +#define L3_STATUS_0_SGXIA_MERROR (shift << 11) +#define L3_STATUS_0_CAMIA_BRST (shift << 12) +#define L3_STATUS_0_CAMIA_RSP (shift << 13) +#define L3_STATUS_0_CAMIA_INBAND (shift << 14) +#define L3_STATUS_0_DISPIA_BRST (shift << 15) +#define L3_STATUS_0_DISPIA_RSP (shift << 16) +#define L3_STATUS_0_DMARDIA_BRST (shift << 18) +#define L3_STATUS_0_DMARDIA_RSP (shift << 19) +#define L3_STATUS_0_DMAWRIA_BRST (shift << 21) +#define L3_STATUS_0_DMAWRIA_RSP (shift << 22) +#define L3_STATUS_0_USBOTGIA_BRST (shift << 24) +#define L3_STATUS_0_USBOTGIA_RSP (shift << 25) +#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26) +#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27) +#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28) +#define L3_STATUS_0_SMSTA_REQ (shift << 48) +#define L3_STATUS_0_GPMCTA_REQ (shift << 49) +#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50) +#define L3_STATUS_0_OCMROMTA_REQ (shift << 51) +#define L3_STATUS_0_IVATA_REQ (shift << 54) +#define L3_STATUS_0_SGXTA_REQ (shift << 55) +#define L3_STATUS_0_SGXTA_SERROR (shift << 56) +#define L3_STATUS_0_GPMCTA_SERROR (shift << 57) +#define L3_STATUS_0_L4CORETA_REQ (shift << 58) +#define L3_STATUS_0_L4PERTA_REQ (shift << 59) +#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) +#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) + +#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ + | L3_STATUS_0_MPUIA_RSP \ + | L3_STATUS_0_IVAIA_BRST \ + | L3_STATUS_0_IVAIA_RSP \ + | L3_STATUS_0_SGXIA_BRST \ + | L3_STATUS_0_SGXIA_RSP \ + | L3_STATUS_0_CAMIA_BRST \ + | L3_STATUS_0_CAMIA_RSP \ + | L3_STATUS_0_DISPIA_BRST \ + | L3_STATUS_0_DISPIA_RSP \ + | L3_STATUS_0_DMARDIA_BRST \ + | L3_STATUS_0_DMARDIA_RSP \ + | L3_STATUS_0_DMAWRIA_BRST \ + | L3_STATUS_0_DMAWRIA_RSP \ + | L3_STATUS_0_USBOTGIA_BRST \ + | L3_STATUS_0_USBOTGIA_RSP \ + | L3_STATUS_0_USBHOSTIA_BRST \ + | L3_STATUS_0_SMSTA_REQ \ + | L3_STATUS_0_GPMCTA_REQ \ + | L3_STATUS_0_OCMRAMTA_REQ \ + | L3_STATUS_0_OCMROMTA_REQ \ + | L3_STATUS_0_IVATA_REQ \ + | L3_STATUS_0_SGXTA_REQ \ + | L3_STATUS_0_L4CORETA_REQ \ + | L3_STATUS_0_L4PERTA_REQ \ + | L3_STATUS_0_L4EMUTA_REQ \ + | L3_STATUS_0_MAD2DTA_REQ) + +#define L3_SI_FLAG_STATUS_1 0x530 + +#define L3_STATUS_1_MPU_DATAIA (1 << 0) +#define L3_STATUS_1_DAPIA0 (1 << 3) +#define L3_STATUS_1_DAPIA1 (1 << 4) +#define L3_STATUS_1_IVAIA (1 << 6) + +#define L3_PM_ERROR_LOG 0x020 +#define L3_PM_CONTROL 0x028 +#define L3_PM_ERROR_CLEAR_SINGLE 0x030 +#define L3_PM_ERROR_CLEAR_MULTI 0x038 +#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n)) +#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n)) +#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n)) +#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n)) + +/* L3 error log bit fields. Common for IA and TA */ +#define L3_ERROR_LOG_CODE 24 +#define L3_ERROR_LOG_INITID 8 +#define L3_ERROR_LOG_CMD 0 + +/* L3 agent status bit fields. */ +#define L3_AGENT_STATUS_CLEAR_IA 0x10000000 +#define L3_AGENT_STATUS_CLEAR_TA 0x01000000 + +#define OMAP34xx_IRQ_L3_APP 10 +#define L3_APPLICATION_ERROR 0x0 +#define L3_DEBUG_ERROR 0x1 + +enum omap3_l3_initiator_id { + /* LCD has 1 ID */ + OMAP_L3_LCD = 29, + /* SAD2D has 1 ID */ + OMAP_L3_SAD2D = 28, + /* MPU has 5 IDs */ + OMAP_L3_IA_MPU_SS_1 = 27, + OMAP_L3_IA_MPU_SS_2 = 26, + OMAP_L3_IA_MPU_SS_3 = 25, + OMAP_L3_IA_MPU_SS_4 = 24, + OMAP_L3_IA_MPU_SS_5 = 23, + /* IVA2.2 SS has 3 IDs*/ + OMAP_L3_IA_IVA_SS_1 = 22, + OMAP_L3_IA_IVA_SS_2 = 21, + OMAP_L3_IA_IVA_SS_3 = 20, + /* IVA 2.2 SS DMA has 6 IDS */ + OMAP_L3_IA_IVA_SS_DMA_1 = 19, + OMAP_L3_IA_IVA_SS_DMA_2 = 18, + OMAP_L3_IA_IVA_SS_DMA_3 = 17, + OMAP_L3_IA_IVA_SS_DMA_4 = 16, + OMAP_L3_IA_IVA_SS_DMA_5 = 15, + OMAP_L3_IA_IVA_SS_DMA_6 = 14, + /* SGX has 1 ID */ + OMAP_L3_IA_SGX = 13, + /* CAM has 3 ID */ + OMAP_L3_IA_CAM_1 = 12, + OMAP_L3_IA_CAM_2 = 11, + OMAP_L3_IA_CAM_3 = 10, + /* DAP has 1 ID */ + OMAP_L3_IA_DAP = 9, + /* SDMA WR has 2 IDs */ + OMAP_L3_SDMA_WR_1 = 8, + OMAP_L3_SDMA_WR_2 = 7, + /* SDMA RD has 4 IDs */ + OMAP_L3_SDMA_RD_1 = 6, + OMAP_L3_SDMA_RD_2 = 5, + OMAP_L3_SDMA_RD_3 = 4, + OMAP_L3_SDMA_RD_4 = 3, + /* HSUSB OTG has 1 ID */ + OMAP_L3_USBOTG = 2, + /* HSUSB HOST has 1 ID */ + OMAP_L3_USBHOST = 1, +}; + +enum omap3_l3_code { + OMAP_L3_CODE_NOERROR = 0, + OMAP_L3_CODE_UNSUP_CMD = 1, + OMAP_L3_CODE_ADDR_HOLE = 2, + OMAP_L3_CODE_PROTECT_VIOLATION = 3, + OMAP_L3_CODE_IN_BAND_ERR = 4, + /* codes 5 and 6 are reserved */ + OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7, + OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8, + /* codes 9 - 15 are also reserved */ +}; + +struct omap3_l3 { + struct device *dev; + struct clk *ick; + + /* memory base*/ + void __iomem *rt; + + int debug_irq; + int app_irq; + + /* true when and inband functional error occurs */ + unsigned inband:1; +}; + +/* offsets for l3 agents in order with the Flag status register */ +unsigned int __iomem omap3_l3_app_bases[] = { + /* MPU IA */ + 0x1400, + 0x1400, + 0x1400, + /* RESERVED */ + 0, + 0, + 0, + /* IVA 2.2 IA */ + 0x1800, + 0x1800, + 0x1800, + /* SGX IA */ + 0x1c00, + 0x1c00, + /* RESERVED */ + 0, + /* CAMERA IA */ + 0x5800, + 0x5800, + 0x5800, + /* DISPLAY IA */ + 0x5400, + 0x5400, + /* RESERVED */ + 0, + /*SDMA RD IA */ + 0x4c00, + 0x4c00, + /* RESERVED */ + 0, + /* SDMA WR IA */ + 0x5000, + 0x5000, + /* RESERVED */ + 0, + /* USB OTG IA */ + 0x4400, + 0x4400, + 0x4400, + /* USB HOST IA */ + 0x4000, + 0x4000, + /* RESERVED */ + 0, + 0, + 0, + 0, + /* SAD2D IA */ + 0x3000, + 0x3000, + 0x3000, + /* RESERVED */ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + /* SMA TA */ + 0x2000, + /* GPMC TA */ + 0x2400, + /* OCM RAM TA */ + 0x2800, + /* OCM ROM TA */ + 0x2C00, + /* L4 CORE TA */ + 0x6800, + /* L4 PER TA */ + 0x6c00, + /* IVA 2.2 TA */ + 0x6000, + /* SGX TA */ + 0x6400, + /* L4 EMU TA */ + 0x7000, + /* GPMC TA */ + 0x2400, + /* L4 CORE TA */ + 0x6800, + /* L4 PER TA */ + 0x6c00, + /* L4 EMU TA */ + 0x7000, + /* MAD2D TA */ + 0x3400, + /* RESERVED */ + 0, + 0, +}; + +unsigned int __iomem omap3_l3_debug_bases[] = { + /* MPU DATA IA */ + 0x1400, + /* RESERVED */ + 0, + 0, + /* DAP IA */ + 0x5c00, + 0x5c00, + /* RESERVED */ + 0, + /* IVA 2.2 IA */ + 0x1800, + /* REST RESERVED */ +}; + +u32 *omap3_l3_bases[] = { + omap3_l3_app_bases, + omap3_l3_debug_bases, +}; + +/* + * REVISIT define __raw_readll/__raw_writell here, but move them to + * at some point + */ +#define __raw_writell(v, a) (__chk_io_ptr(a), \ + *(volatile u64 __force *)(a) = (v)) +#define __raw_readll(a) (__chk_io_ptr(a), \ + *(volatile u64 __force *)(a)) + +#endif -- cgit v1.2.3-70-g09d2 From c464523488063f240652c445fcae2ca8a0eb2647 Mon Sep 17 00:00:00 2001 From: sricharan Date: Mon, 7 Feb 2011 21:12:11 +0530 Subject: OMAP4: hwmod_data: Add address space and irq in L3 hwmod. Add the address spaces, irqs of the l3 interconnect to the hwmod data. The hwmod change is aligned with Benoit Cousson. Signed-off-by: Santosh Shilimkar Signed-off-by: sricharan Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7b72316781d..3e88dd3f8ef 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -264,11 +264,27 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L3 target configuration and error log registers */ +static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = { + { .irq = 9 + OMAP44XX_IRQ_GIC_START }, + { .irq = 10 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { + { + .pa_start = 0x44000000, + .pa_end = 0x44000fff, + .flags = ADDR_TYPE_RT, + }, +}; + /* mpu -> l3_main_1 */ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { .master = &omap44xx_mpu_hwmod, .slave = &omap44xx_l3_main_1_hwmod, .clk = "l3_div_ck", + .addr = omap44xx_l3_main_1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -286,6 +302,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { static struct omap_hwmod omap44xx_l3_main_1_hwmod = { .name = "l3_main_1", .class = &omap44xx_l3_hwmod_class, + .mpu_irqs = omap44xx_l3_targ_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs), .slaves = omap44xx_l3_main_1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), @@ -332,11 +350,21 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { + { + .pa_start = 0x44800000, + .pa_end = 0x44801fff, + .flags = ADDR_TYPE_RT, + }, +}; + /* l3_main_1 -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { .master = &omap44xx_l3_main_1_hwmod, .slave = &omap44xx_l3_main_2_hwmod, .clk = "l3_div_ck", + .addr = omap44xx_l3_main_2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -377,11 +405,21 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = { }; /* l3_main_3 interface data */ +static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { + { + .pa_start = 0x45000000, + .pa_end = 0x45000fff, + .flags = ADDR_TYPE_RT, + }, +}; + /* l3_main_1 -> l3_main_3 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { .master = &omap44xx_l3_main_1_hwmod, .slave = &omap44xx_l3_main_3_hwmod, .clk = "l3_div_ck", + .addr = omap44xx_l3_main_3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, }; -- cgit v1.2.3-70-g09d2 From a4dc616ae321b5007fba0700fbd39ef13ced750b Mon Sep 17 00:00:00 2001 From: sricharan Date: Wed, 9 Mar 2011 16:00:29 +0530 Subject: OMAP4: Initialise the l3 device with the hwmod data. The l3 interconnect device is build with all the data required to handle the error logging. The data is extracted from the hwmod data base. Signed-off-by: Santosh Shilimkar Signed-off-by: sricharan Acked-by: Benoit Cousson --- arch/arm/mach-omap2/devices.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 6a320b61631..0d2d6a9c303 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -37,6 +37,7 @@ #include "control.h" #define L3_MODULES_MAX_LEN 12 +#define L3_MODULES 3 static int __init omap3_l3_init(void) { @@ -68,6 +69,37 @@ static int __init omap3_l3_init(void) } postcore_initcall(omap3_l3_init); +static int __init omap4_l3_init(void) +{ + int l, i; + struct omap_hwmod *oh[3]; + struct omap_device *od; + char oh_name[L3_MODULES_MAX_LEN]; + + /* + * To avoid code running on other OMAPs in + * multi-omap builds + */ + if (!(cpu_is_omap44xx())) + return -ENODEV; + + for (i = 0; i < L3_MODULES; i++) { + l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); + + oh[i] = omap_hwmod_lookup(oh_name); + if (!(oh[i])) + pr_err("could not look up %s\n", oh_name); + } + + od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, + 0, NULL, 0, 0); + + WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); + + return PTR_ERR(od); +} +postcore_initcall(omap4_l3_init); + #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) static struct resource cam_resources[] = { -- cgit v1.2.3-70-g09d2 From 2722e56de60390969cf118933842b3f2f3c8d6b8 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 7 Mar 2011 20:53:10 +0530 Subject: OMAP4: l3: Introduce l3-interconnect error handling driver The driver provides the information regarding the ocp errors that gets logged in the interconnect. The error information gives the detail regarding the target that was attempted to be accessed and its corresponding address. Signed-off-by: sricharan Signed-off-by: Santosh Shilimkar Acked-by: Benoit Cousson --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/omap_l3_noc.c | 253 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/omap_l3_noc.h | 132 ++++++++++++++++++++ 3 files changed, 386 insertions(+) create mode 100644 arch/arm/mach-omap2/omap_l3_noc.c create mode 100644 arch/arm/mach-omap2/omap_l3_noc.h (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index e4c9bb3ad89..8ef8711eac9 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -137,6 +137,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o # L3 interconnect obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o +obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c new file mode 100644 index 00000000000..82632c24076 --- /dev/null +++ b/arch/arm/mach-omap2/omap_l3_noc.c @@ -0,0 +1,253 @@ +/* + * OMAP4XXX L3 Interconnect error handling driver + * + * Copyright (C) 2011 Texas Corporation + * Santosh Shilimkar + * Sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +#include +#include +#include +#include +#include +#include + +#include "omap_l3_noc.h" + +/* + * Interrupt Handler for L3 error detection. + * 1) Identify the L3 clockdomain partition to which the error belongs to. + * 2) Identify the slave where the error information is logged + * 3) Print the logged information. + * 4) Add dump stack to provide kernel trace. + * + * Two Types of errors : + * 1) Custom errors in L3 : + * Target like DMM/FW/EMIF generates SRESP=ERR error + * 2) Standard L3 error: + * - Unsupported CMD. + * L3 tries to access target while it is idle + * - OCP disconnect. + * - Address hole error: + * If DSS/ISS/FDIF/USBHOSTFS access a target where they + * do not have connectivity, the error is logged in + * their default target which is DMM2. + * + * On High Secure devices, firewall errors are possible and those + * can be trapped as well. But the trapping is implemented as part + * secure software and hence need not be implemented here. + */ +static irqreturn_t l3_interrupt_handler(int irq, void *_l3) +{ + + struct omap4_l3 *l3 = _l3; + int inttype, i, j; + int err_src = 0; + u32 std_err_main_addr, std_err_main, err_reg; + u32 base, slave_addr, clear; + char *source_name; + + /* Get the Type of interrupt */ + if (irq == l3->app_irq) + inttype = L3_APPLICATION_ERROR; + else + inttype = L3_DEBUG_ERROR; + + for (i = 0; i < L3_MODULES; i++) { + /* + * Read the regerr register of the clock domain + * to determine the source + */ + base = (u32)l3->l3_base[i]; + err_reg = readl(base + l3_flagmux[i] + (inttype << 3)); + + /* Get the corresponding error and analyse */ + if (err_reg) { + /* Identify the source from control status register */ + for (j = 0; !(err_reg & (1 << j)); j++) + ; + + err_src = j; + /* Read the stderrlog_main_source from clk domain */ + std_err_main_addr = base + (*(l3_targ[i] + err_src)); + std_err_main = readl(std_err_main_addr); + + switch ((std_err_main & CUSTOM_ERROR)) { + case STANDARD_ERROR: + source_name = + l3_targ_stderrlog_main_name[i][err_src]; + + slave_addr = std_err_main_addr + + L3_SLAVE_ADDRESS_OFFSET; + WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", + source_name, readl(slave_addr)); + /* clear the std error log*/ + clear = std_err_main | CLEAR_STDERR_LOG; + writel(clear, std_err_main_addr); + break; + + case CUSTOM_ERROR: + source_name = + l3_targ_stderrlog_main_name[i][err_src]; + + WARN(true, "CUSTOM SRESP error with SOURCE:%s\n", + source_name); + /* clear the std error log*/ + clear = std_err_main | CLEAR_STDERR_LOG; + writel(clear, std_err_main_addr); + break; + + default: + /* Nothing to be handled here as of now */ + break; + } + /* Error found so break the for loop */ + break; + } + } + return IRQ_HANDLED; +} + +static int __init omap4_l3_probe(struct platform_device *pdev) +{ + static struct omap4_l3 *l3; + struct resource *res; + int ret; + int irq; + + l3 = kzalloc(sizeof(*l3), GFP_KERNEL); + if (!l3) + ret = -ENOMEM; + + platform_set_drvdata(pdev, l3); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource 0\n"); + ret = -ENODEV; + goto err1; + } + + l3->l3_base[0] = ioremap(res->start, resource_size(res)); + if (!(l3->l3_base[0])) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err2; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource 1\n"); + ret = -ENODEV; + goto err3; + } + + l3->l3_base[1] = ioremap(res->start, resource_size(res)); + if (!(l3->l3_base[1])) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err4; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource 2\n"); + ret = -ENODEV; + goto err5; + } + + l3->l3_base[2] = ioremap(res->start, resource_size(res)); + if (!(l3->l3_base[2])) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err6; + } + + /* + * Setup interrupt Handlers + */ + irq = platform_get_irq(pdev, 0); + ret = request_irq(irq, + l3_interrupt_handler, + IRQF_DISABLED, "l3-dbg-irq", l3); + if (ret) { + pr_crit("L3: request_irq failed to register for 0x%x\n", + OMAP44XX_IRQ_L3_DBG); + goto err7; + } + l3->debug_irq = irq; + + irq = platform_get_irq(pdev, 1); + ret = request_irq(irq, + l3_interrupt_handler, + IRQF_DISABLED, "l3-app-irq", l3); + if (ret) { + pr_crit("L3: request_irq failed to register for 0x%x\n", + OMAP44XX_IRQ_L3_APP); + goto err8; + } + l3->app_irq = irq; + + goto err0; +err8: +err7: + iounmap(l3->l3_base[2]); +err6: +err5: + iounmap(l3->l3_base[1]); +err4: +err3: + iounmap(l3->l3_base[0]); +err2: +err1: + kfree(l3); +err0: + return ret; +} + +static int __exit omap4_l3_remove(struct platform_device *pdev) +{ + struct omap4_l3 *l3 = platform_get_drvdata(pdev); + + free_irq(l3->app_irq, l3); + free_irq(l3->debug_irq, l3); + iounmap(l3->l3_base[0]); + iounmap(l3->l3_base[1]); + iounmap(l3->l3_base[2]); + kfree(l3); + + return 0; +} + +static struct platform_driver omap4_l3_driver = { + .remove = __exit_p(omap4_l3_remove), + .driver = { + .name = "omap_l3_noc", + }, +}; + +static int __init omap4_l3_init(void) +{ + return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe); +} +postcore_initcall_sync(omap4_l3_init); + +static void __exit omap4_l3_exit(void) +{ + platform_driver_unregister(&omap4_l3_driver); +} +module_exit(omap4_l3_exit); diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h new file mode 100644 index 00000000000..359b83348ae --- /dev/null +++ b/arch/arm/mach-omap2/omap_l3_noc.h @@ -0,0 +1,132 @@ + /* + * OMAP4XXX L3 Interconnect error handling driver header + * + * Copyright (C) 2011 Texas Corporation + * Santosh Shilimkar + * sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H +#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H + +/* + * L3 register offsets + */ +#define L3_MODULES 3 +#define CLEAR_STDERR_LOG (1 << 31) +#define CUSTOM_ERROR 0x2 +#define STANDARD_ERROR 0x0 +#define INBAND_ERROR 0x0 +#define EMIF_KERRLOG_OFFSET 0x10 +#define L3_SLAVE_ADDRESS_OFFSET 0x14 +#define LOGICAL_ADDR_ERRORLOG 0x4 +#define L3_APPLICATION_ERROR 0x0 +#define L3_DEBUG_ERROR 0x1 + +u32 l3_flagmux[L3_MODULES] = { + 0x50C, + 0x100C, + 0X020C +}; + +/* + * L3 Target standard Error register offsets + */ +u32 l3_targ_stderrlog_main_clk1[] = { + 0x148, /* DMM1 */ + 0x248, /* DMM2 */ + 0x348, /* ABE */ + 0x448, /* L4CFG */ + 0x648 /* CLK2 PWR DISC */ +}; + +u32 l3_targ_stderrlog_main_clk2[] = { + 0x548, /* CORTEX M3 */ + 0x348, /* DSS */ + 0x148, /* GPMC */ + 0x448, /* ISS */ + 0x748, /* IVAHD */ + 0xD48, /* missing in TRM corresponds to AES1*/ + 0x948, /* L4 PER0*/ + 0x248, /* OCMRAM */ + 0x148, /* missing in TRM corresponds to GPMC sERROR*/ + 0x648, /* SGX */ + 0x848, /* SL2 */ + 0x1648, /* C2C */ + 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ + 0xF48, /* missing in TRM corrsponds to SHA1*/ + 0xE48, /* missing in TRM corresponds to AES2*/ + 0xC48, /* L4 PER3 */ + 0xA48, /* L4 PER1*/ + 0xB48 /* L4 PER2*/ +}; + +u32 l3_targ_stderrlog_main_clk3[] = { + 0x0148 /* EMUSS */ +}; + +char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { + { + "DMM1", + "DMM2", + "ABE", + "L4CFG", + "CLK2 PWR DISC", + }, + { + "CORTEX M3" , + "DSS ", + "GPMC ", + "ISS ", + "IVAHD ", + "AES1", + "L4 PER0", + "OCMRAM ", + "GPMC sERROR", + "SGX ", + "SL2 ", + "C2C ", + "PWR DISC CLK1", + "SHA1", + "AES2", + "L4 PER3", + "L4 PER1", + "L4 PER2", + }, + { + "EMUSS", + }, +}; + +u32 *l3_targ[L3_MODULES] = { + l3_targ_stderrlog_main_clk1, + l3_targ_stderrlog_main_clk2, + l3_targ_stderrlog_main_clk3, +}; + +struct omap4_l3 { + struct device *dev; + struct clk *ick; + + /* memory base */ + void __iomem *l3_base[4]; + + int debug_irq; + int app_irq; +}; + +#endif -- cgit v1.2.3-70-g09d2 From c39bee8ac4aca750c85609ba0847599b36feb693 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 4 Mar 2011 06:02:15 +0000 Subject: OMAP2/3: VENC hwmod: add OCPIF_SWSUP_IDLE flag to interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the hwmod interface data, the DSS submodule "VENC" uses a clock, "dss_54m_fck"/"dss_tv_fck", which the PRCM cannot autoidle. By default, the hwmod code assumes that interface clocks can be autoidled by the PRCM. When the interface clock can't be autoidled by the PRCM, those interfaces must be marked with the OCPIF_SWSUP_IDLE flag. Otherwise, the "interface clock" will always have a non-zero use count, and the device won't enter idle. This problem was observed on N8x0. Fix the immediate problem by marking the VENC interface with the OCPIF_SWSUP_IDLE flag. But it's not clear that "dss_54m_fck"/"dss_tv_fck" is really the correct interface clock for VENC. It may be that the VENC interface should use a hardware-autoidling interface clock. This is the situation on OMAP4, which uses "l3_div_ck" as the VENC interface clock, which can be autoidled by the PRCM. Clarification from TI is needed. Problem found and patch tested on N8x0 by Tony Lindgren . Signed-off-by: Paul Walmsley Cc: Tony Lindgren Cc: Senthilvadivu Guruswamy Cc: Sumit Semwal Cc: Kevin Hilman Cc: Benoît Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 + arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index e0bc2c7a15d..61e58bd27ae 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1410,6 +1410,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { .flags = OMAP_FIREWALL_L4, } }, + .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4aa74d78289..490789a6bed 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1485,6 +1485,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { .clk = "dss_54m_fck", .addr = omap2430_dss_venc_addrs, .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), + .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e2792cf9c54..eb48b8c7723 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1844,6 +1844,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { .flags = OMAP_FIREWALL_L4, } }, + .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; -- cgit v1.2.3-70-g09d2 From b481cea34bb41f3731567c8c1be0625bf80d20b7 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 9 Mar 2011 18:44:28 -0700 Subject: OMAP: clock: fix compile warning if building kernels without OMAP2 support, we will see a warning such as: arch/arm/mach-omap2/io.c: In function 'omap2_init_common_infrastructure': arch/arm/mach-omap2/io.c:389:3: warning: statement with no effect arch/arm/mach-omap2/io.c:391:3: warning: statement with no effect Signed-off-by: Felipe Balbi Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2xxx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index cc5c8d422c5..cb6df8ca9e4 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -23,13 +23,13 @@ void omap2xxx_clk_prepare_for_reboot(void); #ifdef CONFIG_SOC_OMAP2420 int omap2420_clk_init(void); #else -#define omap2420_clk_init() 0 +#define omap2420_clk_init() do { } while(0) #endif #ifdef CONFIG_SOC_OMAP2430 int omap2430_clk_init(void); #else -#define omap2430_clk_init() 0 +#define omap2430_clk_init() do { } while(0) #endif extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; -- cgit v1.2.3-70-g09d2 From b9ccf8afe2d2eafe18f90d2925f8464313fe0b56 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Thu, 10 Mar 2011 10:53:15 +0100 Subject: OMAP3: hwmod data: Fix incorrect SmartReflex -> L4 CORE interconnect links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit d34427267186827dfd62bd8cf726601fffb22534 ("OMAP3: PM: Adding smartreflex hwmod data") added data that claims that the L4 CORE has two slave interfaces that originate from the SmartReflex modules, omap3_l4_core__sr1 and omap3_l4_core__sr2. But as those two data structure records show, it's L4 CORE that has a master port towards SR1 and SR2. Move the incorrect data from slaves list to master list. Based on a path by Paul Walmsley https://patchwork.kernel.org/patch/623171/ That is based on a patch by Benoît Cousson : https://patchwork.kernel.org/patch/590561/ Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson Cc: Sanjeev Premi Cc: Thara Gopinath --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c4ca005f8bb..dec329ff092 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -491,8 +491,6 @@ static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, - &omap3_l4_core__sr1, - &omap3_l4_core__sr2, }; /* Master interfaces on the L4_CORE interconnect */ @@ -503,6 +501,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3_l4_core__i2c1, &omap3_l4_core__i2c2, &omap3_l4_core__i2c3, + &omap3_l4_core__sr1, + &omap3_l4_core__sr2, }; /* L4 CORE */ -- cgit v1.2.3-70-g09d2 From 478f478bc1a58f97f09fd2048488bafdfa9d8fce Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Fri, 25 Feb 2011 17:46:33 +0100 Subject: OMAP3: hwmod data: Remove masters port links for interconnects. Master ports from interconnect are generating some annoying circular references that become tricky to handle if we have to dynamically remove some IP on some variant platforms. Since they are not used for the moment, and since we can still build that relation using the reverse relation (slave port from the IP toward master port of the interconnect), let remove them for the moment like it is done on OMAP4. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Sanjeev Premi --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index dec329ff092..229eb94d343 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -493,24 +493,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, }; -/* Master interfaces on the L4_CORE interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { - &omap3xxx_l4_core__l4_wkup, - &omap3_l4_core__uart1, - &omap3_l4_core__uart2, - &omap3_l4_core__i2c1, - &omap3_l4_core__i2c2, - &omap3_l4_core__i2c3, - &omap3_l4_core__sr1, - &omap3_l4_core__sr2, -}; - /* L4 CORE */ static struct omap_hwmod omap3xxx_l4_core_hwmod = { .name = "l4_core", .class = &l4_hwmod_class, - .masters = omap3xxx_l4_core_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), .slaves = omap3xxx_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), @@ -522,18 +508,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { &omap3xxx_l3_main__l4_per, }; -/* Master interfaces on the L4_PER interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { - &omap3_l4_per__uart3, - &omap3_l4_per__uart4, -}; - /* L4 PER */ static struct omap_hwmod omap3xxx_l4_per_hwmod = { .name = "l4_per", .class = &l4_hwmod_class, - .masters = omap3xxx_l4_per_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), .slaves = omap3xxx_l4_per_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), @@ -545,16 +523,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { &omap3xxx_l4_core__l4_wkup, }; -/* Master interfaces on the L4_WKUP interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { -}; - /* L4 WKUP */ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { .name = "l4_wkup", .class = &l4_hwmod_class, - .masters = omap3xxx_l4_wkup_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), .slaves = omap3xxx_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -- cgit v1.2.3-70-g09d2 From 43b01643355672a266b95c4719f47cd1abac4680 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 10 Mar 2011 03:50:07 -0700 Subject: OMAP2+: hwmod: allow board files to prevent devices from being reset upon init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some boards can't tolerate IP blocks being reset when they are initialized. Michael Büsch cites a case with the Nokia N810: http://www.spinics.net/lists/linux-omap/msg47277.html To allow such boards to continue working normally, allow board file maintainers to mark IP blocks to prevent them from being reset upon init. This is done via a hwmod function, omap_hwmod_no_setup_reset(). Signed-off-by: Paul Walmsley Cc: Michael Buesch --- arch/arm/mach-omap2/omap_hwmod.c | 26 ++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 ++ 2 files changed, 28 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e282e35769f..816aeb97ba2 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2218,3 +2218,29 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) return ret; } + +/** + * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup + * @oh: struct omap_hwmod * + * + * Prevent the hwmod @oh from being reset during the setup process. + * Intended for use by board-*.c files on boards with devices that + * cannot tolerate being reset. Must be called before the hwmod has + * been set up. Returns 0 upon success or negative error code upon + * failure. + */ +int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + if (oh->_state != _HWMOD_STATE_REGISTERED) { + pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", + oh->name); + return -EINVAL; + } + + oh->flags |= HWMOD_INIT_NO_RESET; + + return 0; +} diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 1eee85a8abb..bba234337d0 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -589,6 +589,8 @@ int omap_hwmod_for_each_by_class(const char *classname, int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); +int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); + /* * Chip variant-specific hwmod init routines - XXX should be converted * to use initcalls once the initial boot ordering is straightened out -- cgit v1.2.3-70-g09d2 From 9599217a06da5f5a95794ca9192c14317d441187 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 10 Mar 2011 03:50:08 -0700 Subject: OMAP2+: hwmod: add API to handle autoidle mode Create a new API that forms a wrapper to _set_module_autoidle() to modify the AUTOIDLE bit. This API is intended to be used by drivers that requires direct manipulation of the AUTOIDLE bits in SYSCONFIG register. McBSP driver requires autoidle bit to be enabled/disabled while using sidetone feature. Signed-off-by: Kishon Vijay Abraham I Cc: Paul Walmsley Cc: Benoit Cousson [paul@pwsan.com: restrict the hwmod states that the autoidle bit can be changed in; changed function name; dropped "int" from "unsigned int long"] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 36 ++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 + 2 files changed, 37 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 816aeb97ba2..a68a2cf1be3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1287,6 +1287,42 @@ static int _idle(struct omap_hwmod *oh) return 0; } +/** + * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit + * @oh: struct omap_hwmod * + * @autoidle: desired AUTOIDLE bitfield value (0 or 1) + * + * Sets the IP block's OCP autoidle bit in hardware, and updates our + * local copy. Intended to be used by drivers that require + * direct manipulation of the AUTOIDLE bits. + * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes + * along the return value from _set_module_autoidle(). + * + * Any users of this function should be scrutinized carefully. + */ +int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) +{ + u32 v; + int retval = 0; + unsigned long flags; + + if (!oh || oh->_state != _HWMOD_STATE_ENABLED) + return -EINVAL; + + spin_lock_irqsave(&oh->_lock, flags); + + v = oh->_sysc_cache; + + retval = _set_module_autoidle(oh, autoidle, &v); + + if (!retval) + _write_sysconfig(v, oh); + + spin_unlock_irqrestore(&oh->_lock, flags); + + return retval; +} + /** * _shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index bba234337d0..98f7f618a91 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -555,6 +555,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); +int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle); int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); -- cgit v1.2.3-70-g09d2 From 570b54c7fae65b65320d5a7d4b2249c86eeaa497 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 10 Mar 2011 03:50:09 -0700 Subject: OMAP2+: clockdomain: add flag that will block autodeps from being added for a clockdomain Add a new clockdomain flag, CLKDM_NO_AUTODEPS, which, when marked on a clockdomain, will prevent "autodeps" from being associated with the clockdomain. ("Autodeps" are sleep dependencies and wakeup dependencies from/to processor modules that are automatically added to a clockdomain when it is in hardware-supervised idle mode. They are deprecated -- a relic from the old CDP trees -- but are still in use for OMAP3.) Also, prevent the hwmod code from adding or removing initiator dependencies for clockdomains with this flag set. This patch should allow others to test which clockdomains actually still need autodeps. Thanks to Kevin Hilman for noting that the original version should also modify the hwmod code. Signed-off-by: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/clockdomain.c | 4 ++-- arch/arm/mach-omap2/clockdomain.h | 12 ++++++++++-- arch/arm/mach-omap2/omap_hwmod.c | 16 ++++++++++++---- 3 files changed, 24 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 58e42f76603..2b4ab0beff4 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -181,7 +181,7 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) { struct clkdm_autodep *autodep; - if (!autodeps) + if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) return; for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { @@ -215,7 +215,7 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) { struct clkdm_autodep *autodep; - if (!autodeps) + if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) return; for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 9b459c26fb8..5add0716943 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -4,7 +4,7 @@ * OMAP2/3 clockdomain framework functions * * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008-2010 Nokia Corporation + * Copyright (C) 2008-2011 Nokia Corporation * * Paul Walmsley * @@ -22,11 +22,19 @@ #include #include -/* Clockdomain capability flags */ +/* + * Clockdomain flags + * + * XXX Document CLKDM_CAN_* flags + * + * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this + * clockdomain. (Currently, this applies to OMAP3 clockdomains only.) + */ #define CLKDM_CAN_FORCE_SLEEP (1 << 0) #define CLKDM_CAN_FORCE_WAKEUP (1 << 1) #define CLKDM_CAN_ENABLE_AUTO (1 << 2) #define CLKDM_CAN_DISABLE_AUTO (1 << 3) +#define CLKDM_NO_AUTODEPS (1 << 4) #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index a68a2cf1be3..2dd1ea9859b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -460,14 +460,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) * will be accessed by a particular initiator (e.g., if a module will * be accessed by the IVA, there should be a sleepdep between the IVA * initiator and the module). Only applies to modules in smart-idle - * mode. Returns -EINVAL upon error or passes along - * clkdm_add_sleepdep() value upon success. + * mode. If the clockdomain is marked as not needing autodeps, return + * 0 without doing anything. Otherwise, returns -EINVAL upon error or + * passes along clkdm_add_sleepdep() value upon success. */ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { if (!oh->_clk) return -EINVAL; + if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + return 0; + return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); } @@ -480,14 +484,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) * be accessed by a particular initiator (e.g., if a module will not * be accessed by the IVA, there should be no sleepdep between the IVA * initiator and the module). Only applies to modules in smart-idle - * mode. Returns -EINVAL upon error or passes along - * clkdm_del_sleepdep() value upon success. + * mode. If the clockdomain is marked as not needing autodeps, return + * 0 without doing anything. Returns -EINVAL upon error or passes + * along clkdm_del_sleepdep() value upon success. */ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { if (!oh->_clk) return -EINVAL; + if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + return 0; + return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); } -- cgit v1.2.3-70-g09d2 From 2f4dd595f6d60ec3ccbb68def73df457970cf671 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 10 Mar 2011 22:40:06 -0700 Subject: OMAP3: wdtimer: Fix CORE idle transition The HW superwised smart idle for wdtimer in OMAP3 prevents CORE power domain idle transitions. Disable it by swithing to SW supervised transitions. This could be a hardware bug in the OMAP3 wdtimer2 block. Signed-off-by: Kalle Jokiniemi Signed-off-by: Paul Walmsley Cc: Benoit Cousson Acked-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-omap2') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index c4ca005f8bb..477ba543b22 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1312,6 +1312,11 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { .slaves = omap3xxx_wd_timer2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + /* + * XXX: Use software supervised mode, HW supervised smartidle seems to + * block CORE power domain idle transitions. Maybe a HW bug in wdt2? + */ + .flags = HWMOD_SWSUP_SIDLE, }; /* UART common */ -- cgit v1.2.3-70-g09d2