From c085052bc52d7caaca1172aabbedc06777253961 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 29 Nov 2010 22:56:00 +0800 Subject: ARM: pxa: add clock for static memory controller Signed-off-by: Eric Miao --- arch/arm/mach-pxa/clock-pxa3xx.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-pxa/clock-pxa3xx.c') diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 25be4adf6f4..1b08a34ab23 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c @@ -9,7 +9,9 @@ #include #include #include +#include +#include #include #include "clock.h" @@ -23,9 +25,6 @@ #define ACCR_D0CS (1 << 26) #define ACCR_PCCE (1 << 11) -/* crystal frequency to static memory controller multiplier (SMCFS) */ -static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; - /* crystal frequency to HSIO bus frequency multiplier (HSS) */ static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; @@ -108,6 +107,20 @@ static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) return hsio_clk; } +/* crystal frequency to static memory controller multiplier (SMCFS) */ +static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; +static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 }; + +static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk) +{ + unsigned long acsr = ACSR; + unsigned long memclkcfg = __raw_readl(MEMCLKCFG); + unsigned int smcfs = (acsr >> 23) & 0x7; + + return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] / + df_clkdiv[(memclkcfg >> 16) & 0x3]; +} + void clk_pxa3xx_cken_enable(struct clk *clk) { unsigned long mask = 1ul << (clk->cken & 0x1f); @@ -145,6 +158,12 @@ const struct clkops clk_pxa3xx_ac97_ops = { .getrate = clk_pxa3xx_ac97_getrate, }; +const struct clkops clk_pxa3xx_smemc_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_smemc_getrate, +}; + static void clk_pout_enable(struct clk *clk) { OSCC |= OSCC_PEN; -- cgit v1.2.3-70-g09d2