From c9840daa70fbb8f6031fcd1f254a3da49a41ea7b Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Tue, 16 Mar 2010 16:48:01 +0800 Subject: [ARM] pxa: correct SSCR0_SCR to support multiple SoCs The previous definitions of SSCR0_SCR and SSCR0_SerClkDiv() prevented them being used simultaneously when supporting multiple PXA SoCs, esp. in drivers/spi/pxa2xx_spi.c, make them correct. The change from SSCR0_SerClkDiv(2) to SSCR0_SCR(2), will make the result a little bit different in pxa2xx_spi_probe(), however, since that's only used as a default initialization value, it's acceptable. Signed-off-by: Eric Miao --- arch/arm/mach-pxa/include/mach/regs-ssp.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'arch/arm/mach-pxa/include/mach') diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h index 6a2ed35acd5..dd15dc35a24 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ssp.h +++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h @@ -33,14 +33,7 @@ #define SSCR0_National (0x2 << 4) /* National Microwire */ #define SSCR0_ECS (1 << 6) /* External clock select */ #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ - -#if defined(CONFIG_PXA25x) -#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ -#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) -#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ -#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ -#endif +#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) #define SSCR0_EDSS (1 << 20) /* Extended data size select */ -- cgit v1.2.3-70-g09d2