From dd4153d9af67496f6545831e72c743060d33a830 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 22 Dec 2011 23:31:28 +0100 Subject: ARM: 7247/1: S5PC100: introduce arch/arm/mach-s5pc100/common.[ch] This patch introduces common.[ch] which are used only in the arch/arm/mach-s5pc100/ directory. The common.c file merges the cpu.c and init.c which are used commonly on S5PC100 SoC and the common.h local header file replaces with plat/s5pc100.h file. Cc: Ben Dooks Signed-off-by: Kukjin Kim Signed-off-by: Russell King --- arch/arm/mach-s5pc100/common.c | 223 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 223 insertions(+) create mode 100644 arch/arm/mach-s5pc100/common.c (limited to 'arch/arm/mach-s5pc100/common.c') diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c new file mode 100644 index 00000000000..e6eadacc108 --- /dev/null +++ b/arch/arm/mach-s5pc100/common.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min + * + * Common Codes for S5PC100 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" + +static const char name_s5pc100[] = "S5PC100"; + +static struct cpu_table cpu_ids[] __initdata = { + { + .idcode = S5PC100_CPU_ID, + .idmask = S5PC100_CPU_MASK, + .map_io = s5pc100_map_io, + .init_clocks = s5pc100_init_clocks, + .init_uarts = s5pc100_init_uarts, + .init = s5pc100_init, + .name = name_s5pc100, + }, +}; + +/* Initial IO mappings */ + +static struct map_desc s5pc100_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_CHIPID, + .pfn = __phys_to_pfn(S5PC100_PA_CHIPID), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_SYS, + .pfn = __phys_to_pfn(S5PC100_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_TIMER, + .pfn = __phys_to_pfn(S5PC100_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(S5PC100_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GPIO, + .pfn = __phys_to_pfn(S5PC100_PA_GPIO), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC0, + .pfn = __phys_to_pfn(S5PC100_PA_VIC0), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC1, + .pfn = __phys_to_pfn(S5PC100_PA_VIC1), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC2, + .pfn = __phys_to_pfn(S5PC100_PA_VIC2), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_UART, + .pfn = __phys_to_pfn(S3C_PA_UART), + .length = SZ_512K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5PC100_VA_OTHERS, + .pfn = __phys_to_pfn(S5PC100_PA_OTHERS), + .length = SZ_4K, + .type = MT_DEVICE, + } +}; + +static void s5pc100_idle(void) +{ + if (!need_resched()) + cpu_do_idle(); + + local_irq_enable(); +} + +/* + * s5pc100_map_io + * + * register the standard CPU IO areas + */ + +void __init s5pc100_init_io(struct map_desc *mach_desc, int size) +{ + /* initialize the io descriptors we need for initialization */ + iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); + if (mach_desc) + iotable_init(mach_desc, size); + + /* detect cpu id and rev. */ + s5p_init_cpu(S5P_VA_CHIPID); + + s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); +} + +void __init s5pc100_map_io(void) +{ + /* initialise device information early */ + s5pc100_default_sdhci0(); + s5pc100_default_sdhci1(); + s5pc100_default_sdhci2(); + + s3c_adc_setname("s3c64xx-adc"); + + /* the i2c devices are directly compatible with s3c2440 */ + s3c_i2c0_setname("s3c2440-i2c"); + s3c_i2c1_setname("s3c2440-i2c"); + + s3c_onenand_setname("s5pc100-onenand"); + s3c_fb_setname("s5pc100-fb"); + s3c_cfcon_setname("s5pc100-pata"); +} + +void __init s5pc100_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + s5pc100_register_clocks(); + s5pc100_setup_clocks(); +} + +void __init s5pc100_init_irq(void) +{ + u32 vic[] = {~0, ~0, ~0}; + + /* VIC0, VIC1, and VIC2 are fully populated. */ + s5p_init_irq(vic, ARRAY_SIZE(vic)); +} + +static struct sysdev_class s5pc100_sysclass = { + .name = "s5pc100-core", +}; + +static struct sys_device s5pc100_sysdev = { + .cls = &s5pc100_sysclass, +}; + +static int __init s5pc100_core_init(void) +{ + return sysdev_class_register(&s5pc100_sysclass); +} +core_initcall(s5pc100_core_init); + +int __init s5pc100_init(void) +{ + printk(KERN_INFO "S5PC100: Initializing architecture\n"); + + /* set idle function */ + pm_idle = s5pc100_idle; + + return sysdev_register(&s5pc100_sysdev); +} + +/* uart registration process */ + +void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); +} -- cgit v1.2.3-70-g09d2