From 02474a41e6180521a2b9b30b84888670e290dba0 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 9 Jun 2013 00:36:05 +0400 Subject: ARM: shmobile: r8a7778: add USB support Add USB clock and EHCI, OHCI, and USB PHY platform devices for R8A7778 SoC; add a function to register PHY device with board-specific platform data and register EHCI and OHCI platfrom devices from the init_late() board method. Also, don't forget to enable CONFIG_ARCH_HAS_[EO]HCI options for R8A7778 SoC in Kconfig... The patch has been tested on the BOCK-W board. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7778.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/mach-shmobile/clock-r8a7778.c') diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index b251e4d0924..696d206adc3 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -105,6 +105,7 @@ static struct clk *main_clks[] = { enum { MSTP323, MSTP322, MSTP321, MSTP114, + MSTP100, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, MSTP_NR }; @@ -114,6 +115,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ + [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */ @@ -130,6 +132,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ + CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ + CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ -- cgit v1.2.3-70-g09d2