From bc19d892a14cbb31d838813b2225e262a6c01341 Mon Sep 17 00:00:00 2001 From: dmitry pervushin Date: Wed, 22 Apr 2009 23:57:28 +0100 Subject: [ARM] 5464/1: Freescale STMP platform support [7/10] Sources: support for 378x boards Signed-off-by: dmitry pervushin Signed-off-by: Russell King --- arch/arm/mach-stmp378x/stmp378x.c | 225 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 225 insertions(+) create mode 100644 arch/arm/mach-stmp378x/stmp378x.c (limited to 'arch/arm/mach-stmp378x/stmp378x.c') diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c new file mode 100644 index 00000000000..f156ec7306c --- /dev/null +++ b/arch/arm/mach-stmp378x/stmp378x.c @@ -0,0 +1,225 @@ +/* + * Freescale STMP378X platform support + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmp378x.h" +/* + * IRQ handling + */ +static void stmp378x_ack_irq(unsigned int irq) +{ + /* Tell ICOLL to release IRQ line */ + HW_ICOLL_VECTOR_WR(0x0); + + /* ACK current interrupt */ + HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0); + + /* Barrier */ + (void) HW_ICOLL_STAT_RD(); +} + +static void stmp378x_mask_irq(unsigned int irq) +{ + /* IRQ disable */ + HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE); +} + +static void stmp378x_unmask_irq(unsigned int irq) +{ + /* IRQ enable */ + HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE); +} + +static struct irq_chip stmp378x_chip = { + .ack = stmp378x_ack_irq, + .mask = stmp378x_mask_irq, + .unmask = stmp378x_unmask_irq, +}; + +void __init stmp378x_init_irq(void) +{ + stmp3xxx_init_irq(&stmp378x_chip); +} + +/* + * DMA interrupt handling + */ +void stmp3xxx_arch_dma_enable_interrupt(int channel) +{ + int dmabus = channel / 16; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL1_SET(1 << (16 + (channel % 16))); + HW_APBH_CTRL2_SET(1 << (16 + (channel % 16))); + break; + + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL1_SET(1 << (16 + (channel % 16))); + HW_APBX_CTRL2_SET(1 << (16 + (channel % 16))); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); + +void stmp3xxx_arch_dma_clear_interrupt(int channel) +{ + int dmabus = channel / 16; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL1_CLR(1 << (channel % 16)); + HW_APBH_CTRL2_CLR(1 << (channel % 16)); + break; + + case STMP3XXX_BUS_APBX: + HW_APBX_CTRL1_CLR(1 << (channel % 16)); + HW_APBX_CTRL2_CLR(1 << (channel % 16)); + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); + +int stmp3xxx_arch_dma_is_interrupt(int channel) +{ + int dmabus = channel / 16; + int r = 0; + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + r = HW_APBH_CTRL1_RD() & (1 << (channel % 16)); + break; + + case STMP3XXX_BUS_APBX: + r = HW_APBX_CTRL1_RD() & (1 << (channel % 16)); + break; + } + return r; +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); + +void stmp3xxx_arch_dma_reset_channel(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + /* Reset channel and wait for it to complete */ + HW_APBH_CTRL0_SET(chbit << + BP_APBH_CTRL0_RESET_CHANNEL); + while (HW_APBH_CTRL0_RD() & + (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) + continue; + break; + + case STMP3XXX_BUS_APBX: + /* Reset channel and wait for it to complete */ + HW_APBX_CHANNEL_CTRL_SET( + BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit)); + while (HW_APBX_CHANNEL_CTRL_RD() & + BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit)) + continue; + break; + } +} +EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); + +void stmp3xxx_arch_dma_freeze(int channel) +{ + int dmabus = channel / 16; + unsigned chbit = 1 << (channel % 16); + + switch (dmabus) { + case STMP3XXX_BUS_APBH: + HW_APBH_CTRL0_SET(1< Date: Sun, 31 May 2009 13:32:11 +0100 Subject: [ARM] 5532/1: Freescale STMP: register definitions [3/3] Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls Signed-off-by: dmitry pervushin Signed-off-by: Russell King --- arch/arm/mach-stmp378x/stmp378x.c | 109 +++++++----- arch/arm/mach-stmp37xx/stmp37xx.c | 84 ++++----- arch/arm/plat-stmp3xxx/clock.c | 167 ++++++++++-------- arch/arm/plat-stmp3xxx/core.c | 3 +- arch/arm/plat-stmp3xxx/dma.c | 137 ++++++++------- arch/arm/plat-stmp3xxx/include/mach/dma.h | 16 +- arch/arm/plat-stmp3xxx/include/mach/pinmux.h | 7 +- arch/arm/plat-stmp3xxx/include/mach/platform.h | 21 +++ .../arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h | 195 --------------------- arch/arm/plat-stmp3xxx/include/mach/system.h | 8 +- arch/arm/plat-stmp3xxx/irq.c | 22 +-- arch/arm/plat-stmp3xxx/pinmux.c | 163 ++++++++--------- arch/arm/plat-stmp3xxx/timer.c | 111 +++++++----- 13 files changed, 462 insertions(+), 581 deletions(-) delete mode 100644 arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h (limited to 'arch/arm/mach-stmp378x/stmp378x.c') diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c index f156ec7306c..9a363fb2acf 100644 --- a/arch/arm/mach-stmp378x/stmp378x.c +++ b/arch/arm/mach-stmp378x/stmp378x.c @@ -47,25 +47,28 @@ static void stmp378x_ack_irq(unsigned int irq) { /* Tell ICOLL to release IRQ line */ - HW_ICOLL_VECTOR_WR(0x0); + __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); /* ACK current interrupt */ - HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0); + __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */, + REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); /* Barrier */ - (void) HW_ICOLL_STAT_RD(); + (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); } static void stmp378x_mask_irq(unsigned int irq) { /* IRQ disable */ - HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE); + stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE, + REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10); } static void stmp378x_unmask_irq(unsigned int irq) { /* IRQ enable */ - HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE); + stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE, + REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10); } static struct irq_chip stmp378x_chip = { @@ -84,52 +87,63 @@ void __init stmp378x_init_irq(void) */ void stmp3xxx_arch_dma_enable_interrupt(int channel) { - int dmabus = channel / 16; + void __iomem *c1, *c2; - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - HW_APBH_CTRL1_SET(1 << (16 + (channel % 16))); - HW_APBH_CTRL2_SET(1 << (16 + (channel % 16))); + c1 = REGS_APBH_BASE + HW_APBH_CTRL1; + c2 = REGS_APBH_BASE + HW_APBH_CTRL2; break; case STMP3XXX_BUS_APBX: - HW_APBX_CTRL1_SET(1 << (16 + (channel % 16))); - HW_APBX_CTRL2_SET(1 << (16 + (channel % 16))); + c1 = REGS_APBX_BASE + HW_APBX_CTRL1; + c2 = REGS_APBX_BASE + HW_APBX_CTRL2; break; + + default: + return; } + stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1); + stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2); } EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); void stmp3xxx_arch_dma_clear_interrupt(int channel) { - int dmabus = channel / 16; + void __iomem *c1, *c2; - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - HW_APBH_CTRL1_CLR(1 << (channel % 16)); - HW_APBH_CTRL2_CLR(1 << (channel % 16)); + c1 = REGS_APBH_BASE + HW_APBH_CTRL1; + c2 = REGS_APBH_BASE + HW_APBH_CTRL2; break; case STMP3XXX_BUS_APBX: - HW_APBX_CTRL1_CLR(1 << (channel % 16)); - HW_APBX_CTRL2_CLR(1 << (channel % 16)); + c1 = REGS_APBX_BASE + HW_APBX_CTRL1; + c2 = REGS_APBX_BASE + HW_APBX_CTRL2; break; + + default: + return; } + stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1); + stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2); } EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); int stmp3xxx_arch_dma_is_interrupt(int channel) { - int dmabus = channel / 16; int r = 0; - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - r = HW_APBH_CTRL1_RD() & (1 << (channel % 16)); + r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & + (1 << STMP3XXX_DMA_CHANNEL(channel)); break; case STMP3XXX_BUS_APBX: - r = HW_APBX_CTRL1_RD() & (1 << (channel % 16)); + r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) & + (1 << STMP3XXX_DMA_CHANNEL(channel)); break; } return r; @@ -138,42 +152,41 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); void stmp3xxx_arch_dma_reset_channel(int channel) { - int dmabus = channel / 16; - unsigned chbit = 1 << (channel % 16); + unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); + void __iomem *c0; + u32 mask; - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - /* Reset channel and wait for it to complete */ - HW_APBH_CTRL0_SET(chbit << - BP_APBH_CTRL0_RESET_CHANNEL); - while (HW_APBH_CTRL0_RD() & - (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) - continue; + c0 = REGS_APBH_BASE + HW_APBH_CTRL0; + mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL; break; - case STMP3XXX_BUS_APBX: - /* Reset channel and wait for it to complete */ - HW_APBX_CHANNEL_CTRL_SET( - BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit)); - while (HW_APBX_CHANNEL_CTRL_RD() & - BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit)) - continue; + c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL; + mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL; break; + default: + return; } + + /* Reset channel and wait for it to complete */ + stmp3xxx_setl(mask, c0); + while (__raw_readl(c0) & mask) + cpu_relax(); } EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); void stmp3xxx_arch_dma_freeze(int channel) { - int dmabus = channel / 16; - unsigned chbit = 1 << (channel % 16); + unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); + u32 mask = 1 << chbit; - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - HW_APBH_CTRL0_SET(1< #include +#include #include #include #include @@ -45,25 +46,28 @@ static void stmp37xx_ack_irq(unsigned int irq) { /* Disable IRQ */ - HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8)); + stmp3xxx_clearl(0x04 << ((irq % 4) * 8), + REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10); /* ACK current interrupt */ - HW_ICOLL_LEVELACK_WR(1); + __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); /* Barrier */ - (void) HW_ICOLL_STAT_RD(); + (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); } static void stmp37xx_mask_irq(unsigned int irq) { /* IRQ disable */ - HW_ICOLL_PRIORITYn_CLR(irq / 4, 0x04 << ((irq % 4) * 8)); + stmp3xxx_clearl(0x04 << ((irq % 4) * 8), + REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10); } static void stmp37xx_unmask_irq(unsigned int irq) { /* IRQ enable */ - HW_ICOLL_PRIORITYn_SET(irq / 4, 0x04 << ((irq % 4) * 8)); + stmp3xxx_setl(0x04 << ((irq % 4) * 8), + REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10); } static struct irq_chip stmp37xx_chip = { @@ -82,15 +86,15 @@ void __init stmp37xx_init_irq(void) */ void stmp3xxx_arch_dma_enable_interrupt(int channel) { - int dmabus = channel / 16; - - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - HW_APBH_CTRL1_SET(1 << (8 + (channel % 16))); + stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), + REGS_APBH_BASE + HW_APBH_CTRL1); break; case STMP3XXX_BUS_APBX: - HW_APBX_CTRL1_SET(1 << (8 + (channel % 16))); + stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), + REGS_APBX_BASE + HW_APBX_CTRL1); break; } } @@ -98,15 +102,15 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); void stmp3xxx_arch_dma_clear_interrupt(int channel) { - int dmabus = channel / 16; - - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - HW_APBH_CTRL1_CLR(1 << (channel % 16)); + stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), + REGS_APBH_BASE + HW_APBH_CTRL1); break; case STMP3XXX_BUS_APBX: - HW_APBX_CTRL1_CLR(1 << (channel % 16)); + stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), + REGS_APBX_BASE + HW_APBX_CTRL1); break; } } @@ -116,15 +120,15 @@ int stmp3xxx_arch_dma_is_interrupt(int channel) { int r = 0; - int dmabus = channel / 16; - - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - r = HW_APBH_CTRL1_RD() & (1 << (channel % 16)); + r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & + (1 << STMP3XXX_DMA_CHANNEL(channel)); break; case STMP3XXX_BUS_APBX: - r = HW_APBX_CTRL1_RD() & (1 << (channel % 16)); + r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & + (1 << STMP3XXX_DMA_CHANNEL(channel)); break; } return r; @@ -133,24 +137,24 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); void stmp3xxx_arch_dma_reset_channel(int channel) { - int dmabus = channel / 16; - unsigned chbit = 1 << (channel % 16); + unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: /* Reset channel and wait for it to complete */ - HW_APBH_CTRL0_SET(chbit << BP_APBH_CTRL0_RESET_CHANNEL); - while (HW_APBH_CTRL0_RD() & + stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL, + REGS_APBH_BASE + HW_APBH_CTRL0); + while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) & (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) - continue; + cpu_relax(); break; case STMP3XXX_BUS_APBX: - /* Reset channel and wait for it to complete */ - HW_APBX_CTRL0_SET(chbit << BP_APBX_CTRL0_RESET_CHANNEL); - while (HW_APBX_CTRL0_RD() & + stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL, + REGS_APBX_BASE + HW_APBX_CTRL0); + while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) & (chbit << BP_APBX_CTRL0_RESET_CHANNEL)) - continue; + cpu_relax(); break; } } @@ -158,15 +162,14 @@ EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); void stmp3xxx_arch_dma_freeze(int channel) { - int dmabus = channel / 16; - unsigned chbit = 1 << (channel % 16); + unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - switch (dmabus) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - HW_APBH_CTRL0_SET(1< #include #include @@ -27,6 +28,7 @@ #include #include +#include #include #include "clock.h" @@ -187,8 +189,8 @@ static long lcdif_get_rate(struct clk *clk) div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; if (div) { rate /= div; - div = (HW_CLKCTRL_FRAC_RD() & BM_CLKCTRL_FRAC_PIXFRAC) >> - BP_CLKCTRL_FRAC_PIXFRAC; + div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC; rate /= div; } clk->rate = rate; @@ -263,15 +265,19 @@ static int lcdif_set_rate(struct clk *clk, u32 rate) lowest_result / 1000, lowest_result % 1000); /* Program ref_pix phase fractional divider */ - HW_CLKCTRL_FRAC_WR((HW_CLKCTRL_FRAC_RD() & ~BM_CLKCTRL_FRAC_PIXFRAC) | - BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv)); + reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); + reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC; + reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC); + __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); + /* Ungate PFD */ - HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX); + stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX, + REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); /* Program pix divider */ reg_val = __raw_readl(clk->scale_reg); reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); - reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div); + reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV); __raw_writel(reg_val, clk->scale_reg); /* Wait for divider update */ @@ -287,7 +293,9 @@ static int lcdif_set_rate(struct clk *clk, u32 rate) } /* Switch to ref_pix source */ - HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX); + reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); + reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX; + __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); out: return ret; @@ -296,6 +304,8 @@ out: static int cpu_set_rate(struct clk *clk, u32 rate) { + u32 reg_val; + if (rate < 24000) return -EINVAL; else if (rate == 24000) { @@ -344,7 +354,12 @@ static int cpu_set_rate(struct clk *clk, u32 rate) __raw_writel(1<<7, clk->scale_reg + 8); /* write clkctrl_cpu */ clk->saved_div = clkctrl_cpu; - HW_CLKCTRL_CPU_WR((HW_CLKCTRL_CPU_RD() & ~0x3f) | clkctrl_cpu); + + reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); + reg_val &= ~0x3F; + reg_val |= clkctrl_cpu; + __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); + for (i = 10000; i; i--) if (!clk_is_busy(clk)) break; @@ -364,7 +379,7 @@ static long cpu_get_rate(struct clk *clk) long rate = clk->parent->rate * 18; rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= HW_CLKCTRL_CPU_RD() & 0x3f; + rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f; rate = ((rate + 9) / 10) * 10; clk->rate = rate; @@ -411,7 +426,7 @@ static long emi_get_rate(struct clk *clk) long rate = clk->parent->rate * 18; rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= HW_CLKCTRL_EMI_RD() & 0x3f; + rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f; clk->rate = rate; return rate; @@ -427,44 +442,52 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent) shift = 4; if (clk->bypass_reg) { - u32 hbus_mask = BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV; +#ifdef CONFIG_ARCH_STMP378X + u32 hbus_val, cpu_val; if (clk == &cpu_clk && shift == 4) { - u32 hbus_val = HW_CLKCTRL_HBUS_RD(); - u32 cpu_val = HW_CLKCTRL_CPU_RD(); - hbus_val &= ~hbus_mask; - hbus_val |= 1; + hbus_val = __raw_readl(REGS_CLKCTRL_BASE + + HW_CLKCTRL_HBUS); + cpu_val = __raw_readl(REGS_CLKCTRL_BASE + + HW_CLKCTRL_CPU); + + hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | + BM_CLKCTRL_HBUS_DIV); clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; cpu_val |= 1; - __raw_writel(1 << clk->bypass_shift, - clk->bypass_reg + shift); + if (machine_is_stmp378x()) { - HW_CLKCTRL_HBUS_WR(hbus_val); - HW_CLKCTRL_CPU_WR(cpu_val); + __raw_writel(hbus_val, + REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); + __raw_writel(cpu_val, + REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); hclk.rate = 0; } } else if (clk == &cpu_clk && shift == 8) { - u32 hbus_val = HW_CLKCTRL_HBUS_RD(); - u32 cpu_val = HW_CLKCTRL_CPU_RD(); - hbus_val &= ~hbus_mask; + hbus_val = __raw_readl(REGS_CLKCTRL_BASE + + HW_CLKCTRL_HBUS); + cpu_val = __raw_readl(REGS_CLKCTRL_BASE + + HW_CLKCTRL_CPU); + hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | + BM_CLKCTRL_HBUS_DIV); hbus_val |= 2; cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; if (clk->saved_div) cpu_val |= clk->saved_div; else cpu_val |= 2; + if (machine_is_stmp378x()) { - HW_CLKCTRL_HBUS_WR(hbus_val); - HW_CLKCTRL_CPU_WR(cpu_val); + __raw_writel(hbus_val, + REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); + __raw_writel(cpu_val, + REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); hclk.rate = 0; } - __raw_writel(1 << clk->bypass_shift, - clk->bypass_reg + shift); - } else - __raw_writel(1 << clk->bypass_shift, - clk->bypass_reg + shift); + } +#endif + __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift); ret = 0; } @@ -640,7 +663,7 @@ static struct clk osc_24M = { static struct clk pll_clk = { .parent = &osc_24M, - .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, .enable_shift = 16, .enable_wait = 10, .flags = FIXED_RATE | ENABLED, @@ -650,11 +673,11 @@ static struct clk pll_clk = { static struct clk cpu_clk = { .parent = &pll_clk, - .scale_reg = HW_CLKCTRL_FRAC_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, .scale_shift = 0, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 7, - .busy_reg = HW_CLKCTRL_CPU_ADDR, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU, .busy_bit = 28, .flags = RATE_PROPAGATES | ENABLED, .ops = &cpu_ops, @@ -662,10 +685,10 @@ static struct clk cpu_clk = { static struct clk io_clk = { .parent = &pll_clk, - .enable_reg = HW_CLKCTRL_FRAC_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, .enable_shift = 31, .enable_negate = 1, - .scale_reg = HW_CLKCTRL_FRAC_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, .scale_shift = 24, .flags = RATE_PROPAGATES | ENABLED, .ops = &io_ops, @@ -673,10 +696,10 @@ static struct clk io_clk = { static struct clk hclk = { .parent = &cpu_clk, - .scale_reg = HW_CLKCTRL_HBUS_ADDR, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 7, - .busy_reg = HW_CLKCTRL_HBUS_ADDR, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, .busy_bit = 29, .flags = RATE_PROPAGATES | ENABLED, .ops = &hbus_ops, @@ -684,8 +707,8 @@ static struct clk hclk = { static struct clk xclk = { .parent = &osc_24M, - .scale_reg = HW_CLKCTRL_XBUS_ADDR, - .busy_reg = HW_CLKCTRL_XBUS_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, .busy_bit = 31, .flags = RATE_PROPAGATES | ENABLED, .ops = &xbus_ops, @@ -693,7 +716,7 @@ static struct clk xclk = { static struct clk uart_clk = { .parent = &xclk, - .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, .enable_shift = 31, .enable_negate = 1, .flags = ENABLED, @@ -702,7 +725,7 @@ static struct clk uart_clk = { static struct clk audio_clk = { .parent = &xclk, - .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, .enable_shift = 30, .enable_negate = 1, .ops = &min_ops, @@ -710,7 +733,7 @@ static struct clk audio_clk = { static struct clk pwm_clk = { .parent = &xclk, - .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, .enable_shift = 29, .enable_negate = 1, .ops = &min_ops, @@ -718,7 +741,7 @@ static struct clk pwm_clk = { static struct clk dri_clk = { .parent = &xclk, - .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, .enable_shift = 28, .enable_negate = 1, .ops = &min_ops, @@ -726,7 +749,7 @@ static struct clk dri_clk = { static struct clk digctl_clk = { .parent = &xclk, - .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, .enable_shift = 27, .enable_negate = 1, .ops = &min_ops, @@ -734,7 +757,7 @@ static struct clk digctl_clk = { static struct clk timer_clk = { .parent = &xclk, - .enable_reg = HW_CLKCTRL_XTAL_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, .enable_shift = 26, .enable_negate = 1, .flags = ENABLED, @@ -743,13 +766,13 @@ static struct clk timer_clk = { static struct clk lcdif_clk = { .parent = &pll_clk, - .scale_reg = HW_CLKCTRL_PIX_ADDR, - .busy_reg = HW_CLKCTRL_PIX_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, .busy_bit = 29, - .enable_reg = HW_CLKCTRL_PIX_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, .enable_shift = 31, .enable_negate = 1, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 1, .flags = NEEDS_SET_PARENT, .ops = &lcdif_ops, @@ -757,12 +780,12 @@ static struct clk lcdif_clk = { static struct clk ssp_clk = { .parent = &io_clk, - .scale_reg = HW_CLKCTRL_SSP_ADDR, - .busy_reg = HW_CLKCTRL_SSP_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, .busy_bit = 29, - .enable_reg = HW_CLKCTRL_SSP_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, .enable_shift = 31, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 5, .enable_negate = 1, .flags = NEEDS_SET_PARENT, @@ -771,13 +794,13 @@ static struct clk ssp_clk = { static struct clk gpmi_clk = { .parent = &io_clk, - .scale_reg = HW_CLKCTRL_GPMI_ADDR, - .busy_reg = HW_CLKCTRL_GPMI_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, .busy_bit = 29, - .enable_reg = HW_CLKCTRL_GPMI_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, .enable_shift = 31, .enable_negate = 1, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 4, .flags = NEEDS_SET_PARENT, .ops = &std_ops, @@ -785,7 +808,7 @@ static struct clk gpmi_clk = { static struct clk spdif_clk = { .parent = &pll_clk, - .enable_reg = HW_CLKCTRL_SPDIF_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF, .enable_shift = 31, .enable_negate = 1, .ops = &min_ops, @@ -793,14 +816,14 @@ static struct clk spdif_clk = { static struct clk emi_clk = { .parent = &pll_clk, - .enable_reg = HW_CLKCTRL_EMI_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, .enable_shift = 31, .enable_negate = 1, - .scale_reg = HW_CLKCTRL_FRAC_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, .scale_shift = 8, - .busy_reg = HW_CLKCTRL_EMI_ADDR, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, .busy_bit = 28, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 6, .flags = ENABLED, .ops = &emi_ops, @@ -808,37 +831,37 @@ static struct clk emi_clk = { static struct clk ir_clk = { .parent = &io_clk, - .enable_reg = HW_CLKCTRL_IR_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR, .enable_shift = 31, .enable_negate = 1, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 3, .ops = &min_ops, }; static struct clk saif_clk = { .parent = &pll_clk, - .scale_reg = HW_CLKCTRL_SAIF_ADDR, - .busy_reg = HW_CLKCTRL_SAIF_ADDR, + .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, + .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, .busy_bit = 29, - .enable_reg = HW_CLKCTRL_SAIF_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, .enable_shift = 31, .enable_negate = 1, - .bypass_reg = HW_CLKCTRL_CLKSEQ_ADDR, + .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, .bypass_shift = 0, .ops = &std_ops, }; static struct clk usb_clk = { .parent = &pll_clk, - .enable_reg = HW_CLKCTRL_PLLCTRL0_ADDR, + .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, .enable_shift = 18, .enable_negate = 1, .ops = &min_ops, }; /* list of all the clocks */ -static __initdata struct clk_lookup onchip_clks[] = { +static struct clk_lookup onchip_clks[] = { { .con_id = "osc_24M", .clk = &osc_24M, diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c index 6e2fef1639b..37b8a09148a 100644 --- a/arch/arm/plat-stmp3xxx/core.c +++ b/arch/arm/plat-stmp3xxx/core.c @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -121,7 +122,7 @@ struct platform_device stmp3xxx_dbguart = { void __init stmp3xxx_init(void) { /* Turn off auto-slow and other tricks */ - HW_CLKCTRL_HBUS_CLR(0x07f00000U); + stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); stmp3xxx_dma_init(); } diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c index cf42de05e56..d2f497764dc 100644 --- a/arch/arm/plat-stmp3xxx/dma.c +++ b/arch/arm/plat-stmp3xxx/dma.c @@ -23,6 +23,7 @@ #include +#include #include #include #include @@ -35,16 +36,6 @@ static struct stmp3xxx_dma_user { const char *name; } channels[MAX_DMA_CHANNELS]; -static inline int dmach(int ch) -{ - return ch % 16; -} - -static inline int dmabus(int ch) -{ - return ch / 16; -} - #define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) #define IS_USED(ch) (channels[ch].inuse) @@ -101,17 +92,19 @@ int stmp3xxx_dma_read_semaphore(int channel) { int sem = -1; - switch (dmabus(channel)) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - sem = - (HW_APBH_CHn_SEMA_RD(dmach(channel)) & - BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; + sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + + STMP3XXX_DMA_CHANNEL(channel) * 0x70); + sem &= BM_APBH_CHn_SEMA_PHORE; + sem >>= BP_APBH_CHn_SEMA_PHORE; break; case STMP3XXX_BUS_APBX: - sem = - (HW_APBX_CHn_SEMA_RD(dmach(channel)) & - BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; + sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + + STMP3XXX_DMA_CHANNEL(channel) * 0x70); + sem &= BM_APBX_CHn_SEMA_PHORE; + sem >>= BP_APBX_CHn_SEMA_PHORE; break; default: BUG(); @@ -189,39 +182,44 @@ EXPORT_SYMBOL(stmp3xxx_dma_free_command); void stmp3xxx_dma_go(int channel, struct stmp3xxx_dma_descriptor *head, u32 semaphore) { - int ch = dmach(channel); + int ch = STMP3XXX_DMA_CHANNEL(channel); + void __iomem *c, *s; - switch (dmabus(channel)) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - /* Set next command */ - HW_APBH_CHn_NXTCMDAR_WR(ch, head->handle); - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - HW_APBH_CHn_SEMA_WR(ch, semaphore); + c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch; + s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch; break; case STMP3XXX_BUS_APBX: - /* Set next command */ - HW_APBX_CHn_NXTCMDAR_WR(ch, head->handle); - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - HW_APBX_CHn_SEMA_WR(ch, semaphore); + c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch; + s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch; break; + + default: + return; } + + /* Set next command */ + __raw_writel(head->handle, c); + /* Set counting semaphore (kicks off transfer). Assumes + peripheral has been set up correctly */ + __raw_writel(semaphore, s); } EXPORT_SYMBOL(stmp3xxx_dma_go); int stmp3xxx_dma_running(int channel) { - switch (dmabus(channel)) { + switch (STMP3XXX_DMA_BUS(channel)) { case STMP3XXX_BUS_APBH: - return HW_APBH_CHn_SEMA_RD(dmach(channel)) & - BM_APBH_CHn_SEMA_PHORE; + return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + + 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & + BM_APBH_CHn_SEMA_PHORE; case STMP3XXX_BUS_APBX: - return HW_APBX_CHn_SEMA_RD(dmach(channel)) & - BM_APBX_CHn_SEMA_PHORE; - + return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + + 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & + BM_APBX_CHn_SEMA_PHORE; default: BUG(); return 0; @@ -238,7 +236,7 @@ void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain) for (i = 0; i < chain->total_count; i++) stmp3xxx_dma_free_command( - STMP3xxx_DMA(chain->channel, chain->bus), + STMP3XXX_DMA(chain->channel, chain->bus), &chain->chain[i]); } EXPORT_SYMBOL(stmp3xxx_dma_free_chain); @@ -291,16 +289,15 @@ int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, chain->free_count = items; chain->active_count = 0; chain->cooked_count = 0; - chain->bus = dmabus(ch); - chain->channel = dmach(ch); + chain->bus = STMP3XXX_DMA_BUS(ch); + chain->channel = STMP3XXX_DMA_CHANNEL(ch); return err; } EXPORT_SYMBOL(stmp3xxx_dma_make_chain); void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) { - BUG_ON(stmp3xxx_dma_running(STMP3xxx_DMA(chain->channel, chain->bus)) > - 0); + BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus))); chain->free_index = 0; chain->active_index = 0; chain->cooked_index = 0; @@ -325,6 +322,8 @@ EXPORT_SYMBOL(stmp37xx_circ_advance_free); void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, unsigned count) { + void __iomem *c; + u32 mask_clr, mask; BUG_ON(chain->free_count < count); chain->free_count -= count; @@ -334,26 +333,24 @@ void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, switch (chain->bus) { case STMP3XXX_BUS_APBH: - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - HW_APBH_CHn_SEMA_CLR(chain->channel, - BM_APBH_CHn_SEMA_INCREMENT_SEMA); - HW_APBH_CHn_SEMA_SET(chain->channel, - BF_APBH_CHn_SEMA_INCREMENT_SEMA(count)); + c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel; + mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA; + mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA); break; - case STMP3XXX_BUS_APBX: - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - HW_APBX_CHn_SEMA_CLR(chain->channel, - BM_APBX_CHn_SEMA_INCREMENT_SEMA); - HW_APBX_CHn_SEMA_SET(chain->channel, - BF_APBX_CHn_SEMA_INCREMENT_SEMA(count)); + c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel; + mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA; + mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA); break; - default: BUG(); + return; } + + /* Set counting semaphore (kicks off transfer). Assumes + peripheral has been set up correctly */ + stmp3xxx_clearl(mask_clr, c); + stmp3xxx_setl(mask, c); } EXPORT_SYMBOL(stmp37xx_circ_advance_active); @@ -362,7 +359,7 @@ unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain) unsigned cooked; cooked = chain->active_count - - stmp3xxx_dma_read_semaphore(STMP3xxx_DMA(chain->channel, chain->bus)); + stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus)); chain->active_count -= cooked; chain->active_index += cooked; @@ -383,38 +380,41 @@ void stmp3xxx_dma_set_alt_target(int channel, int function) #else #error wrong arch #endif - int shift = dmach(channel) * bits; + int shift = STMP3XXX_DMA_CHANNEL(channel) * bits; unsigned mask = (1<= (1< +#endif #include /* Virtual address where registers are mapped */ @@ -44,4 +47,22 @@ #define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR #endif +#define HW_STMP3XXX_SET 0x04 +#define HW_STMP3XXX_CLR 0x08 +#define HW_STMP3XXX_TOG 0x0c + +#ifndef __ASSEMBLER__ +static inline void stmp3xxx_clearl(u32 v, void __iomem *r) +{ + __raw_writel(v, r + HW_STMP3XXX_CLR); +} + +static inline void stmp3xxx_setl(u32 v, void __iomem *r) +{ + __raw_writel(v, r + HW_STMP3XXX_SET); +} +#endif + +#define BF(value, field) (((value) << BP_##field) & BM_##field) + #endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h deleted file mode 100644 index 47797b2b36a..00000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X SoC register access interfaces - * - * The SoC registers may be accessed via: - * - * - single 32 bit address, or - * - four 32 bit addresses - general purpose, set, clear and toggle bits - * - * Multiple IP blocks (e.g. SSP, UART) provide identical register sets per - * each module - * - * Embedded Alley Solutions, Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_REGS_H -#define __ASM_PLAT_STMP3XXX_REGS_H - -#ifndef __ASSEMBLER__ -#include -#endif - -#include "platform.h" - -#define REGS_BASE STMP3XXX_REGS_BASE - -#define HW_STMP3xxx_SET 0x04 -#define HW_STMP3xxx_CLR 0x08 -#define HW_STMP3xxx_TOG 0x0c - -#ifndef __ASSEMBLER__ -#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \ - static const u32 id##_OFFSET = offset; \ - static inline u32 id##_RD_NB(const void __iomem *regbase) { \ - if (!rd) \ - printk(KERN_ERR"%s: cannot READ at %p+%x\n", \ - #id, regbase, offset); \ - return __raw_readl(regbase + offset); \ - } \ - static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \ - #id, regbase, offset); \ - __raw_writel(v, regbase + offset); \ - } \ - static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot SET at %p+%x\n", \ - #id, regbase, offset); \ - if (regset) \ - __raw_writel(v, regbase + \ - offset + HW_STMP3xxx_SET); \ - else \ - __raw_writel(v | __raw_readl(regbase + offset), \ - regbase + offset); \ - } \ - static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \ - #id, regbase, offset); \ - if (regset) \ - __raw_writel(v, regbase + \ - offset + HW_STMP3xxx_CLR); \ - else \ - __raw_writel( \ - ~v & __raw_readl(regbase + offset), \ - regbase + offset); \ - } \ - static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \ - if (!wr) \ - printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \ - #id, regbase, offset); \ - if (regset) \ - __raw_writel(v, regbase + \ - offset + HW_STMP3xxx_TOG); \ - else \ - __raw_writel(v ^ __raw_readl(regbase + offset), \ - regbase + offset); \ - } \ - static inline u32 id##_RD(void) { return id##_RD_NB(base); } \ - static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \ - static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \ - static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \ - static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); } - -#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\ - static inline u32 id##_OFFSET(int i) { \ - return offset + i * step; \ - } \ - static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\ - if (!rd) \ - printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - return __raw_readl(regbase + offset + i * step); \ - } \ - static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\ - #id, i, regbase, offset + i * step); \ - __raw_writel(v, regbase + offset + i * step); \ - } \ - static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - if (regset) \ - __raw_writel(v, regbase + offset + \ - i * step + HW_STMP3xxx_SET); \ - else \ - __raw_writel(v | __raw_readl(regbase + \ - offset + i * step), \ - regbase + offset + i * step); \ - } \ - static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - if (regset) \ - __raw_writel(v, regbase + offset + \ - i * step + HW_STMP3xxx_CLR); \ - else \ - __raw_writel(~v & __raw_readl(regbase + \ - offset + i * step), \ - regbase + offset + i * step); \ - } \ - static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\ - if (!wr) \ - printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \ - #id, i, regbase, offset + i * step); \ - if (regset) \ - __raw_writel(v, regbase + offset + \ - i * step + HW_STMP3xxx_TOG); \ - else \ - __raw_writel(v ^ __raw_readl(regbase + offset \ - + i * step), \ - regbase + offset + i * step); \ - } \ - static inline u32 id##_RD(int i) \ - { \ - return id##_RD_NB(base, i); \ - } \ - static inline void id##_WR(int i, u32 v) \ - { \ - id##_WR_NB(base, i, v); \ - } \ - static inline void id##_SET(int i, u32 v) \ - { \ - id##_SET_NB(base, i, v); \ - } \ - static inline void id##_CLR(int i, u32 v) \ - { \ - id##_CLR_NB(base, i, v); \ - } \ - static inline void id##_TOG(int i, u32 v) \ - { \ - id##_TOG_NB(base, i, v); \ - } - -#define HW_REGISTER_WO(id, base, offset)\ - HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1) -#define HW_REGISTER_RO(id, base, offset)\ - HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0) -#define HW_REGISTER(id, base, offset) \ - HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1) -#define HW_REGISTER_0(id, base, offset) \ - HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1) -#define HW_REGISTER_INDEXED(id, base, offset, step) \ - HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step) -#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \ - HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step) -#define HW_REGISTER_0_INDEXED(id, base, offset, step) \ - HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step) -#else /* __ASSEMBLER__ */ -#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) -#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step) -#define HW_REGISTER_WO(id, base, offset) -#define HW_REGISTER_RO(id, base, offset) -#define HW_REGISTER(id, base, offset) -#define HW_REGISTER_0(id, base, offset) -#define HW_REGISTER_INDEXED(id, base, offset, step) -#define HW_REGISTER_RO_INDEXED(id, base, offset, step) -#define HW_REGISTER_0_INDEXED(id, base, offset, step) -#endif /* __ASSEMBLER__ */ - -#endif /* __ASM_PLAT_STMP3XXX_REGS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h index dac48d26714..28a98888931 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/system.h +++ b/arch/arm/plat-stmp3xxx/include/mach/system.h @@ -17,6 +17,7 @@ #define __ASM_ARCH_SYSTEM_H #include +#include #include #include @@ -33,13 +34,14 @@ static inline void arch_idle(void) static inline void arch_reset(char mode, const char *cmd) { /* Set BATTCHRG to default value */ - HW_POWER_CHARGE_WR(0x00010000); + __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE); /* Set MINPWR to default value */ - HW_POWER_MINPWR_WR(0); + __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR); /* Reset digital side of chip (but not power or RTC) */ - HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG); + __raw_writel(BM_CLKCTRL_RESET_DIG, + REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET); /* Should not return */ } diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c index cb365909668..20de4e0401e 100644 --- a/arch/arm/plat-stmp3xxx/irq.c +++ b/arch/arm/plat-stmp3xxx/irq.c @@ -22,21 +22,15 @@ #include #include +#include #include void __init stmp3xxx_init_irq(struct irq_chip *chip) { - unsigned int i; + unsigned int i, lv; /* Reset the interrupt controller */ - HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_CLKGATE); - udelay(10); - HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST); - udelay(10); - HW_ICOLL_CTRL_SET(BM_ICOLL_CTRL_SFTRST); - while (!(HW_ICOLL_CTRL_RD() & BM_ICOLL_CTRL_CLKGATE)) - continue; - HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_CLKGATE); + stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true); /* Disable all interrupts initially */ for (i = 0; i < NR_REAL_IRQS; i++) { @@ -47,13 +41,11 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip) } /* Ensure vector is cleared */ - HW_ICOLL_LEVELACK_WR(1); - HW_ICOLL_LEVELACK_WR(2); - HW_ICOLL_LEVELACK_WR(4); - HW_ICOLL_LEVELACK_WR(8); + for (lv = 0; lv < 4; lv++) + __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); + __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); - HW_ICOLL_VECTOR_WR(0); /* Barrier */ - (void) HW_ICOLL_STAT_RD(); + (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); } diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c index 9b28cc83f31..d4120038220 100644 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ b/arch/arm/plat-stmp3xxx/pinmux.c @@ -15,6 +15,7 @@ * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ +#define DEBUG #include #include #include @@ -25,6 +26,7 @@ #include #include +#include #include #include #include @@ -33,97 +35,94 @@ static struct stmp3xxx_pinmux_bank pinmux_banks[] = { [0] = { .hw_muxsel = { - HW_PINCTRL_MUXSEL0_ADDR, - HW_PINCTRL_MUXSEL1_ADDR + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0, + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1, }, .hw_drive = { - HW_PINCTRL_DRIVE0_ADDR, - HW_PINCTRL_DRIVE1_ADDR, - HW_PINCTRL_DRIVE2_ADDR, - HW_PINCTRL_DRIVE3_ADDR + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3, }, - .hw_pull = HW_PINCTRL_PULL0_ADDR, + .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0, .functions = { 0x0, 0x1, 0x2, 0x3 }, .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - .hw_gpio_read = HW_PINCTRL_DIN0_ADDR, - .hw_gpio_set = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_SET, - .hw_gpio_clr = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_CLR, - .hw_gpio_doe = HW_PINCTRL_DOE0_ADDR, + .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0, + .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0, + .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0, .irq = IRQ_GPIO0, - .pin2irq = HW_PINCTRL_PIN2IRQ0_ADDR, - .irqstat = HW_PINCTRL_IRQSTAT0_ADDR, - .irqlevel = HW_PINCTRL_IRQLEVEL0_ADDR, - .irqpolarity = HW_PINCTRL_IRQPOL0_ADDR, - .irqen = HW_PINCTRL_IRQEN0_ADDR, + .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0, + .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0, + .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0, + .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0, + .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0, }, [1] = { .hw_muxsel = { - HW_PINCTRL_MUXSEL2_ADDR, - HW_PINCTRL_MUXSEL3_ADDR + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2, + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3, }, .hw_drive = { - HW_PINCTRL_DRIVE4_ADDR, - HW_PINCTRL_DRIVE5_ADDR, - HW_PINCTRL_DRIVE6_ADDR, - HW_PINCTRL_DRIVE7_ADDR + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7, }, - .hw_pull = HW_PINCTRL_PULL1_ADDR, + .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1, .functions = { 0x0, 0x1, 0x2, 0x3 }, .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - .hw_gpio_read = HW_PINCTRL_DIN1_ADDR, - .hw_gpio_set = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_SET, - .hw_gpio_clr = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_CLR, - .hw_gpio_doe = HW_PINCTRL_DOE1_ADDR, + .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1, + .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1, + .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1, .irq = IRQ_GPIO1, - .pin2irq = HW_PINCTRL_PIN2IRQ1_ADDR, - .irqstat = HW_PINCTRL_IRQSTAT1_ADDR, - .irqlevel = HW_PINCTRL_IRQLEVEL1_ADDR, - .irqpolarity = HW_PINCTRL_IRQPOL1_ADDR, - .irqen = HW_PINCTRL_IRQEN1_ADDR, + .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1, + .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1, + .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1, + .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1, + .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1, }, [2] = { .hw_muxsel = { - HW_PINCTRL_MUXSEL4_ADDR, - HW_PINCTRL_MUXSEL5_ADDR, + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4, + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5, }, .hw_drive = { - HW_PINCTRL_DRIVE8_ADDR, - HW_PINCTRL_DRIVE9_ADDR, - HW_PINCTRL_DRIVE10_ADDR, - HW_PINCTRL_DRIVE11_ADDR, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11, }, - .hw_pull = HW_PINCTRL_PULL2_ADDR, + .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2, .functions = { 0x0, 0x1, 0x2, 0x3 }, .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 }, - .hw_gpio_read = HW_PINCTRL_DIN2_ADDR, - .hw_gpio_set = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_SET, - .hw_gpio_clr = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_CLR, - .hw_gpio_doe = HW_PINCTRL_DOE2_ADDR, + .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2, + .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2, + .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2, .irq = IRQ_GPIO2, - .pin2irq = HW_PINCTRL_PIN2IRQ2_ADDR, - .irqstat = HW_PINCTRL_IRQSTAT2_ADDR, - .irqlevel = HW_PINCTRL_IRQLEVEL2_ADDR, - .irqpolarity = HW_PINCTRL_IRQPOL2_ADDR, - .irqen = HW_PINCTRL_IRQEN2_ADDR, + .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2, + .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2, + .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2, + .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2, + .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2, }, [3] = { .hw_muxsel = { - HW_PINCTRL_MUXSEL6_ADDR, - HW_PINCTRL_MUXSEL7_ADDR, + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6, + REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7, }, .hw_drive = { - HW_PINCTRL_DRIVE12_ADDR, - HW_PINCTRL_DRIVE13_ADDR, - HW_PINCTRL_DRIVE14_ADDR, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13, + REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14, NULL, }, - .hw_pull = HW_PINCTRL_PULL3_ADDR, + .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3, .functions = {0x0, 0x1, 0x2, 0x3}, .strengths = {0x0, 0x1, 0x2, 0x3, 0xff}, }, @@ -196,8 +195,8 @@ void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, pr_debug("%s: writing 0x%x to 0x%p register\n", __func__, val << shift, hwdrive); - __raw_writel(HW_DRIVE_PINDRV_MASK << shift, hwdrive + HW_STMP3xxx_CLR); - __raw_writel(val << shift, hwdrive + HW_STMP3xxx_SET); + stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive); + stmp3xxx_setl(val << shift, hwdrive); } void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, @@ -221,11 +220,9 @@ void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, pr_debug("%s: changing 0x%x bit in 0x%p register\n", __func__, HW_DRIVE_PINV_MASK << shift, hwdrive); if (voltage == PIN_1_8V) - __raw_writel(HW_DRIVE_PINV_MASK << shift, - hwdrive + HW_STMP3xxx_CLR); + stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive); else - __raw_writel(HW_DRIVE_PINV_MASK << shift, - hwdrive + HW_STMP3xxx_SET); + stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive); } void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label) @@ -245,8 +242,10 @@ void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label) pr_debug("%s: changing 0x%x bit in 0x%p register\n", __func__, 1 << pin, hwpull); - __raw_writel(1 << pin, - hwpull + (enable ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); + if (enable) + stmp3xxx_setl(1 << pin, hwpull); + else + stmp3xxx_clearl(1 << pin, hwpull); } int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label) @@ -290,8 +289,8 @@ void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun) shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; pr_debug("%s: writing 0x%x to 0x%p register\n", __func__, val << shift, hwmux); - __raw_writel(HW_MUXSEL_PINFUN_MASK << shift, hwmux + HW_STMP3xxx_CLR); - __raw_writel(val << shift, hwmux + HW_STMP3xxx_SET); + stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux); + stmp3xxx_setl(val << shift, hwmux); } void stmp3xxx_release_pin(unsigned id, const char *label) @@ -388,10 +387,15 @@ static int stmp3xxx_set_irqtype(unsigned irq, unsigned type) __func__, type); return -ENXIO; } - __raw_writel(1 << gpio, - pm->irqlevel + (l ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); - __raw_writel(1 << gpio, - pm->irqpolarity + (p ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR)); + + if (l) + stmp3xxx_setl(1 << gpio, pm->irqlevel); + else + stmp3xxx_clearl(1 << gpio, pm->irqlevel); + if (p) + stmp3xxx_setl(1 << gpio, pm->irqpolarity); + else + stmp3xxx_clearl(1 << gpio, pm->irqpolarity); return 0; } @@ -402,8 +406,8 @@ static void stmp3xxx_pin_ack_irq(unsigned irq) unsigned gpio; stmp3xxx_irq_to_gpio(irq, &pm, &gpio); - stat = __raw_readl(pm->irqstat) & (1<irqstat + HW_STMP3xxx_CLR); + stat = __raw_readl(pm->irqstat) & (1 << gpio); + stmp3xxx_clearl(stat, pm->irqstat); } static void stmp3xxx_pin_mask_irq(unsigned irq) @@ -412,8 +416,8 @@ static void stmp3xxx_pin_mask_irq(unsigned irq) unsigned gpio; stmp3xxx_irq_to_gpio(irq, &pm, &gpio); - __raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_CLR); - __raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_CLR); + stmp3xxx_clearl(1 << gpio, pm->irqen); + stmp3xxx_clearl(1 << gpio, pm->pin2irq); } static void stmp3xxx_pin_unmask_irq(unsigned irq) @@ -422,8 +426,8 @@ static void stmp3xxx_pin_unmask_irq(unsigned irq) unsigned gpio; stmp3xxx_irq_to_gpio(irq, &pm, &gpio); - __raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_SET); - __raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_SET); + stmp3xxx_setl(1 << gpio, pm->irqen); + stmp3xxx_setl(1 << gpio, pm->pin2irq); } static inline @@ -443,7 +447,7 @@ static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset) struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); unsigned v; - v = __raw_readl(pm->hw_gpio_read) & (1 << offset); + v = __raw_readl(pm->hw_gpio_in) & (1 << offset); return v ? 1 : 0; } @@ -451,14 +455,17 @@ static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v) { struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - __raw_writel(1 << offset, v ? pm->hw_gpio_set : pm->hw_gpio_clr); + if (v) + stmp3xxx_setl(1 << offset, pm->hw_gpio_out); + else + stmp3xxx_clearl(1 << offset, pm->hw_gpio_out); } static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v) { struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - __raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_SET); + stmp3xxx_setl(1 << offset, pm->hw_gpio_doe); stmp3xxx_gpio_set(chip, offset, v); return 0; } @@ -467,7 +474,7 @@ static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset) { struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - __raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_CLR); + stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe); return 0; } diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c index 7d872f0aee7..063c7bc0e74 100644 --- a/arch/arm/plat-stmp3xxx/timer.c +++ b/arch/arm/plat-stmp3xxx/timer.c @@ -26,6 +26,7 @@ #include #include +#include #include static irqreturn_t @@ -33,13 +34,22 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *c = dev_id; - if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) { - HW_TIMROT_TIMCTRLn_CLR(0, (1<<15)); + /* timer 0 */ + if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) & + BM_TIMROT_TIMCTRLn_IRQ) { + stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); c->event_handler(c); - } else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) { - HW_TIMROT_TIMCTRLn_CLR(1, (1<<15)); - HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN); - HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); + } + + /* timer 1 */ + else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1) + & BM_TIMROT_TIMCTRLn_IRQ) { + stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); + stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); + __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); } return IRQ_HANDLED; @@ -47,14 +57,16 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id) static cycle_t stmp3xxx_clock_read(struct clocksource *cs) { - return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16); + return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1) + & 0xFFFF0000) >> 16); } static int stmp3xxx_timrot_set_next_event(unsigned long delta, struct clock_event_device *dev) { - HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */ + /* reload the timer */ + __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); return 0; } @@ -102,25 +114,29 @@ static void __init stmp3xxx_init_timer(void) ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); ckevt_timrot.cpumask = cpumask_of(0); - HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST | - BM_TIMROT_ROTCTRL_CLKGATE); - HW_TIMROT_TIMCOUNTn_WR(0, 0); - HW_TIMROT_TIMCOUNTn_WR(1, 0); - - HW_TIMROT_TIMCTRLn_WR(0, - (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ - BF_TIMROT_TIMCTRLn_PRESCALE(0) | - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN)); - HW_TIMROT_TIMCTRLn_WR(1, - (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ - BF_TIMROT_TIMCTRLn_PRESCALE(0) | - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE)); - - HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1); - HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */ + stmp3xxx_reset_block(REGS_TIMROT_BASE, false); + + /* clear two timers */ + __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); + __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); + + /* configure them */ + __raw_writel( + (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); + __raw_writel( + (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); + + __raw_writel(CLOCK_TICK_RATE / HZ - 1, + REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); + __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); @@ -132,30 +148,31 @@ static void __init stmp3xxx_init_timer(void) void stmp3xxx_suspend_timer(void) { - HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN); - HW_TIMROT_TIMCTRLn_CLR(0, (1<<15)); - HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE); + stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); + stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE, + REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); } void stmp3xxx_resume_timer(void) { - HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST | - BM_TIMROT_ROTCTRL_CLKGATE); - - - HW_TIMROT_TIMCTRLn_WR(0, - (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ - BF_TIMROT_TIMCTRLn_PRESCALE(0) | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN)); - HW_TIMROT_TIMCTRLn_WR(1, - (BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */ - BF_TIMROT_TIMCTRLn_PRESCALE(0) | - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE)); - - HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1); - HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */ + stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE, + REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); + __raw_writel( + 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); + __raw_writel( + 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); + __raw_writel(CLOCK_TICK_RATE / HZ - 1, + REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); + __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); } #else -- cgit v1.2.3-70-g09d2 From c11c22177ae2929598051a39e4655be4a42cb805 Mon Sep 17 00:00:00 2001 From: dmitry pervushin Date: Thu, 4 Jun 2009 13:51:05 +0100 Subject: [ARM] 5539/1: Freescale STMP: onboard devices declaration Define onboard devices for Freescale STMP3xxx boards Signed-off-by: dmitry pervushin Signed-off-by: Russell King --- arch/arm/mach-stmp378x/stmp378x.c | 61 ++++ arch/arm/mach-stmp378x/stmp378x.h | 1 + arch/arm/mach-stmp378x/stmp378x_devb.c | 254 ++++++++++++++++ arch/arm/mach-stmp37xx/stmp37xx_devb.c | 18 ++ arch/arm/plat-stmp3xxx/Makefile | 2 +- arch/arm/plat-stmp3xxx/devices.c | 389 +++++++++++++++++++++++++ arch/arm/plat-stmp3xxx/include/mach/gpmi.h | 12 + arch/arm/plat-stmp3xxx/include/mach/mmc.h | 14 + arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h | 22 +- 9 files changed, 771 insertions(+), 2 deletions(-) create mode 100644 arch/arm/plat-stmp3xxx/devices.c create mode 100644 arch/arm/plat-stmp3xxx/include/mach/gpmi.h create mode 100644 arch/arm/plat-stmp3xxx/include/mach/mmc.h (limited to 'arch/arm/mach-stmp378x/stmp378x.c') diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c index 9a363fb2acf..ddd49a760fd 100644 --- a/arch/arm/mach-stmp378x/stmp378x.c +++ b/arch/arm/mach-stmp378x/stmp378x.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,8 @@ #include #include #include +#include +#include #include "stmp378x.h" /* @@ -232,6 +235,64 @@ static struct map_desc stmp378x_io_desc[] __initdata = { }, }; + +static u64 common_dmamask = DMA_BIT_MASK(32); + +/* + * devices that are present only on stmp378x, not on all 3xxx boards: + * PxP + * I2C + */ +static struct resource pxp_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = REGS_PXP_PHYS, + .end = REGS_PXP_PHYS + REGS_PXP_SIZE, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_PXP, + .end = IRQ_PXP, + }, +}; + +struct platform_device stmp378x_pxp = { + .name = "stmp3xxx-pxp", + .id = -1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(pxp_resource), + .resource = pxp_resource, +}; + +static struct resource i2c_resources[] = { + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C_ERROR, + .end = IRQ_I2C_ERROR, + }, { + .flags = IORESOURCE_MEM, + .start = REGS_I2C_PHYS, + .end = REGS_I2C_PHYS + REGS_I2C_SIZE, + }, { + .flags = IORESOURCE_DMA, + .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), + .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), + }, +}; + +struct platform_device stmp378x_i2c = { + .name = "i2c_stmp3xxx", + .id = 0, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = i2c_resources, + .num_resources = ARRAY_SIZE(i2c_resources), +}; + void __init stmp378x_map_io(void) { iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc)); diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h index 473de64cf8f..0dc15b3c891 100644 --- a/arch/arm/mach-stmp378x/stmp378x.h +++ b/arch/arm/mach-stmp378x/stmp378x.h @@ -21,4 +21,5 @@ void stmp378x_map_io(void); void stmp378x_init_irq(void); +extern struct platform_device stmp378x_pxp, stmp378x_i2c; #endif /* __MACH_STMP378X_COMMON_H */ diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c index bc643f686b1..90d8fe6f10f 100644 --- a/arch/arm/mach-stmp378x/stmp378x_devb.c +++ b/arch/arm/mach-stmp378x/stmp378x_devb.c @@ -17,7 +17,12 @@ */ #include #include +#include #include +#include +#include +#include +#include #include #include @@ -25,12 +30,39 @@ #include #include +#include #include +#include +#include #include "stmp378x.h" static struct platform_device *devices[] = { &stmp3xxx_dbguart, + &stmp3xxx_appuart, + &stmp3xxx_watchdog, + &stmp3xxx_touchscreen, + &stmp3xxx_rtc, + &stmp3xxx_keyboard, + &stmp3xxx_framebuffer, + &stmp3xxx_backlight, + &stmp3xxx_rotdec, + &stmp3xxx_persistent, + &stmp3xxx_dcp_bootstream, + &stmp3xxx_dcp, + &stmp3xxx_battery, + &stmp378x_pxp, + &stmp378x_i2c, +}; + +static struct pin_desc i2c_pins_desc[] = { + { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, +}; + +static struct pin_group i2c_pins = { + .pins = i2c_pins_desc, + .nr_pins = ARRAY_SIZE(i2c_pins_desc), }; static struct pin_desc dbguart_pins_0[] = { @@ -56,6 +88,215 @@ static int dbguart_pins_control(int id, int request) return r; } +static struct pin_desc appuart_pins_0[] = { + { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, +}; + +static struct pin_desc appuart_pins_1[] = { +#if 0 /* enable these when second appuart will be connected */ + { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, +#endif +}; + +static struct pin_desc mmc_pins_desc[] = { + { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, + { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, + { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, + { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, + { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, + { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, + { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, +}; + +static struct pin_group mmc_pins = { + .pins = mmc_pins_desc, + .nr_pins = ARRAY_SIZE(mmc_pins_desc), +}; + +static int stmp3xxxmmc_get_wp(void) +{ + return gpio_get_value(PINID_PWM4); +} + +static int stmp3xxxmmc_hw_init_ssp1(void) +{ + int ret; + + ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc"); + if (ret) + goto out; + + /* Configure write protect GPIO pin */ + ret = gpio_request(PINID_PWM4, "mmc wp"); + if (ret) + goto out_wp; + + gpio_direction_input(PINID_PWM4); + + /* Configure POWER pin as gpio to drive power to MMC slot */ + ret = gpio_request(PINID_PWM3, "mmc power"); + if (ret) + goto out_power; + + gpio_direction_output(PINID_PWM3, 0); + mdelay(100); + + return 0; + +out_power: + gpio_free(PINID_PWM4); +out_wp: + stmp3xxx_release_pin_group(&mmc_pins, "mmc"); +out: + return ret; +} + +static void stmp3xxxmmc_hw_release_ssp1(void) +{ + gpio_free(PINID_PWM3); + gpio_free(PINID_PWM4); + stmp3xxx_release_pin_group(&mmc_pins, "mmc"); +} + +static void stmp3xxxmmc_cmd_pullup_ssp1(int enable) +{ + stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc"); +} + +static unsigned long +stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz) +{ + struct clk *ssp, *parent; + char *p; + long r; + + ssp = clk_get(NULL, "ssp"); + + /* using SSP1, no timeout, clock rate 1 */ + writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) | + BF(0xFFFF, SSP_TIMING_TIMEOUT), + base + HW_SSP_TIMING); + + p = (hz > 1000000) ? "io" : "osc_24M"; + parent = clk_get(NULL, p); + clk_set_parent(ssp, parent); + r = clk_set_rate(ssp, 2 * hz / 1000); + clk_put(parent); + clk_put(ssp); + + return hz; +} + +static struct stmp3xxxmmc_platform_data mmc_data = { + .hw_init = stmp3xxxmmc_hw_init_ssp1, + .hw_release = stmp3xxxmmc_hw_release_ssp1, + .get_wp = stmp3xxxmmc_get_wp, + .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1, + .setclock = stmp3xxxmmc_setclock_ssp1, +}; + + +static struct pin_group appuart_pins[] = { + [0] = { + .pins = appuart_pins_0, + .nr_pins = ARRAY_SIZE(appuart_pins_0), + }, + [1] = { + .pins = appuart_pins_1, + .nr_pins = ARRAY_SIZE(appuart_pins_1), + }, +}; + +static struct pin_desc ssp1_pins_desc[] = { + { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, }, + { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, + { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, + { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, +}; + +static struct pin_desc ssp2_pins_desc[] = { + { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, }, + { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, + { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, + { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, +}; + +static struct pin_group ssp1_pins = { + .pins = ssp1_pins_desc, + .nr_pins = ARRAY_SIZE(ssp1_pins_desc), +}; + +static struct pin_group ssp2_pins = { + .pins = ssp1_pins_desc, + .nr_pins = ARRAY_SIZE(ssp2_pins_desc), +}; + +static struct pin_desc gpmi_pins_desc[] = { + { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, + { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, + { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, + { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, +}; + +static struct pin_group gpmi_pins = { + .pins = gpmi_pins_desc, + .nr_pins = ARRAY_SIZE(gpmi_pins_desc), +}; + +static struct mtd_partition gpmi_partitions[] = { + [0] = { + .name = "boot", + .size = 10 * SZ_1M, + .offset = 0, + }, + [1] = { + .name = "data", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + }, +}; + +static struct gpmi_platform_data gpmi_data = { + .pins = &gpmi_pins, + .nr_parts = ARRAY_SIZE(gpmi_partitions), + .parts = gpmi_partitions, + .part_types = { "cmdline", NULL }, +}; + +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) + { + .modalias = "enc28j60", + .max_speed_hz = 6 * 1000 * 1000, + .bus_num = 1, + .chip_select = 0, + .platform_data = NULL, + }, +#endif +}; + static void __init stmp378x_devb_init(void) { stmp3xxx_pinmux_init(NR_REAL_IRQS); @@ -64,9 +305,22 @@ static void __init stmp378x_devb_init(void) stmp3xxx_init(); stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; + stmp3xxx_appuart.dev.platform_data = appuart_pins; + stmp3xxx_mmc.dev.platform_data = &mmc_data; + stmp3xxx_gpmi.dev.platform_data = &gpmi_data; + stmp3xxx_spi1.dev.platform_data = &ssp1_pins; + stmp3xxx_spi2.dev.platform_data = &ssp2_pins; + stmp378x_i2c.dev.platform_data = &i2c_pins; + + /* register spi devices */ + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); /* add board's devices */ platform_add_devices(devices, ARRAY_SIZE(devices)); + + /* add devices selected by command line ssp1= and ssp2= options */ + stmp3xxx_ssp1_device_register(); + stmp3xxx_ssp2_device_register(); } MACHINE_START(STMP378X, "STMP378X") diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c index adfbdc7f8e2..394f21ab59e 100644 --- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c +++ b/arch/arm/mach-stmp37xx/stmp37xx_devb.c @@ -33,6 +33,7 @@ */ static struct platform_device *stmp37xx_devb_devices[] = { &stmp3xxx_dbguart, + &stmp3xxx_appuart, }; static struct pin_desc dbguart_pins_0[] = { @@ -40,6 +41,21 @@ static struct pin_desc dbguart_pins_0[] = { { PINID_PWM1, PIN_FUN3, }, }; +struct pin_desc appuart_pins_0[] = { + { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, + { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, +}; + +static struct pin_group appuart_pins[] = { + [0] = { + .pins = appuart_pins_0, + .nr_pins = ARRAY_SIZE(appuart_pins_0), + }, + /* 37xx has the only app uart */ +}; + static struct pin_group dbguart_pins[] = { [0] = { .pins = dbguart_pins_0, @@ -67,6 +83,8 @@ static void __init stmp37xx_devb_init(void) stmp3xxx_init(); stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; + stmp3xxx_appuart.dev.platform_data = appuart_pins; + /* Add STMP37xx development board devices */ platform_add_devices(stmp37xx_devb_devices, ARRAY_SIZE(stmp37xx_devb_devices)); diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile index b63480066d6..31dd518f37a 100644 --- a/arch/arm/plat-stmp3xxx/Makefile +++ b/arch/arm/plat-stmp3xxx/Makefile @@ -2,4 +2,4 @@ # Makefile for the linux kernel. # # Object file lists. -obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o +obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c new file mode 100644 index 00000000000..68fed4b8746 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/devices.c @@ -0,0 +1,389 @@ +/* +* Freescale STMP37XX/STMP378X platform devices +* +* Embedded Alley Solutions, Inc +* +* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. +* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. +*/ + +/* +* The code contained herein is licensed under the GNU General Public +* License. You may obtain a copy of the GNU General Public License +* Version 2 or later at the following locations: +* +* http://www.opensource.org/licenses/gpl-license.html +* http://www.gnu.org/copyleft/gpl.html +*/ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static u64 common_dmamask = DMA_BIT_MASK(32); + +static struct resource appuart_resources[] = { + { + .start = IRQ_UARTAPP_INTERNAL, + .end = IRQ_UARTAPP_INTERNAL, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_UARTAPP_RX_DMA, + .end = IRQ_UARTAPP_RX_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_UARTAPP_TX_DMA, + .end = IRQ_UARTAPP_TX_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = REGS_UARTAPP1_PHYS, + .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE, + .flags = IORESOURCE_MEM, + }, { + /* Rx DMA channel */ + .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), + .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), + .flags = IORESOURCE_DMA, + }, { + /* Tx DMA channel */ + .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), + .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device stmp3xxx_appuart = { + .name = "stmp3xxx-appuart", + .id = 0, + .resource = appuart_resources, + .num_resources = ARRAY_SIZE(appuart_resources), + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device stmp3xxx_watchdog = { + .name = "stmp3xxx_wdt", + .id = -1, +}; + +static struct resource ts_resource[] = { + { + .flags = IORESOURCE_IRQ, + .start = IRQ_TOUCH_DETECT, + .end = IRQ_TOUCH_DETECT, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH5, + .end = IRQ_LRADC_CH5, + }, +}; + +struct platform_device stmp3xxx_touchscreen = { + .name = "stmp3xxx_ts", + .id = -1, + .resource = ts_resource, + .num_resources = ARRAY_SIZE(ts_resource), +}; + +/* +* Keypad device +*/ +struct platform_device stmp3xxx_keyboard = { + .name = "stmp3xxx-keyboard", + .id = -1, +}; + +static struct resource gpmi_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = REGS_GPMI_PHYS, + .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_DMA, + .end = IRQ_GPMI_DMA, + }, { + .flags = IORESOURCE_DMA, + .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH), + .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH), + }, +}; + +struct platform_device stmp3xxx_gpmi = { + .name = "gpmi", + .id = -1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = gpmi_resources, + .num_resources = ARRAY_SIZE(gpmi_resources), +}; + +static struct resource mmc1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = REGS_SSP1_PHYS, + .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, + }, { + .flags = IORESOURCE_DMA, + .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), + .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP1_DMA, + .end = IRQ_SSP1_DMA, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP_ERROR, + .end = IRQ_SSP_ERROR, + }, +}; + +struct platform_device stmp3xxx_mmc = { + .name = "stmp3xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = mmc1_resource, + .num_resources = ARRAY_SIZE(mmc1_resource), +}; + +static struct resource usb_resources[] = { + { + .start = REGS_USBCTRL_PHYS, + .end = REGS_USBCTRL_PHYS + SZ_4K, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_USB_CTRL, + .end = IRQ_USB_CTRL, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device stmp3xxx_udc = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = usb_resources, + .num_resources = ARRAY_SIZE(usb_resources), +}; + +struct platform_device stmp3xxx_ehci = { + .name = "fsl-ehci", + .id = -1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = usb_resources, + .num_resources = ARRAY_SIZE(usb_resources), +}; + +static struct resource rtc_resources[] = { + { + .start = REGS_RTC_PHYS, + .end = REGS_RTC_PHYS + REGS_RTC_SIZE, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_RTC_1MSEC, + .end = IRQ_RTC_1MSEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device stmp3xxx_rtc = { + .name = "stmp3xxx-rtc", + .id = -1, + .resource = rtc_resources, + .num_resources = ARRAY_SIZE(rtc_resources), +}; + +static struct resource ssp1_resources[] = { + { + .start = REGS_SSP1_PHYS, + .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_SSP1_DMA, + .end = IRQ_SSP1_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), + .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource ssp2_resources[] = { + { + .start = REGS_SSP2_PHYS, + .end = REGS_SSP2_PHYS + REGS_SSP_SIZE, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_SSP2_DMA, + .end = IRQ_SSP2_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), + .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device stmp3xxx_spi1 = { + .name = "stmp3xxx_ssp", + .id = 1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = ssp1_resources, + .num_resources = ARRAY_SIZE(ssp1_resources), +}; + +struct platform_device stmp3xxx_spi2 = { + .name = "stmp3xxx_ssp", + .id = 2, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = ssp2_resources, + .num_resources = ARRAY_SIZE(ssp2_resources), +}; + +static struct resource fb_resource[] = { + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LCDIF_DMA, + .end = IRQ_LCDIF_DMA, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_LCDIF_ERROR, + .end = IRQ_LCDIF_ERROR, + }, { + .flags = IORESOURCE_MEM, + .start = REGS_LCDIF_PHYS, + .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE, + }, +}; + +struct platform_device stmp3xxx_framebuffer = { + .name = "stmp3xxx-fb", + .id = -1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(fb_resource), + .resource = fb_resource, +}; + +#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \ + static char *cmdline_device_##name; \ + static int cmdline_device_##name##_setup(char *dev) \ + { \ + cmdline_device_##name = dev + 1; \ + return 0; \ + } \ + __setup(#name, cmdline_device_##name##_setup); \ + int stmp3xxx_##name##_device_register(void) \ + { \ + struct platform_device *d = NULL; \ + if (!cmdline_device_##name || \ + !strcmp(cmdline_device_##name, #dev1)) \ + d = &stmp3xxx_##dev1; \ + else if (!strcmp(cmdline_device_##name, #dev2)) \ + d = &stmp3xxx_##dev2; \ + else \ + printk(KERN_ERR"Unknown %s assignment '%s'.\n", \ + #name, cmdline_device_##name); \ + return d ? platform_device_register(d) : -ENOENT; \ + } + +CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1) +CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2) + +struct platform_device stmp3xxx_backlight = { + .name = "stmp3xxx-bl", + .id = -1, +}; + +struct platform_device stmp3xxx_rotdec = { + .name = "stmp3xxx-rotdec", + .id = -1, +}; + +struct platform_device stmp3xxx_persistent = { + .name = "stmp3xxx-persistent", + .id = -1, +}; + +struct platform_device stmp3xxx_dcp_bootstream = { + .name = "stmp3xxx-dcpboot", + .id = -1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dcp_resources[] = { + { + .start = IRQ_DCP_VMI, + .end = IRQ_DCP_VMI, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_DCP, + .end = IRQ_DCP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device stmp3xxx_dcp = { + .name = "stmp3xxx-dcp", + .id = -1, + .resource = dcp_resources, + .num_resources = ARRAY_SIZE(dcp_resources), + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource battery_resource[] = { + { + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD5V, + .end = IRQ_VDD5V, + }, +}; + +struct platform_device stmp3xxx_battery = { + .name = "stmp3xxx-battery", + .resource = battery_resource, + .num_resources = ARRAY_SIZE(battery_resource), +}; diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h new file mode 100644 index 00000000000..e166432910a --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h @@ -0,0 +1,12 @@ +#ifndef __MACH_GPMI_H + +#include +#include + +struct gpmi_platform_data { + void *pins; + int nr_parts; + struct mtd_partition *parts; + const char *part_types[]; +}; +#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h new file mode 100644 index 00000000000..ba81e154376 --- /dev/null +++ b/arch/arm/plat-stmp3xxx/include/mach/mmc.h @@ -0,0 +1,14 @@ +#ifndef _MACH_MMC_H +#define _MACH_MMC_H + +#include + +struct stmp3xxxmmc_platform_data { + int (*get_wp)(void); + unsigned long (*setclock)(void __iomem *base, unsigned long); + void (*cmd_pullup)(int); + int (*hw_init)(void); + void (*hw_release)(void); +}; + +#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h index 78cf1be7551..2e300feaa4c 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h +++ b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h @@ -25,7 +25,27 @@ extern struct sys_timer stmp3xxx_timer; void stmp3xxx_init_irq(struct irq_chip *chip); void stmp3xxx_init(void); int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable); -extern struct platform_device stmp3xxx_dbguart; +extern struct platform_device stmp3xxx_dbguart, + stmp3xxx_appuart, + stmp3xxx_watchdog, + stmp3xxx_touchscreen, + stmp3xxx_keyboard, + stmp3xxx_gpmi, + stmp3xxx_mmc, + stmp3xxx_udc, + stmp3xxx_ehci, + stmp3xxx_rtc, + stmp3xxx_spi1, + stmp3xxx_spi2, + stmp3xxx_backlight, + stmp3xxx_rotdec, + stmp3xxx_dcp, + stmp3xxx_dcp_bootstream, + stmp3xxx_persistent, + stmp3xxx_framebuffer, + stmp3xxx_battery; +int stmp3xxx_ssp1_device_register(void); +int stmp3xxx_ssp2_device_register(void); struct pin_group; void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label); -- cgit v1.2.3-70-g09d2