From 5f47c38704e15f9db356dd799391bc9f9efc4e0c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 15 Mar 2014 23:07:07 +0000 Subject: ARM: l2c: add decode for L2C-220 cache ways Rather than assuming these are always 8-way, it can be decoded from the auxillary register in the same manner as L2C-210. Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b4dd2f4b491..69a18316b23 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -701,6 +701,7 @@ static void __init __l2c_init(const struct l2c_init_data *data, break; case L2X0_CACHE_ID_PART_L210: + case L2X0_CACHE_ID_PART_L220: ways = (aux >> 13) & 0xf; break; -- cgit v1.2.3-70-g09d2