From 59b479e0985f0b795d68331d6443a7f89c47768d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 27 Jan 2011 16:39:40 -0800 Subject: omap: Start using CONFIG_SOC_OMAP We want to have just CONFIG_ARCH_OMAP2, 3 and 4. The rest are nowadays just subcategories of these. Search and replace the following: ARCH_OMAP2420 SOC_OMAP2420 ARCH_OMAP2430 SOC_OMAP2430 ARCH_OMAP3430 SOC_OMAP3430 No functional changes. Signed-off-by: Tony Lindgren Signed-off-by: Thomas Weber Acked-by: Sourav Poddar --- arch/arm/plat-omap/include/plat/cpu.h | 10 +++++----- arch/arm/plat-omap/include/plat/io.h | 4 ++-- arch/arm/plat-omap/include/plat/multi.h | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 3fd8b405572..73d91ee43de 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -170,11 +170,11 @@ IS_OMAP_SUBCLASS(443x, 0x443) # undef cpu_is_omap24xx # define cpu_is_omap24xx() is_omap24xx() # endif -# if defined (CONFIG_ARCH_OMAP2420) +# if defined (CONFIG_SOC_OMAP2420) # undef cpu_is_omap242x # define cpu_is_omap242x() is_omap242x() # endif -# if defined (CONFIG_ARCH_OMAP2430) +# if defined (CONFIG_SOC_OMAP2430) # undef cpu_is_omap243x # define cpu_is_omap243x() is_omap243x() # endif @@ -189,11 +189,11 @@ IS_OMAP_SUBCLASS(443x, 0x443) # undef cpu_is_omap24xx # define cpu_is_omap24xx() 1 # endif -# if defined(CONFIG_ARCH_OMAP2420) +# if defined(CONFIG_SOC_OMAP2420) # undef cpu_is_omap242x # define cpu_is_omap242x() 1 # endif -# if defined(CONFIG_ARCH_OMAP2430) +# if defined(CONFIG_SOC_OMAP2430) # undef cpu_is_omap243x # define cpu_is_omap243x() 1 # endif @@ -201,7 +201,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) # undef cpu_is_omap34xx # define cpu_is_omap34xx() 1 # endif -# if defined(CONFIG_ARCH_OMAP3430) +# if defined(CONFIG_SOC_OMAP3430) # undef cpu_is_omap343x # define cpu_is_omap343x() 1 # endif diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index ef4106c1318..478c5d9b2bd 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -259,7 +259,7 @@ struct omap_sdrc_params; extern void omap1_map_common_io(void); extern void omap1_init_common_hw(void); -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 extern void omap242x_map_common_io(void); #else static inline void omap242x_map_common_io(void) @@ -267,7 +267,7 @@ static inline void omap242x_map_common_io(void) } #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 extern void omap243x_map_common_io(void); #else static inline void omap243x_map_common_io(void) diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h index ffd909fa528..999ffba2690 100644 --- a/arch/arm/plat-omap/include/plat/multi.h +++ b/arch/arm/plat-omap/include/plat/multi.h @@ -66,7 +66,7 @@ # error "OMAP1 and OMAP2PLUS can't be selected at the same time" # endif #endif -#ifdef CONFIG_ARCH_OMAP2420 +#ifdef CONFIG_SOC_OMAP2420 # ifdef OMAP_NAME # undef MULTI_OMAP2 # define MULTI_OMAP2 @@ -74,7 +74,7 @@ # define OMAP_NAME omap2420 # endif #endif -#ifdef CONFIG_ARCH_OMAP2430 +#ifdef CONFIG_SOC_OMAP2430 # ifdef OMAP_NAME # undef MULTI_OMAP2 # define MULTI_OMAP2 -- cgit v1.2.3-70-g09d2 From 58dfaba789dbba34b86ed7dbe1aa648294d63f0b Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 27 Jan 2011 16:39:41 -0800 Subject: arm: omap1: fix compile warnings Fix the following compile warnings: arch/arm/mach-omap1/board-innovator.c:165:3: warning: initialization makes integer from pointer without a cast arch/arm/mach-omap1/board-perseus2.c:305:3: warning: initialization makes integer from pointer without a cast arch/arm/mach-omap1/board-fsample.c:338:3: warning: initialization makes integer from pointer without a cast Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/fpga.h | 92 +++++++++++++++++----------------- 1 file changed, 46 insertions(+), 46 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h index ae39bcb3f5b..bd3c6324ae1 100644 --- a/arch/arm/plat-omap/include/plat/fpga.h +++ b/arch/arm/plat-omap/include/plat/fpga.h @@ -30,18 +30,18 @@ extern void omap1510_fpga_init_irq(void); * --------------------------------------------------------------------------- */ /* maps in the FPGA registers and the ETHR registers */ -#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */ +#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ #define H2P2_DBG_FPGA_START 0x04000000 /* PA */ #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) -#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ -#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ -#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ -#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ -#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ -#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ -#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ +#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ +#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ +#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ +#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ +#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ +#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ +#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ /* NOTE: most boards don't have a static mapping for the FPGA ... */ struct h2p2_dbg_fpga { @@ -81,55 +81,55 @@ struct h2p2_dbg_fpga { * OMAP-1510 FPGA * --------------------------------------------------------------------------- */ -#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */ +#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ #define OMAP1510_FPGA_SIZE SZ_4K #define OMAP1510_FPGA_START 0x08000000 /* PA */ /* Revision */ -#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) -#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) +#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) +#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) -#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) -#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) -#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) -#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) +#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) +#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) +#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) +#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) /* Interrupt status */ -#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) -#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) +#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) +#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) /* Interrupt mask */ -#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) -#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) +#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) +#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) /* Reset registers */ -#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) -#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) - -#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) -#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) -#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) -#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) -#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) -#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) -#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) -#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) -#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) -#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) - -#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) - -#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) -#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) -#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) -#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) -#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) -#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) -#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) -#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) -#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) -#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) -#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) +#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) +#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) + +#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) +#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) +#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) +#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) +#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) +#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) +#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) +#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) +#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) +#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) + +#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) + +#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) +#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) +#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) +#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) +#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) +#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) +#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) +#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) +#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) +#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) +#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) -- cgit v1.2.3-70-g09d2 From ee54dba9c360944b34e06478c05c6f283bf64eda Mon Sep 17 00:00:00 2001 From: Russell King - ARM Linux Date: Thu, 27 Jan 2011 16:39:45 -0800 Subject: ARM: OMAP: Allow platforms to hook reset cleanly This adds a clean method to allow platforms to hook into the reset code if they require to. Signed-off-by: Russell King Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/Makefile | 2 +- arch/arm/mach-omap1/board-voiceblue.c | 106 +++++++++++++++++-------------- arch/arm/mach-omap1/reset.c | 25 ++++++++ arch/arm/mach-omap2/prcm.c | 5 +- arch/arm/plat-omap/include/plat/prcm.h | 1 - arch/arm/plat-omap/include/plat/system.h | 38 +---------- 6 files changed, 91 insertions(+), 86 deletions(-) create mode 100644 arch/arm/mach-omap1/reset.c (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index ba6009f2767..af98117043d 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o -obj-y += clock.o clock_data.o opp_data.o +obj-y += clock.o clock_data.o opp_data.o reset.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 815a69ce821..67128171409 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -163,52 +164,6 @@ static void __init voiceblue_init_irq(void) omap_init_irq(); } -static void __init voiceblue_init(void) -{ - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - /* Watchdog */ - gpio_request(0, "Watchdog"); - /* smc91x reset */ - gpio_request(7, "SMC91x reset"); - gpio_direction_output(7, 1); - udelay(2); /* wait at least 100ns */ - gpio_set_value(7, 0); - mdelay(50); /* 50ms until PHY ready */ - /* smc91x interrupt pin */ - gpio_request(8, "SMC91x irq"); - /* 16C554 reset*/ - gpio_request(6, "16C554 reset"); - gpio_direction_output(6, 0); - /* 16C554 interrupt pins */ - gpio_request(12, "16C554 irq"); - gpio_request(13, "16C554 irq"); - gpio_request(14, "16C554 irq"); - gpio_request(15, "16C554 irq"); - set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); - - platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); - omap_board_config = voiceblue_config; - omap_board_config_size = ARRAY_SIZE(voiceblue_config); - omap_serial_init(); - omap1_usb_init(&voiceblue_usb_config); - omap_register_i2c_bus(1, 100, NULL, 0); - - /* There is a good chance board is going up, so enable power LED - * (it is connected through invertor) */ - omap_writeb(0x00, OMAP_LPG1_LCR); - omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ -} - static void __init voiceblue_map_io(void) { omap1_map_common_io(); @@ -275,8 +230,17 @@ void voiceblue_wdt_ping(void) gpio_set_value(0, wdt_gpio_state); } -void voiceblue_reset(void) +static void voiceblue_reset(char mode, const char *cmd) { + /* + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 + * "Global Software Reset Affects Traffic Controller Frequency". + */ + if (cpu_is_omap5912()) { + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); + omap_writew(0x8, ARM_RSTCT1); + } + set_bit(MACHINE_REBOOT, &machine_state); voiceblue_wdt_enable(); while (1) ; @@ -286,6 +250,54 @@ EXPORT_SYMBOL(voiceblue_wdt_enable); EXPORT_SYMBOL(voiceblue_wdt_disable); EXPORT_SYMBOL(voiceblue_wdt_ping); +static void __init voiceblue_init(void) +{ + /* mux pins for uarts */ + omap_cfg_reg(UART1_TX); + omap_cfg_reg(UART1_RTS); + omap_cfg_reg(UART2_TX); + omap_cfg_reg(UART2_RTS); + omap_cfg_reg(UART3_TX); + omap_cfg_reg(UART3_RX); + + /* Watchdog */ + gpio_request(0, "Watchdog"); + /* smc91x reset */ + gpio_request(7, "SMC91x reset"); + gpio_direction_output(7, 1); + udelay(2); /* wait at least 100ns */ + gpio_set_value(7, 0); + mdelay(50); /* 50ms until PHY ready */ + /* smc91x interrupt pin */ + gpio_request(8, "SMC91x irq"); + /* 16C554 reset*/ + gpio_request(6, "16C554 reset"); + gpio_direction_output(6, 0); + /* 16C554 interrupt pins */ + gpio_request(12, "16C554 irq"); + gpio_request(13, "16C554 irq"); + gpio_request(14, "16C554 irq"); + gpio_request(15, "16C554 irq"); + set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); + set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); + + platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); + omap_board_config = voiceblue_config; + omap_board_config_size = ARRAY_SIZE(voiceblue_config); + omap_serial_init(); + omap1_usb_init(&voiceblue_usb_config); + omap_register_i2c_bus(1, 100, NULL, 0); + + /* There is a good chance board is going up, so enable power LED + * (it is connected through invertor) */ + omap_writeb(0x00, OMAP_LPG1_LCR); + omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ + + arch_reset = voiceblue_reset; +} + MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") /* Maintainer: Ladislav Michl */ .boot_params = 0x10000100, diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c new file mode 100644 index 00000000000..ad951ee6920 --- /dev/null +++ b/arch/arm/mach-omap1/reset.c @@ -0,0 +1,25 @@ +/* + * OMAP1 reset support + */ +#include +#include + +#include +#include +#include + +void omap1_arch_reset(char mode, const char *cmd) +{ + /* + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 + * "Global Software Reset Affects Traffic Controller Frequency". + */ + if (cpu_is_omap5912()) { + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); + omap_writew(0x8, ARM_RSTCT1); + } + + omap_writew(1, ARM_RSTCT1); +} + +void (*arch_reset)(char, const char *) = omap1_arch_reset; diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 679bcd28576..6be14389e4f 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -57,7 +58,7 @@ u32 omap_prcm_get_reset_sources(void) EXPORT_SYMBOL(omap_prcm_get_reset_sources); /* Resets clock rates and reboots the system. Only called from system.h */ -void omap_prcm_arch_reset(char mode, const char *cmd) +static void omap_prcm_arch_reset(char mode, const char *cmd) { s16 prcm_offs = 0; @@ -108,6 +109,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd) omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ } +void (*arch_reset)(char, const char *) = omap_prcm_arch_reset; + /** * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness * @reg: physical address of module IDLEST register diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index 2fdf8c80d39..267f43bb2a4 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h @@ -28,7 +28,6 @@ #define __ASM_ARM_ARCH_OMAP_PRCM_H u32 omap_prcm_get_reset_sources(void); -void omap_prcm_arch_reset(char mode, const char *cmd); int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, const char *name); diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h index d0a119f735b..c5fa9e92900 100644 --- a/arch/arm/plat-omap/include/plat/system.h +++ b/arch/arm/plat-omap/include/plat/system.h @@ -4,48 +4,14 @@ */ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H -#include -#include -#include - -#include - -#ifndef CONFIG_MACH_VOICEBLUE -#define voiceblue_reset() do {} while (0) -#else -extern void voiceblue_reset(void); -#endif +#include static inline void arch_idle(void) { cpu_do_idle(); } -static inline void omap1_arch_reset(char mode, const char *cmd) -{ - /* - * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 - * "Global Software Reset Affects Traffic Controller Frequency". - */ - if (cpu_is_omap5912()) { - omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), - DPLL_CTL); - omap_writew(0x8, ARM_RSTCT1); - } - - if (machine_is_voiceblue()) - voiceblue_reset(); - else - omap_writew(1, ARM_RSTCT1); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - if (!cpu_class_is_omap2()) - omap1_arch_reset(mode, cmd); - else - omap_prcm_arch_reset(mode, cmd); -} +extern void (*arch_reset)(char, const char *); #endif -- cgit v1.2.3-70-g09d2 From b6338bdc8305b27688a7feb8689e4ccfd42f0292 Mon Sep 17 00:00:00 2001 From: Jean Pihet Date: Wed, 2 Feb 2011 16:38:06 +0100 Subject: ARM: 6649/1: omap: use fncpy to copy the PM code functions to SRAM The new fncpy API is better suited* for copying some code to SRAM at runtime. This patch changes the ad-hoc code to the more generic fncpy API. *: 1. fncpy ensures that the thumb mode bit is propagated, 2. fncpy provides the security of type safety between the original function and the sram function pointer. Tested OK on OMAP3 in low power modes (RET/OFF) using omap2plus_defconfig with !CONFIG_THUMB2_KERNEL. Compile tested on OMAP1/2 using omap1_defconfig. Boot tested on OMAP1 & OMAP2 Tested OK with suspend/resume on OMAP2420/n810 Boots fine on osk5912 and n800 Signed-off-by: Jean Pihet Acked-by: Kevin Hilman Acked-by: Tony Lindgren Reviewed-by: Dave Martin Tested-by: Kevin Hilman Tested-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap1/pm.h | 6 +++--- arch/arm/mach-omap1/sleep.S | 3 +++ arch/arm/mach-omap1/sram.S | 1 + arch/arm/mach-omap2/pm.h | 2 +- arch/arm/mach-omap2/sleep24xx.S | 2 ++ arch/arm/mach-omap2/sleep34xx.S | 2 ++ arch/arm/mach-omap2/sram242x.S | 3 +++ arch/arm/mach-omap2/sram243x.S | 3 +++ arch/arm/mach-omap2/sram34xx.S | 1 + arch/arm/plat-omap/include/plat/sram.h | 14 +++++++++++++- arch/arm/plat-omap/sram.c | 14 +++++++++----- 11 files changed, 41 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index 56a647986ae..cd926dcb5e7 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h @@ -123,9 +123,9 @@ extern void allow_idle_sleep(void); extern void omap1_pm_idle(void); extern void omap1_pm_suspend(void); -extern void omap7xx_cpu_suspend(unsigned short, unsigned short); -extern void omap1510_cpu_suspend(unsigned short, unsigned short); -extern void omap1610_cpu_suspend(unsigned short, unsigned short); +extern void omap7xx_cpu_suspend(unsigned long, unsigned long); +extern void omap1510_cpu_suspend(unsigned long, unsigned long); +extern void omap1610_cpu_suspend(unsigned long, unsigned long); extern void omap7xx_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S index ef771ce8b03..c875bdc902c 100644 --- a/arch/arm/mach-omap1/sleep.S +++ b/arch/arm/mach-omap1/sleep.S @@ -58,6 +58,7 @@ */ #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) + .align 3 ENTRY(omap7xx_cpu_suspend) @ save registers on stack @@ -137,6 +138,7 @@ ENTRY(omap7xx_cpu_suspend_sz) #endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ #ifdef CONFIG_ARCH_OMAP15XX + .align 3 ENTRY(omap1510_cpu_suspend) @ save registers on stack @@ -211,6 +213,7 @@ ENTRY(omap1510_cpu_suspend_sz) #endif /* CONFIG_ARCH_OMAP15XX */ #if defined(CONFIG_ARCH_OMAP16XX) + .align 3 ENTRY(omap1610_cpu_suspend) @ save registers on stack diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S index 7724e520d07..692587d07ea 100644 --- a/arch/arm/mach-omap1/sram.S +++ b/arch/arm/mach-omap1/sram.S @@ -18,6 +18,7 @@ /* * Reprograms ULPD and CKCTL. */ + .align 3 ENTRY(omap1_sram_reprogram_clock) stmfd sp!, {r0 - r12, lr} @ save registers on stack diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 1c1b0ab5b97..39580e6060e 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -92,7 +92,7 @@ extern void omap24xx_idle_loop_suspend(void); extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, void __iomem *sdrc_power); extern void omap34xx_cpu_suspend(u32 *addr, int save_state); -extern void save_secure_ram_context(u32 *addr); +extern int save_secure_ram_context(u32 *addr); extern void omap3_save_scratchpad_contents(void); extern unsigned int omap24xx_idle_loop_suspend_sz; diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S index c7780cc8d91..b5071a47ec3 100644 --- a/arch/arm/mach-omap2/sleep24xx.S +++ b/arch/arm/mach-omap2/sleep24xx.S @@ -47,6 +47,7 @@ * Note: This code get's copied to internal SRAM at boot. When the OMAP * wakes up it continues execution at the point it went to sleep. */ + .align 3 ENTRY(omap24xx_idle_loop_suspend) stmfd sp!, {r0, lr} @ save registers on stack mov r0, #0 @ clear for mcr setup @@ -82,6 +83,7 @@ ENTRY(omap24xx_idle_loop_suspend_sz) * The DLL load value is not kept in RETENTION or OFF. It needs to be restored * at wake */ + .align 3 ENTRY(omap24xx_cpu_suspend) stmfd sp!, {r0 - r12, lr} @ save registers on stack mov r3, #0x0 @ clear for mcr call diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 98d8232808b..951a0be66cf 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -118,6 +118,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore) .text /* Function to call rom code to save secure ram context */ + .align 3 ENTRY(save_secure_ram_context) stmfd sp!, {r1-r12, lr} @ save registers on stack adr r3, api_params @ r3 points to parameters @@ -169,6 +170,7 @@ ENTRY(save_secure_ram_context_sz) * depending on the low power mode (non-OFF vs OFF modes), * cf. 'Resume path for xxx mode' comments. */ + .align 3 ENTRY(omap34xx_cpu_suspend) stmfd sp!, {r0-r12, lr} @ save registers on stack diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index 055310cc77d..ff9b9dbcb30 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -39,6 +39,7 @@ .text + .align 3 ENTRY(omap242x_sram_ddr_init) stmfd sp!, {r0 - r12, lr} @ save registers on stack @@ -143,6 +144,7 @@ ENTRY(omap242x_sram_ddr_init_sz) * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 */ + .align 3 ENTRY(omap242x_sram_reprogram_sdrc) stmfd sp!, {r0 - r10, lr} @ save registers on stack mov r3, #0x0 @ clear for mrc call @@ -238,6 +240,7 @@ ENTRY(omap242x_sram_reprogram_sdrc_sz) /* * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. */ + .align 3 ENTRY(omap242x_sram_set_prcm) stmfd sp!, {r0-r12, lr} @ regs to stack adr r4, pbegin @ addr of preload start diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index f9007580aea..76730209fa0 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -39,6 +39,7 @@ .text + .align 3 ENTRY(omap243x_sram_ddr_init) stmfd sp!, {r0 - r12, lr} @ save registers on stack @@ -143,6 +144,7 @@ ENTRY(omap243x_sram_ddr_init_sz) * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 */ + .align 3 ENTRY(omap243x_sram_reprogram_sdrc) stmfd sp!, {r0 - r10, lr} @ save registers on stack mov r3, #0x0 @ clear for mrc call @@ -238,6 +240,7 @@ ENTRY(omap243x_sram_reprogram_sdrc_sz) /* * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. */ + .align 3 ENTRY(omap243x_sram_set_prcm) stmfd sp!, {r0-r12, lr} @ regs to stack adr r4, pbegin @ addr of preload start diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 7f893a29d50..25011ca2145 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -111,6 +111,7 @@ * since it will cause the ARM MMU to attempt to walk the page tables. * These crashes may be intermittent. */ + .align 3 ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h index 9967d5e855c..f500fc34d06 100644 --- a/arch/arm/plat-omap/include/plat/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h @@ -12,7 +12,19 @@ #define __ARCH_ARM_OMAP_SRAM_H #ifndef __ASSEMBLY__ -extern void * omap_sram_push(void * start, unsigned long size); +#include + +extern void *omap_sram_push_address(unsigned long size); + +/* Macro to push a function to the internal SRAM, using the fncpy API */ +#define omap_sram_push(funcp, size) ({ \ + typeof(&(funcp)) _res = NULL; \ + void *_sram_address = omap_sram_push_address(size); \ + if (_sram_address) \ + _res = fncpy(_sram_address, &(funcp), size); \ + _res; \ +}) + extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index e26e50487d6..68fcc7dc56e 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -242,7 +242,14 @@ static void __init omap_map_sram(void) omap_sram_size - SRAM_BOOTLOADER_SZ); } -void * omap_sram_push(void * start, unsigned long size) +/* + * Memory allocator for SRAM: calculates the new ceiling address + * for pushing a function using the fncpy API. + * + * Note that fncpy requires the returned address to be aligned + * to an 8-byte boundary. + */ +void *omap_sram_push_address(unsigned long size) { if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) { printk(KERN_ERR "Not enough space in SRAM\n"); @@ -250,10 +257,7 @@ void * omap_sram_push(void * start, unsigned long size) } omap_sram_ceil -= size; - omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); - memcpy((void *)omap_sram_ceil, start, size); - flush_icache_range((unsigned long)omap_sram_ceil, - (unsigned long)(omap_sram_ceil + size)); + omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, FNCPY_ALIGN); return (void *)omap_sram_ceil; } -- cgit v1.2.3-70-g09d2 From 2354f64a24924f87ed74f6ff1a38be4b05938c04 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 9 Feb 2011 21:40:08 +0100 Subject: ARM: omap: move omap_get_config et al. to .init.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All callers of these functions live in .init.text, so these can go there, too. There they must not be exported anymore, this is no problem though, as all callers are always built-in. Signed-off-by: Uwe Kleine-König Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/common.c | 6 ++---- arch/arm/plat-omap/include/plat/board.h | 4 ++-- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index f0473182030..30c698e7a02 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -49,17 +49,15 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) return kinfo->data; } -const void *__omap_get_config(u16 tag, size_t len, int nr) +const void *__init __omap_get_config(u16 tag, size_t len, int nr) { return get_config(tag, len, nr, NULL); } -EXPORT_SYMBOL(__omap_get_config); -const void *omap_get_var_config(u16 tag, size_t *len) +const void *__init omap_get_var_config(u16 tag, size_t *len) { return get_config(tag, NO_LENGTH_CHECK, 0, len); } -EXPORT_SYMBOL(omap_get_var_config); void __init omap_reserve(void) { diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index 3cf4fa25ab3..97126dfd288 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h @@ -151,14 +151,14 @@ struct omap_board_config_kernel { const void *data; }; -extern const void *__omap_get_config(u16 tag, size_t len, int nr); +extern const void *__init __omap_get_config(u16 tag, size_t len, int nr); #define omap_get_config(tag, type) \ ((const type *) __omap_get_config((tag), sizeof(type), 0)) #define omap_get_nr_config(tag, type, nr) \ ((const type *) __omap_get_config((tag), sizeof(type), (nr))) -extern const void *omap_get_var_config(u16 tag, size_t *len); +extern const void *__init omap_get_var_config(u16 tag, size_t *len); extern struct omap_board_config_kernel *omap_board_config; extern int omap_board_config_size; -- cgit v1.2.3-70-g09d2 From 37cd4fef6ebfa76acc6ef6de911123739098cff4 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 4 Feb 2011 09:15:09 +0000 Subject: omap: McBSP: Remove unused audio macros in mcbsp.h Some macros defined in mcbsp.h related to audio, which are never being used is removed. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Charulatha V Cc: Jarkko Nikula Acked-by: Jarkko Nikula Acked-by: Peter Ujfalusi Acked-by: G, Manjunath Kondaiah Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/mcbsp.h | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index b87d83ccd54..6ecf1051e5f 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -106,13 +106,6 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP_MCBSP_REG_XCCR 0x00 #define OMAP_MCBSP_REG_RCCR 0x00 -#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) -#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) - -#define AUDIO_MCBSP OMAP_MCBSP1 -#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX -#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX - #else #define OMAP_MCBSP_REG_DRR2 0x00 @@ -168,13 +161,6 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP_ST_REG_SFIRCR 0x28 #define OMAP_ST_REG_SSELCR 0x2C -#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) -#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) - -#define AUDIO_MCBSP OMAP_MCBSP2 -#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX -#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX - #endif /************************** McBSP SPCR1 bit definitions ***********************/ -- cgit v1.2.3-70-g09d2 From 44dc046e93eb98d41048954f700b1927f7e288ed Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Feb 2011 15:40:20 -0800 Subject: omap2+: Make omap_hwmod_late_init into core_initcall Otherwise things will fail with early_init changes. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 2 -- arch/arm/mach-omap2/omap_hwmod.c | 3 ++- arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 - 3 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c2032041d26..f89173ab4ab 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -400,8 +400,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, { omap_serial_early_init(); - omap_hwmod_late_init(); - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e282e35769f..eacdfd3a14d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1628,7 +1628,7 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs) * to struct clk pointers for each registered omap_hwmod. Also calls * _setup() on each hwmod. Returns 0. */ -int omap_hwmod_late_init(void) +static int __init omap_hwmod_late_init(void) { int r; @@ -1644,6 +1644,7 @@ int omap_hwmod_late_init(void) return 0; } +core_initcall(omap_hwmod_late_init); /** * omap_hwmod_enable - enable an omap_hwmod diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 1eee85a8abb..fedd82971c9 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -539,7 +539,6 @@ int omap_hwmod_init(struct omap_hwmod **ohs); struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); -int omap_hwmod_late_init(void); int omap_hwmod_enable(struct omap_hwmod *oh); int _omap_hwmod_enable(struct omap_hwmod *oh); -- cgit v1.2.3-70-g09d2 From 3e16f92536334ccb464ed88cf4d8cc0dd43da106 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 14 Feb 2011 15:40:20 -0800 Subject: omap2+: Fix omap_serial_early_init to work with init_early hook The new init_early hook happens at the end of setup_arch, which is too early for kzalloc. However, there's no need to call omap_serial_early_init that early, so fix this by setting it up as a core_initcall. Signed-off-by: Tony Lindgren Tested-by: Kevin Hilman --- arch/arm/mach-omap2/io.c | 2 -- arch/arm/mach-omap2/serial.c | 7 +++++-- arch/arm/plat-omap/include/plat/serial.h | 1 - 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index f89173ab4ab..26a61cf2729 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -398,8 +398,6 @@ void __init omap2_init_common_infrastructure(void) void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { - omap_serial_early_init(); - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 32e91a9c8b6..74e25cd4bd3 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -655,7 +655,7 @@ static void serial_out_override(struct uart_port *up, int offset, int value) } #endif -void __init omap_serial_early_init(void) +static int __init omap_serial_early_init(void) { int i = 0; @@ -672,7 +672,7 @@ void __init omap_serial_early_init(void) uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); if (WARN_ON(!uart)) - return; + return -ENODEV; uart->oh = oh; uart->num = i++; @@ -691,7 +691,10 @@ void __init omap_serial_early_init(void) */ uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; } while (1); + + return 0; } +core_initcall(omap_serial_early_init); /** * omap_serial_init_port() - initialize single serial port diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index cec5d56db2e..a1a118d052e 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -96,7 +96,6 @@ struct omap_board_data; -extern void __init omap_serial_early_init(void); extern void omap_serial_init(void); extern void omap_serial_init_port(struct omap_board_data *bdata); extern int omap_uart_can_sleep(void); -- cgit v1.2.3-70-g09d2 From 4bd7be22f4b25fc87e236a29da3a625621699074 Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Wed, 16 Feb 2011 08:31:39 -0800 Subject: TI816X: Update common omap platform files This patch updates the common platform files with TI816X support. The approach taken in this patch is to add TI816X as part of OMAP3 variant where the cpu class is considered as OMAP34XX and the type is TI816X. This means, both cpu_is_omap34xx() and cpu_is_ti816x() checks return success on TI816X. A kernel config option CONFIG_SOC_OMAPTI816X is added under OMAP3 to include support for TI816X build. Signed-off-by: Hemant Pedanekar Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 5 +++++ arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 + arch/arm/plat-omap/include/plat/clock.h | 1 + arch/arm/plat-omap/include/plat/common.h | 1 + arch/arm/plat-omap/include/plat/cpu.h | 18 ++++++++++++++++++ 5 files changed, 26 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1a2cf6226a5..23548b60bb1 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -72,6 +72,11 @@ config ARCH_OMAP3430 default y select ARCH_OMAP_OTG +config SOC_OMAPTI816X + bool "TI816X support" + depends on ARCH_OMAP3 + default y + config OMAP_PACKAGE_ZAF bool diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 256ab3f1ec8..f1899a3e417 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -38,6 +38,7 @@ struct omap_clk { #define CK_3517 (1 << 9) #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ #define CK_443X (1 << 11) +#define CK_TI816X (1 << 12) #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 8eb0adab19e..d43e6234dbb 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -53,6 +53,7 @@ struct clkops { #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ #define RATE_IN_36XX (1 << 4) #define RATE_IN_4430 (1 << 5) +#define RATE_IN_TI816X (1 << 6) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 29b2afb4288..1dd97e7461c 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -66,6 +66,7 @@ void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_3xxx(void); void omap2_set_globals_443x(void); +void omap2_set_globals_ti816x(void); /* These get called from omap2_set_globals_xxxx(), do not call these */ void omap2_set_globals_tap(struct omap_globals *); diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 3fd8b405572..ac7dcd9a80c 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -105,6 +105,12 @@ static inline int is_omap ##subclass (void) \ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ } +#define IS_TI_SUBCLASS(subclass, id) \ +static inline int is_ti ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + IS_OMAP_CLASS(7xx, 0x07) IS_OMAP_CLASS(15xx, 0x15) IS_OMAP_CLASS(16xx, 0x16) @@ -118,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343) IS_OMAP_SUBCLASS(363x, 0x363) IS_OMAP_SUBCLASS(443x, 0x443) +IS_TI_SUBCLASS(816x, 0x816) + #define cpu_is_omap7xx() 0 #define cpu_is_omap15xx() 0 #define cpu_is_omap16xx() 0 @@ -126,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443) #define cpu_is_omap243x() 0 #define cpu_is_omap34xx() 0 #define cpu_is_omap343x() 0 +#define cpu_is_ti816x() 0 #define cpu_is_omap44xx() 0 #define cpu_is_omap443x() 0 @@ -330,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517) # undef cpu_is_omap3530 # undef cpu_is_omap3505 # undef cpu_is_omap3517 +# undef cpu_is_ti816x # define cpu_is_omap3430() is_omap3430() # define cpu_is_omap3503() (cpu_is_omap3430() && \ (!omap3_has_iva()) && \ @@ -345,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517) # define cpu_is_omap3517() is_omap3517() # undef cpu_is_omap3630 # define cpu_is_omap3630() is_omap363x() +# define cpu_is_ti816x() is_ti816x() #endif # if defined(CONFIG_ARCH_OMAP4) @@ -389,6 +400,10 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) +#define TI816X_CLASS 0x81600034 +#define TI8168_REV_ES1_0 TI816X_CLASS +#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) + #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 OMAP443X_CLASS #define OMAP4430_REV_ES2_0 0x44301044 @@ -419,6 +434,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP4430ES2 (1 << 11) +#define CHIP_IS_TI816X (1 << 14) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) @@ -455,6 +471,7 @@ extern u32 omap3_features; #define OMAP3_HAS_ISP BIT(4) #define OMAP3_HAS_192MHZ_CLK BIT(5) #define OMAP3_HAS_IO_WAKEUP BIT(6) +#define OMAP3_HAS_SDRC BIT(7) #define OMAP3_HAS_FEATURE(feat,flag) \ static inline unsigned int omap3_has_ ##feat(void) \ @@ -469,5 +486,6 @@ OMAP3_HAS_FEATURE(neon, NEON) OMAP3_HAS_FEATURE(isp, ISP) OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) +OMAP3_HAS_FEATURE(sdrc, SDRC) #endif -- cgit v1.2.3-70-g09d2 From 01001712c96f82e6317b1e09729d8fc4bcc66957 Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Wed, 16 Feb 2011 08:31:39 -0800 Subject: TI816X: Update common OMAP machine specific sources This patch updates the common machine specific source files with support for TI816X. Signed-off-by: Hemant Pedanekar Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock3xxx_data.c | 5 +++- arch/arm/mach-omap2/common.c | 21 ++++++++++++++++ arch/arm/mach-omap2/control.h | 6 +++++ arch/arm/mach-omap2/id.c | 33 ++++++++++++++++++++++++-- arch/arm/mach-omap2/include/mach/entry-macro.S | 13 ++++++++++ arch/arm/mach-omap2/io.c | 22 ++++++++++++++++- arch/arm/mach-omap2/irq.c | 5 +++- arch/arm/mach-omap2/serial.c | 8 +++---- arch/arm/plat-omap/include/plat/hardware.h | 1 + arch/arm/plat-omap/include/plat/io.h | 8 +++++++ arch/arm/plat-omap/include/plat/ti816x.h | 27 +++++++++++++++++++++ arch/arm/plat-omap/io.c | 5 +++- 12 files changed, 144 insertions(+), 10 deletions(-) create mode 100644 arch/arm/plat-omap/include/plat/ti816x.h (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 403a4a1d3f9..f14d986f0b5 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3471,6 +3471,9 @@ int __init omap3xxx_clk_init(void) } else if (cpu_is_omap3630()) { cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); cpu_clkflg = CK_36XX; + } else if (cpu_is_ti816x()) { + cpu_mask = RATE_IN_TI816X; + cpu_clkflg = CK_TI816X; } else if (cpu_is_omap34xx()) { if (omap_rev() == OMAP3430_REV_ES1_0) { cpu_mask = RATE_IN_3430ES1; @@ -3550,7 +3553,7 @@ int __init omap3xxx_clk_init(void) /* * Lock DPLL5 and put it in autoidle. */ - if (omap_rev() >= OMAP3430_REV_ES2_0) + if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 778929f7e92..79fb948f814 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -108,6 +108,27 @@ void __init omap3_map_io(void) omap2_set_globals_3xxx(); omap34xx_map_common_io(); } + +/* + * Adjust TAP register base such that omap3_check_revision accesses the correct + * TI816X register for checking device ID (it adds 0x204 to tap base while + * TI816X DEVICE ID register is at offset 0x600 from control base). + */ +#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \ + TI816X_CONTROL_DEVICE_ID - 0x204) + +static struct omap_globals ti816x_globals = { + .class = OMAP343X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), + .ctrl = TI816X_CTRL_BASE, + .prm = TI816X_PRCM_BASE, + .cm = TI816X_PRCM_BASE, +}; + +void __init omap2_set_globals_ti816x(void) +{ + __omap2_set_globals(&ti816x_globals); +} #endif #if defined(CONFIG_ARCH_OMAP4) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index f0629ae0410..c2804c1c4ef 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -52,6 +52,9 @@ #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 +/* TI816X spefic control submodules */ +#define TI816X_CONTROL_DEVCONF 0x600 + /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) @@ -241,6 +244,9 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 +/* TI816X CONTROL_DEVCONF register offsets */ +#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000) + /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 5f9086c65e4..5c25f1b5523 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -191,12 +191,19 @@ static void __init omap3_check_features(void) if (!cpu_is_omap3505() && !cpu_is_omap3517()) omap3_features |= OMAP3_HAS_IO_WAKEUP; + omap3_features |= OMAP3_HAS_SDRC; + /* * TODO: Get additional info (where applicable) * e.g. Size of L2 cache. */ } +static void __init ti816x_check_features(void) +{ + omap3_features = OMAP3_HAS_NEON; +} + static void __init omap3_check_revision(void) { u32 cpuid, idcode; @@ -287,6 +294,20 @@ static void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; } break; + case 0xb81e: + omap_chip.oc = CHIP_IS_TI816X; + + switch (rev) { + case 0: + omap_revision = TI8168_REV_ES1_0; + break; + case 1: + omap_revision = TI8168_REV_ES1_1; + break; + default: + omap_revision = TI8168_REV_ES1_1; + } + break; default: /* Unknown default to latest silicon rev as default*/ omap_revision = OMAP3630_REV_ES1_2; @@ -372,6 +393,8 @@ static void __init omap3_cpuinfo(void) /* Already set in omap3_check_revision() */ strcpy(cpu_name, "AM3505"); } + } else if (cpu_is_ti816x()) { + strcpy(cpu_name, "TI816X"); } else if (omap3_has_iva() && omap3_has_sgx()) { /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ strcpy(cpu_name, "OMAP3430/3530"); @@ -386,7 +409,7 @@ static void __init omap3_cpuinfo(void) strcpy(cpu_name, "OMAP3503"); } - if (cpu_is_omap3630()) { + if (cpu_is_omap3630() || cpu_is_ti816x()) { switch (rev) { case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); @@ -462,7 +485,13 @@ void __init omap2_check_revision(void) omap24xx_check_revision(); } else if (cpu_is_omap34xx()) { omap3_check_revision(); - omap3_check_features(); + + /* TI816X doesn't have feature register */ + if (!cpu_is_ti816x()) + omap3_check_features(); + else + ti816x_check_features(); + omap3_cpuinfo(); return; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 81985a665cb..a48690b9099 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S @@ -61,6 +61,14 @@ bne 9998f ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ cmp \irqnr, #0x0 + bne 9998f + + /* + * ti816x has additional IRQ pending register. Checking this + * register on omap2 & omap3 has no effect (read as 0). + */ + ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ + cmp \irqnr, #0x0 9998: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ @@ -133,6 +141,11 @@ bne 9999f ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ cmp \irqnr, #0x0 +#ifdef CONFIG_SOC_OMAPTI816X + bne 9999f + ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ + cmp \irqnr, #0x0 +#endif 9999: ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 26a61cf2729..f992a81c393 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -175,6 +175,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = { #endif }; #endif + +#ifdef CONFIG_SOC_OMAPTI816X +static struct map_desc omapti816x_io_desc[] __initdata = { + { + .virtual = L4_34XX_VIRT, + .pfn = __phys_to_pfn(L4_34XX_PHYS), + .length = L4_34XX_SIZE, + .type = MT_DEVICE + }, +}; +#endif + #ifdef CONFIG_ARCH_OMAP4 static struct map_desc omap44xx_io_desc[] __initdata = { { @@ -267,6 +279,14 @@ void __init omap34xx_map_common_io(void) } #endif +#ifdef CONFIG_SOC_OMAPTI816X +void __init omapti816x_map_common_io(void) +{ + iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); + _omap2_map_common_io(); +} +#endif + #ifdef CONFIG_ARCH_OMAP4 void __init omap44xx_map_common_io(void) { @@ -398,7 +418,7 @@ void __init omap2_init_common_infrastructure(void) void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + if (cpu_is_omap24xx() || omap3_has_sdrc()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); } diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 23049c487c4..0b9a23d721f 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -110,7 +110,7 @@ static void omap_mask_irq(struct irq_data *d) unsigned int irq = d->irq; int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() && !cpu_is_ti816x()) { int spurious = 0; /* @@ -205,6 +205,9 @@ void __init omap_init_irq(void) BUG_ON(!base); + if (cpu_is_ti816x()) + bank->nr_irqs = 128; + /* Static mapping, never released */ bank->base_reg = ioremap(base, SZ_4K); if (!bank->base_reg) { diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 74e25cd4bd3..47eef48b883 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) mod_timer(&uart->timer, jiffies + uart->timeout); omap_uart_smart_idle_enable(uart, 0); - if (cpu_is_omap34xx()) { + if (cpu_is_omap34xx() && !cpu_is_ti816x()) { u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; u32 wk_mask = 0; u32 padconf = 0; @@ -762,13 +762,13 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) p->private_data = uart; /* - * omap44xx: Never read empty UART fifo + * omap44xx, ti816x: Never read empty UART fifo * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ uart->regshift = p->regshift; uart->membase = p->membase; - if (cpu_is_omap44xx()) + if (cpu_is_omap44xx() || cpu_is_ti816x()) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) @@ -850,7 +850,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata) } /* Enable the MDR1 errata for OMAP3 */ - if (cpu_is_omap34xx()) + if (cpu_is_omap34xx() && !cpu_is_ti816x()) uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; } diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index d5b26adfb89..e87efe1499b 100644 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -286,5 +286,6 @@ #include #include #include +#include #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index ef4106c1318..427fc8a7c07 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h @@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void) } #endif +#ifdef CONFIG_SOC_OMAPTI816X +extern void omapti816x_map_common_io(void); +#else +static inline void omapti816x_map_common_io(void) +{ +} +#endif + #ifdef CONFIG_ARCH_OMAP4 extern void omap44xx_map_common_io(void); #else diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h new file mode 100644 index 00000000000..50510f5dda1 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/ti816x.h @@ -0,0 +1,27 @@ +/* + * This file contains the address data for various TI816X modules. + * + * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_TI816X_H +#define __ASM_ARCH_TI816X_H + +#define L4_SLOW_TI816X_BASE 0x48000000 + +#define TI816X_SCM_BASE 0x48140000 +#define TI816X_CTRL_BASE TI816X_SCM_BASE +#define TI816X_PRCM_BASE 0x48180000 + +#define TI816X_ARM_INTC_BASE 0x48200000 + +#endif /* __ASM_ARCH_TI816X_H */ diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index f1295fafcd3..f1ecfa9fc61 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c @@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) } #endif #ifdef CONFIG_ARCH_OMAP3 - if (cpu_is_omap34xx()) { + if (cpu_is_ti816x()) { + if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) + return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); + } else if (cpu_is_omap34xx()) { if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE)) return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) -- cgit v1.2.3-70-g09d2 From 4d887a250d6294d4e17851da46d6eab4de83c91e Mon Sep 17 00:00:00 2001 From: Hemant Pedanekar Date: Tue, 15 Feb 2011 23:06:17 +0530 Subject: TI816X: Add low level debug support This patch adds support for low level debugging on TI816X boards. Currently the support for UART3 console on TI816X EVM is added. Signed-off-by: Hemant Pedanekar Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/debug-macro.S | 12 ++++++++++++ arch/arm/plat-omap/include/plat/serial.h | 8 ++++++++ arch/arm/plat-omap/include/plat/uncompress.h | 7 +++++++ 3 files changed, 27 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 6a4d4136002..e1b0f17b092 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -69,6 +69,12 @@ omap_uart_lsr: .word 0 beq 34f @ configure OMAP3UART4 cmp \rp, #OMAP4UART4 @ only on 44xx beq 44f @ configure OMAP4UART4 + cmp \rp, #TI816XUART1 @ ti816x UART offsets different + beq 81f @ configure UART1 + cmp \rp, #TI816XUART2 @ ti816x UART offsets different + beq 82f @ configure UART2 + cmp \rp, #TI816XUART3 @ ti816x UART offsets different + beq 83f @ configure UART3 cmp \rp, #ZOOM_UART @ only on zoom2/3 beq 95f @ configure ZOOM_UART @@ -91,6 +97,12 @@ omap_uart_lsr: .word 0 b 98f 44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) b 98f +81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE) + b 98f +82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE) + b 98f +83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) + b 98f 95: ldr \rp, =ZOOM_UART_BASE mrc p15, 0, \rv, c1, c0 tst \rv, #1 @ MMU enabled? diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index a1a118d052e..8061695aa52 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -51,6 +51,11 @@ #define OMAP4_UART3_BASE 0x48020000 #define OMAP4_UART4_BASE 0x4806e000 +/* TI816X serial ports */ +#define TI816X_UART1_BASE 0x48020000 +#define TI816X_UART2_BASE 0x48022000 +#define TI816X_UART3_BASE 0x48024000 + /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 @@ -81,6 +86,9 @@ #define OMAP4UART2 OMAP2UART2 #define OMAP4UART3 43 #define OMAP4UART4 44 +#define TI816XUART1 81 +#define TI816XUART2 82 +#define TI816XUART3 83 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ad98b85cae2..30b891c4a93 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -93,6 +93,10 @@ static inline void flush(void) #define DEBUG_LL_ZOOM(mach) \ _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) +#define DEBUG_LL_TI816X(p, mach) \ + _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \ + TI816XUART##p) + static inline void __arch_decomp_setup(unsigned long arch_id) { int port = 0; @@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_ZOOM(omap_zoom2); DEBUG_LL_ZOOM(omap_zoom3); + /* TI8168 base boards using UART3 */ + DEBUG_LL_TI816X(3, ti8168evm); + } while (0); } -- cgit v1.2.3-70-g09d2 From fe5a4901c20c09b4380b7d4a0197efb6489c4ce8 Mon Sep 17 00:00:00 2001 From: Hema HK Date: Wed, 16 Feb 2011 17:34:40 +0530 Subject: usb: musb: AM35x: moving internal phy functions out of usb_musb.c file Moved all the board specific internal PHY functions out of usb_musb.c file as this file is shared between the OMAP2+ and AM35xx platforms. There exists a file which has the functions specific to internal PHY used for OMAP4 platform. Moved all phy specific functions to this file and passing these functions through board data in the board file. Signed-off-by: Hema HK Cc: Paul Walmsley Cc: Tony Lindgren Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/board-am3517evm.c | 4 ++ arch/arm/mach-omap2/omap_phy_internal.c | 93 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/usb-musb.c | 97 --------------------------------- arch/arm/plat-omap/include/plat/usb.h | 4 ++ 5 files changed, 103 insertions(+), 98 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1c0c2b02d87..43d4e14d0ec 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -218,7 +218,8 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ hsmmc.o \ omap_phy_internal.o -obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o +obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \ + omap_phy_internal.o \ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 10d60b7743c..3413bf993c7 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -409,6 +409,10 @@ static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_ULPI, .mode = MUSB_OTG, .power = 500, + .set_phy_power = am35x_musb_phy_power, + .clear_irq = am35x_musb_clear_irq, + .set_mode = am35x_musb_set_mode, + .reset = am35x_musb_reset, }; static __init void am3517_evm_musb_init(void) diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index 745252c60e3..f172ec06c06 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -29,6 +29,7 @@ #include #include +#include "control.h" /* OMAP control module register for UTMI PHY */ #define CONTROL_DEV_CONF 0x300 @@ -147,3 +148,95 @@ int omap4430_phy_exit(struct device *dev) return 0; } + +void am35x_musb_reset(void) +{ + u32 regval; + + /* Reset the musb interface */ + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); + + regval |= AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval &= ~AM35XX_USBOTGSS_SW_RST; + omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); + + regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); +} + +void am35x_musb_phy_power(u8 on) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(100); + u32 devconf2; + + if (on) { + /* + * Start the on-chip PHY and its PLL. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); + devconf2 |= CONF2_PHY_PLLON; + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + + pr_info(KERN_INFO "Waiting for PHY clock good...\n"); + while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) + & CONF2_PHYCLKGD)) { + cpu_relax(); + + if (time_after(jiffies, timeout)) { + pr_err(KERN_ERR "musb PHY clock good timed out\n"); + break; + } + } + } else { + /* + * Power down the on-chip PHY. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_PHY_PLLON; + devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + } +} + +void am35x_musb_clear_irq(void) +{ + u32 regval; + + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); + regval |= AM35XX_USBOTGSS_INT_CLR; + omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); + regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); +} + +void am35x_musb_set_mode(u8 musb_mode) +{ + u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + devconf2 &= ~CONF2_OTGMODE; + switch (musb_mode) { +#ifdef CONFIG_USB_MUSB_HDRC_HCD + case MUSB_HOST: /* Force VBUS valid, ID = 0 */ + devconf2 |= CONF2_FORCE_HOST; + break; +#endif +#ifdef CONFIG_USB_GADGET_MUSB_HDRC + case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ + devconf2 |= CONF2_FORCE_DEVICE; + break; +#endif +#ifdef CONFIG_USB_MUSB_OTG + case MUSB_OTG: /* Don't override the VBUS/ID comparators */ + devconf2 |= CONF2_NO_OVERRIDE; + break; +#endif + default: + pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); + } + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); +} diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 5298949d4b1..9107883287f 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -30,102 +30,9 @@ #include #include #include -#include "control.h" #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) -static void am35x_musb_reset(void) -{ - u32 regval; - - /* Reset the musb interface */ - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); - - regval |= AM35XX_USBOTGSS_SW_RST; - omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); - - regval &= ~AM35XX_USBOTGSS_SW_RST; - omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); - - regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); -} - -static void am35x_musb_phy_power(u8 on) -{ - unsigned long timeout = jiffies + msecs_to_jiffies(100); - u32 devconf2; - - if (on) { - /* - * Start the on-chip PHY and its PLL. - */ - devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); - devconf2 |= CONF2_PHY_PLLON; - - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); - - pr_info(KERN_INFO "Waiting for PHY clock good...\n"); - while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) - & CONF2_PHYCLKGD)) { - cpu_relax(); - - if (time_after(jiffies, timeout)) { - pr_err(KERN_ERR "musb PHY clock good timed out\n"); - break; - } - } - } else { - /* - * Power down the on-chip PHY. - */ - devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~CONF2_PHY_PLLON; - devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); - } -} - -static void am35x_musb_clear_irq(void) -{ - u32 regval; - - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); - regval |= AM35XX_USBOTGSS_INT_CLR; - omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); - regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -} - -static void am35x_musb_set_mode(u8 musb_mode) -{ - u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); - - devconf2 &= ~CONF2_OTGMODE; - switch (musb_mode) { -#ifdef CONFIG_USB_MUSB_HDRC_HCD - case MUSB_HOST: /* Force VBUS valid, ID = 0 */ - devconf2 |= CONF2_FORCE_HOST; - break; -#endif -#ifdef CONFIG_USB_GADGET_MUSB_HDRC - case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ - devconf2 |= CONF2_FORCE_DEVICE; - break; -#endif -#ifdef CONFIG_USB_MUSB_OTG - case MUSB_OTG: /* Don't override the VBUS/ID comparators */ - devconf2 |= CONF2_NO_OVERRIDE; - break; -#endif - default: - pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); - } - - omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -} - static struct resource musb_resources[] = { [0] = { /* start and end set dynamically */ .flags = IORESOURCE_MEM, @@ -189,10 +96,6 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) musb_device.name = "musb-am35x"; musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; musb_resources[1].start = INT_35XX_USBOTG_IRQ; - board_data->set_phy_power = am35x_musb_phy_power; - board_data->clear_irq = am35x_musb_clear_irq; - board_data->set_mode = am35x_musb_set_mode; - board_data->reset = am35x_musb_reset; } else if (cpu_is_omap34xx()) { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 450a332f100..077192759af 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -91,6 +91,10 @@ extern int omap4430_phy_exit(struct device *dev); #endif +extern void am35x_musb_reset(void); +extern void am35x_musb_phy_power(u8 on); +extern void am35x_musb_clear_irq(void); +extern void am35x_musb_set_mode(u8 musb_mode); /* * FIXME correct answer depends on hmc_mode, -- cgit v1.2.3-70-g09d2 From 617871deacea4e1a5713dd37564dc94a392d80c3 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 17 Feb 2011 09:53:09 -0800 Subject: OMAP2420: hwmod data: Add McSPI Update the omap2420 hwmod data with the McSPI info. Add a device attribute structure which will be used for passing number of chipselects from hwmod data. Add revision macros to be passed from rev field from hwmod. Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Grant Likely Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 156 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcspi.h | 8 ++ 2 files changed, 164 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index b85c630b64d..7fffd340c76 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -44,6 +45,8 @@ static struct omap_hwmod omap2420_gpio2_hwmod; static struct omap_hwmod omap2420_gpio3_hwmod; static struct omap_hwmod omap2420_gpio4_hwmod; static struct omap_hwmod omap2420_dma_system_hwmod; +static struct omap_hwmod omap2420_mcspi1_hwmod; +static struct omap_hwmod omap2420_mcspi2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -88,6 +91,42 @@ static struct omap_hwmod omap2420_uart3_hwmod; static struct omap_hwmod omap2420_i2c1_hwmod; static struct omap_hwmod omap2420_i2c2_hwmod; +/* l4 core -> mcspi1 interface */ +static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { + { + .pa_start = 0x48098000, + .pa_end = 0x480980ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi1_hwmod, + .clk = "mcspi1_ick", + .addr = omap2420_mcspi1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4 core -> mcspi2 interface */ +static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { + { + .pa_start = 0x4809a000, + .pa_end = 0x4809a0ff, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_mcspi2_hwmod, + .clk = "mcspi2_ick", + .addr = omap2420_mcspi2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { .master = &omap2420_l4_core_hwmod, @@ -864,6 +903,119 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * 'mcspi' class + * multichannel serial port interface (mcspi) / master/slave synchronous serial + * bus + */ + +static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_mcspi_class = { + .name = "mcspi", + .sysc = &omap2420_mcspi_sysc, + .rev = OMAP2_MCSPI_REV, +}; + +/* mcspi1 */ +static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { + { .irq = 65 }, +}; + +static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { + { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ + { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ + { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ + { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ + { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ + { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ + { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ + { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { + &omap2420_l4_core__mcspi1, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod omap2420_mcspi1_hwmod = { + .name = "mcspi1_hwmod", + .mpu_irqs = omap2420_mcspi1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), + .sdma_reqs = omap2420_mcspi1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), + .main_clk = "mcspi1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, + }, + }, + .slaves = omap2420_mcspi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), + .class = &omap2420_mcspi_class, + .dev_attr = &omap_mcspi1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* mcspi2 */ +static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { + { .irq = 66 }, +}; + +static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { + { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ + { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ + { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ + { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ +}; + +static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { + &omap2420_l4_core__mcspi2, +}; + +static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod omap2420_mcspi2_hwmod = { + .name = "mcspi2_hwmod", + .mpu_irqs = omap2420_mcspi2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), + .sdma_reqs = omap2420_mcspi2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), + .main_clk = "mcspi2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, + }, + }, + .slaves = omap2420_mcspi2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), + .class = &omap2420_mcspi_class, + .dev_attr = &omap_mcspi2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, @@ -885,6 +1037,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { /* dma_system class*/ &omap2420_dma_system_hwmod, + + /* mcspi class */ + &omap2420_mcspi1_hwmod, + &omap2420_mcspi2_hwmod, NULL, }; diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h index 1254e4945b6..560e266da8a 100644 --- a/arch/arm/plat-omap/include/plat/mcspi.h +++ b/arch/arm/plat-omap/include/plat/mcspi.h @@ -1,10 +1,18 @@ #ifndef _OMAP2_MCSPI_H #define _OMAP2_MCSPI_H +#define OMAP2_MCSPI_REV 0 +#define OMAP3_MCSPI_REV 1 +#define OMAP4_MCSPI_REV 2 + struct omap2_mcspi_platform_config { unsigned short num_cs; }; +struct omap2_mcspi_dev_attr { + unsigned short num_chipselect; +}; + struct omap2_mcspi_device_config { unsigned turbo_mode:1; -- cgit v1.2.3-70-g09d2 From 1a5d81905aec1536783fb6ab875f31910f449941 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Wed, 2 Feb 2011 17:52:14 +0530 Subject: OMAP: devices: Modify McSPI device to adapt to hwmod framework Cleans up all base address definitions for omap_mcspi and adapts the device registration and driver to hwmod framework. Changes involves: 1) Removing all base address macro defines. 2) Using omap-device layer to register device and utilizing data from hwmod data file for base address, dma channel number, Irq_number, device attribute(number of chipselect). 3) Appending base address with pdata reg_offset for omap4 boards. For omap4 all regs used in driver deviate with reg_offset_macros defined with an value of 0x100. So pass this offset through pdata and append the same to base address retrieved from hwmod data file and we are not mapping *_HL_* regs which are not used in driver. Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Grant Likely Reviewed-by: Partha Basak Reviewed-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 187 +++++++------------------------- arch/arm/plat-omap/include/plat/mcspi.h | 3 + drivers/spi/omap2_mcspi.c | 112 +++++-------------- 3 files changed, 72 insertions(+), 230 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index e0f0ef952bc..71f099b85e7 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -279,163 +280,55 @@ static inline void omap_init_audio(void) {} #include -#define OMAP2_MCSPI1_BASE 0x48098000 -#define OMAP2_MCSPI2_BASE 0x4809a000 -#define OMAP2_MCSPI3_BASE 0x480b8000 -#define OMAP2_MCSPI4_BASE 0x480ba000 - -#define OMAP4_MCSPI1_BASE 0x48098100 -#define OMAP4_MCSPI2_BASE 0x4809a100 -#define OMAP4_MCSPI3_BASE 0x480b8100 -#define OMAP4_MCSPI4_BASE 0x480ba100 - -static struct omap2_mcspi_platform_config omap2_mcspi1_config = { - .num_cs = 4, -}; - -static struct resource omap2_mcspi1_resources[] = { - { - .start = OMAP2_MCSPI1_BASE, - .end = OMAP2_MCSPI1_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi1 = { - .name = "omap2_mcspi", - .id = 1, - .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), - .resource = omap2_mcspi1_resources, - .dev = { - .platform_data = &omap2_mcspi1_config, - }, -}; - -static struct omap2_mcspi_platform_config omap2_mcspi2_config = { - .num_cs = 2, -}; - -static struct resource omap2_mcspi2_resources[] = { - { - .start = OMAP2_MCSPI2_BASE, - .end = OMAP2_MCSPI2_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi2 = { - .name = "omap2_mcspi", - .id = 2, - .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), - .resource = omap2_mcspi2_resources, - .dev = { - .platform_data = &omap2_mcspi2_config, - }, -}; - -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) -static struct omap2_mcspi_platform_config omap2_mcspi3_config = { - .num_cs = 2, -}; - -static struct resource omap2_mcspi3_resources[] = { - { - .start = OMAP2_MCSPI3_BASE, - .end = OMAP2_MCSPI3_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi3 = { - .name = "omap2_mcspi", - .id = 3, - .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), - .resource = omap2_mcspi3_resources, - .dev = { - .platform_data = &omap2_mcspi3_config, - }, -}; -#endif - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -static struct omap2_mcspi_platform_config omap2_mcspi4_config = { - .num_cs = 1, -}; - -static struct resource omap2_mcspi4_resources[] = { - { - .start = OMAP2_MCSPI4_BASE, - .end = OMAP2_MCSPI4_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap2_mcspi4 = { - .name = "omap2_mcspi", - .id = 4, - .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), - .resource = omap2_mcspi4_resources, - .dev = { - .platform_data = &omap2_mcspi4_config, +struct omap_device_pm_latency omap_mcspi_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, }; -#endif -#ifdef CONFIG_ARCH_OMAP4 -static inline void omap4_mcspi_fixup(void) +static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) { - omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; - omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; - omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; - omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; - omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; - omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; - omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; - omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; -} -#else -static inline void omap4_mcspi_fixup(void) -{ -} -#endif + struct omap_device *od; + char *name = "omap2_mcspi"; + struct omap2_mcspi_platform_config *pdata; + static int spi_num; + struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) { + pr_err("Memory allocation for McSPI device failed\n"); + return -ENOMEM; + } -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) -static inline void omap2_mcspi3_init(void) -{ - platform_device_register(&omap2_mcspi3); -} -#else -static inline void omap2_mcspi3_init(void) -{ -} -#endif + pdata->num_cs = mcspi_attrib->num_chipselect; + switch (oh->class->rev) { + case OMAP2_MCSPI_REV: + case OMAP3_MCSPI_REV: + pdata->regs_offset = 0; + break; + case OMAP4_MCSPI_REV: + pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; + break; + default: + pr_err("Invalid McSPI Revision value\n"); + return -EINVAL; + } -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -static inline void omap2_mcspi4_init(void) -{ - platform_device_register(&omap2_mcspi4); -} -#else -static inline void omap2_mcspi4_init(void) -{ + spi_num++; + od = omap_device_build(name, spi_num, oh, pdata, + sizeof(*pdata), omap_mcspi_latency, + ARRAY_SIZE(omap_mcspi_latency), 0); + WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", + name, oh->name); + kfree(pdata); + return 0; } -#endif static void omap_init_mcspi(void) { - if (cpu_is_omap44xx()) - omap4_mcspi_fixup(); - - platform_device_register(&omap2_mcspi1); - platform_device_register(&omap2_mcspi2); - - if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) - omap2_mcspi3_init(); - - if (cpu_is_omap343x() || cpu_is_omap44xx()) - omap2_mcspi4_init(); + omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); } #else diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h index 560e266da8a..3d51b18131c 100644 --- a/arch/arm/plat-omap/include/plat/mcspi.h +++ b/arch/arm/plat-omap/include/plat/mcspi.h @@ -5,8 +5,11 @@ #define OMAP3_MCSPI_REV 1 #define OMAP4_MCSPI_REV 2 +#define OMAP4_MCSPI_REG_OFFSET 0x100 + struct omap2_mcspi_platform_config { unsigned short num_cs; + unsigned int regs_offset; }; struct omap2_mcspi_dev_attr { diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index f076cc5c6fb..f7851325c61 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -3,7 +3,7 @@ * * Copyright (C) 2005, 2006 Nokia Corporation * Author: Samuel Ortiz and - * Juha Yrjölä + * Juha Yrj�l� * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1087,91 +1087,14 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) return 0; } -static u8 __initdata spi1_rxdma_id [] = { - OMAP24XX_DMA_SPI1_RX0, - OMAP24XX_DMA_SPI1_RX1, - OMAP24XX_DMA_SPI1_RX2, - OMAP24XX_DMA_SPI1_RX3, -}; - -static u8 __initdata spi1_txdma_id [] = { - OMAP24XX_DMA_SPI1_TX0, - OMAP24XX_DMA_SPI1_TX1, - OMAP24XX_DMA_SPI1_TX2, - OMAP24XX_DMA_SPI1_TX3, -}; - -static u8 __initdata spi2_rxdma_id[] = { - OMAP24XX_DMA_SPI2_RX0, - OMAP24XX_DMA_SPI2_RX1, -}; - -static u8 __initdata spi2_txdma_id[] = { - OMAP24XX_DMA_SPI2_TX0, - OMAP24XX_DMA_SPI2_TX1, -}; - -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ - || defined(CONFIG_ARCH_OMAP4) -static u8 __initdata spi3_rxdma_id[] = { - OMAP24XX_DMA_SPI3_RX0, - OMAP24XX_DMA_SPI3_RX1, -}; - -static u8 __initdata spi3_txdma_id[] = { - OMAP24XX_DMA_SPI3_TX0, - OMAP24XX_DMA_SPI3_TX1, -}; -#endif - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -static u8 __initdata spi4_rxdma_id[] = { - OMAP34XX_DMA_SPI4_RX0, -}; - -static u8 __initdata spi4_txdma_id[] = { - OMAP34XX_DMA_SPI4_TX0, -}; -#endif static int __init omap2_mcspi_probe(struct platform_device *pdev) { struct spi_master *master; + struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data; struct omap2_mcspi *mcspi; struct resource *r; int status = 0, i; - const u8 *rxdma_id, *txdma_id; - unsigned num_chipselect; - - switch (pdev->id) { - case 1: - rxdma_id = spi1_rxdma_id; - txdma_id = spi1_txdma_id; - num_chipselect = 4; - break; - case 2: - rxdma_id = spi2_rxdma_id; - txdma_id = spi2_txdma_id; - num_chipselect = 2; - break; -#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ - || defined(CONFIG_ARCH_OMAP4) - case 3: - rxdma_id = spi3_rxdma_id; - txdma_id = spi3_txdma_id; - num_chipselect = 2; - break; -#endif -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - case 4: - rxdma_id = spi4_rxdma_id; - txdma_id = spi4_txdma_id; - num_chipselect = 1; - break; -#endif - default: - return -EINVAL; - } master = spi_alloc_master(&pdev->dev, sizeof *mcspi); if (master == NULL) { @@ -1188,7 +1111,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) master->setup = omap2_mcspi_setup; master->transfer = omap2_mcspi_transfer; master->cleanup = omap2_mcspi_cleanup; - master->num_chipselect = num_chipselect; + master->num_chipselect = pdata->num_cs; dev_set_drvdata(&pdev->dev, master); @@ -1206,6 +1129,8 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) goto err1; } + r->start += pdata->regs_offset; + r->end += pdata->regs_offset; mcspi->phys = r->start; mcspi->base = ioremap(r->start, r->end - r->start + 1); if (!mcspi->base) { @@ -1240,11 +1165,32 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) if (mcspi->dma_channels == NULL) goto err3; - for (i = 0; i < num_chipselect; i++) { + for (i = 0; i < master->num_chipselect; i++) { + char dma_ch_name[14]; + struct resource *dma_res; + + sprintf(dma_ch_name, "rx%d", i); + dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, + dma_ch_name); + if (!dma_res) { + dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); + status = -ENODEV; + break; + } + mcspi->dma_channels[i].dma_rx_channel = -1; - mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; + mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; + sprintf(dma_ch_name, "tx%d", i); + dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, + dma_ch_name); + if (!dma_res) { + dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); + status = -ENODEV; + break; + } + mcspi->dma_channels[i].dma_tx_channel = -1; - mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; + mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; } if (omap2_mcspi_reset(mcspi) < 0) -- cgit v1.2.3-70-g09d2 From f4117ac9e237b74afdf5e001d5ea26a4d15e9847 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Jan 2011 18:07:14 +0000 Subject: ARM: P2V: separate PHYS_OFFSET from platform definitions This uncouple PHYS_OFFSET from the platform definitions, thereby facilitating run-time computation of the physical memory offset. Acked-by: Nicolas Pitre Acked-by: Viresh Kumar Acked-by: H Hartley Sweeten Acked-by: Magnus Damm Acked-by: Tony Lindgren Acked-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Wan ZongShun Acked-by: Kukjin Kim Acked-by: Eric Miao Acked-by: Jiandong Zheng Signed-off-by: Russell King --- arch/arm/include/asm/memory.h | 2 ++ arch/arm/kernel/tcm.c | 2 +- arch/arm/mach-aaec2000/include/mach/memory.h | 2 +- arch/arm/mach-at91/include/mach/memory.h | 2 +- arch/arm/mach-bcmring/include/mach/hardware.h | 2 +- arch/arm/mach-bcmring/include/mach/memory.h | 2 +- arch/arm/mach-clps711x/include/mach/memory.h | 2 +- arch/arm/mach-cns3xxx/include/mach/memory.h | 2 +- arch/arm/mach-davinci/include/mach/memory.h | 4 ++-- arch/arm/mach-dove/include/mach/memory.h | 2 +- arch/arm/mach-ebsa110/include/mach/memory.h | 2 +- arch/arm/mach-ep93xx/include/mach/memory.h | 10 +++++----- arch/arm/mach-footbridge/include/mach/memory.h | 2 +- arch/arm/mach-gemini/include/mach/memory.h | 4 ++-- arch/arm/mach-h720x/include/mach/memory.h | 2 +- arch/arm/mach-integrator/include/mach/memory.h | 2 +- arch/arm/mach-iop13xx/include/mach/memory.h | 2 +- arch/arm/mach-iop32x/include/mach/memory.h | 2 +- arch/arm/mach-iop33x/include/mach/memory.h | 2 +- arch/arm/mach-ixp2000/include/mach/memory.h | 2 +- arch/arm/mach-ixp23xx/include/mach/memory.h | 2 +- arch/arm/mach-ixp4xx/include/mach/memory.h | 2 +- arch/arm/mach-kirkwood/include/mach/memory.h | 2 +- arch/arm/mach-ks8695/include/mach/memory.h | 2 +- arch/arm/mach-lh7a40x/include/mach/memory.h | 2 +- arch/arm/mach-loki/include/mach/memory.h | 2 +- arch/arm/mach-lpc32xx/include/mach/memory.h | 2 +- arch/arm/mach-mmp/include/mach/memory.h | 2 +- arch/arm/mach-msm/board-msm7x30.c | 2 +- arch/arm/mach-msm/include/mach/memory.h | 10 +++++----- arch/arm/mach-mv78xx0/include/mach/memory.h | 2 +- arch/arm/mach-mx3/mach-kzm_arm11_01.c | 2 +- arch/arm/mach-netx/include/mach/memory.h | 2 +- arch/arm/mach-nomadik/include/mach/memory.h | 2 +- arch/arm/mach-ns9xxx/include/mach/memory.h | 2 +- arch/arm/mach-nuc93x/include/mach/memory.h | 2 +- arch/arm/mach-orion5x/include/mach/memory.h | 2 +- arch/arm/mach-pnx4008/include/mach/memory.h | 2 +- arch/arm/mach-pxa/include/mach/memory.h | 2 +- arch/arm/mach-realview/include/mach/memory.h | 4 ++-- arch/arm/mach-rpc/include/mach/memory.h | 2 +- arch/arm/mach-s3c2400/include/mach/memory.h | 2 +- arch/arm/mach-s3c2410/include/mach/memory.h | 2 +- arch/arm/mach-s3c24a0/include/mach/memory.h | 2 +- arch/arm/mach-s3c64xx/include/mach/memory.h | 2 +- arch/arm/mach-s5p6442/include/mach/memory.h | 2 +- arch/arm/mach-s5p64x0/include/mach/memory.h | 2 +- arch/arm/mach-s5pc100/include/mach/memory.h | 2 +- arch/arm/mach-s5pv210/include/mach/memory.h | 2 +- arch/arm/mach-s5pv310/include/mach/memory.h | 2 +- arch/arm/mach-sa1100/include/mach/memory.h | 2 +- arch/arm/mach-shark/include/mach/memory.h | 2 +- arch/arm/mach-shmobile/include/mach/memory.h | 2 +- arch/arm/mach-tegra/include/mach/memory.h | 2 +- arch/arm/mach-u300/include/mach/memory.h | 6 +++--- arch/arm/mach-u300/u300.c | 2 +- arch/arm/mach-ux500/include/mach/memory.h | 2 +- arch/arm/mach-versatile/include/mach/memory.h | 2 +- arch/arm/mach-vexpress/include/mach/memory.h | 2 +- arch/arm/mach-w90x900/include/mach/memory.h | 2 +- arch/arm/plat-mxc/include/mach/memory.h | 18 +++++++++--------- arch/arm/plat-omap/include/plat/memory.h | 4 ++-- arch/arm/plat-spear/include/plat/memory.h | 2 +- arch/arm/plat-stmp3xxx/include/mach/memory.h | 2 +- arch/arm/plat-tcc/include/mach/memory.h | 2 +- 65 files changed, 88 insertions(+), 86 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index d0ee74b7cf8..2efec578a62 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -24,6 +24,8 @@ */ #define UL(x) _AC(x, UL) +#define PHYS_OFFSET PLAT_PHYS_OFFSET + #ifdef CONFIG_MMU /* diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c index 26685c2f7a4..f5cf660eefc 100644 --- a/arch/arm/kernel/tcm.c +++ b/arch/arm/kernel/tcm.c @@ -15,7 +15,7 @@ #include /* memcpy */ #include #include -#include +#include #include "tcm.h" static struct gen_pool *tcm_pool; diff --git a/arch/arm/mach-aaec2000/include/mach/memory.h b/arch/arm/mach-aaec2000/include/mach/memory.h index 4f93c567a35..4a10bf0bd36 100644 --- a/arch/arm/mach-aaec2000/include/mach/memory.h +++ b/arch/arm/mach-aaec2000/include/mach/memory.h @@ -12,6 +12,6 @@ #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0xf0000000) +#define PLAT_PHYS_OFFSET UL(0xf0000000) #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h index 14f4ef4b6a9..c2cfe504064 100644 --- a/arch/arm/mach-at91/include/mach/memory.h +++ b/arch/arm/mach-at91/include/mach/memory.h @@ -23,6 +23,6 @@ #include -#define PHYS_OFFSET (AT91_SDRAM_BASE) +#define PLAT_PHYS_OFFSET (AT91_SDRAM_BASE) #endif diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h index 447eb340c61..8bf3564fba5 100644 --- a/arch/arm/mach-bcmring/include/mach/hardware.h +++ b/arch/arm/mach-bcmring/include/mach/hardware.h @@ -31,7 +31,7 @@ * *_SIZE is the size of the region * *_BASE is the virtual address */ -#define RAM_START PHYS_OFFSET +#define RAM_START PLAT_PHYS_OFFSET #define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED) #define RAM_BASE PAGE_OFFSET diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h index 114f942bb4f..15162e4c75f 100644 --- a/arch/arm/mach-bcmring/include/mach/memory.h +++ b/arch/arm/mach-bcmring/include/mach/memory.h @@ -23,7 +23,7 @@ * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. */ -#define PHYS_OFFSET CFG_GLOBAL_RAM_BASE +#define PLAT_PHYS_OFFSET CFG_GLOBAL_RAM_BASE /* * Maximum DMA memory allowed is 14M diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h index f45c8e892cb..3a032a67725 100644 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ b/arch/arm/mach-clps711x/include/mach/memory.h @@ -23,7 +23,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0xc0000000) +#define PLAT_PHYS_OFFSET UL(0xc0000000) #if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12) diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h index 3b6b769b7a2..dc16c5c5d86 100644 --- a/arch/arm/mach-cns3xxx/include/mach/memory.h +++ b/arch/arm/mach-cns3xxx/include/mach/memory.h @@ -13,7 +13,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define __phys_to_bus(x) ((x) + PHYS_OFFSET) #define __bus_to_phys(x) ((x) - PHYS_OFFSET) diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 22eb97c1c30..78822723f38 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -26,9 +26,9 @@ #if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) #error Cannot enable DaVinci and DA8XX platforms concurrently #elif defined(CONFIG_ARCH_DAVINCI_DA8XX) -#define PHYS_OFFSET DA8XX_DDR_BASE +#define PLAT_PHYS_OFFSET DA8XX_DDR_BASE #else -#define PHYS_OFFSET DAVINCI_DDR_BASE +#define PLAT_PHYS_OFFSET DAVINCI_DDR_BASE #endif #define DDR2_SDRCR_OFFSET 0xc diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h index d6687207494..bbc93fee6c7 100644 --- a/arch/arm/mach-dove/include/mach/memory.h +++ b/arch/arm/mach-dove/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ebsa110/include/mach/memory.h b/arch/arm/mach-ebsa110/include/mach/memory.h index 0ca66d080c6..8e49066ad85 100644 --- a/arch/arm/mach-ebsa110/include/mach/memory.h +++ b/arch/arm/mach-ebsa110/include/mach/memory.h @@ -19,7 +19,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) /* * Cache flushing area - SRAM diff --git a/arch/arm/mach-ep93xx/include/mach/memory.h b/arch/arm/mach-ep93xx/include/mach/memory.h index 554064e9030..c9400cf0051 100644 --- a/arch/arm/mach-ep93xx/include/mach/memory.h +++ b/arch/arm/mach-ep93xx/include/mach/memory.h @@ -6,15 +6,15 @@ #define __ASM_ARCH_MEMORY_H #if defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #elif defined(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xc0000000) +#define PLAT_PHYS_OFFSET UL(0xc0000000) #elif defined(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xd0000000) +#define PLAT_PHYS_OFFSET UL(0xd0000000) #elif defined(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xe0000000) +#define PLAT_PHYS_OFFSET UL(0xe0000000) #elif defined(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) -#define PHYS_OFFSET UL(0xf0000000) +#define PLAT_PHYS_OFFSET UL(0xf0000000) #else #error "Kconfig bug: No EP93xx PHYS_OFFSET set" #endif diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h index 8d64f457408..5c6df377f96 100644 --- a/arch/arm/mach-footbridge/include/mach/memory.h +++ b/arch/arm/mach-footbridge/include/mach/memory.h @@ -62,7 +62,7 @@ extern unsigned long __bus_to_pfn(unsigned long); /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define FLUSH_BASE_PHYS 0x50000000 diff --git a/arch/arm/mach-gemini/include/mach/memory.h b/arch/arm/mach-gemini/include/mach/memory.h index 2d14d5bf1f9..a50915f764d 100644 --- a/arch/arm/mach-gemini/include/mach/memory.h +++ b/arch/arm/mach-gemini/include/mach/memory.h @@ -11,9 +11,9 @@ #define __MACH_MEMORY_H #ifdef CONFIG_GEMINI_MEM_SWAP -# define PHYS_OFFSET UL(0x00000000) +# define PLAT_PHYS_OFFSET UL(0x00000000) #else -# define PHYS_OFFSET UL(0x10000000) +# define PLAT_PHYS_OFFSET UL(0x10000000) #endif #endif /* __MACH_MEMORY_H */ diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h index ef4c1e26f18..9d368765146 100644 --- a/arch/arm/mach-h720x/include/mach/memory.h +++ b/arch/arm/mach-h720x/include/mach/memory.h @@ -7,7 +7,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x40000000) +#define PLAT_PHYS_OFFSET UL(0x40000000) /* * This is the maximum DMA address that can be DMAd to. * There should not be more than (0xd0000000 - 0xc0000000) diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h index 991f24d2c11..334d5e27188 100644 --- a/arch/arm/mach-integrator/include/mach/memory.h +++ b/arch/arm/mach-integrator/include/mach/memory.h @@ -23,7 +23,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define BUS_OFFSET UL(0x80000000) #define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index 3ad45531886..1afa99ef97f 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h @@ -6,7 +6,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h index c30f6450ad5..169cc239f76 100644 --- a/arch/arm/mach-iop32x/include/mach/memory.h +++ b/arch/arm/mach-iop32x/include/mach/memory.h @@ -8,6 +8,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0xa0000000) +#define PLAT_PHYS_OFFSET UL(0xa0000000) #endif diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h index a30a96aa6d2..8e1daf7006b 100644 --- a/arch/arm/mach-iop33x/include/mach/memory.h +++ b/arch/arm/mach-iop33x/include/mach/memory.h @@ -8,6 +8,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h index 98e3471be15..5f0c4fd4076 100644 --- a/arch/arm/mach-ixp2000/include/mach/memory.h +++ b/arch/arm/mach-ixp2000/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #include diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h index 6ef65d813f1..6cf0704e946 100644 --- a/arch/arm/mach-ixp23xx/include/mach/memory.h +++ b/arch/arm/mach-ixp23xx/include/mach/memory.h @@ -17,7 +17,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET (0x00000000) +#define PLAT_PHYS_OFFSET (0x00000000) #define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0) diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index 0136eaa2922..6d388c9d0e2 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -12,7 +12,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) diff --git a/arch/arm/mach-kirkwood/include/mach/memory.h b/arch/arm/mach-kirkwood/include/mach/memory.h index 45431e13146..4600b44e3ad 100644 --- a/arch/arm/mach-kirkwood/include/mach/memory.h +++ b/arch/arm/mach-kirkwood/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h index bace9a681ad..f7e1b9bce34 100644 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ b/arch/arm/mach-ks8695/include/mach/memory.h @@ -18,7 +18,7 @@ /* * Physical SRAM offset. */ -#define PHYS_OFFSET KS8695_SDRAM_PA +#define PLAT_PHYS_OFFSET KS8695_SDRAM_PA #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h index edb8f5faf5d..f77bde80fe4 100644 --- a/arch/arm/mach-lh7a40x/include/mach/memory.h +++ b/arch/arm/mach-lh7a40x/include/mach/memory.h @@ -17,7 +17,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0xc0000000) +#define PLAT_PHYS_OFFSET UL(0xc0000000) /* * Sparsemem version of the above diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h index 2ed7e6e732c..66366657a87 100644 --- a/arch/arm/mach-loki/include/mach/memory.h +++ b/arch/arm/mach-loki/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h index 044e1acecbe..a647dd624af 100644 --- a/arch/arm/mach-lpc32xx/include/mach/memory.h +++ b/arch/arm/mach-lpc32xx/include/mach/memory.h @@ -22,6 +22,6 @@ /* * Physical DRAM offset of bank 0 */ -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h index bdb21d70714..d68b50a2d6a 100644 --- a/arch/arm/mach-mmp/include/mach/memory.h +++ b/arch/arm/mach-mmp/include/mach/memory.h @@ -9,6 +9,6 @@ #ifndef __ASM_MACH_MEMORY_H #define __ASM_MACH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 6f3b9735e97..decbf80b429 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -26,11 +26,11 @@ #include #include +#include #include #include #include -#include #include #include diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index 070e17d237f..176875df241 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h @@ -18,15 +18,15 @@ /* physical offset of RAM */ #if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A) -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #elif defined(CONFIG_ARCH_QSD8X50) -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #elif defined(CONFIG_ARCH_MSM7X30) -#define PHYS_OFFSET UL(0x00200000) +#define PLAT_PHYS_OFFSET UL(0x00200000) #elif defined(CONFIG_ARCH_MSM8X60) -#define PHYS_OFFSET UL(0x40200000) +#define PLAT_PHYS_OFFSET UL(0x40200000) #else -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) #endif #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h index e663042d307..a648c51f2e4 100644 --- a/arch/arm/mach-mv78xx0/include/mach/memory.h +++ b/arch/arm/mach-mv78xx0/include/mach/memory.h @@ -5,6 +5,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index a5f3eb24e4d..df1a6ce8e3e 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -36,7 +37,6 @@ #include #include #include -#include #include "devices-imx31.h" #include "devices.h" diff --git a/arch/arm/mach-netx/include/mach/memory.h b/arch/arm/mach-netx/include/mach/memory.h index 9a363f297f9..59561496c36 100644 --- a/arch/arm/mach-netx/include/mach/memory.h +++ b/arch/arm/mach-netx/include/mach/memory.h @@ -20,7 +20,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/mach-nomadik/include/mach/memory.h b/arch/arm/mach-nomadik/include/mach/memory.h index 1e5689d98ec..d3325211ba6 100644 --- a/arch/arm/mach-nomadik/include/mach/memory.h +++ b/arch/arm/mach-nomadik/include/mach/memory.h @@ -23,6 +23,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h index 6107193adbf..5c65aee6e7a 100644 --- a/arch/arm/mach-ns9xxx/include/mach/memory.h +++ b/arch/arm/mach-ns9xxx/include/mach/memory.h @@ -19,6 +19,6 @@ #define NS9XXX_CS2STAT_LENGTH UL(0x1000) #define NS9XXX_CS3STAT_LENGTH UL(0x1000) -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h index 323ab0db3f7..ef9864b002a 100644 --- a/arch/arm/mach-nuc93x/include/mach/memory.h +++ b/arch/arm/mach-nuc93x/include/mach/memory.h @@ -16,6 +16,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h index 52a2955d0f8..6769917882f 100644 --- a/arch/arm/mach-orion5x/include/mach/memory.h +++ b/arch/arm/mach-orion5x/include/mach/memory.h @@ -7,6 +7,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-pnx4008/include/mach/memory.h b/arch/arm/mach-pnx4008/include/mach/memory.h index 0e877008105..1275db61cee 100644 --- a/arch/arm/mach-pnx4008/include/mach/memory.h +++ b/arch/arm/mach-pnx4008/include/mach/memory.h @@ -16,6 +16,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 92361a66b22..7f68724dcc2 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -15,7 +15,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0xa0000000) +#define PLAT_PHYS_OFFSET UL(0xa0000000) #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index 5dafc157b27..e05fc2c4c08 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -24,9 +24,9 @@ * Physical DRAM offset. */ #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET -#define PHYS_OFFSET UL(0x70000000) +#define PLAT_PHYS_OFFSET UL(0x70000000) #else -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif #if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h index 78191bf2519..18a221093bf 100644 --- a/arch/arm/mach-rpc/include/mach/memory.h +++ b/arch/arm/mach-rpc/include/mach/memory.h @@ -21,7 +21,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) /* * Cache flushing area - ROM diff --git a/arch/arm/mach-s3c2400/include/mach/memory.h b/arch/arm/mach-s3c2400/include/mach/memory.h index cf5901ffd38..3f33670dd01 100644 --- a/arch/arm/mach-s3c2400/include/mach/memory.h +++ b/arch/arm/mach-s3c2400/include/mach/memory.h @@ -15,6 +15,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x0C000000) +#define PLAT_PHYS_OFFSET UL(0x0C000000) #endif diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h index 6f1e5871ae4..f92b97b89c0 100644 --- a/arch/arm/mach-s3c2410/include/mach/memory.h +++ b/arch/arm/mach-s3c2410/include/mach/memory.h @@ -11,6 +11,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x30000000) +#define PLAT_PHYS_OFFSET UL(0x30000000) #endif diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h index 7d74fd5c8d6..7d208a71b17 100644 --- a/arch/arm/mach-s3c24a0/include/mach/memory.h +++ b/arch/arm/mach-s3c24a0/include/mach/memory.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_24A0_MEMORY_H #define __ASM_ARCH_24A0_MEMORY_H __FILE__ -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h index 42cc54e2ee3..4760cdae1eb 100644 --- a/arch/arm/mach-s3c64xx/include/mach/memory.h +++ b/arch/arm/mach-s3c64xx/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x50000000) +#define PLAT_PHYS_OFFSET UL(0x50000000) #define CONSISTENT_DMA_SIZE SZ_8M diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h index 9ddd877ba2e..cfe259dded3 100644 --- a/arch/arm/mach-s5p6442/include/mach/memory.h +++ b/arch/arm/mach-s5p6442/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #define CONSISTENT_DMA_SIZE SZ_8M #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5p64x0/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h index 1b036b0a24c..365a6eb4b88 100644 --- a/arch/arm/mach-s5p64x0/include/mach/memory.h +++ b/arch/arm/mach-s5p64x0/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H __FILE__ -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #define CONSISTENT_DMA_SIZE SZ_8M #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h index 4b60d18179f..bda4e79fd5f 100644 --- a/arch/arm/mach-s5pc100/include/mach/memory.h +++ b/arch/arm/mach-s5pc100/include/mach/memory.h @@ -13,6 +13,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #endif diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h index d503e0c4ce4..7b5fcf0da0c 100644 --- a/arch/arm/mach-s5pv210/include/mach/memory.h +++ b/arch/arm/mach-s5pv210/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) /* diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-s5pv310/include/mach/memory.h index 1dffb482324..470b01bf861 100644 --- a/arch/arm/mach-s5pv310/include/mach/memory.h +++ b/arch/arm/mach-s5pv310/include/mach/memory.h @@ -13,7 +13,7 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H __FILE__ -#define PHYS_OFFSET UL(0x40000000) +#define PLAT_PHYS_OFFSET UL(0x40000000) /* Maximum of 256MiB in one bank */ #define MAX_PHYSMEM_BITS 32 diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index 128a1dfa96b..a44da6a2916 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -12,7 +12,7 @@ /* * Physical DRAM offset is 0xc0000000 on the SA1100 */ -#define PHYS_OFFSET UL(0xc0000000) +#define PLAT_PHYS_OFFSET UL(0xc0000000) #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index d9c4812f1c3..9afb1700000 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -15,7 +15,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x08000000) +#define PLAT_PHYS_OFFSET UL(0x08000000) #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h index 377584e57e0..ad00c3c258f 100644 --- a/arch/arm/mach-shmobile/include/mach/memory.h +++ b/arch/arm/mach-shmobile/include/mach/memory.h @@ -1,7 +1,7 @@ #ifndef __ASM_MACH_MEMORY_H #define __ASM_MACH_MEMORY_H -#define PHYS_OFFSET UL(CONFIG_MEMORY_START) +#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START) #define MEM_SIZE UL(CONFIG_MEMORY_SIZE) /* DMA memory at 0xf6000000 - 0xffdfffff */ diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h index 6151bab62af..537db3aa81a 100644 --- a/arch/arm/mach-tegra/include/mach/memory.h +++ b/arch/arm/mach-tegra/include/mach/memory.h @@ -22,7 +22,7 @@ #define __MACH_TEGRA_MEMORY_H /* physical offset of RAM */ -#define PHYS_OFFSET UL(0) +#define PLAT_PHYS_OFFSET UL(0) #endif diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h index bf134bcc129..888e2e351ee 100644 --- a/arch/arm/mach-u300/include/mach/memory.h +++ b/arch/arm/mach-u300/include/mach/memory.h @@ -15,17 +15,17 @@ #ifdef CONFIG_MACH_U300_DUAL_RAM -#define PHYS_OFFSET UL(0x48000000) +#define PLAT_PHYS_OFFSET UL(0x48000000) #define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100) #else #ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX -#define PHYS_OFFSET (0x28000000 + \ +#define PLAT_PHYS_OFFSET (0x28000000 + \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) #else -#define PHYS_OFFSET (0x28000000 + \ +#define PLAT_PHYS_OFFSET (0x28000000 + \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \ (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) #endif diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c index 07c35a84642..48b3b7f3996 100644 --- a/arch/arm/mach-u300/u300.c +++ b/arch/arm/mach-u300/u300.c @@ -19,9 +19,9 @@ #include #include #include -#include #include #include +#include static void __init u300_reserve(void) { diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h index 510571a59e2..2ef697a6700 100644 --- a/arch/arm/mach-ux500/include/mach/memory.h +++ b/arch/arm/mach-ux500/include/mach/memory.h @@ -12,7 +12,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #define BUS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h index 79aeab86b90..dacc9d8e4e6 100644 --- a/arch/arm/mach-versatile/include/mach/memory.h +++ b/arch/arm/mach-versatile/include/mach/memory.h @@ -23,6 +23,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/mach-vexpress/include/mach/memory.h b/arch/arm/mach-vexpress/include/mach/memory.h index be28232ae63..5b7fcd439d8 100644 --- a/arch/arm/mach-vexpress/include/mach/memory.h +++ b/arch/arm/mach-vexpress/include/mach/memory.h @@ -20,6 +20,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x60000000) +#define PLAT_PHYS_OFFSET UL(0x60000000) #endif diff --git a/arch/arm/mach-w90x900/include/mach/memory.h b/arch/arm/mach-w90x900/include/mach/memory.h index 971b80702c2..f02905ba774 100644 --- a/arch/arm/mach-w90x900/include/mach/memory.h +++ b/arch/arm/mach-w90x900/include/mach/memory.h @@ -18,6 +18,6 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 83861408133..5d51cbb9889 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -23,23 +23,23 @@ #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) # if defined CONFIG_ARCH_MX1 -# define PHYS_OFFSET MX1_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX1_PHYS_OFFSET # elif defined CONFIG_MACH_MX21 -# define PHYS_OFFSET MX21_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX21_PHYS_OFFSET # elif defined CONFIG_ARCH_MX25 -# define PHYS_OFFSET MX25_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX25_PHYS_OFFSET # elif defined CONFIG_MACH_MX27 -# define PHYS_OFFSET MX27_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET # elif defined CONFIG_ARCH_MX3 -# define PHYS_OFFSET MX3x_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 -# define PHYS_OFFSET MXC91231_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET # elif defined CONFIG_ARCH_MX50 -# define PHYS_OFFSET MX50_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET # elif defined CONFIG_ARCH_MX51 -# define PHYS_OFFSET MX51_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX51_PHYS_OFFSET # elif defined CONFIG_ARCH_MX53 -# define PHYS_OFFSET MX53_PHYS_OFFSET +# define PLAT_PHYS_OFFSET MX53_PHYS_OFFSET # endif #endif diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h index f8d922fb558..e6720aa2d55 100644 --- a/arch/arm/plat-omap/include/plat/memory.h +++ b/arch/arm/plat-omap/include/plat/memory.h @@ -37,9 +37,9 @@ * Physical DRAM offset. */ #if defined(CONFIG_ARCH_OMAP1) -#define PHYS_OFFSET UL(0x10000000) +#define PLAT_PHYS_OFFSET UL(0x10000000) #else -#define PHYS_OFFSET UL(0x80000000) +#define PLAT_PHYS_OFFSET UL(0x80000000) #endif /* diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h index 27a4aba7734..7e3599e1104 100644 --- a/arch/arm/plat-spear/include/plat/memory.h +++ b/arch/arm/plat-spear/include/plat/memory.h @@ -15,6 +15,6 @@ #define __PLAT_MEMORY_H /* Physical DRAM offset */ -#define PHYS_OFFSET UL(0x00000000) +#define PLAT_PHYS_OFFSET UL(0x00000000) #endif /* __PLAT_MEMORY_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h index 7b875a07a1a..61fa54882e1 100644 --- a/arch/arm/plat-stmp3xxx/include/mach/memory.h +++ b/arch/arm/plat-stmp3xxx/include/mach/memory.h @@ -17,6 +17,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x40000000) +#define PLAT_PHYS_OFFSET UL(0x40000000) #endif diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h index cd91ba8a670..28a6e0cd13b 100644 --- a/arch/arm/plat-tcc/include/mach/memory.h +++ b/arch/arm/plat-tcc/include/mach/memory.h @@ -13,6 +13,6 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET UL(0x20000000) +#define PLAT_PHYS_OFFSET UL(0x20000000) #endif -- cgit v1.2.3-70-g09d2 From b75c178afaa975896e894bb2b6951dc4cd43c977 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Jan 2011 19:03:16 +0000 Subject: ARM: P2V: avoid initializers and assembly using PHYS_OFFSET As PHYS_OFFSET will be becoming a variable, we can't have it used in initializers nor assembly code. Replace those in generic code with a run-time initialization. Replace those in platform code using the individual platform specific PLAT_PHYS_OFFSET. Acked-by: Nicolas Pitre Acked-by: Tony Lindgren Acked-by: Kukjin Kim Acked-by: David Brown Acked-by: Eric Miao Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 4 +++- arch/arm/mach-msm/board-msm7x27.c | 8 ++++---- arch/arm/mach-msm/board-msm7x30.c | 6 +++--- arch/arm/mach-msm/board-qsd8x50.c | 4 ++-- arch/arm/mach-msm/board-sapphire.c | 2 +- arch/arm/mach-pxa/balloon3.c | 2 +- arch/arm/mach-realview/realview_eb.c | 2 +- arch/arm/mach-realview/realview_pb1176.c | 2 +- arch/arm/mach-realview/realview_pb11mp.c | 2 +- arch/arm/mach-realview/realview_pba8.c | 2 +- arch/arm/mach-realview/realview_pbx.c | 2 +- arch/arm/mach-s5pv210/sleep.S | 2 +- arch/arm/mach-tcc8k/board-tcc8000-sdk.c | 2 +- arch/arm/mach-vexpress/ct-ca9x4.c | 2 +- arch/arm/plat-omap/include/plat/serial.h | 2 +- 15 files changed, 23 insertions(+), 21 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 78678b07901..056bf1878f8 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -740,7 +740,7 @@ static struct init_tags { { tag_size(tag_core), ATAG_CORE }, { 1, PAGE_SIZE, 0xff }, { tag_size(tag_mem32), ATAG_MEM }, - { MEM_SIZE, PHYS_OFFSET }, + { MEM_SIZE }, { 0, ATAG_NONE } }; @@ -839,6 +839,8 @@ void __init setup_arch(char **cmdline_p) struct machine_desc *mdesc; char *from = default_command_line; + init_tags.mem.start = PHYS_OFFSET; + unwind_init(); setup_processor(); diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c index e7a76eff57d..08fcd40a8cb 100644 --- a/arch/arm/mach-msm/board-msm7x27.c +++ b/arch/arm/mach-msm/board-msm7x27.c @@ -132,7 +132,7 @@ static void __init msm7x2x_map_io(void) MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -142,7 +142,7 @@ MACHINE_END MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -152,7 +152,7 @@ MACHINE_END MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, @@ -162,7 +162,7 @@ MACHINE_END MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x2x_map_io, .init_irq = msm7x2x_init_irq, .init_machine = msm7x2x_init, diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index decbf80b429..25db8fd71a7 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -85,7 +85,7 @@ static void __init msm7x30_map_io(void) MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, @@ -95,7 +95,7 @@ MACHINE_END MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, @@ -105,7 +105,7 @@ MACHINE_END MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = msm7x30_map_io, .init_irq = msm7x30_init_irq, .init_machine = msm7x30_init, diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 6dde8185205..15c2bbd2ef8 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -118,7 +118,7 @@ static void __init qsd8x50_init(void) MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, @@ -128,7 +128,7 @@ MACHINE_END MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .map_io = qsd8x50_map_io, .init_irq = qsd8x50_init_irq, .init_machine = qsd8x50_init, diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c index 8919ffb1719..83604f526f0 100644 --- a/arch/arm/mach-msm/board-sapphire.c +++ b/arch/arm/mach-msm/board-sapphire.c @@ -107,7 +107,7 @@ MACHINE_START(SAPPHIRE, "sapphire") /* Maintainer: Brian Swetland */ #ifdef CONFIG_MSM_DEBUG_UART #endif - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, .fixup = sapphire_fixup, .map_io = sapphire_map_io, .init_irq = sapphire_init_irq, diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index a134a1413e0..e194d928cda 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -829,5 +829,5 @@ MACHINE_START(BALLOON3, "Balloon3") .init_irq = balloon3_init_irq, .timer = &pxa_timer, .init_machine = balloon3_init, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = PLAT_PHYS_OFFSET + 0x100, MACHINE_END diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 6ef5c5e528b..8ede983b861 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -484,7 +484,7 @@ static void __init realview_eb_init(void) MACHINE_START(REALVIEW_EB, "ARM-RealView EB") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_eb_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index cbdc97a5685..9f26369555c 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -379,7 +379,7 @@ static void __init realview_pb1176_init(void) MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pb1176_fixup, .map_io = realview_pb1176_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 8e8ab7d29a6..dea06b2da3a 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -381,7 +381,7 @@ static void __init realview_pb11mp_init(void) MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pb11mp_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 841118e3e11..7d0f1734a21 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -331,7 +331,7 @@ static void __init realview_pba8_init(void) MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_fixup, .map_io = realview_pba8_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 02b755b009d..b89e28f8853 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -414,7 +414,7 @@ static void __init realview_pbx_init(void) MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .fixup = realview_pbx_fixup, .map_io = realview_pbx_map_io, .init_irq = gic_init_irq, diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S index d4d222b716b..27376223ea9 100644 --- a/arch/arm/mach-s5pv210/sleep.S +++ b/arch/arm/mach-s5pv210/sleep.S @@ -65,7 +65,7 @@ resume_with_mmu: /* * After MMU is turned on, restore the previous MMU table. */ - ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET) + ldr r9 , =(PAGE_OFFSET - PLAT_PHYS_OFFSET) add r4, r4, r9 str r12, [r4] diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c index 7991415e666..fb6426ddeb7 100644 --- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c +++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c @@ -54,7 +54,7 @@ static void __init tcc8k_map_io(void) } MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .map_io = tcc8k_map_io, .init_irq = tcc8k_init_irq, .init_machine = tcc8k_init, diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index e628402b754..e9bccc5230c 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -243,7 +243,7 @@ static void __init ct_ca9x4_init(void) } MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") - .boot_params = PHYS_OFFSET + 0x00000100, + .boot_params = PLAT_PHYS_OFFSET + 0x00000100, .map_io = ct_ca9x4_map_io, .init_irq = ct_ca9x4_init_irq, #if 0 diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index cec5d56db2e..8ff605c83ac 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -27,7 +27,7 @@ * 2. We assume printascii is called at least once before paging_init, * and addruart has a chance to read OMAP_UART_INFO */ -#define OMAP_UART_INFO (PHYS_OFFSET + 0x3ffc) +#define OMAP_UART_INFO (PLAT_PHYS_OFFSET + 0x3ffc) /* OMAP1 serial ports */ #define OMAP1_UART1_BASE 0xfffb0000 -- cgit v1.2.3-70-g09d2 From 1b0b323c70cd5fdca967d89ed3a03dfebd84ada7 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:04 +0530 Subject: omap3: nand: configurable transfer type per board nand transfer type (sDMA, Polled, prefetch) can be select from board file, enabling all transfer type in driver, by default. this helps in multi-omap build and to select different transfer type for different board. Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/nand.h | 7 +++ drivers/mtd/nand/Kconfig | 17 ------ drivers/mtd/nand/omap2.c | 94 ++++++++++++---------------------- 3 files changed, 41 insertions(+), 77 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 6562cd082bb..78c0bdb98c1 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -10,6 +10,12 @@ #include +enum nand_io { + NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ + NAND_OMAP_POLLED, /* polled mode, without prefetch */ + NAND_OMAP_PREFETCH_DMA /* prefetch enabled sDMA mode */ +}; + struct omap_nand_platform_data { unsigned int options; int cs; @@ -20,6 +26,7 @@ struct omap_nand_platform_data { int (*nand_setup)(void); int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; + enum nand_io xfer_type; unsigned long phys_base; int devsize; }; diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index c89592239bc..178e2006063 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -106,23 +106,6 @@ config MTD_NAND_OMAP2 help Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms. -config MTD_NAND_OMAP_PREFETCH - bool "GPMC prefetch support for NAND Flash device" - depends on MTD_NAND_OMAP2 - default y - help - The NAND device can be accessed for Read/Write using GPMC PREFETCH engine - to improve the performance. - -config MTD_NAND_OMAP_PREFETCH_DMA - depends on MTD_NAND_OMAP_PREFETCH - bool "DMA mode" - default n - help - The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode - or in DMA interrupt mode. - Say y for DMA mode or MPU mode will be used - config MTD_NAND_IDS tristate diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 7c04cd6fb7a..60bac8e6e9f 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -96,27 +96,6 @@ static const char *part_probes[] = { "cmdlinepart", NULL }; #endif -#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH -static int use_prefetch = 1; - -/* "modprobe ... use_prefetch=0" etc */ -module_param(use_prefetch, bool, 0); -MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH"); - -#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA -static int use_dma = 1; - -/* "modprobe ... use_dma=0" etc */ -module_param(use_dma, bool, 0); -MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); -#else -static const int use_dma; -#endif -#else -const int use_prefetch; -static const int use_dma; -#endif - struct omap_nand_info { struct nand_hw_control controller; struct omap_nand_platform_data *pdata; @@ -324,7 +303,6 @@ static void omap_write_buf_pref(struct mtd_info *mtd, } } -#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA /* * omap_nand_dma_cb: callback on the completion of dma transfer * @lch: logical channel @@ -426,14 +404,6 @@ out_copy: : omap_write_buf8(mtd, (u_char *) addr, len); return 0; } -#else -static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {} -static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, - unsigned int len, int is_write) -{ - return 0; -} -#endif /** * omap_read_buf_dma_pref - read data from NAND controller into buffer @@ -842,28 +812,13 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.chip_delay = 50; } - if (use_prefetch) { - + switch (pdata->xfer_type) { + case NAND_OMAP_PREFETCH_POLLED: info->nand.read_buf = omap_read_buf_pref; info->nand.write_buf = omap_write_buf_pref; - if (use_dma) { - err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", - omap_nand_dma_cb, &info->comp, &info->dma_ch); - if (err < 0) { - info->dma_ch = -1; - printk(KERN_WARNING "DMA request failed." - " Non-dma data transfer mode\n"); - } else { - omap_set_dma_dest_burst_mode(info->dma_ch, - OMAP_DMA_DATA_BURST_16); - omap_set_dma_src_burst_mode(info->dma_ch, - OMAP_DMA_DATA_BURST_16); - - info->nand.read_buf = omap_read_buf_dma_pref; - info->nand.write_buf = omap_write_buf_dma_pref; - } - } - } else { + break; + + case NAND_OMAP_POLLED: if (info->nand.options & NAND_BUSWIDTH_16) { info->nand.read_buf = omap_read_buf16; info->nand.write_buf = omap_write_buf16; @@ -871,7 +826,33 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.read_buf = omap_read_buf8; info->nand.write_buf = omap_write_buf8; } + break; + + case NAND_OMAP_PREFETCH_DMA: + err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", + omap_nand_dma_cb, &info->comp, &info->dma_ch); + if (err < 0) { + info->dma_ch = -1; + dev_err(&pdev->dev, "DMA request failed!\n"); + goto out_release_mem_region; + } else { + omap_set_dma_dest_burst_mode(info->dma_ch, + OMAP_DMA_DATA_BURST_16); + omap_set_dma_src_burst_mode(info->dma_ch, + OMAP_DMA_DATA_BURST_16); + + info->nand.read_buf = omap_read_buf_dma_pref; + info->nand.write_buf = omap_write_buf_dma_pref; + } + break; + + default: + dev_err(&pdev->dev, + "xfer_type(%d) not supported!\n", pdata->xfer_type); + err = -EINVAL; + goto out_release_mem_region; } + info->nand.verify_buf = omap_verify_buf; #ifdef CONFIG_MTD_NAND_OMAP_HWECC @@ -897,6 +878,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } } + #ifdef CONFIG_MTD_PARTITIONS err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); if (err > 0) @@ -926,7 +908,7 @@ static int omap_nand_remove(struct platform_device *pdev) mtd); platform_set_drvdata(pdev, NULL); - if (use_dma) + if (info->dma_ch != -1) omap_free_dma(info->dma_ch); /* Release NAND device, its internal structures and partitions */ @@ -947,16 +929,8 @@ static struct platform_driver omap_nand_driver = { static int __init omap_nand_init(void) { - printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME); + pr_info("%s driver initializing\n", DRIVER_NAME); - /* This check is required if driver is being - * loaded run time as a module - */ - if ((1 == use_dma) && (0 == use_prefetch)) { - printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 " - "without use_prefetch'. Prefetch will not be" - " used in either mode (mpu or dma)\n"); - } return platform_driver_register(&omap_nand_driver); } -- cgit v1.2.3-70-g09d2 From db97eb7dfe13f6c04f0a0e77c32e2691f563ab8b Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:05 +0530 Subject: omap: gpmc: enable irq mode in gpmc add support the irq mode in GPMC. gpmc_init() function move after omap_init_irq() as it has dependecy on irq. Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 45 +++++++++++++++++++++++++++++++--- arch/arm/mach-omap2/io.c | 2 -- arch/arm/plat-omap/include/plat/gpmc.h | 5 +++- arch/arm/plat-omap/include/plat/irqs.h | 9 ++++++- 4 files changed, 54 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 1b7b3e7d02f..382dea83e4f 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -14,6 +14,7 @@ */ #undef DEBUG +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include @@ -100,6 +102,8 @@ static void __iomem *gpmc_base; static struct clk *gpmc_l3_clk; +static irqreturn_t gpmc_handle_irq(int irq, void *dev); + static void gpmc_write_reg(int idx, u32 val) { __raw_writel(val, gpmc_base + idx); @@ -497,6 +501,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval) u32 regval = 0; switch (cmd) { + case GPMC_ENABLE_IRQ: + gpmc_write_reg(GPMC_IRQENABLE, wval); + break; + case GPMC_SET_IRQ_STATUS: gpmc_write_reg(GPMC_IRQSTATUS, wval); break; @@ -678,9 +686,10 @@ static void __init gpmc_mem_init(void) } } -void __init gpmc_init(void) +static int __init gpmc_init(void) { - u32 l; + u32 l, irq; + int cs, ret = -EINVAL; char *ck = NULL; if (cpu_is_omap24xx()) { @@ -698,7 +707,7 @@ void __init gpmc_init(void) } if (WARN_ON(!ck)) - return; + return ret; gpmc_l3_clk = clk_get(NULL, ck); if (IS_ERR(gpmc_l3_clk)) { @@ -723,6 +732,36 @@ void __init gpmc_init(void) l |= (0x02 << 3) | (1 << 0); gpmc_write_reg(GPMC_SYSCONFIG, l); gpmc_mem_init(); + + /* initalize the irq_chained */ + irq = OMAP_GPMC_IRQ_BASE; + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + set_irq_handler(irq, handle_simple_irq); + set_irq_flags(irq, IRQF_VALID); + irq++; + } + + ret = request_irq(INT_34XX_GPMC_IRQ, + gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); + if (ret) + pr_err("gpmc: irq-%d could not claim: err %d\n", + INT_34XX_GPMC_IRQ, ret); + return ret; +} +postcore_initcall(gpmc_init); + +static irqreturn_t gpmc_handle_irq(int irq, void *dev) +{ + u8 cs; + + if (irq != INT_34XX_GPMC_IRQ) + return IRQ_HANDLED; + /* check cs to invoke the irq */ + cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; + if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) + generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); + + return IRQ_HANDLED; } #ifdef CONFIG_ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b8b49e4ae92..657f3c84687 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -30,7 +30,6 @@ #include #include -#include #include #include "clock2xxx.h" @@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); } - gpmc_init(); omap_irq_base_init(); } diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 85ded598853..9c060da0a87 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -41,6 +41,8 @@ #define GPMC_NAND_ADDRESS 0x0000000b #define GPMC_NAND_DATA 0x0000000c +#define GPMC_ENABLE_IRQ 0x0000000d + /* ECC commands */ #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ @@ -78,6 +80,8 @@ #define WR_RD_PIN_MONITORING 0x00600000 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) +#define GPMC_IRQ_FIFOEVENTENABLE 0x01 +#define GPMC_IRQ_COUNT_EVENT 0x02 /* * Note that all values in this struct are in nanoseconds except sync_clk @@ -135,7 +139,6 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode, extern int gpmc_prefetch_reset(int cs); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); -extern void gpmc_init(void); extern int gpmc_read_status(int cmd); extern int gpmc_cs_configure(int cs, int cmd, int wval); extern int gpmc_nand_read(int cs, int cmd); diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 2910de921c5..1b911681e91 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -318,6 +318,7 @@ #define INT_34XX_PRCM_MPU_IRQ 11 #define INT_34XX_MCBSP1_IRQ 16 #define INT_34XX_MCBSP2_IRQ 17 +#define INT_34XX_GPMC_IRQ 20 #define INT_34XX_MCBSP3_IRQ 22 #define INT_34XX_MCBSP4_IRQ 23 #define INT_34XX_CAM_IRQ 24 @@ -411,7 +412,13 @@ #define TWL_IRQ_END TWL6030_IRQ_END #endif -#define NR_IRQS TWL_IRQ_END +/* GPMC related */ +#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END) +#define OMAP_GPMC_NR_IRQS 7 +#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) + + +#define NR_IRQS OMAP_GPMC_IRQ_END #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) -- cgit v1.2.3-70-g09d2 From 4e070376165a9b7f245fada77645b81352c6ec78 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:06 +0530 Subject: omap3: nand: prefetch in irq mode support This patch enable prefetch-irq mode for nand transfer(read, write) Signed-off-by: Vimal Singh Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-flash.c | 2 + arch/arm/plat-omap/include/plat/nand.h | 4 +- drivers/mtd/nand/omap2.c | 198 +++++++++++++++++++++++++++++++-- 3 files changed, 194 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index f6b72533c08..19645095d59 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -147,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.nr_parts = nr_parts; board_nand_data.devsize = nand_type; + board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; gpmc_nand_init(&board_nand_data); } #else diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 78c0bdb98c1..ae5e0538303 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -13,7 +13,8 @@ enum nand_io { NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ NAND_OMAP_POLLED, /* polled mode, without prefetch */ - NAND_OMAP_PREFETCH_DMA /* prefetch enabled sDMA mode */ + NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */ + NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */ }; struct omap_nand_platform_data { @@ -26,6 +27,7 @@ struct omap_nand_platform_data { int (*nand_setup)(void); int (*dev_ready)(struct omap_nand_platform_data *); int dma_channel; + int gpmc_irq; enum nand_io xfer_type; unsigned long phys_base; int devsize; diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 60bac8e6e9f..fbe84146717 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #define DRIVER_NAME "omap2-nand" +#define OMAP_NAND_TIMEOUT_MS 5000 #define NAND_Ecc_P1e (1 << 0) #define NAND_Ecc_P2e (1 << 1) @@ -108,6 +110,13 @@ struct omap_nand_info { unsigned long phys_base; struct completion comp; int dma_ch; + int gpmc_irq; + enum { + OMAP_NAND_IO_READ = 0, /* read */ + OMAP_NAND_IO_WRITE, /* write */ + } iomode; + u_char *buf; + int buf_len; }; /** @@ -267,9 +276,10 @@ static void omap_write_buf_pref(struct mtd_info *mtd, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - uint32_t pref_count = 0, w_count = 0; + uint32_t w_count = 0; int i = 0, ret = 0; u16 *p; + unsigned long tim, limit; /* take care of subpage writes */ if (len % 2 != 0) { @@ -295,9 +305,12 @@ static void omap_write_buf_pref(struct mtd_info *mtd, iowrite16(*p++, info->nand.IO_ADDR_W); } /* wait for data to flushed-out before reset the prefetch */ - do { - pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT); - } while (pref_count); + tim = 0; + limit = (loops_per_jiffy * + msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); + while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + cpu_relax(); + /* disable and stop the PFPW engine */ gpmc_prefetch_reset(info->gpmc_cs); } @@ -326,11 +339,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); - uint32_t prefetch_status = 0; enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; dma_addr_t dma_addr; int ret; + unsigned long tim, limit; /* The fifo depth is 64 bytes. We have a sync at each frame and frame * length is 64 bytes. @@ -376,7 +389,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, /* configure and start prefetch transfer */ ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); if (ret) - /* PFPW engine is busy, use cpu copy methode */ + /* PFPW engine is busy, use cpu copy method */ goto out_copy; init_completion(&info->comp); @@ -385,10 +398,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, /* setup and start DMA using dma_addr */ wait_for_completion(&info->comp); + tim = 0; + limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); + while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + cpu_relax(); - do { - prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT); - } while (prefetch_status); /* disable and stop the PFPW engine */ gpmc_prefetch_reset(info->gpmc_cs); @@ -436,6 +450,155 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd, omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); } +/* + * omap_nand_irq - GMPC irq handler + * @this_irq: gpmc irq number + * @dev: omap_nand_info structure pointer is passed here + */ +static irqreturn_t omap_nand_irq(int this_irq, void *dev) +{ + struct omap_nand_info *info = (struct omap_nand_info *) dev; + u32 bytes; + u32 irq_stat; + + irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); + bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); + bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ + if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ + if (irq_stat & 0x2) + goto done; + + if (info->buf_len && (info->buf_len < bytes)) + bytes = info->buf_len; + else if (!info->buf_len) + bytes = 0; + iowrite32_rep(info->nand.IO_ADDR_W, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + info->buf_len -= bytes; + + } else { + ioread32_rep(info->nand.IO_ADDR_R, + (u32 *)info->buf, bytes >> 2); + info->buf = info->buf + bytes; + + if (irq_stat & 0x2) + goto done; + } + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); + + return IRQ_HANDLED; + +done: + complete(&info->comp); + /* disable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); + + /* clear status */ + gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); + + return IRQ_HANDLED; +} + +/* + * omap_read_buf_irq_pref - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + */ +static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + int ret = 0; + + if (len <= mtd->oobsize) { + omap_read_buf_pref(mtd, buf, len); + return; + } + + info->iomode = OMAP_NAND_IO_READ; + info->buf = buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + if (ret) + /* PFPW engine is busy, use cpu copy method */ + goto out_copy; + + info->buf_len = len; + /* enable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + /* waiting for read to complete */ + wait_for_completion(&info->comp); + + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_read_buf16(mtd, buf, len); + else + omap_read_buf8(mtd, buf, len); +} + +/* + * omap_write_buf_irq_pref - write buffer to NAND controller + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + */ +static void omap_write_buf_irq_pref(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct omap_nand_info *info = container_of(mtd, + struct omap_nand_info, mtd); + int ret = 0; + unsigned long tim, limit; + + if (len <= mtd->oobsize) { + omap_write_buf_pref(mtd, buf, len); + return; + } + + info->iomode = OMAP_NAND_IO_WRITE; + info->buf = (u_char *) buf; + init_completion(&info->comp); + + /* configure and start prefetch transfer */ + ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + if (ret) + /* PFPW engine is busy, use cpu copy method */ + goto out_copy; + + info->buf_len = len; + /* enable irq */ + gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, + (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); + + /* waiting for write to complete */ + wait_for_completion(&info->comp); + /* wait for data to flushed-out before reset the prefetch */ + tim = 0; + limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); + while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) + cpu_relax(); + + /* disable and stop the PFPW engine */ + gpmc_prefetch_reset(info->gpmc_cs); + return; + +out_copy: + if (info->nand.options & NAND_BUSWIDTH_16) + omap_write_buf16(mtd, buf, len); + else + omap_write_buf8(mtd, buf, len); +} + /** * omap_verify_buf - Verify chip data against buffer * @mtd: MTD device structure @@ -846,6 +1009,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } break; + case NAND_OMAP_PREFETCH_IRQ: + err = request_irq(pdata->gpmc_irq, + omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); + if (err) { + dev_err(&pdev->dev, "requesting irq(%d) error:%d", + pdata->gpmc_irq, err); + goto out_release_mem_region; + } else { + info->gpmc_irq = pdata->gpmc_irq; + info->nand.read_buf = omap_read_buf_irq_pref; + info->nand.write_buf = omap_write_buf_irq_pref; + } + break; + default: dev_err(&pdev->dev, "xfer_type(%d) not supported!\n", pdata->xfer_type); @@ -911,6 +1088,9 @@ static int omap_nand_remove(struct platform_device *pdev) if (info->dma_ch != -1) omap_free_dma(info->dma_ch); + if (info->gpmc_irq) + free_irq(info->gpmc_irq, info); + /* Release NAND device, its internal structures and partitions */ nand_release(&info->mtd); iounmap(info->nand.IO_ADDR_R); -- cgit v1.2.3-70-g09d2 From 317379a975c07fe63bc4f86dabd668df96ff3df2 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:07 +0530 Subject: omap3: nand: configurable fifo threshold to gain the throughput Configure the FIFO THREASHOLD value different for read and write to keep busy both filling and to drain out of FIFO at reading and writing. Signed-off-by: Vimal Singh Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 11 +++++++---- arch/arm/plat-omap/include/plat/gpmc.h | 5 ++++- drivers/mtd/nand/omap2.c | 22 ++++++++++++++-------- 3 files changed, 25 insertions(+), 13 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 382dea83e4f..674174365f7 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -60,7 +60,6 @@ #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ #define GPMC_SECTION_SHIFT 28 /* 128 MB */ -#define PREFETCH_FIFOTHRESHOLD (0x40 << 8) #define CS_NUM_SHIFT 24 #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 @@ -606,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write); /** * gpmc_prefetch_enable - configures and starts prefetch transfer * @cs: cs (chip select) number + * @fifo_th: fifo threshold to be used for read/ write * @dma_mode: dma mode enable (1) or disable (0) * @u32_count: number of bytes to be transferred * @is_write: prefetch read(0) or write post(1) mode */ -int gpmc_prefetch_enable(int cs, int dma_mode, +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, unsigned int u32_count, int is_write) { - if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { + if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { + pr_err("gpmc: fifo threshold is not supported\n"); + return -1; + } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { /* Set the amount of bytes to be prefetched */ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); @@ -622,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode, * enable the engine. Set which cs is has requested for. */ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | - PREFETCH_FIFOTHRESHOLD | + PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) | (0x1 & is_write))); diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 9c060da0a87..a2434639063 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -83,6 +83,9 @@ #define GPMC_IRQ_FIFOEVENTENABLE 0x01 #define GPMC_IRQ_COUNT_EVENT 0x02 +#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 +#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) + /* * Note that all values in this struct are in nanoseconds except sync_clk * (which is in picoseconds), while the register values are in gpmc_fck cycles. @@ -134,7 +137,7 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); extern int gpmc_cs_set_reserved(int cs, int reserved); extern int gpmc_cs_reserved(int cs); -extern int gpmc_prefetch_enable(int cs, int dma_mode, +extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, unsigned int u32_count, int is_write); extern int gpmc_prefetch_reset(int cs); extern void omap3_gpmc_save_context(void); diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index fbe84146717..f1648fd5924 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -244,7 +244,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -289,7 +290,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd, } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); if (ret) { /* PFPW engine is busy, use cpu copy method */ if (info->nand.options & NAND_BUSWIDTH_16) @@ -345,8 +347,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, int ret; unsigned long tim, limit; - /* The fifo depth is 64 bytes. We have a sync at each frame and frame - * length is 64 bytes. + /* The fifo depth is 64 bytes max. + * But configure the FIFO-threahold to 32 to get a sync at each frame + * and frame length is 32 bytes. */ int buf_len = len >> 6; @@ -387,7 +390,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); } /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; @@ -522,7 +526,8 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) init_completion(&info->comp); /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); + ret = gpmc_prefetch_enable(info->gpmc_cs, + PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; @@ -569,8 +574,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd, info->buf = (u_char *) buf; init_completion(&info->comp); - /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); + /* configure and start prefetch transfer : size=24 */ + ret = gpmc_prefetch_enable(info->gpmc_cs, + (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1); if (ret) /* PFPW engine is busy, use cpu copy method */ goto out_copy; -- cgit v1.2.3-70-g09d2 From f3d73f362d689a1d044e77964864f0a8ea0217f3 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:08 +0530 Subject: omap3: nand: ecc layout select from board file This patch makes it possible to select sw or hw (different layout options) ecc scheme supported by omap nand driver. Signed-off-by: Vimal Singh Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-flash.c | 1 + arch/arm/plat-omap/include/plat/gpmc.h | 6 ++++++ arch/arm/plat-omap/include/plat/nand.h | 2 ++ drivers/mtd/nand/omap2.c | 26 +++++++++++--------------- 4 files changed, 20 insertions(+), 15 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 19645095d59..a7681981201 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -148,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.nr_parts = nr_parts; board_nand_data.devsize = nand_type; + board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; gpmc_nand_init(&board_nand_data); } diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index a2434639063..773351bc25a 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -86,6 +86,12 @@ #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) +enum omap_ecc { + /* 1-bit ecc: stored at end of spare area */ + OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ + OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ +}; + /* * Note that all values in this struct are in nanoseconds except sync_clk * (which is in picoseconds), while the register values are in gpmc_fck cycles. diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index ae5e0538303..d86d1ecf006 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ +#include #include enum nand_io { @@ -31,6 +32,7 @@ struct omap_nand_platform_data { enum nand_io xfer_type; unsigned long phys_base; int devsize; + enum omap_ecc ecc_opt; }; /* minimum size for IO mapping */ diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index f1648fd5924..6d4a42e3938 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -626,8 +626,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) return 0; } -#ifdef CONFIG_MTD_NAND_OMAP_HWECC - /** * gen_true_ecc - This function will generate true ECC value * @ecc_buf: buffer to store ecc code @@ -847,8 +845,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode) gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); } -#endif - /** * omap_wait - wait until the command is done * @mtd: MTD device structure @@ -1038,17 +1034,17 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) info->nand.verify_buf = omap_verify_buf; -#ifdef CONFIG_MTD_NAND_OMAP_HWECC - info->nand.ecc.bytes = 3; - info->nand.ecc.size = 512; - info->nand.ecc.calculate = omap_calculate_ecc; - info->nand.ecc.hwctl = omap_enable_hwecc; - info->nand.ecc.correct = omap_correct_data; - info->nand.ecc.mode = NAND_ECC_HW; - -#else - info->nand.ecc.mode = NAND_ECC_SOFT; -#endif + /* selsect the ecc type */ + if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) + info->nand.ecc.mode = NAND_ECC_SOFT; + else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) { + info->nand.ecc.bytes = 3; + info->nand.ecc.size = 512; + info->nand.ecc.calculate = omap_calculate_ecc; + info->nand.ecc.hwctl = omap_enable_hwecc; + info->nand.ecc.correct = omap_correct_data; + info->nand.ecc.mode = NAND_ECC_HW; + } /* DIP switches on some boards change between 8 and 16 bit * bus widths for flash. Try the other width if the first try fails. -- cgit v1.2.3-70-g09d2 From f040d33253b2daf6f305fc35fca2399047ced028 Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Fri, 28 Jan 2011 15:42:09 +0530 Subject: omap3: nand: making ecc layout as compatible with romcode ecc This patch overrides nand ecc layout and bad block descriptor (for 8-bit device) to support hw ecc in romcode layout. So as to have in sync with ecc layout throughout; i.e. x-loader, u-boot and kernel. This enables to flash x-loader, u-boot, kernel, FS images from kernel itself and compatiable with other tools. This patch does not enables this feature by default and need to pass from board file to enable for any board. Signed-off-by: Vimal Singh Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/gpmc.h | 2 ++ drivers/mtd/nand/omap2.c | 37 +++++++++++++++++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 773351bc25a..12b31616503 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -90,6 +90,8 @@ enum omap_ecc { /* 1-bit ecc: stored at end of spare area */ OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ + /* 1-bit ecc: stored at begining of spare area as romcode */ + OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */ }; /* diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 6d4a42e3938..4e33972ad17 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -98,6 +98,20 @@ static const char *part_probes[] = { "cmdlinepart", NULL }; #endif +/* oob info generated runtime depending on ecc algorithm and layout selected */ +static struct nand_ecclayout omap_oobinfo; +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks + */ +static uint8_t scan_ff_pattern[] = { 0xff }; +static struct nand_bbt_descr bb_descrip_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0, + .len = 1, + .pattern = scan_ff_pattern, +}; + + struct omap_nand_info { struct nand_hw_control controller; struct omap_nand_platform_data *pdata; @@ -914,6 +928,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) struct omap_nand_info *info; struct omap_nand_platform_data *pdata; int err; + int i, offset; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1037,7 +1052,8 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) /* selsect the ecc type */ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) info->nand.ecc.mode = NAND_ECC_SOFT; - else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) { + else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || + (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { info->nand.ecc.bytes = 3; info->nand.ecc.size = 512; info->nand.ecc.calculate = omap_calculate_ecc; @@ -1057,6 +1073,25 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) } } + /* rom code layout */ + if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { + + if (info->nand.options & NAND_BUSWIDTH_16) + offset = 2; + else { + offset = 1; + info->nand.badblock_pattern = &bb_descrip_flashbased; + } + omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); + for (i = 0; i < omap_oobinfo.eccbytes; i++) + omap_oobinfo.eccpos[i] = i+offset; + + omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; + omap_oobinfo.oobfree->length = info->mtd.oobsize - + (offset + omap_oobinfo.eccbytes); + + info->nand.ecc.layout = &omap_oobinfo; + } #ifdef CONFIG_MTD_PARTITIONS err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); -- cgit v1.2.3-70-g09d2 From 3ad2d861362031dac8b2bba78a8f4c575300948f Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 7 Feb 2011 10:46:59 +0200 Subject: OMAP: OneNAND: determine frequency in one place OneNAND frequency is determined when calculating GPMC timings. Return that value instead of determining it again in the OMAP OneNAND driver. Signed-off-by: Adrian Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-onenand.c | 10 ++++++---- arch/arm/plat-omap/include/plat/onenand.h | 2 +- drivers/mtd/onenand/omap2.c | 28 +++++----------------------- 3 files changed, 12 insertions(+), 28 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 3a4307b8f7c..46786a606e9 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -123,7 +123,7 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency, static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, void __iomem *onenand_base, - int freq) + int *freq_ptr) { struct gpmc_timings t; const int t_cer = 15; @@ -136,7 +136,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; int err, ticks_cez; - int cs = cfg->cs; + int cs = cfg->cs, freq = *freq_ptr; u32 reg; if (cfg->flags & ONENAND_SYNC_READ) { @@ -330,16 +330,18 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); + *freq_ptr = freq; + return 0; } -static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) +static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) { struct device *dev = &gpmc_onenand_device.dev; /* Set sync timings in GPMC */ if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, - freq) < 0) { + freq_ptr) < 0) { dev_err(dev, "Unable to set synchronous mode\n"); return -EINVAL; } diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index affe87e9ece..86118dc3f19 100644 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h @@ -20,7 +20,7 @@ struct omap_onenand_platform_data { int gpio_irq; struct mtd_partition *parts; int nr_parts; - int (*onenand_setup)(void __iomem *, int freq); + int (*onenand_setup)(void __iomem *, int *freq_ptr); int dma_channel; u8 flags; u8 regulator_can_sleep; diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c index ac31f461cc1..3e1bb956882 100644 --- a/drivers/mtd/onenand/omap2.c +++ b/drivers/mtd/onenand/omap2.c @@ -63,7 +63,7 @@ struct omap2_onenand { struct completion dma_done; int dma_channel; int freq; - int (*setup)(void __iomem *base, int freq); + int (*setup)(void __iomem *base, int *freq_ptr); struct regulator *regulator; }; @@ -581,7 +581,7 @@ static int __adjust_timing(struct device *dev, void *data) /* DMA is not in use so this is all that is needed */ /* Revisit for OMAP3! */ - ret = c->setup(c->onenand.base, c->freq); + ret = c->setup(c->onenand.base, &c->freq); return ret; } @@ -673,7 +673,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev) } if (pdata->onenand_setup != NULL) { - r = pdata->onenand_setup(c->onenand.base, c->freq); + r = pdata->onenand_setup(c->onenand.base, &c->freq); if (r < 0) { dev_err(&pdev->dev, "Onenand platform setup failed: " "%d\n", r); @@ -718,8 +718,8 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev) } dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual " - "base %p\n", c->gpmc_cs, c->phys_base, - c->onenand.base); + "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base, + c->onenand.base, c->freq); c->pdev = pdev; c->mtd.name = dev_name(&pdev->dev); @@ -754,24 +754,6 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev) if ((r = onenand_scan(&c->mtd, 1)) < 0) goto err_release_regulator; - switch ((c->onenand.version_id >> 4) & 0xf) { - case 0: - c->freq = 40; - break; - case 1: - c->freq = 54; - break; - case 2: - c->freq = 66; - break; - case 3: - c->freq = 83; - break; - case 4: - c->freq = 104; - break; - } - #ifdef CONFIG_MTD_PARTITIONS r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0); if (r > 0) -- cgit v1.2.3-70-g09d2 From 5714b7ed6b3e3c00c0d4719bb66757e64c30ecf6 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 7 Feb 2011 10:47:00 +0200 Subject: OMAP: OneNAND: let boards determine OneNAND frequency OneNAND version ID may not give the highest frequency supported and some OneNAND's have setup times that are clock dependent. Let the board provide that information. Signed-off-by: Adrian Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-onenand.c | 80 +++++++++++++++++++++++-------- arch/arm/plat-omap/include/plat/onenand.h | 8 ++++ 2 files changed, 67 insertions(+), 21 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 46786a606e9..d776ded9830 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -121,6 +121,47 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency, writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); } +static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, + void __iomem *onenand_base, bool *clk_dep) +{ + u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); + int freq = 0; + + if (cfg->get_freq) { + struct onenand_freq_info fi; + + fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID); + fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID); + fi.ver_id = ver; + freq = cfg->get_freq(&fi, clk_dep); + if (freq) + return freq; + } + + switch ((ver >> 4) & 0xf) { + case 0: + freq = 40; + break; + case 1: + freq = 54; + break; + case 2: + freq = 66; + break; + case 3: + freq = 83; + break; + case 4: + freq = 104; + break; + default: + freq = 54; + break; + } + + return freq; +} + static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, void __iomem *onenand_base, int *freq_ptr) @@ -138,6 +179,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, int err, ticks_cez; int cs = cfg->cs, freq = *freq_ptr; u32 reg; + bool clk_dep = false; if (cfg->flags & ONENAND_SYNC_READ) { sync_read = 1; @@ -152,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, err = omap2_onenand_set_async_mode(cs, onenand_base); if (err) return err; - reg = readw(onenand_base + ONENAND_REG_VERSION_ID); - switch ((reg >> 4) & 0xf) { - case 0: - freq = 40; - break; - case 1: - freq = 54; - break; - case 2: - freq = 66; - break; - case 3: - freq = 83; - break; - case 4: - freq = 104; - break; - default: - freq = 54; - break; - } + freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep); first_time = 1; } @@ -232,6 +254,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, else latency = 4; + if (clk_dep) { + if (gpmc_clk_ns < 12) { /* >83Mhz */ + t_ces = 3; + t_avds = 4; + } else if (gpmc_clk_ns < 15) { /* >66Mhz */ + t_ces = 5; + t_avds = 4; + } else if (gpmc_clk_ns < 25) { /* >40Mhz */ + t_ces = 6; + t_avds = 5; + } else { + t_ces = 7; + t_avds = 7; + } + } + if (first_time) set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h index 86118dc3f19..cbe897ca7f9 100644 --- a/arch/arm/plat-omap/include/plat/onenand.h +++ b/arch/arm/plat-omap/include/plat/onenand.h @@ -15,12 +15,20 @@ #define ONENAND_SYNC_READ (1 << 0) #define ONENAND_SYNC_READWRITE (1 << 1) +struct onenand_freq_info { + u16 maf_id; + u16 dev_id; + u16 ver_id; +}; + struct omap_onenand_platform_data { int cs; int gpio_irq; struct mtd_partition *parts; int nr_parts; int (*onenand_setup)(void __iomem *, int *freq_ptr); + int (*get_freq)(const struct onenand_freq_info *freq_info, + bool *clk_dep); int dma_channel; u8 flags; u8 regulator_can_sleep; -- cgit v1.2.3-70-g09d2 From 4f85f99b1e9ae9d62e3ea9f0cd3827020e0d9ba2 Mon Sep 17 00:00:00 2001 From: David Cohen Date: Tue, 15 Feb 2011 11:31:13 +0000 Subject: omap: IOMMU: add missing function declaration Declaration of exported function 'iopgtable_lookup_entry' is missing from header file. Currently we have a sparse warning as it's not being used externally. Adding its declaration to avoid such warning and allow its usage in future. Signed-off-by: David Cohen Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/iommu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 69230d68553..19cbb5e9ece 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -154,6 +154,8 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); extern void flush_iotlb_all(struct iommu *obj); extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); +extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, + u32 **ppte); extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); -- cgit v1.2.3-70-g09d2 From e49c4d27ab5ffd0d8707685af9ca2866a95660e8 Mon Sep 17 00:00:00 2001 From: Nishant Kamat Date: Thu, 17 Feb 2011 09:55:03 -0800 Subject: omap: Add chip id recognition for OMAP4 ES2.1 and ES2.2 Allow OMAP4 ES2.1 and ES2.2 revisions to be recognized in the omap4_check_revision() function. Mainly, ES2.1 has fixes that allow LPDDR to be used at 100% OPP (400MHz). ES2.2 additionally has a couple of power management fixes (to reduce leakage), an I2C1 SDA line state fix, and a floating point write corruption fix (cortex erratum). Even though the current mainline support doesn't need to distinguish between ES2.X versions, it's still useful to know the correct silicon rev when issues are reported. Moreover, these id checks can be used by power management code that selects suitable OPPs considering the memory speed limitation on ES2.0. For details about the silicon errata on OMAP4430, refer http://focus.ti.com/pdfs/wtbu/SWPZ009A_OMAP4430_Errata_Public_vA.pdf Signed-off-by: Nishant Kamat Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/id.c | 31 ++++++++++++++++++++----------- arch/arm/plat-omap/include/plat/cpu.h | 16 +++++++++++----- 2 files changed, 31 insertions(+), 16 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 5c25f1b5523..3168b17bc26 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -6,7 +6,7 @@ * Copyright (C) 2005 Nokia Corporation * Written by Tony Lindgren * - * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2009-11 Texas Instruments * Added OMAP4 support - Santosh Shilimkar * * This program is free software; you can redistribute it and/or modify @@ -328,7 +328,7 @@ static void __init omap4_check_revision(void) */ idcode = read_tap_reg(OMAP_TAP_IDCODE); hawkeye = (idcode >> 12) & 0xffff; - rev = (idcode >> 28) & 0xff; + rev = (idcode >> 28) & 0xf; /* * Few initial ES2.0 samples IDCODE is same as ES1.0 @@ -347,22 +347,31 @@ static void __init omap4_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP4430ES1; break; case 1: + default: omap_revision = OMAP4430_REV_ES2_0; omap_chip.oc |= CHIP_IS_OMAP4430ES2; + } + break; + case 0xb95c: + switch (rev) { + case 3: + omap_revision = OMAP4430_REV_ES2_1; + omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; break; + case 4: default: - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; - } - break; + omap_revision = OMAP4430_REV_ES2_2; + omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; + } + break; default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; + /* Unknown default to latest silicon rev as default */ + omap_revision = OMAP4430_REV_ES2_2; + omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; } - pr_info("OMAP%04x ES%d.0\n", - omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); + pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, + ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); } #define OMAP3_SHOW_FEATURE(feat) \ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index be99438d385..8198bb6cdb5 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -5,7 +5,7 @@ * * Copyright (C) 2004, 2008 Nokia Corporation * - * Copyright (C) 2009 Texas Instruments. + * Copyright (C) 2009-11 Texas Instruments. * * Written by Tony Lindgren * @@ -405,8 +405,10 @@ IS_OMAP_TYPE(3517, 0x3517) #define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) #define OMAP443X_CLASS 0x44300044 -#define OMAP4430_REV_ES1_0 OMAP443X_CLASS -#define OMAP4430_REV_ES2_0 0x44301044 +#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) +#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) +#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) +#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) /* * omap_chip bits @@ -434,12 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) #define CHIP_IS_OMAP4430ES2 (1 << 11) +#define CHIP_IS_OMAP4430ES2_1 (1 << 12) +#define CHIP_IS_OMAP4430ES2_2 (1 << 13) #define CHIP_IS_TI816X (1 << 14) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ - CHIP_IS_OMAP4430ES2) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ + CHIP_IS_OMAP4430ES2 | \ + CHIP_IS_OMAP4430ES2_1 | \ + CHIP_IS_OMAP4430ES2_2) /* * "GE" here represents "greater than or equal to" in terms of ES -- cgit v1.2.3-70-g09d2 From ee896e348cf6f323a00e4ee52e6386f515f86cee Mon Sep 17 00:00:00 2001 From: Hema HK Date: Thu, 17 Feb 2011 12:06:07 +0530 Subject: usb: otg: OMAP4430: Introducing suspend function for power management Introduced the suspend/resume function for the OMAP4430 internal PHY. This will be used by the twl6030-usb transceiver driver. Moved the clock enable/disable function calls and power on/off of the PHY code from power on/off functions to suspend/resume function. Pass the suspend function through board data for OMAP4430sdp and OMAP4panda. This will be used by the twl6030-usb transceiver driver. Signed-off-by: Hema HK Cc: Tony Lindgren Cc: Paul Walmsley Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/board-4430sdp.c | 1 + arch/arm/mach-omap2/board-omap4panda.c | 1 + arch/arm/mach-omap2/omap_phy_internal.c | 22 +++++++++++++++------- arch/arm/plat-omap/include/plat/usb.h | 1 + 4 files changed, 18 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 07d1b20b114..9cf8e333255 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -272,6 +272,7 @@ static struct twl4030_usb_data omap4_usbphy_data = { .phy_exit = omap4430_phy_exit, .phy_power = omap4430_phy_power, .phy_set_clock = omap4430_phy_set_clk, + .phy_suspend = omap4430_phy_suspend, }; static struct omap2_hsmmc_info mmc[] = { diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index e944025d5ef..77748f81366 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -153,6 +153,7 @@ static struct twl4030_usb_data omap4_usbphy_data = { .phy_exit = omap4430_phy_exit, .phy_power = omap4430_phy_power, .phy_set_clock = omap4430_phy_set_clk, + .phy_suspend = omap4430_phy_suspend, }; static struct omap2_hsmmc_info mmc[] = { diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index 745252c60e3..3ce675899fc 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -103,13 +103,6 @@ int omap4430_phy_set_clk(struct device *dev, int on) int omap4430_phy_power(struct device *dev, int ID, int on) { if (on) { - /* enabled the clocks */ - omap4430_phy_set_clk(dev, 1); - /* power on the phy */ - if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { - __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); - mdelay(200); - } if (ID) /* enable VBUS valid, IDDIG groung */ __raw_writel(AVALID | VBUSVALID, ctrl_base + @@ -125,10 +118,25 @@ int omap4430_phy_power(struct device *dev, int ID, int on) /* Enable session END and IDIG to high impedence. */ __raw_writel(SESSEND | IDDIG, ctrl_base + USBOTGHS_CONTROL); + } + return 0; +} + +int omap4430_phy_suspend(struct device *dev, int suspend) +{ + if (suspend) { /* Disable the clocks */ omap4430_phy_set_clk(dev, 0); /* Power down the phy */ __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); + } else { + /* Enable the internel phy clcoks */ + omap4430_phy_set_clk(dev, 1); + /* power on the phy */ + if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { + __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); + mdelay(200); + } } return 0; diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 450a332f100..f888e0e57dc 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -88,6 +88,7 @@ extern int omap4430_phy_power(struct device *dev, int ID, int on); extern int omap4430_phy_set_clk(struct device *dev, int on); extern int omap4430_phy_init(struct device *dev); extern int omap4430_phy_exit(struct device *dev); +extern int omap4430_phy_suspend(struct device *dev, int suspend); #endif -- cgit v1.2.3-70-g09d2 From 996746ca127d722c279325552cdcc48b20079a61 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Tue, 22 Feb 2011 09:50:36 +0200 Subject: OMAP2420: hwmod data: add DSS DISPC RFBI VENC Hwmod needs database of all IPs in a system. This patch generates the hwmod database for OMAP2420 Display Sub System,. Since DSS is also considered as an IP as DISPC, RFBI, name it as dss_core. Acked-by: Benoit Cousson Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 310 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/l3_2xxx.h | 20 ++ arch/arm/plat-omap/include/plat/l4_2xxx.h | 24 +++ 3 files changed, 354 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/l3_2xxx.h create mode 100644 arch/arm/plat-omap/include/plat/l4_2xxx.h (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 7fffd340c76..f323c6bb22d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include "omap_hwmod_common_data.h" @@ -39,6 +41,10 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_iva_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_dss_core_hwmod; +static struct omap_hwmod omap2420_dss_dispc_hwmod; +static struct omap_hwmod omap2420_dss_rfbi_hwmod; +static struct omap_hwmod omap2420_dss_venc_hwmod; static struct omap_hwmod omap2420_wd_timer2_hwmod; static struct omap_hwmod omap2420_gpio1_hwmod; static struct omap_hwmod omap2420_gpio2_hwmod; @@ -67,6 +73,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { &omap2420_mpu__l3_main, }; +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap2420_dss__l3 = { + .master = &omap2420_dss_core_hwmod, + .slave = &omap2420_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Master interfaces on the L3 interconnect */ static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { &omap2420_l3_main__l4_core, @@ -509,6 +528,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_dss_hwmod_class = { + .name = "dss", + .sysc = &omap2420_dss_sysc, +}; + +/* dss */ +static struct omap_hwmod_irq_info omap2420_dss_irqs[] = { + { .irq = 25 }, +}; + +static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { + &omap2420_dss__l3, +}; + +static struct omap_hwmod_addr_space omap2420_dss_addrs[] = { + { + .pa_start = 0x48050000, + .pa_end = 0x480503FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap2420_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { + &omap2420_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_54m_fck" }, + { .role = "sys_clk", .clk = "dss2_fck" }, +}; + +static struct omap_hwmod omap2420_dss_core_hwmod = { + .name = "dss_core", + .class = &omap2420_dss_hwmod_class, + .main_clk = "dss1_fck", /* instead of dss_fck */ + .mpu_irqs = omap2420_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs), + .sdma_reqs = omap2420_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap2420_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), + .masters = omap2420_dss_masters, + .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap2420_dispc_sysc, +}; + +static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { + { + .pa_start = 0x48050400, + .pa_end = 0x480507FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap2420_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { + &omap2420_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap2420_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap2420_dispc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, + }, + }, + .slaves = omap2420_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap2420_rfbi_sysc, +}; + +static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = { + { + .pa_start = 0x48050800, + .pa_end = 0x48050BFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap2420_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { + &omap2420_l4_core__dss_rfbi, +}; + +static struct omap_hwmod omap2420_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap2420_rfbi_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2420_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap2420_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = { + { + .pa_start = 0x48050C00, + .pa_end = 0x48050FFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_dss_venc_hwmod, + .clk = "dss_54m_fck", + .addr = omap2420_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { + &omap2420_l4_core__dss_venc, +}; + +static struct omap_hwmod omap2420_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap2420_venc_hwmod_class, + .main_clk = "dss1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_DSS1_SHIFT, + .module_offs = CORE_MOD, + }, + }, + .slaves = omap2420_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, +}; + /* I2C common */ static struct omap_hwmod_class_sysconfig i2c_sysc = { .rev_offs = 0x00, @@ -1026,6 +1330,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_uart1_hwmod, &omap2420_uart2_hwmod, &omap2420_uart3_hwmod, + /* dss class */ + &omap2420_dss_core_hwmod, + &omap2420_dss_dispc_hwmod, + &omap2420_dss_rfbi_hwmod, + &omap2420_dss_venc_hwmod, + /* i2c class */ &omap2420_i2c1_hwmod, &omap2420_i2c2_hwmod, diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h new file mode 100644 index 00000000000..b8b5641379b --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l3_2xxx.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H + +/* L3 CONNIDs */ +/* Display Sub system (DSS) */ +#define OMAP2_L3_CORE_FW_CONNID_DSS 8 + +#endif diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h new file mode 100644 index 00000000000..3f39cf8a35c --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l4_2xxx.h @@ -0,0 +1,24 @@ +/* + * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H + +/* L4 CORE */ +/* Display Sub system (DSS) */ +#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28 +#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29 +#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30 +#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31 +#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32 + +#endif -- cgit v1.2.3-70-g09d2 From e04d9e1e4825cb3f6cfc238d7357ef084952eab1 Mon Sep 17 00:00:00 2001 From: Senthilvadivu Guruswamy Date: Mon, 24 Jan 2011 06:21:51 +0000 Subject: OMAP3: hwmod data: add DSS DISPC RFBI DSI VENC Hwmod needs database of all IPs in a system. This patch generates the hwmod database for Display Sub System applicable for OMAP3430 and OMAP36xx. DSS is also considered as an IP as DISPC, RFBI and named as dss_core. For all the IP modules in DSS, same clock is needed for enabling. Hwmod sees DSS IPs as independent IPs, so same clock has to be repeated for .main_clk in each IP. This patch defines separate hwmod databases for OMAP3430ES1 and (OMAP3430ES2 and OMAP36xx) as OMAP3430ES1 does not have IDLEST bit to poll on for dss IP, and also the firewall regions are different between 3430es1 and later. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Sumit Semwal Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 433 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/l3_3xxx.h | 20 ++ arch/arm/plat-omap/include/plat/l4_3xxx.h | 10 + 3 files changed, 463 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/l3_3xxx.h (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 879f55f272e..e9d00122856 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +47,12 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; static struct omap_hwmod omap3xxx_wd_timer2_hwmod; +static struct omap_hwmod omap3430es1_dss_core_hwmod; +static struct omap_hwmod omap3xxx_dss_core_hwmod; +static struct omap_hwmod omap3xxx_dss_dispc_hwmod; +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; +static struct omap_hwmod omap3xxx_dss_venc_hwmod; static struct omap_hwmod omap3xxx_i2c1_hwmod; static struct omap_hwmod omap3xxx_i2c2_hwmod; static struct omap_hwmod omap3xxx_i2c3_hwmod; @@ -91,6 +98,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { &omap3xxx_mpu__l3_main, }; +/* DSS -> l3 */ +static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { + .master = &omap3xxx_dss_core_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .fw = { + .omap2 = { + .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, + .flags = OMAP_FIREWALL_L3, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Master interfaces on the L3 interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { &omap3xxx_l3_main__l4_core, @@ -742,6 +762,410 @@ static struct omap_hwmod_class i2c_class = { .sysc = &i2c_sysc, }; +/* + * 'dss' class + * display sub-system + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { + .name = "dss", + .sysc = &omap3xxx_dss_sysc, +}; + +/* dss */ +static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = { + { .irq = 25 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { + { .name = "dispc", .dma_req = 5 }, + { .name = "dsi1", .dma_req = 74 }, +}; + +/* dss */ +/* dss master ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { + &omap3xxx_dss__l3, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = { + { + .pa_start = 0x48050000, + .pa_end = 0x480503FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss */ +static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3430es1_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_core_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss slave ports */ +static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { + &omap3430es1_l4_core__dss, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { + &omap3xxx_l4_core__dss, +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "tv_clk", .clk = "dss_tv_fck" }, + { .role = "dssclk", .clk = "dss_96m_fck" }, + { .role = "sys_clk", .clk = "dss2_alwon_fck" }, +}; + +static struct omap_hwmod omap3430es1_dss_core_hwmod = { + .name = "dss_core", + .class = &omap3xxx_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .mpu_irqs = omap3xxx_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), + .sdma_reqs = omap3xxx_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), + + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3430es1_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), + .flags = HWMOD_NO_IDLEST, +}; + +static struct omap_hwmod omap3xxx_dss_core_hwmod = { + .name = "dss_core", + .class = &omap3xxx_dss_hwmod_class, + .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ + .mpu_irqs = omap3xxx_dss_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), + .sdma_reqs = omap3xxx_dss_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), + + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, + .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), + .slaves = omap3xxx_dss_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), + .masters = omap3xxx_dss_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | + CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap3xxx_dispc_sysc, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { + { + .pa_start = 0x48050400, + .pa_end = 0x480507FF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dispc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dispc_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_dispc_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dispc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { + &omap3xxx_l4_core__dss_dispc, +}; + +static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &omap3xxx_dispc_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_dispc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'dsi' class + * display serial interface controller + */ + +static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { + .name = "dsi", +}; + +/* dss_dsi1 */ +static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { + { + .pa_start = 0x4804FC00, + .pa_end = 0x4804FFFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_dsi1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_dsi1_hwmod, + .addr = omap3xxx_dss_dsi1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_dsi1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { + &omap3xxx_l4_core__dss_dsi1, +}; + +static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { + .name = "dss_dsi1", + .class = &omap3xxx_dsi_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_dsi1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'rfbi' class + * remote frame buffer interface + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = { + .name = "rfbi", + .sysc = &omap3xxx_rfbi_sysc, +}; + +static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = { + { + .pa_start = 0x48050800, + .pa_end = 0x48050BFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_rfbi */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_rfbi_hwmod, + .clk = "dss_ick", + .addr = omap3xxx_dss_rfbi_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_rfbi slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { + &omap3xxx_l4_core__dss_rfbi, +}; + +static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { + .name = "dss_rfbi", + .class = &omap3xxx_rfbi_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_rfbi_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + +/* + * 'venc' class + * video encoder + */ + +static struct omap_hwmod_class omap3xxx_venc_hwmod_class = { + .name = "venc", +}; + +/* dss_venc */ +static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = { + { + .pa_start = 0x48050C00, + .pa_end = 0x48050FFF, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> dss_venc */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_dss_venc_hwmod, + .clk = "dss_tv_fck", + .addr = omap3xxx_dss_venc_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, + .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dss_venc slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { + &omap3xxx_l4_core__dss_venc, +}; + +static struct omap_hwmod omap3xxx_dss_venc_hwmod = { + .name = "dss_venc", + .class = &omap3xxx_venc_hwmod_class, + .main_clk = "dss1_alwon_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_DSS1_SHIFT, + .module_offs = OMAP3430_DSS_MOD, + }, + }, + .slaves = omap3xxx_dss_venc_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | + CHIP_GE_OMAP3630ES1_1), + .flags = HWMOD_NO_IDLEST, +}; + /* I2C1 */ static struct omap_i2c_dev_attr i2c1_dev_attr = { @@ -1800,6 +2224,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, &omap3xxx_uart4_hwmod, + /* dss class */ + &omap3430es1_dss_core_hwmod, + &omap3xxx_dss_core_hwmod, + &omap3xxx_dss_dispc_hwmod, + &omap3xxx_dss_dsi1_hwmod, + &omap3xxx_dss_rfbi_hwmod, + &omap3xxx_dss_venc_hwmod, + + /* i2c class */ &omap3xxx_i2c1_hwmod, &omap3xxx_i2c2_hwmod, &omap3xxx_i2c3_hwmod, diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h new file mode 100644 index 00000000000..cde1938c5f8 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l3_3xxx.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H + +/* L3 Initiator IDs */ +/* Display Sub system (DSS) */ +#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29 + +#endif diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h index 5e194937542..881a858b1ff 100644 --- a/arch/arm/plat-omap/include/plat/l4_3xxx.h +++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h @@ -21,4 +21,14 @@ #define OMAP3_L4_CORE_FW_I2C3_REGION 73 #define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 +/* Display Sub system (DSS) */ +#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2 + +#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104 +#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3 +#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4 +#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4 +#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5 +#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6 +#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7 #endif -- cgit v1.2.3-70-g09d2 From b7ee79abcc1bd549eadf5a9852657058e6ecca47 Mon Sep 17 00:00:00 2001 From: Sumit Semwal Date: Mon, 24 Jan 2011 06:21:54 +0000 Subject: OMAP2, 3: DSS2: Create new file display.c for central dss driver registration. A new file display.c is introduced for display driver init, which adds a function omap_display_init to do the DSS driver registration. This is the first step in moving away registration of DSS from board files into a common place. Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Senthilvadivu Guruswamy Signed-off-by: Sumit Semwal Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/Makefile | 3 +++ arch/arm/mach-omap2/display.c | 45 +++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/display.h | 11 ++++++++ 3 files changed, 59 insertions(+) create mode 100644 arch/arm/mach-omap2/display.c (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ee72a9787bf..1c3635d7f4c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -245,3 +245,6 @@ obj-y += $(smc91x-m) $(smc91x-y) smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o obj-y += $(smsc911x-m) $(smsc911x-y) obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o + +disp-$(CONFIG_OMAP2_DSS) := display.o +obj-y += $(disp-m) $(disp-y) diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c new file mode 100644 index 00000000000..b18db84b034 --- /dev/null +++ b/arch/arm/mach-omap2/display.c @@ -0,0 +1,45 @@ +/* + * OMAP2plus display device setup / initialization. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Senthilvadivu Guruswamy + * Sumit Semwal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +static struct platform_device omap_display_device = { + .name = "omapdss", + .id = -1, + .dev = { + .platform_data = NULL, + }, +}; + +int __init omap_display_init(struct omap_dss_board_info *board_data) +{ + int r = 0; + omap_display_device.dev.platform_data = board_data; + + r = platform_device_register(&omap_display_device); + if (r < 0) + printk(KERN_ERR "Unable to register OMAP-Display device\n"); + + return r; +} diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h index 537f4e449f5..0f140ecedb0 100644 --- a/arch/arm/plat-omap/include/plat/display.h +++ b/arch/arm/plat-omap/include/plat/display.h @@ -23,6 +23,7 @@ #include #include #include +#include #include #define DISPC_IRQ_FRAMEDONE (1 << 0) @@ -226,6 +227,16 @@ struct omap_dss_board_info { struct omap_dss_device *default_device; }; +#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS) +/* Init with the board info */ +extern int omap_display_init(struct omap_dss_board_info *board_data); +#else +static inline int omap_display_init(struct omap_dss_board_info *board_data) +{ + return 0; +} +#endif + struct omap_video_timings { /* Unit: pixels */ u16 x_res; -- cgit v1.2.3-70-g09d2 From cd5038024d6c92fbe4bf67af91eea5c6fb24a192 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 12:51:45 -0800 Subject: OMAP: hwmod: allow hwmod to provide address space accessible from SDMA Adds support for resource API to get address space info other than just MPU. The drivers can now use platform_get_resource_byname() to get resource of type 'IORESOURCE_MEM' by name. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson Acked-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 1 + arch/arm/plat-omap/include/plat/omap_hwmod.h | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 9e89a58711b..c7762ab0dc8 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1883,6 +1883,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) os = oh->slaves[i]; for (j = 0; j < os->addr_cnt; j++) { + (res + r)->name = (os->addr + j)->name; (res + r)->start = (os->addr + j)->pa_start; (res + r)->end = (os->addr + j)->pa_end; (res + r)->flags = IORESOURCE_MEM; diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index fedd82971c9..04b1ea16a67 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -178,7 +178,8 @@ struct omap_hwmod_omap2_firewall { #define ADDR_TYPE_RT (1 << 1) /** - * struct omap_hwmod_addr_space - MPU address space handled by the hwmod + * struct omap_hwmod_addr_space - address space handled by the hwmod + * @name: name of the address space * @pa_start: starting physical address * @pa_end: ending physical address * @flags: (see omap_hwmod_addr_space.flags macros above) @@ -187,6 +188,7 @@ struct omap_hwmod_omap2_firewall { * structure. GPMC is one example. */ struct omap_hwmod_addr_space { + const char *name; u32 pa_start; u32 pa_end; u8 flags; -- cgit v1.2.3-70-g09d2 From 3cf32bba8ca0e0052ca41d74d455a5805b7fea85 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 12:51:45 -0800 Subject: OMAP: McBSP: Convert McBSP to platform device model Implement McBSP as platform device and add support for registering through platform device layer using resource structures. Later in this patch series, OMAP2+ McBSP driver would be modified to use hwmod framework after populating the omap2+ hwmod database. Signed-off-by: Kishon Vijay Abraham I Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mcbsp.c | 327 +++++++++++++---- arch/arm/mach-omap2/mcbsp.c | 613 ++++++++++++++++++++++++++------ arch/arm/plat-omap/devices.c | 10 +- arch/arm/plat-omap/include/plat/mcbsp.h | 14 +- arch/arm/plat-omap/mcbsp.c | 59 ++- 5 files changed, 818 insertions(+), 205 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 820973666f3..e68f6c012fd 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -10,6 +10,7 @@ * * Multichannel mode not supported. */ +#include #include #include #include @@ -78,100 +79,288 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = { }; #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) +struct resource omap7xx_mcbsp_res[][6] = { + { + { + .start = OMAP7XX_MCBSP1_BASE, + .end = OMAP7XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_7XX_McBSP1RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_7XX_McBSP1TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP7XX_MCBSP2_BASE, + .end = OMAP7XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_7XX_McBSP2RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_7XX_McBSP2TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { { - .phys_base = OMAP7XX_MCBSP1_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP_DMA_MCBSP1_TX, - .rx_irq = INT_7XX_McBSP1RX, - .tx_irq = INT_7XX_McBSP1TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP7XX_MCBSP2_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP_DMA_MCBSP3_TX, - .rx_irq = INT_7XX_McBSP2RX, - .tx_irq = INT_7XX_McBSP2TX, .ops = &omap1_mcbsp_ops, }, }; -#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) -#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) +#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1]) +#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res) #else +#define omap7xx_mcbsp_res NULL #define omap7xx_mcbsp_pdata NULL -#define OMAP7XX_MCBSP_PDATA_SZ 0 -#define OMAP7XX_MCBSP_REG_NUM 0 +#define OMAP7XX_MCBSP_RES_SZ 0 +#define OMAP7XX_MCBSP_COUNT 0 #endif #ifdef CONFIG_ARCH_OMAP15XX +struct resource omap15xx_mcbsp_res[][6] = { + { + { + .start = OMAP1510_MCBSP1_BASE, + .end = OMAP1510_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP1RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP1TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1510_MCBSP2_BASE, + .end = OMAP1510_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_1510_SPI_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_1510_SPI_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1510_MCBSP3_BASE, + .end = OMAP1510_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP3RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP3TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { { - .phys_base = OMAP1510_MCBSP1_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP_DMA_MCBSP1_TX, - .rx_irq = INT_McBSP1RX, - .tx_irq = INT_McBSP1TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1510_MCBSP2_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP_DMA_MCBSP2_TX, - .rx_irq = INT_1510_SPI_RX, - .tx_irq = INT_1510_SPI_TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1510_MCBSP3_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP_DMA_MCBSP3_TX, - .rx_irq = INT_McBSP3RX, - .tx_irq = INT_McBSP3TX, .ops = &omap1_mcbsp_ops, }, }; -#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) -#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) +#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1]) +#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res) #else +#define omap15xx_mcbsp_res NULL #define omap15xx_mcbsp_pdata NULL -#define OMAP15XX_MCBSP_PDATA_SZ 0 -#define OMAP15XX_MCBSP_REG_NUM 0 +#define OMAP15XX_MCBSP_RES_SZ 0 +#define OMAP15XX_MCBSP_COUNT 0 #endif #ifdef CONFIG_ARCH_OMAP16XX +struct resource omap16xx_mcbsp_res[][6] = { + { + { + .start = OMAP1610_MCBSP1_BASE, + .end = OMAP1610_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP1RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP1TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1610_MCBSP2_BASE, + .end = OMAP1610_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_1610_McBSP2_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_1610_McBSP2_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP1610_MCBSP3_BASE, + .end = OMAP1610_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_McBSP3RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_McBSP3TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { { - .phys_base = OMAP1610_MCBSP1_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP_DMA_MCBSP1_TX, - .rx_irq = INT_McBSP1RX, - .tx_irq = INT_McBSP1TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1610_MCBSP2_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP_DMA_MCBSP2_TX, - .rx_irq = INT_1610_McBSP2_RX, - .tx_irq = INT_1610_McBSP2_TX, .ops = &omap1_mcbsp_ops, }, { - .phys_base = OMAP1610_MCBSP3_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP_DMA_MCBSP3_TX, - .rx_irq = INT_McBSP3RX, - .tx_irq = INT_McBSP3TX, .ops = &omap1_mcbsp_ops, }, }; -#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) -#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) +#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1]) +#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res) #else +#define omap16xx_mcbsp_res NULL #define omap16xx_mcbsp_pdata NULL -#define OMAP16XX_MCBSP_PDATA_SZ 0 -#define OMAP16XX_MCBSP_REG_NUM 0 +#define OMAP16XX_MCBSP_RES_SZ 0 +#define OMAP16XX_MCBSP_COUNT 0 #endif static int __init omap1_mcbsp_init(void) @@ -179,16 +368,12 @@ static int __init omap1_mcbsp_init(void) if (!cpu_class_is_omap1()) return -ENODEV; - if (cpu_is_omap7xx()) { - omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); - } else if (cpu_is_omap15xx()) { - omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); - } else if (cpu_is_omap16xx()) { - omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16); - } + if (cpu_is_omap7xx()) + omap_mcbsp_count = OMAP7XX_MCBSP_COUNT; + else if (cpu_is_omap15xx()) + omap_mcbsp_count = OMAP15XX_MCBSP_COUNT; + else if (cpu_is_omap16xx()) + omap_mcbsp_count = OMAP16XX_MCBSP_COUNT; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); @@ -196,16 +381,22 @@ static int __init omap1_mcbsp_init(void) return -ENOMEM; if (cpu_is_omap7xx()) - omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, - OMAP7XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0], + OMAP7XX_MCBSP_RES_SZ, + omap7xx_mcbsp_pdata, + OMAP7XX_MCBSP_COUNT); if (cpu_is_omap15xx()) - omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, - OMAP15XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0], + OMAP15XX_MCBSP_RES_SZ, + omap15xx_mcbsp_pdata, + OMAP15XX_MCBSP_COUNT); if (cpu_is_omap16xx()) - omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, - OMAP16XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0], + OMAP16XX_MCBSP_RES_SZ, + omap16xx_mcbsp_pdata, + OMAP16XX_MCBSP_COUNT); return omap_mcbsp_init(); } diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 0526b758bdc..765ebe7da72 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -105,173 +105,542 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); /* Platform data */ #ifdef CONFIG_SOC_OMAP2420 -static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { +struct resource omap2420_mcbsp_res[][6] = { { - .phys_base = OMAP24XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + { + .start = OMAP24XX_MCBSP1_BASE, + .end = OMAP24XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP24XX_MCBSP2_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + { + .start = OMAP24XX_MCBSP2_BASE, + .end = OMAP24XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) -#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1]) +#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res) #else -#define omap2420_mcbsp_pdata NULL -#define OMAP2420_MCBSP_PDATA_SZ 0 -#define OMAP2420_MCBSP_REG_NUM 0 +#define omap2420_mcbsp_res NULL +#define OMAP2420_MCBSP_RES_SZ 0 +#define OMAP2420_MCBSP_COUNT 0 #endif +#define omap2420_mcbsp_pdata NULL + #ifdef CONFIG_SOC_OMAP2430 -static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { +struct resource omap2430_mcbsp_res[][6] = { { - .phys_base = OMAP24XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, + { + .start = OMAP24XX_MCBSP1_BASE, + .end = OMAP24XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP24XX_MCBSP2_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, + { + .start = OMAP24XX_MCBSP2_BASE, + .end = OMAP24XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP3_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, + { + .start = OMAP2430_MCBSP3_BASE, + .end = OMAP2430_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP3_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP3_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP4_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, + { + .start = OMAP2430_MCBSP4_BASE, + .end = OMAP2430_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP4_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP4_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP2430_MCBSP5_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, - .rx_irq = INT_24XX_MCBSP5_IRQ_RX, - .tx_irq = INT_24XX_MCBSP5_IRQ_TX, + { + .start = OMAP2430_MCBSP5_BASE, + .end = OMAP2430_MCBSP5_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP5_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP5_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP5_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP5_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) -#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1]) +#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res) #else -#define omap2430_mcbsp_pdata NULL -#define OMAP2430_MCBSP_PDATA_SZ 0 -#define OMAP2430_MCBSP_REG_NUM 0 +#define omap2430_mcbsp_res NULL +#define OMAP2430_MCBSP_RES_SZ 0 +#define OMAP2430_MCBSP_COUNT 0 #endif +#define omap2430_mcbsp_pdata NULL + #ifdef CONFIG_ARCH_OMAP3 +struct resource omap34xx_mcbsp_res[][7] = { + { + { + .start = OMAP34XX_MCBSP1_BASE, + .end = OMAP34XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP1_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP1_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP2_BASE, + .end = OMAP34XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "sidetone", + .start = OMAP34XX_MCBSP2_ST_BASE, + .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP2_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP2_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP3_BASE, + .end = OMAP34XX_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "sidetone", + .start = OMAP34XX_MCBSP3_ST_BASE, + .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP3_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP3_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP4_BASE, + .end = OMAP34XX_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP4_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP4_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, + }, + { + { + .start = OMAP34XX_MCBSP5_BASE, + .end = OMAP34XX_MCBSP5_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = INT_24XX_MCBSP5_IRQ_RX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = INT_24XX_MCBSP5_IRQ_TX, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP24XX_DMA_MCBSP5_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP24XX_DMA_MCBSP5_TX, + .flags = IORESOURCE_DMA, + }, + }, +}; + static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { { - .phys_base = OMAP34XX_MCBSP1_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, - .rx_irq = INT_24XX_MCBSP1_IRQ_RX, - .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP2_BASE, - .phys_base_st = OMAP34XX_MCBSP2_ST_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, - .rx_irq = INT_24XX_MCBSP2_IRQ_RX, - .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { - .phys_base = OMAP34XX_MCBSP3_BASE, - .phys_base_st = OMAP34XX_MCBSP3_ST_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, - .rx_irq = INT_24XX_MCBSP3_IRQ_RX, - .tx_irq = INT_24XX_MCBSP3_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP4_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, - .rx_irq = INT_24XX_MCBSP4_IRQ_RX, - .tx_irq = INT_24XX_MCBSP4_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { - .phys_base = OMAP34XX_MCBSP5_BASE, - .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, - .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, - .rx_irq = INT_24XX_MCBSP5_IRQ_RX, - .tx_irq = INT_24XX_MCBSP5_IRQ_TX, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; -#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) -#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1]) +#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res) #else #define omap34xx_mcbsp_pdata NULL -#define OMAP34XX_MCBSP_PDATA_SZ 0 -#define OMAP34XX_MCBSP_REG_NUM 0 +#define omap34XX_mcbsp_res NULL +#define OMAP34XX_MCBSP_RES_SZ 0 +#define OMAP34XX_MCBSP_COUNT 0 #endif -static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { +struct resource omap44xx_mcbsp_res[][6] = { { - .phys_base = OMAP44XX_MCBSP1_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP1, + { + .name = "mpu", + .start = OMAP44XX_MCBSP1_BASE, + .end = OMAP44XX_MCBSP1_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP1_DMA_BASE, + .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP1, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP1_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP1_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP2_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP2, + { + .name = "mpu", + .start = OMAP44XX_MCBSP2_BASE, + .end = OMAP44XX_MCBSP2_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP2_DMA_BASE, + .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP2, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP2_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP2_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP3_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP3, + { + .name = "mpu", + .start = OMAP44XX_MCBSP3_BASE, + .end = OMAP44XX_MCBSP3_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "dma", + .start = OMAP44XX_MCBSP3_DMA_BASE, + .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP3, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP3_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP3_TX, + .flags = IORESOURCE_DMA, + }, }, { - .phys_base = OMAP44XX_MCBSP4_BASE, - .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, - .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, - .tx_irq = OMAP44XX_IRQ_MCBSP4, + { + .start = OMAP44XX_MCBSP4_BASE, + .end = OMAP44XX_MCBSP4_BASE + SZ_256, + .flags = IORESOURCE_MEM, + }, + { + .name = "rx", + .start = 0, + .flags = IORESOURCE_IRQ, + }, + { + .name = "tx", + .start = OMAP44XX_IRQ_MCBSP4, + .flags = IORESOURCE_IRQ, + }, + { + .name = "rx", + .start = OMAP44XX_DMA_MCBSP4_RX, + .flags = IORESOURCE_DMA, + }, + { + .name = "tx", + .start = OMAP44XX_DMA_MCBSP4_TX, + .flags = IORESOURCE_DMA, + }, }, }; -#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) -#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) +#define omap44xx_mcbsp_pdata NULL +#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1]) +#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res) static int __init omap2_mcbsp_init(void) { - if (cpu_is_omap2420()) { - omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); - } else if (cpu_is_omap2430()) { - omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); - } else if (cpu_is_omap34xx()) { - omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32); - } else if (cpu_is_omap44xx()) { - omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; - omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32); - } + if (cpu_is_omap2420()) + omap_mcbsp_count = OMAP2420_MCBSP_COUNT; + else if (cpu_is_omap2430()) + omap_mcbsp_count = OMAP2430_MCBSP_COUNT; + else if (cpu_is_omap34xx()) + omap_mcbsp_count = OMAP34XX_MCBSP_COUNT; + else if (cpu_is_omap44xx()) + omap_mcbsp_count = OMAP44XX_MCBSP_COUNT; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); @@ -279,17 +648,25 @@ static int __init omap2_mcbsp_init(void) return -ENOMEM; if (cpu_is_omap2420()) - omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, - OMAP2420_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0], + OMAP2420_MCBSP_RES_SZ, + omap2420_mcbsp_pdata, + OMAP2420_MCBSP_COUNT); if (cpu_is_omap2430()) - omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, - OMAP2430_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0], + OMAP2420_MCBSP_RES_SZ, + omap2430_mcbsp_pdata, + OMAP2430_MCBSP_COUNT); if (cpu_is_omap34xx()) - omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, - OMAP34XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0], + OMAP34XX_MCBSP_RES_SZ, + omap34xx_mcbsp_pdata, + OMAP34XX_MCBSP_COUNT); if (cpu_is_omap44xx()) - omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, - OMAP44XX_MCBSP_PDATA_SZ); + omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0], + OMAP44XX_MCBSP_RES_SZ, + omap44xx_mcbsp_pdata, + OMAP44XX_MCBSP_COUNT); return omap_mcbsp_init(); } diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 10245b837c1..7d9f815cede 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -35,8 +35,8 @@ static struct platform_device **omap_mcbsp_devices; -void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, - int size) +void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, + struct omap_mcbsp_platform_data *config, int size) { int i; @@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); if (!new_mcbsp) continue; + platform_device_add_resources(new_mcbsp, &res[i * res_count], + res_count); new_mcbsp->dev.platform_data = &config[i]; ret = platform_device_add(new_mcbsp); if (ret) { @@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, } #else -void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, - int size) +void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, + struct omap_mcbsp_platform_data *config, int size) { } #endif diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 6ecf1051e5f..dc1a28299ae 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -63,9 +63,12 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP34XX_MCBSP4_BASE 0x49026000 #define OMAP34XX_MCBSP5_BASE 0x48096000 -#define OMAP44XX_MCBSP1_BASE 0x49022000 -#define OMAP44XX_MCBSP2_BASE 0x49024000 -#define OMAP44XX_MCBSP3_BASE 0x49026000 +#define OMAP44XX_MCBSP1_BASE 0x40122000 +#define OMAP44XX_MCBSP1_DMA_BASE 0x49022000 +#define OMAP44XX_MCBSP2_BASE 0x40124000 +#define OMAP44XX_MCBSP2_DMA_BASE 0x49024000 +#define OMAP44XX_MCBSP3_BASE 0x40126000 +#define OMAP44XX_MCBSP3_DMA_BASE 0x49026000 #define OMAP44XX_MCBSP4_BASE 0x48096000 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) @@ -431,6 +434,7 @@ struct omap_mcbsp_st_data { struct omap_mcbsp { struct device *dev; unsigned long phys_base; + unsigned long phys_dma_base; void __iomem *io_base; u8 id; u8 free; @@ -474,8 +478,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size; #define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; int omap_mcbsp_init(void); -void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, - int size); +void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, + struct omap_mcbsp_platform_data *config, int size); void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); #ifdef CONFIG_ARCH_OMAP3 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index b5a6e178a7f..5f25ae5f9c1 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1649,7 +1649,8 @@ static const struct attribute_group sidetone_attr_group = { static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) { - struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; + struct platform_device *pdev; + struct resource *res; struct omap_mcbsp_st_data *st_data; int err; @@ -1659,7 +1660,10 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) goto err1; } - st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); + pdev = container_of(mcbsp->dev, struct platform_device, dev); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); + st_data->io_base_st = ioremap(res->start, resource_size(res)); if (!st_data->io_base_st) { err = -ENOMEM; goto err2; @@ -1748,6 +1752,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; struct omap_mcbsp *mcbsp; int id = pdev->id - 1; + struct resource *res; int ret = 0; if (!pdata) { @@ -1777,25 +1782,59 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->dma_tx_lch = -1; mcbsp->dma_rx_lch = -1; - mcbsp->phys_base = pdata->phys_base; - mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); + if (!res) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory" + "resource\n", __func__, pdev->id); + ret = -ENOMEM; + goto exit; + } + } + mcbsp->phys_base = res->start; + omap_mcbsp_cache_size = resource_size(res); + mcbsp->io_base = ioremap(res->start, resource_size(res)); if (!mcbsp->io_base) { ret = -ENOMEM; goto err_ioremap; } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); + if (!res) + mcbsp->phys_dma_base = mcbsp->phys_base; + else + mcbsp->phys_dma_base = res->start; + /* Default I/O is IRQ based */ mcbsp->io_type = OMAP_MCBSP_IRQ_IO; - mcbsp->tx_irq = pdata->tx_irq; - mcbsp->rx_irq = pdata->rx_irq; - mcbsp->dma_rx_sync = pdata->dma_rx_sync; - mcbsp->dma_tx_sync = pdata->dma_tx_sync; + + mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); + mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); + + res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); + if (!res) { + dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n", + __func__, pdev->id); + ret = -ENODEV; + goto err_res; + } + mcbsp->dma_rx_sync = res->start; + + res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); + if (!res) { + dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n", + __func__, pdev->id); + ret = -ENODEV; + goto err_res; + } + mcbsp->dma_tx_sync = res->start; mcbsp->iclk = clk_get(&pdev->dev, "ick"); if (IS_ERR(mcbsp->iclk)) { ret = PTR_ERR(mcbsp->iclk); dev_err(&pdev->dev, "unable to get ick: %d\n", ret); - goto err_iclk; + goto err_res; } mcbsp->fclk = clk_get(&pdev->dev, "fck"); @@ -1817,7 +1856,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) err_fclk: clk_put(mcbsp->iclk); -err_iclk: +err_res: iounmap(mcbsp->io_base); err_ioremap: kfree(mcbsp); -- cgit v1.2.3-70-g09d2 From 37801b3df60a000cc1d65ea8b472e841dc93ea75 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 24 Feb 2011 12:51:46 -0800 Subject: OMAP2430: hwmod data: Add McBSP Add McBSP hwmod data for OMAP2430. Added a revision member inorder to facilitate the driver to differentiate between mcbsp in different omap. Signed-off-by: Charulatha V Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Shubhrajyoti D Cc: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 320 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 2 + 2 files changed, 322 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 91d2581c770..1e65a4f5117 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -51,6 +52,11 @@ static struct omap_hwmod omap2430_gpio3_hwmod; static struct omap_hwmod omap2430_gpio4_hwmod; static struct omap_hwmod omap2430_gpio5_hwmod; static struct omap_hwmod omap2430_dma_system_hwmod; +static struct omap_hwmod omap2430_mcbsp1_hwmod; +static struct omap_hwmod omap2430_mcbsp2_hwmod; +static struct omap_hwmod omap2430_mcbsp3_hwmod; +static struct omap_hwmod omap2430_mcbsp4_hwmod; +static struct omap_hwmod omap2430_mcbsp5_hwmod; static struct omap_hwmod omap2430_mcspi1_hwmod; static struct omap_hwmod omap2430_mcspi2_hwmod; static struct omap_hwmod omap2430_mcspi3_hwmod; @@ -1575,7 +1581,314 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { + .rev_offs = 0x007C, + .sysc_offs = 0x008C, + .sysc_flags = (SYSC_HAS_SOFTRESET), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap2430_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE2, +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, + { .name = "ovr", .irq = 61 }, + { .name = "common", .irq = 64 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = { + { .name = "rx", .dma_req = 32 }, + { .name = "tx", .dma_req = 31 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap2430_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { + &omap2430_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap2430_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), + .sdma_reqs = omap2430_mcbsp1_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap2430_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, + { .name = "common", .irq = 16 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = { + { .name = "rx", .dma_req = 34 }, + { .name = "tx", .dma_req = 33 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48076000, + .pa_end = 0x480760ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap2430_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { + &omap2430_l4_core__mcbsp2, +}; + +static struct omap_hwmod omap2430_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs), + .sdma_reqs = omap2430_mcbsp2_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap2430_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, + { .name = "common", .irq = 17 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = { + { .name = "rx", .dma_req = 18 }, + { .name = "tx", .dma_req = 17 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808C000, + .pa_end = 0x4808C0ff, + .flags = ADDR_TYPE_RT + }, +}; +/* l4_core -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap2430_mcbsp3_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { + &omap2430_l4_core__mcbsp3, +}; + +static struct omap_hwmod omap2430_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs), + .sdma_reqs = omap2430_mcbsp3_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap2430_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, + { .name = "common", .irq = 18 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x4808E000, + .pa_end = 0x4808E0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap2430_mcbsp4_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { + &omap2430_l4_core__mcbsp4, +}; + +static struct omap_hwmod omap2430_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs), + .sdma_reqs = omap2430_mcbsp4_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs), + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, + }, + }, + .slaves = omap2430_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, + { .name = "common", .irq = 19 }, +}; + +static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, +}; + +static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap2430_mcbsp5_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp5 slave ports */ +static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { + &omap2430_l4_core__mcbsp5, +}; + +static struct omap_hwmod omap2430_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap2430_mcbsp_hwmod_class, + .mpu_irqs = omap2430_mcbsp5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs), + .sdma_reqs = omap2430_mcbsp5_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs), + .main_clk = "mcbsp5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, + }, + }, + .slaves = omap2430_mcbsp5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, @@ -1606,6 +1919,13 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { /* dma_system class*/ &omap2430_dma_system_hwmod, + /* mcbsp class */ + &omap2430_mcbsp1_hwmod, + &omap2430_mcbsp2_hwmod, + &omap2430_mcbsp3_hwmod, + &omap2430_mcbsp4_hwmod, + &omap2430_mcbsp5_hwmod, + /* mailbox class */ &omap2430_mailbox_hwmod, diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index dc1a28299ae..64491a5385e 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -37,6 +37,8 @@ static struct platform_device omap_mcbsp##port_nr = { \ .id = OMAP_MCBSP##port_nr, \ } +#define MCBSP_CONFIG_TYPE2 0x2 + #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 -- cgit v1.2.3-70-g09d2 From dc48e5fc782f8d447aae2e82ba7453ddcf32c617 Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Thu, 24 Feb 2011 15:16:49 +0530 Subject: OMAP3: hwmod data: Add McBSP Add McBSP hwmod data for OMAP3. Added a revision member inorder to facilitate the driver to differentiate between mcbsp in different omap. Signed-off-by: Charulatha V Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Shubhrajyoti D Cc: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 439 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 1 + 2 files changed, 440 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 510d5e11a4e..e1d89c0607e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "omap_hwmod_common_data.h" @@ -72,6 +73,14 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod; static struct omap_hwmod omap3xxx_dma_system_hwmod; +static struct omap_hwmod omap3xxx_mcbsp1_hwmod; +static struct omap_hwmod omap3xxx_mcbsp2_hwmod; +static struct omap_hwmod omap3xxx_mcbsp3_hwmod; +static struct omap_hwmod omap3xxx_mcbsp4_hwmod; +static struct omap_hwmod omap3xxx_mcbsp5_hwmod; +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; + /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { .master = &omap3xxx_l3_main_hwmod, @@ -1729,6 +1738,427 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { .flags = HWMOD_NO_IDLEST, }; +/* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, + .clockact = 0x2, +}; + +static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap3xxx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE3, +}; + +/* mcbsp1 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { + { .name = "irq", .irq = 16 }, + { .name = "tx", .irq = 59 }, + { .name = "rx", .irq = 60 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = { + { .name = "rx", .dma_req = 32 }, + { .name = "tx", .dma_req = 31 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48074000, + .pa_end = 0x480740ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp1_hwmod, + .clk = "mcbsp1_ick", + .addr = omap3xxx_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { + &omap3xxx_l4_core__mcbsp1, +}; + +static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), + .sdma_reqs = omap3xxx_mcbsp1_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP1_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp2 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { + { .name = "irq", .irq = 17 }, + { .name = "tx", .irq = 62 }, + { .name = "rx", .irq = 63 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = { + { .name = "rx", .dma_req = 34 }, + { .name = "tx", .dma_req = 33 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { + &omap3xxx_l4_per__mcbsp2, +}; + +static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), + .sdma_reqs = omap3xxx_mcbsp2_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp3 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { + { .name = "irq", .irq = 22 }, + { .name = "tx", .irq = 89 }, + { .name = "rx", .irq = 90 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = { + { .name = "rx", .dma_req = 18 }, + { .name = "tx", .dma_req = 17 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { + &omap3xxx_l4_per__mcbsp3, +}; + +static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), + .sdma_reqs = omap3xxx_mcbsp3_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp4 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { + { .name = "irq", .irq = 23 }, + { .name = "tx", .irq = 54 }, + { .name = "rx", .irq = 55 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { + { .name = "rx", .dma_req = 20 }, + { .name = "tx", .dma_req = 19 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { + { + .name = "mpu", + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp4_hwmod, + .clk = "mcbsp4_ick", + .addr = omap3xxx_mcbsp4_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { + &omap3xxx_l4_per__mcbsp4, +}; + +static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs), + .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs), + .main_clk = "mcbsp4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP4_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp5 */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { + { .name = "irq", .irq = 27 }, + { .name = "tx", .irq = 81 }, + { .name = "rx", .irq = 82 }, +}; + +static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { + { .name = "rx", .dma_req = 22 }, + { .name = "tx", .dma_req = 21 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> mcbsp5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_mcbsp5_hwmod, + .clk = "mcbsp5_ick", + .addr = omap3xxx_mcbsp5_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp5 slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { + &omap3xxx_l4_core__mcbsp5, +}; + +static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { + .name = "mcbsp5", + .class = &omap3xxx_mcbsp_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp5_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs), + .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, + .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs), + .main_clk = "mcbsp5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp5_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; +/* 'mcbsp sidetone' class */ + +static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_AUTOIDLE, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { + .name = "mcbsp_sidetone", + .sysc = &omap3xxx_mcbsp_sidetone_sysc, +}; + +/* mcbsp2_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { + { .name = "irq", .irq = 4 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x49028000, + .pa_end = 0x490280ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp2_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp2_sidetone_hwmod, + .clk = "mcbsp2_ick", + .addr = omap3xxx_mcbsp2_sidetone_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs), + .user = OCP_USER_MPU, +}; + +/* mcbsp2_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp2_sidetone, +}; + +static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { + .name = "mcbsp2_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP2_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp2_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* mcbsp3_sidetone */ +static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { + { .name = "irq", .irq = 5 }, +}; + +static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { + { + .name = "sidetone", + .pa_start = 0x4902A000, + .pa_end = 0x4902A0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp3_sidetone */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_mcbsp3_sidetone_hwmod, + .clk = "mcbsp3_ick", + .addr = omap3xxx_mcbsp3_sidetone_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs), + .user = OCP_USER_MPU, +}; + +/* mcbsp3_sidetone slave ports */ +static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { + &omap3xxx_l4_per__mcbsp3_sidetone, +}; + +static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { + .name = "mcbsp3_sidetone", + .class = &omap3xxx_mcbsp_sidetone_hwmod_class, + .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MCBSP3_SHIFT, + .module_offs = OMAP3430_PER_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, + }, + }, + .slaves = omap3xxx_mcbsp3_sidetone_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + + /* SR common */ static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { .clkact_shift = 20, @@ -2321,6 +2751,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { /* dma_system class*/ &omap3xxx_dma_system_hwmod, + /* mcbsp class */ + &omap3xxx_mcbsp1_hwmod, + &omap3xxx_mcbsp2_hwmod, + &omap3xxx_mcbsp3_hwmod, + &omap3xxx_mcbsp4_hwmod, + &omap3xxx_mcbsp5_hwmod, + &omap3xxx_mcbsp2_sidetone_hwmod, + &omap3xxx_mcbsp3_sidetone_hwmod, + /* mailbox class */ &omap3xxx_mailbox_hwmod, diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 64491a5385e..f084b6acfbf 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -38,6 +38,7 @@ static struct platform_device omap_mcbsp##port_nr = { \ } #define MCBSP_CONFIG_TYPE2 0x2 +#define MCBSP_CONFIG_TYPE3 0x3 #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 -- cgit v1.2.3-70-g09d2 From cb7e9ded3240d717d1d24812d33b3ef2c98c084e Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:50 +0530 Subject: OMAP4: hwmod: Naming of address space Added a name to address space belonging to SDMA and MPU facilitating the driver to get the address space info by name. Added a revision member inorder to facilitate the driver to differentiate between mcbsp in different omap. Also added a platform_get_irq in probe to get irq number by index since from OMAP4, there will be a single irq line. Signed-off-by: Benoit Cousson Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 ++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 1 + arch/arm/plat-omap/mcbsp.c | 4 ++++ 3 files changed, 13 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 79a86017891..673b011403c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -2737,6 +2738,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { .name = "mcbsp", .sysc = &omap44xx_mcbsp_sysc, + .rev = MCBSP_CONFIG_TYPE4, }; /* mcbsp1 */ @@ -2752,6 +2754,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { { + .name = "mpu", .pa_start = 0x40122000, .pa_end = 0x401220ff, .flags = ADDR_TYPE_RT @@ -2770,6 +2773,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { { + .name = "dma", .pa_start = 0x49022000, .pa_end = 0x490220ff, .flags = ADDR_TYPE_RT @@ -2823,6 +2827,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { { + .name = "mpu", .pa_start = 0x40124000, .pa_end = 0x401240ff, .flags = ADDR_TYPE_RT @@ -2841,6 +2846,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { { + .name = "dma", .pa_start = 0x49024000, .pa_end = 0x490240ff, .flags = ADDR_TYPE_RT @@ -2894,6 +2900,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { { + .name = "mpu", .pa_start = 0x40126000, .pa_end = 0x401260ff, .flags = ADDR_TYPE_RT @@ -2912,6 +2919,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { { + .name = "dma", .pa_start = 0x49026000, .pa_end = 0x490260ff, .flags = ADDR_TYPE_RT diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index f084b6acfbf..afcbb7bb016 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -39,6 +39,7 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define MCBSP_CONFIG_TYPE2 0x2 #define MCBSP_CONFIG_TYPE3 0x3 +#define MCBSP_CONFIG_TYPE4 0x4 #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 5f25ae5f9c1..62bd073b0f8 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1812,6 +1812,10 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); + /* From OMAP4 there will be a single irq line */ + if (mcbsp->tx_irq == -ENXIO) + mcbsp->tx_irq = platform_get_irq(pdev, 0); + res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); if (!res) { dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n", -- cgit v1.2.3-70-g09d2 From 8b1906f12a60d377b11d8a3dd256ce0a0ef6c614 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:51 +0530 Subject: OMAP3: hwmod: add dev_attr for McBSP sidetone Since the sidetone block is tightly coupled to the mcbsp, sidetone information is directly added to mcbsp2 & 3 hwmod dev_attr. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 10 ++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 9 +++++++++ 2 files changed, 19 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e1d89c0607e..25226bf063e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1852,6 +1852,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { &omap3xxx_l4_per__mcbsp2, }; +static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { + .sidetone = "mcbsp2_sidetone", +}; + static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { .name = "mcbsp2", .class = &omap3xxx_mcbsp_hwmod_class, @@ -1871,6 +1875,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { }, .slaves = omap3xxx_mcbsp2_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), + .dev_attr = &omap34xx_mcbsp2_dev_attr, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; @@ -1910,6 +1915,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { &omap3xxx_l4_per__mcbsp3, }; +static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { + .sidetone = "mcbsp3_sidetone", +}; + static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { .name = "mcbsp3", .class = &omap3xxx_mcbsp_hwmod_class, @@ -1929,6 +1938,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { }, .slaves = omap3xxx_mcbsp3_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), + .dev_attr = &omap34xx_mcbsp3_dev_attr, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index afcbb7bb016..1fe06372c9c 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -475,6 +475,15 @@ struct omap_mcbsp { #endif void *reg_cache; }; + +/** + * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod + * @sidetone: name of the sidetone device + */ +struct omap_mcbsp_dev_attr { + const char *sidetone; +}; + extern struct omap_mcbsp **mcbsp_ptr; extern int omap_mcbsp_count, omap_mcbsp_cache_size; -- cgit v1.2.3-70-g09d2 From 64bcbd33c7c70d0aea4e614212a2568321a0396b Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:52 +0530 Subject: OMAP2+: McBSP: hwmod adaptation for McBSP Modify OMAP2+ McBSP to use omap hwmod framework APIs Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Charulatha V Signed-off-by: Shubhrajyoti D Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 595 +++----------------------------- arch/arm/plat-omap/include/plat/mcbsp.h | 2 +- 2 files changed, 46 insertions(+), 551 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 765ebe7da72..275d6cfa0b2 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -22,10 +22,10 @@ #include #include #include +#include #include "control.h" - /* McBSP internal signal muxing functions */ void omap2_mcbsp1_mux_clkr_src(u8 mux) @@ -101,573 +101,68 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) } EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); - -/* Platform data */ - -#ifdef CONFIG_SOC_OMAP2420 -struct resource omap2420_mcbsp_res[][6] = { +struct omap_device_pm_latency omap2_mcbsp_latency[] = { { - { - .start = OMAP24XX_MCBSP1_BASE, - .end = OMAP24XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP1_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP1_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP24XX_MCBSP2_BASE, - .end = OMAP24XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP2_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP2_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, }; -#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1]) -#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res) -#else -#define omap2420_mcbsp_res NULL -#define OMAP2420_MCBSP_RES_SZ 0 -#define OMAP2420_MCBSP_COUNT 0 -#endif -#define omap2420_mcbsp_pdata NULL +static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) +{ + int id, count = 1; + char *name = "omap-mcbsp"; + struct omap_hwmod *oh_device[2]; + struct omap_mcbsp_platform_data *pdata = NULL; + struct omap_device *od; -#ifdef CONFIG_SOC_OMAP2430 -struct resource omap2430_mcbsp_res[][6] = { - { - { - .start = OMAP24XX_MCBSP1_BASE, - .end = OMAP24XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP1_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP1_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP24XX_MCBSP2_BASE, - .end = OMAP24XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP2_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP2_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP2430_MCBSP3_BASE, - .end = OMAP2430_MCBSP3_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP3_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP3_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP3_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP3_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP2430_MCBSP4_BASE, - .end = OMAP2430_MCBSP4_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP4_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP4_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP4_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP4_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP2430_MCBSP5_BASE, - .end = OMAP2430_MCBSP5_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP5_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP5_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP5_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP5_TX, - .flags = IORESOURCE_DMA, - }, - }, -}; -#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1]) -#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res) -#else -#define omap2430_mcbsp_res NULL -#define OMAP2430_MCBSP_RES_SZ 0 -#define OMAP2430_MCBSP_COUNT 0 -#endif + sscanf(oh->name, "mcbsp%d", &id); -#define omap2430_mcbsp_pdata NULL + pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL); + if (!pdata) { + pr_err("%s: No memory for mcbsp\n", __func__); + return -ENOMEM; + } -#ifdef CONFIG_ARCH_OMAP3 -struct resource omap34xx_mcbsp_res[][7] = { - { - { - .start = OMAP34XX_MCBSP1_BASE, - .end = OMAP34XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP1_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP1_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP2_BASE, - .end = OMAP34XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "sidetone", - .start = OMAP34XX_MCBSP2_ST_BASE, - .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP2_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP2_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP3_BASE, - .end = OMAP34XX_MCBSP3_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "sidetone", - .start = OMAP34XX_MCBSP3_ST_BASE, - .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP3_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP3_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP3_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP3_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP4_BASE, - .end = OMAP34XX_MCBSP4_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP4_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP4_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP4_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP4_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP34XX_MCBSP5_BASE, - .end = OMAP34XX_MCBSP5_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_24XX_MCBSP5_IRQ_RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_24XX_MCBSP5_IRQ_TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP24XX_DMA_MCBSP5_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP24XX_DMA_MCBSP5_TX, - .flags = IORESOURCE_DMA, - }, - }, -}; + if (oh->class->rev == MCBSP_CONFIG_TYPE3) { + if (id == 2) + /* The FIFO has 1024 + 256 locations */ + pdata->buffer_size = 0x500; + else + /* The FIFO has 128 locations */ + pdata->buffer_size = 0x80; + } -static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, - { - .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ - }, - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, - { - .buffer_size = 0x80, /* The FIFO has 128 locations */ - }, -}; -#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1]) -#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res) -#else -#define omap34xx_mcbsp_pdata NULL -#define omap34XX_mcbsp_res NULL -#define OMAP34XX_MCBSP_RES_SZ 0 -#define OMAP34XX_MCBSP_COUNT 0 -#endif + oh_device[0] = oh; -struct resource omap44xx_mcbsp_res[][6] = { - { - { - .name = "mpu", - .start = OMAP44XX_MCBSP1_BASE, - .end = OMAP44XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "dma", - .start = OMAP44XX_MCBSP1_DMA_BASE, - .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP1, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP1_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP1_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .name = "mpu", - .start = OMAP44XX_MCBSP2_BASE, - .end = OMAP44XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "dma", - .start = OMAP44XX_MCBSP2_DMA_BASE, - .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP2, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP2_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP2_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .name = "mpu", - .start = OMAP44XX_MCBSP3_BASE, - .end = OMAP44XX_MCBSP3_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "dma", - .start = OMAP44XX_MCBSP3_DMA_BASE, - .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP3, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP3_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP3_TX, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP44XX_MCBSP4_BASE, - .end = OMAP44XX_MCBSP4_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = 0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = OMAP44XX_IRQ_MCBSP4, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = OMAP44XX_DMA_MCBSP4_RX, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = OMAP44XX_DMA_MCBSP4_TX, - .flags = IORESOURCE_DMA, - }, - }, -}; -#define omap44xx_mcbsp_pdata NULL -#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1]) -#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res) + if (oh->dev_attr) { + oh_device[1] = omap_hwmod_lookup(( + (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); + count++; + } + od = omap_device_build_ss(name, id, oh_device, count, pdata, + sizeof(*pdata), omap2_mcbsp_latency, + ARRAY_SIZE(omap2_mcbsp_latency), false); + kfree(pdata); + if (IS_ERR(od)) { + pr_err("%s: Cant build omap_device for %s:%s.\n", __func__, + name, oh->name); + return PTR_ERR(od); + } + omap_mcbsp_count++; + return 0; +} static int __init omap2_mcbsp_init(void) { - if (cpu_is_omap2420()) - omap_mcbsp_count = OMAP2420_MCBSP_COUNT; - else if (cpu_is_omap2430()) - omap_mcbsp_count = OMAP2430_MCBSP_COUNT; - else if (cpu_is_omap34xx()) - omap_mcbsp_count = OMAP34XX_MCBSP_COUNT; - else if (cpu_is_omap44xx()) - omap_mcbsp_count = OMAP44XX_MCBSP_COUNT; + omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); if (!mcbsp_ptr) return -ENOMEM; - if (cpu_is_omap2420()) - omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0], - OMAP2420_MCBSP_RES_SZ, - omap2420_mcbsp_pdata, - OMAP2420_MCBSP_COUNT); - if (cpu_is_omap2430()) - omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0], - OMAP2420_MCBSP_RES_SZ, - omap2430_mcbsp_pdata, - OMAP2430_MCBSP_COUNT); - if (cpu_is_omap34xx()) - omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0], - OMAP34XX_MCBSP_RES_SZ, - omap34xx_mcbsp_pdata, - OMAP34XX_MCBSP_COUNT); - if (cpu_is_omap44xx()) - omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0], - OMAP44XX_MCBSP_RES_SZ, - omap44xx_mcbsp_pdata, - OMAP44XX_MCBSP_COUNT); - return omap_mcbsp_init(); } arch_initcall(omap2_mcbsp_init); diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 1fe06372c9c..c6cabfc77a1 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -421,8 +421,8 @@ struct omap_mcbsp_platform_data { #ifdef CONFIG_ARCH_OMAP3 /* Sidetone block for McBSP 2 and 3 */ unsigned long phys_base_st; - u16 buffer_size; #endif + u16 buffer_size; }; struct omap_mcbsp_st_data { -- cgit v1.2.3-70-g09d2 From e95496d4acadd0b72c4947be61e8d44700fdaae7 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:54 +0530 Subject: OMAP: McBSP: Add pm runtime support Add pm runtime support for McBSP driver. Reference to fclk is not removed because it is required when the functional clock is switched from one source to another. Signed-off-by: Kishon Vijay Abraham I Cc: Paul Walmsley Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 5 +++-- arch/arm/plat-omap/include/plat/mcbsp.h | 1 - arch/arm/plat-omap/mcbsp.c | 23 ++++++----------------- 3 files changed, 9 insertions(+), 20 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 275d6cfa0b2..4ada6a9ca4a 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "control.h" @@ -83,7 +84,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) return -EINVAL; } - clk_disable(mcbsp->fclk); + pm_runtime_put_sync(mcbsp->dev); r = clk_set_parent(mcbsp->fclk, fck_src); if (IS_ERR_VALUE(r)) { @@ -93,7 +94,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) return -EINVAL; } - clk_enable(mcbsp->fclk); + pm_runtime_get_sync(mcbsp->dev); clk_put(fck_src); diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index c6cabfc77a1..964a940c475 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -465,7 +465,6 @@ struct omap_mcbsp { /* Protect the field .free, while checking if the mcbsp is in use */ spinlock_t lock; struct omap_mcbsp_platform_data *pdata; - struct clk *iclk; struct clk *fclk; #ifdef CONFIG_ARCH_OMAP3 struct omap_mcbsp_st_data *st_data; diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 67ec74ea253..6d230164b4f 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -28,6 +28,7 @@ #include #include #include +#include /* XXX These "sideways" includes are a sign that something is wrong */ #include "../mach-omap2/cm2xxx_3xxx.h" @@ -757,8 +758,7 @@ int omap_mcbsp_request(unsigned int id) if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) mcbsp->pdata->ops->request(id); - clk_enable(mcbsp->iclk); - clk_enable(mcbsp->fclk); + pm_runtime_get_sync(mcbsp->dev); /* Do procedure specific to omap34xx arch, if applicable */ omap34xx_mcbsp_request(mcbsp); @@ -806,8 +806,7 @@ err_clk_disable: /* Do procedure specific to omap34xx arch, if applicable */ omap34xx_mcbsp_free(mcbsp); - clk_disable(mcbsp->fclk); - clk_disable(mcbsp->iclk); + pm_runtime_put_sync(mcbsp->dev); spin_lock(&mcbsp->lock); mcbsp->free = true; @@ -837,8 +836,7 @@ void omap_mcbsp_free(unsigned int id) /* Do procedure specific to omap34xx arch, if applicable */ omap34xx_mcbsp_free(mcbsp); - clk_disable(mcbsp->fclk); - clk_disable(mcbsp->iclk); + pm_runtime_put_sync(mcbsp->dev); if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { /* Free IRQs */ @@ -1827,32 +1825,24 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) } mcbsp->dma_tx_sync = res->start; - mcbsp->iclk = clk_get(&pdev->dev, "ick"); - if (IS_ERR(mcbsp->iclk)) { - ret = PTR_ERR(mcbsp->iclk); - dev_err(&pdev->dev, "unable to get ick: %d\n", ret); - goto err_res; - } - mcbsp->fclk = clk_get(&pdev->dev, "fck"); if (IS_ERR(mcbsp->fclk)) { ret = PTR_ERR(mcbsp->fclk); dev_err(&pdev->dev, "unable to get fck: %d\n", ret); - goto err_fclk; + goto err_res; } mcbsp->pdata = pdata; mcbsp->dev = &pdev->dev; mcbsp_ptr[id] = mcbsp; platform_set_drvdata(pdev, mcbsp); + pm_runtime_enable(mcbsp->dev); /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ omap34xx_device_init(mcbsp); return 0; -err_fclk: - clk_put(mcbsp->iclk); err_res: iounmap(mcbsp->io_base); err_ioremap: @@ -1875,7 +1865,6 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) omap34xx_device_exit(mcbsp); clk_put(mcbsp->fclk); - clk_put(mcbsp->iclk); iounmap(mcbsp->io_base); kfree(mcbsp); -- cgit v1.2.3-70-g09d2 From 9504ba64f014cfd50a64106e49c8ba729522db5b Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:55 +0530 Subject: OMAP: McBSP: APIs to pass DMA params from McBSP driver to client drivers After McBSP driver is hwmod adapted, the information about the hw would be obtained from the hwmod database by the mcbsp driver. Since DMA programming is handled by the client driver, APIs are provided to pass the DMA channel number and base address of data register required by the client driver for DMA programming. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Charulatha V Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 2 ++ arch/arm/plat-omap/include/plat/mcbsp.h | 7 ++++ arch/arm/plat-omap/mcbsp.c | 64 +++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 4ada6a9ca4a..565b9064a32 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -126,6 +126,8 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) return -ENOMEM; } + pdata->mcbsp_config_type = oh->class->rev; + if (oh->class->rev == MCBSP_CONFIG_TYPE3) { if (id == 2) /* The FIFO has 1024 + 256 locations */ diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 964a940c475..21c9b104c61 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -81,6 +81,8 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP_MCBSP_REG_DRR1 0x02 #define OMAP_MCBSP_REG_DXR2 0x04 #define OMAP_MCBSP_REG_DXR1 0x06 +#define OMAP_MCBSP_REG_DRR 0x02 +#define OMAP_MCBSP_REG_DXR 0x06 #define OMAP_MCBSP_REG_SPCR2 0x08 #define OMAP_MCBSP_REG_SPCR1 0x0a #define OMAP_MCBSP_REG_RCR2 0x0c @@ -423,6 +425,7 @@ struct omap_mcbsp_platform_data { unsigned long phys_base_st; #endif u16 buffer_size; + unsigned int mcbsp_config_type; }; struct omap_mcbsp_st_data { @@ -473,6 +476,7 @@ struct omap_mcbsp { u16 max_rx_thres; #endif void *reg_cache; + unsigned int mcbsp_config_type; }; /** @@ -541,6 +545,9 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); void omap2_mcbsp1_mux_clkr_src(u8 mux); void omap2_mcbsp1_mux_fsr_src(u8 mux); +int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); +int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); + #ifdef CONFIG_ARCH_OMAP3 /* Sidetone specific API */ int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 6d230164b4f..d598d9fd65a 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -229,6 +229,69 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) } EXPORT_SYMBOL(omap_mcbsp_config); +/** + * omap_mcbsp_dma_params - returns the dma channel number + * @id - mcbsp id + * @stream - indicates the direction of data flow (rx or tx) + * + * Returns the dma channel number for the rx channel or tx channel + * based on the value of @stream for the requested mcbsp given by @id + */ +int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream) +{ + struct omap_mcbsp *mcbsp; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + if (stream) + return mcbsp->dma_rx_sync; + else + return mcbsp->dma_tx_sync; +} +EXPORT_SYMBOL(omap_mcbsp_dma_ch_params); + +/** + * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register + * @id - mcbsp id + * @stream - indicates the direction of data flow (rx or tx) + * + * Returns the address of mcbsp data transmit register or data receive register + * to be used by DMA for transferring/receiving data based on the value of + * @stream for the requested mcbsp given by @id + */ +int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream) +{ + struct omap_mcbsp *mcbsp; + int data_reg; + + if (!omap_mcbsp_check_valid_id(id)) { + printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); + return -ENODEV; + } + mcbsp = id_to_mcbsp_ptr(id); + + data_reg = mcbsp->phys_dma_base; + + if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) { + if (stream) + data_reg += OMAP_MCBSP_REG_DRR1; + else + data_reg += OMAP_MCBSP_REG_DXR1; + } else { + if (stream) + data_reg += OMAP_MCBSP_REG_DRR; + else + data_reg += OMAP_MCBSP_REG_DXR; + } + + return data_reg; +} +EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); + #ifdef CONFIG_ARCH_OMAP3 static struct omap_device *find_omap_device_by_dev(struct device *dev) { @@ -1835,6 +1898,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) mcbsp->pdata = pdata; mcbsp->dev = &pdev->dev; mcbsp_ptr[id] = mcbsp; + mcbsp->mcbsp_config_type = pdata->mcbsp_config_type; platform_set_drvdata(pdev, mcbsp); pm_runtime_enable(mcbsp->dev); -- cgit v1.2.3-70-g09d2 From b176654e7796b2812632e7c4a1a4b6efbfae5f1b Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Feb 2011 15:16:57 +0530 Subject: OMAP: hwmod: Removal of macros for data that is obtained from hwmod database Information like base address and DMA channel nubers should no longer be obtained using macros. These information should be obtained from hwmod database. Hence the macros that define the base address are removed. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Charulatha V Acked-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/mcbsp.h | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 21c9b104c61..f8f690ab299 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -52,30 +52,7 @@ static struct platform_device omap_mcbsp##port_nr = { \ #define OMAP1610_MCBSP2_BASE 0xfffb1000 #define OMAP1610_MCBSP3_BASE 0xe1017000 -#define OMAP24XX_MCBSP1_BASE 0x48074000 -#define OMAP24XX_MCBSP2_BASE 0x48076000 -#define OMAP2430_MCBSP3_BASE 0x4808c000 -#define OMAP2430_MCBSP4_BASE 0x4808e000 -#define OMAP2430_MCBSP5_BASE 0x48096000 - -#define OMAP34XX_MCBSP1_BASE 0x48074000 -#define OMAP34XX_MCBSP2_BASE 0x49022000 -#define OMAP34XX_MCBSP2_ST_BASE 0x49028000 -#define OMAP34XX_MCBSP3_BASE 0x49024000 -#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000 -#define OMAP34XX_MCBSP3_BASE 0x49024000 -#define OMAP34XX_MCBSP4_BASE 0x49026000 -#define OMAP34XX_MCBSP5_BASE 0x48096000 - -#define OMAP44XX_MCBSP1_BASE 0x40122000 -#define OMAP44XX_MCBSP1_DMA_BASE 0x49022000 -#define OMAP44XX_MCBSP2_BASE 0x40124000 -#define OMAP44XX_MCBSP2_DMA_BASE 0x49024000 -#define OMAP44XX_MCBSP3_BASE 0x40126000 -#define OMAP44XX_MCBSP3_DMA_BASE 0x49026000 -#define OMAP44XX_MCBSP4_BASE 0x48096000 - -#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) +#ifdef CONFIG_ARCH_OMAP1 #define OMAP_MCBSP_REG_DRR2 0x00 #define OMAP_MCBSP_REG_DRR1 0x02 -- cgit v1.2.3-70-g09d2 From d594f1f31afe13edd8c02f3854a65cc58cfb3b74 Mon Sep 17 00:00:00 2001 From: David Cohen Date: Wed, 16 Feb 2011 19:35:51 +0000 Subject: omap: IOMMU: add support to callback during fault handling Add support to register an isr for IOMMU fault situations and adapt it to allow such (*isr)() to be used as fault callback. Drivers using IOMMU module might want to be informed when errors happen in order to debug it or react. Signed-off-by: David Cohen Acked-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/iommu2.c | 17 +++++++++-- arch/arm/plat-omap/include/plat/iommu.h | 14 ++++++++- arch/arm/plat-omap/iommu.c | 52 +++++++++++++++++++++++---------- 3 files changed, 65 insertions(+), 18 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index 49a1e5e841c..adb083e41ac 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -146,18 +146,31 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on) static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) { u32 stat, da; + u32 errs = 0; stat = iommu_read_reg(obj, MMU_IRQSTATUS); stat &= MMU_IRQ_MASK; - if (!stat) + if (!stat) { + *ra = 0; return 0; + } da = iommu_read_reg(obj, MMU_FAULT_AD); *ra = da; + if (stat & MMU_IRQ_TLBMISS) + errs |= OMAP_IOMMU_ERR_TLB_MISS; + if (stat & MMU_IRQ_TRANSLATIONFAULT) + errs |= OMAP_IOMMU_ERR_TRANS_FAULT; + if (stat & MMU_IRQ_EMUMISS) + errs |= OMAP_IOMMU_ERR_EMU_MISS; + if (stat & MMU_IRQ_TABLEWALKFAULT) + errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT; + if (stat & MMU_IRQ_MULTIHITFAULT) + errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT; iommu_write_reg(obj, stat, MMU_IRQSTATUS); - return stat; + return errs; } static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 19cbb5e9ece..174f1b9c8c0 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h @@ -31,6 +31,7 @@ struct iommu { struct clk *clk; void __iomem *regbase; struct device *dev; + void *isr_priv; unsigned int refcount; struct mutex iommu_lock; /* global for this whole object */ @@ -47,7 +48,7 @@ struct iommu { struct list_head mmap; struct mutex mmap_lock; /* protect mmap */ - int (*isr)(struct iommu *obj); + int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv); void *ctx; /* iommu context: registres saved area */ u32 da_start; @@ -109,6 +110,13 @@ struct iommu_platform_data { u32 da_end; }; +/* IOMMU errors */ +#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0) +#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1) +#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2) +#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3) +#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4) + #if defined(CONFIG_ARCH_OMAP1) #error "iommu for this processor not implemented yet" #else @@ -161,6 +169,10 @@ extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); extern struct iommu *iommu_get(const char *name); extern void iommu_put(struct iommu *obj); +extern int iommu_set_isr(const char *name, + int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, + void *priv), + void *isr_priv); extern void iommu_save_ctx(struct iommu *obj); extern void iommu_restore_ctx(struct iommu *obj); diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 4b3218eaf3e..e3eb0380090 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -783,25 +783,19 @@ static void iopgtable_clear_entry_all(struct iommu *obj) */ static irqreturn_t iommu_fault_handler(int irq, void *data) { - u32 stat, da; + u32 da, errs; u32 *iopgd, *iopte; - int err = -EIO; struct iommu *obj = data; if (!obj->refcount) return IRQ_NONE; - /* Dynamic loading TLB or PTE */ - if (obj->isr) - err = obj->isr(obj); - - if (!err) - return IRQ_HANDLED; - clk_enable(obj->clk); - stat = iommu_report_fault(obj, &da); + errs = iommu_report_fault(obj, &da); clk_disable(obj->clk); - if (!stat) + + /* Fault callback or TLB/PTE Dynamic loading */ + if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) return IRQ_HANDLED; iommu_disable(obj); @@ -809,15 +803,16 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) iopgd = iopgd_offset(obj, da); if (!iopgd_is_table(*iopgd)) { - dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", obj->name, - da, iopgd, *iopgd); + dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " + "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); return IRQ_NONE; } iopte = iopte_offset(iopgd, da); - dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", - obj->name, da, iopgd, *iopgd, iopte, *iopte); + dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " + "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, + iopte, *iopte); return IRQ_NONE; } @@ -920,6 +915,33 @@ void iommu_put(struct iommu *obj) } EXPORT_SYMBOL_GPL(iommu_put); +int iommu_set_isr(const char *name, + int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, + void *priv), + void *isr_priv) +{ + struct device *dev; + struct iommu *obj; + + dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, + device_match_by_alias); + if (!dev) + return -ENODEV; + + obj = to_iommu(dev); + mutex_lock(&obj->iommu_lock); + if (obj->refcount != 0) { + mutex_unlock(&obj->iommu_lock); + return -EBUSY; + } + obj->isr = isr; + obj->isr_priv = isr_priv; + mutex_unlock(&obj->iommu_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(iommu_set_isr); + /* * OMAP Device MMU(IOMMU) detection */ -- cgit v1.2.3-70-g09d2 From 58e846fe7870d0ba22f8eeb1d522fbae37e80cbf Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:49:00 -0700 Subject: OMAP: clock: Add allow_idle/deny_idle support in clkops On OMAP various clock nodes (dpll's, mx post dividers, interface clocks) support hardware level autogating which can be controlled from software. Support such functionality by adding two new function pointer allow_idle and deny_idle in the clkops structure. These function pointers can be populated for any clock node which supports hardware level autogating. Also add 2 new functions (omap_clk_enable_autoidle_all and omap_clk_disable_autoidle_all) which can be called from architecture specific PM core code, if hardware level autogating (for all supported clock nodes) is to be enabled or disabled. Signed-off-by: Rajendra Nayak [paul@pwsan.com: use spinlock rather than mutex due to race; renamed functions; functions now return ints] Signed-off-by: Paul Walmsley --- arch/arm/plat-omap/clock.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/clock.h | 6 ++++++ 2 files changed, 38 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index fc62fb5fc20..0ae0eae01fd 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -335,6 +335,38 @@ struct clk *omap_clk_get_by_name(const char *name) return ret; } +int omap_clk_enable_autoidle_all(void) +{ + struct clk *c; + unsigned long flags; + + spin_lock_irqsave(&clockfw_lock, flags); + + list_for_each_entry(c, &clocks, node) + if (c->ops->allow_idle) + c->ops->allow_idle(c); + + spin_unlock_irqrestore(&clockfw_lock, flags); + + return 0; +} + +int omap_clk_disable_autoidle_all(void) +{ + struct clk *c; + unsigned long flags; + + spin_lock_irqsave(&clockfw_lock, flags); + + list_for_each_entry(c, &clocks, node) + if (c->ops->deny_idle) + c->ops->deny_idle(c); + + spin_unlock_irqrestore(&clockfw_lock, flags); + + return 0; +} + /* * Low level helpers */ diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index d43e6234dbb..be69f5cac32 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -25,6 +25,8 @@ struct clockdomain; * @disable: fn ptr that enables the current clock in hardware * @find_idlest: function returning the IDLEST register for the clock's IP blk * @find_companion: function returning the "companion" clk reg for the clock + * @allow_idle: fn ptr that enables autoidle for the current clock in hardware + * @deny_idle: fn ptr that disables autoidle for the current clock in hardware * * A "companion" clk is an accompanying clock to the one being queried * that must be enabled for the IP module connected to the clock to @@ -42,6 +44,8 @@ struct clkops { u8 *, u8 *); void (*find_companion)(struct clk *, void __iomem **, u8 *); + void (*allow_idle)(struct clk *); + void (*deny_idle)(struct clk *); }; #ifdef CONFIG_ARCH_OMAP2PLUS @@ -293,6 +297,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); #endif extern struct clk *omap_clk_get_by_name(const char *name); +extern int omap_clk_enable_autoidle_all(void); +extern int omap_clk_disable_autoidle_all(void); extern const struct clkops clkops_null; -- cgit v1.2.3-70-g09d2 From 97f678989afe5dd1584a0877dfd8b0d2e124b73a Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 25 Feb 2011 15:49:01 -0700 Subject: OMAP4: DPLL: Add dpll api to control GATE_CTRL On OMAP4, the dpll post divider outputs (MX outputs) along with clockout_x2 output provide a way to allow/deny hardware level autogating. Allowing autoidle would mean that the hw would autogate this clock when there is no dependency for it. Denying idle would mean that this clock output will be forced to stay enabled. Add dpll api's to read/allow/deny idle control for these dpll mx postdividers. NOTE: The gatectrl bit set to 0 allows gatectrl, and the bit set to 1 denies gatectrl. Signed-off-by: Rajendra Nayak [paul@pwsan.com: moved OMAP4-specific DPLL control code to mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/clock.h | 3 ++ arch/arm/mach-omap2/dpll44xx.c | 78 +++++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/clock.h | 14 +++++- 4 files changed, 95 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/dpll44xx.c (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 10c3c8f16ea..89274a9f035 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -123,7 +123,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ clock3517.o clock36xx.o \ dpll3xxx.o clock3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \ - dpll3xxx.o + dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 2a939e5ec6a..c450d69a0dc 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk); int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); int omap3_noncore_dpll_enable(struct clk *clk); void omap3_noncore_dpll_disable(struct clk *clk); +int omap4_dpllmx_gatectrl_read(struct clk *clk); +void omap4_dpllmx_allow_gatectrl(struct clk *clk); +void omap4_dpllmx_deny_gatectrl(struct clk *clk); #ifdef CONFIG_OMAP_RESET_CLOCKS void omap2_clk_disable_unused(struct clk *clk); diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c new file mode 100644 index 00000000000..94a3592cd54 --- /dev/null +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -0,0 +1,78 @@ +/* + * OMAP4-specific DPLL control functions + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Rajendra Nayak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "clock.h" +#include "cm-regbits-44xx.h" + +/* Supported only on OMAP4 */ +int omap4_dpllmx_gatectrl_read(struct clk *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + return -EINVAL; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = __raw_readl(clk->clksel_reg); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +void omap4_dpllmx_allow_gatectrl(struct clk *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + return; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = __raw_readl(clk->clksel_reg); + /* Clear the bit to allow gatectrl */ + v &= ~mask; + __raw_writel(v, clk->clksel_reg); +} + +void omap4_dpllmx_deny_gatectrl(struct clk *clk) +{ + u32 v; + u32 mask; + + if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + return; + + mask = clk->flags & CLOCK_CLKOUTX2 ? + OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : + OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; + + v = __raw_readl(clk->clksel_reg); + /* Set the bit to deny gatectrl */ + v |= mask; + __raw_writel(v, clk->clksel_reg); +} diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index be69f5cac32..dcd7bb81420 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -176,12 +176,24 @@ struct dpll_data { #endif -/* struct clk.flags possibilities */ +/* + * struct clk.flags possibilities + * + * XXX document the rest of the clock flags here + * + * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL + * bits share the same register. This flag allows the + * omap4_dpllmx*() code to determine which GATE_CTRL bit field + * should be used. This is a temporary solution - a better approach + * would be to associate clock type-specific data with the clock, + * similar to the struct dpll_data approach. + */ #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ #define CLOCK_IDLE_CONTROL (1 << 1) #define CLOCK_NO_IDLE_PARENT (1 << 2) #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ +#define CLOCK_CLKOUTX2 (1 << 5) /** * struct clk - OMAP struct clk -- cgit v1.2.3-70-g09d2 From eddb12624d9a8087f1f8f1a2812f840c5e8191ac Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 23 Feb 2011 00:14:04 -0700 Subject: OMAP2420: hwmod data: add dmtimer Add dmtimer data. Signed-off-by: Thara Gopinath Signed-off-by: Tarun Kanti DebBarma Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 634 +++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/dmtimer.h | 11 + 2 files changed, 645 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index f323c6bb22d..c2f84aa114b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -337,6 +338,625 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_timer_hwmod_class = { + .name = "timer", + .sysc = &omap2420_timer_sysc, + .rev = OMAP_TIMER_IP_VERSION_1, +}; + +/* timer1 */ +static struct omap_hwmod omap2420_timer1_hwmod; +static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { + { .irq = 37, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { + { + .pa_start = 0x48028000, + .pa_end = 0x48028000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_timer1_hwmod, + .clk = "gpt1_ick", + .addr = omap2420_timer1_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { + &omap2420_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap2420_timer1_hwmod = { + .name = "timer1", + .mpu_irqs = omap2420_timer1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs), + .main_clk = "gpt1_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT1_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, + }, + }, + .slaves = omap2420_timer1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer2 */ +static struct omap_hwmod omap2420_timer2_hwmod; +static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { + { .irq = 38, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = { + { + .pa_start = 0x4802a000, + .pa_end = 0x4802a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer2_hwmod, + .clk = "gpt2_ick", + .addr = omap2420_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { + &omap2420_l4_core__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap2420_timer2_hwmod = { + .name = "timer2", + .mpu_irqs = omap2420_timer2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs), + .main_clk = "gpt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT2_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, + }, + }, + .slaves = omap2420_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer3 */ +static struct omap_hwmod omap2420_timer3_hwmod; +static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { + { .irq = 39, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = { + { + .pa_start = 0x48078000, + .pa_end = 0x48078000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer3_hwmod, + .clk = "gpt3_ick", + .addr = omap2420_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { + &omap2420_l4_core__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap2420_timer3_hwmod = { + .name = "timer3", + .mpu_irqs = omap2420_timer3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs), + .main_clk = "gpt3_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT3_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, + }, + }, + .slaves = omap2420_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer4 */ +static struct omap_hwmod omap2420_timer4_hwmod; +static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { + { .irq = 40, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = { + { + .pa_start = 0x4807a000, + .pa_end = 0x4807a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer4_hwmod, + .clk = "gpt4_ick", + .addr = omap2420_timer4_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { + &omap2420_l4_core__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap2420_timer4_hwmod = { + .name = "timer4", + .mpu_irqs = omap2420_timer4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs), + .main_clk = "gpt4_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT4_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, + }, + }, + .slaves = omap2420_timer4_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer5 */ +static struct omap_hwmod omap2420_timer5_hwmod; +static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { + { .irq = 41, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = { + { + .pa_start = 0x4807c000, + .pa_end = 0x4807c000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer5_hwmod, + .clk = "gpt5_ick", + .addr = omap2420_timer5_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { + &omap2420_l4_core__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap2420_timer5_hwmod = { + .name = "timer5", + .mpu_irqs = omap2420_timer5_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs), + .main_clk = "gpt5_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT5_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, + }, + }, + .slaves = omap2420_timer5_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + + +/* timer6 */ +static struct omap_hwmod omap2420_timer6_hwmod; +static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { + { .irq = 42, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = { + { + .pa_start = 0x4807e000, + .pa_end = 0x4807e000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer6_hwmod, + .clk = "gpt6_ick", + .addr = omap2420_timer6_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { + &omap2420_l4_core__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap2420_timer6_hwmod = { + .name = "timer6", + .mpu_irqs = omap2420_timer6_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs), + .main_clk = "gpt6_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT6_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, + }, + }, + .slaves = omap2420_timer6_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer7 */ +static struct omap_hwmod omap2420_timer7_hwmod; +static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { + { .irq = 43, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = { + { + .pa_start = 0x48080000, + .pa_end = 0x48080000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer7_hwmod, + .clk = "gpt7_ick", + .addr = omap2420_timer7_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { + &omap2420_l4_core__timer7, +}; + +/* timer7 hwmod */ +static struct omap_hwmod omap2420_timer7_hwmod = { + .name = "timer7", + .mpu_irqs = omap2420_timer7_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs), + .main_clk = "gpt7_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT7_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, + }, + }, + .slaves = omap2420_timer7_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer8 */ +static struct omap_hwmod omap2420_timer8_hwmod; +static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { + { .irq = 44, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = { + { + .pa_start = 0x48082000, + .pa_end = 0x48082000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer8_hwmod, + .clk = "gpt8_ick", + .addr = omap2420_timer8_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { + &omap2420_l4_core__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap2420_timer8_hwmod = { + .name = "timer8", + .mpu_irqs = omap2420_timer8_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs), + .main_clk = "gpt8_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT8_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, + }, + }, + .slaves = omap2420_timer8_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer9 */ +static struct omap_hwmod omap2420_timer9_hwmod; +static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { + { .irq = 45, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = { + { + .pa_start = 0x48084000, + .pa_end = 0x48084000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer9_hwmod, + .clk = "gpt9_ick", + .addr = omap2420_timer9_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { + &omap2420_l4_core__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap2420_timer9_hwmod = { + .name = "timer9", + .mpu_irqs = omap2420_timer9_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs), + .main_clk = "gpt9_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT9_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, + }, + }, + .slaves = omap2420_timer9_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer10 */ +static struct omap_hwmod omap2420_timer10_hwmod; +static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { + { .irq = 46, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = { + { + .pa_start = 0x48086000, + .pa_end = 0x48086000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer10_hwmod, + .clk = "gpt10_ick", + .addr = omap2420_timer10_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { + &omap2420_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap2420_timer10_hwmod = { + .name = "timer10", + .mpu_irqs = omap2420_timer10_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs), + .main_clk = "gpt10_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT10_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, + }, + }, + .slaves = omap2420_timer10_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer11 */ +static struct omap_hwmod omap2420_timer11_hwmod; +static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { + { .irq = 47, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = { + { + .pa_start = 0x48088000, + .pa_end = 0x48088000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer11_hwmod, + .clk = "gpt11_ick", + .addr = omap2420_timer11_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { + &omap2420_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap2420_timer11_hwmod = { + .name = "timer11", + .mpu_irqs = omap2420_timer11_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs), + .main_clk = "gpt11_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT11_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, + }, + }, + .slaves = omap2420_timer11_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + +/* timer12 */ +static struct omap_hwmod omap2420_timer12_hwmod; +static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { + { .irq = 48, }, +}; + +static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = { + { + .pa_start = 0x4808a000, + .pa_end = 0x4808a000 + SZ_1K - 1, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer12_hwmod, + .clk = "gpt12_ick", + .addr = omap2420_timer12_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { + &omap2420_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap2420_timer12_hwmod = { + .name = "timer12", + .mpu_irqs = omap2420_timer12_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs), + .main_clk = "gpt12_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_GPT12_SHIFT, + .module_offs = CORE_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, + }, + }, + .slaves = omap2420_timer12_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { { @@ -1326,6 +1946,20 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, + + &omap2420_timer1_hwmod, + &omap2420_timer2_hwmod, + &omap2420_timer3_hwmod, + &omap2420_timer4_hwmod, + &omap2420_timer5_hwmod, + &omap2420_timer6_hwmod, + &omap2420_timer7_hwmod, + &omap2420_timer8_hwmod, + &omap2420_timer9_hwmod, + &omap2420_timer10_hwmod, + &omap2420_timer11_hwmod, + &omap2420_timer12_hwmod, + &omap2420_wd_timer2_hwmod, &omap2420_uart1_hwmod, &omap2420_uart2_hwmod, diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index dfa3aff9761..d6c70d2f403 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -3,6 +3,12 @@ * * OMAP Dual-Mode Timers * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Tarun Kanti DebBarma + * Thara Gopinath + * + * Platform device conversion and hwmod support. + * * Copyright (C) 2005 Nokia Corporation * Author: Lauri Leukkunen * PWM and clock framwork support by Timo Teras. @@ -44,6 +50,11 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 +/* + * IP revision identifier so that Highlander IP + * in OMAP4 can be distinguished. + */ +#define OMAP_TIMER_IP_VERSION_1 0x1 struct omap_dm_timer; extern struct omap_dm_timer *gptimer_wakeup; extern struct sys_timer omap_timer; -- cgit v1.2.3-70-g09d2 From 550c8092c55c22db8f843bad070fd1731292a75e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Mon, 28 Feb 2011 11:58:14 -0700 Subject: OMAP2+: hwmod: rename some init functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename omap_hwmod_init() to omap_hwmod_register(). Rename omap_hwmod_late_init() to omap_hwmod_setup_all(). Also change all of the callers to reflect the new names. While here, update some copyrights. Suggested by Tony Lindgren . N.B. The comment in mach-omap2/serial.c may no longer be correct, given recent changes in init order. Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Kevin Hilman Cc: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 33 +++++++++++++--------------- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 2 +- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +- arch/arm/mach-omap2/serial.c | 2 +- arch/arm/plat-omap/include/plat/omap_hwmod.h | 6 +++-- 7 files changed, 24 insertions(+), 25 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2a7ab6adee8..557d9eb609a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1,7 +1,7 @@ /* * omap_hwmod implementation for OMAP2/3/4 * - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009-2011 Nokia Corporation * * Paul Walmsley, Benoît Cousson, Kevin Hilman * @@ -901,7 +901,7 @@ static struct omap_hwmod *_lookup(const char *name) * @oh: struct omap_hwmod * * @data: not used; pass NULL * - * Called by omap_hwmod_late_init() (after omap2_clk_init()). + * Called by omap_hwmod_setup_all() (after omap2_clk_init()). * Resolves all clock names embedded in the hwmod. Returns -EINVAL if * the omap_hwmod has not yet been registered or if the clocks have * already been initialized, 0 on success, or a non-zero error on @@ -1580,17 +1580,15 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), return ret; } - /** - * omap_hwmod_init - init omap_hwmod code and register hwmods + * omap_hwmod_register - register an array of hwmods * @ohs: pointer to an array of omap_hwmods to register * * Intended to be called early in boot before the clock framework is * initialized. If @ohs is not null, will register all omap_hwmods - * listed in @ohs that are valid for this chip. Returns -EINVAL if - * omap_hwmod_init() has already been called or 0 otherwise. + * listed in @ohs that are valid for this chip. Returns 0. */ -int __init omap_hwmod_init(struct omap_hwmod **ohs) +int __init omap_hwmod_register(struct omap_hwmod **ohs) { int r, i; @@ -1613,9 +1611,8 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs) /* * _populate_mpu_rt_base - populate the virtual address for a hwmod * - * Must be called only from omap_hwmod_late_init so ioremap works properly. + * Must be called only from omap_hwmod_setup_all() so ioremap works properly. * Assumes the caller takes care of locking if needed. - * */ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) { @@ -1631,13 +1628,13 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) } /** - * omap_hwmod_late_init - do some post-clock framework initialization + * omap_hwmod_setup - do some post-clock framework initialization * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls * _setup() on each hwmod. Returns 0. */ -static int __init omap_hwmod_late_init(void) +static int __init omap_hwmod_setup_all(void) { int r; @@ -1645,7 +1642,7 @@ static int __init omap_hwmod_late_init(void) /* XXX check return value */ r = omap_hwmod_for_each(_init_clocks, NULL); - WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); + WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__); mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", @@ -1655,7 +1652,7 @@ static int __init omap_hwmod_late_init(void) return 0; } -core_initcall(omap_hwmod_late_init); +core_initcall(omap_hwmod_setup_all); /** * omap_hwmod_enable - enable an omap_hwmod @@ -2174,11 +2171,11 @@ int omap_hwmod_for_each_by_class(const char *classname, * @oh: struct omap_hwmod * * @state: state that _setup() should leave the hwmod in * - * Sets the hwmod state that @oh will enter at the end of _setup() (called by - * omap_hwmod_late_init()). Only valid to call between calls to - * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or - * -EINVAL if there is a problem with the arguments or if the hwmod is - * in the wrong state. + * Sets the hwmod state that @oh will enter at the end of _setup() + * (called by omap_hwmod_setup_all()). Only valid to call between + * calling omap_hwmod_register() and omap_hwmod_setup_all(). Returns + * 0 upon success or -EINVAL if there is a problem with the arguments + * or if the hwmod is in the wrong state. */ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) { diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index c2f84aa114b..e58621aa9b3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1990,5 +1990,5 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { int __init omap2420_hwmod_init(void) { - return omap_hwmod_init(omap2420_hwmods); + return omap_hwmod_register(omap2420_hwmods); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c03699653b0..b46a54ce1a4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -2183,5 +2183,5 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { int __init omap2430_hwmod_init(void) { - return omap_hwmod_init(omap2430_hwmods); + return omap_hwmod_register(omap2430_hwmods); } diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index b8776ee241f..fc1b2b963bb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2919,5 +2919,5 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { int __init omap3xxx_hwmod_init(void) { - return omap_hwmod_init(omap3xxx_hwmods); + return omap_hwmod_register(omap3xxx_hwmods); } diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 79a86017891..2c5882792e0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -5125,6 +5125,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { int __init omap44xx_hwmod_init(void) { - return omap_hwmod_init(omap44xx_hwmods); + return omap_hwmod_register(omap44xx_hwmods); } diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 47eef48b883..1ac361b7b8c 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -680,7 +680,7 @@ static int __init omap_serial_early_init(void) num_uarts++; /* - * NOTE: omap_hwmod_init() has not yet been called, + * NOTE: omap_hwmod_setup*() has not yet been called, * so no hwmod functions will work yet. */ diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index fedd82971c9..afdf1971c51 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -1,7 +1,7 @@ /* * omap_hwmod macros, structures * - * Copyright (C) 2009-2010 Nokia Corporation + * Copyright (C) 2009-2011 Nokia Corporation * Paul Walmsley * * Created in collaboration with (alphabetical order): Benoît Cousson, @@ -370,8 +370,10 @@ struct omap_hwmod_omap4_prcm { * of standby, rather than relying on module smart-standby * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for * SDRAM controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_RESET * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM * controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_IDLE * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) * when module is enabled, rather than the default, which is to * enable autoidle @@ -535,7 +537,7 @@ struct omap_hwmod { const struct omap_chip_id omap_chip; }; -int omap_hwmod_init(struct omap_hwmod **ohs); +int omap_hwmod_register(struct omap_hwmod **ohs); struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); -- cgit v1.2.3-70-g09d2 From a2debdbd1ad896a410019c9cf30785cad15930fc Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 23 Feb 2011 00:14:07 -0700 Subject: OMAP2+: hwmod: add ability to setup individual hwmods MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add omap_hwmod_setup_one(), which is intended for use early in boot to selectively setup the hwmods needed for system clocksources and clockevents, and any other hwmod that is needed in early boot. omap_hwmod_setup_all() can then be called later in the boot process. The point is to minimize the amount of code that needs to be run early. Signed-off-by: Paul Walmsley Cc: Benoît Cousson Cc: Kevin Hilman Cc: Santosh Shilimkar Cc: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 62 ++++++++++++++++++++++++---- arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 ++ 2 files changed, 58 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 43aa894174f..f76f133780c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -901,7 +901,7 @@ static struct omap_hwmod *_lookup(const char *name) * @oh: struct omap_hwmod * * @data: not used; pass NULL * - * Called by omap_hwmod_setup_all() (after omap2_clk_init()). + * Called by omap_hwmod_setup_*() (after omap2_clk_init()). * Resolves all clock names embedded in the hwmod. Returns 0 on * success, or a negative error code on failure. */ @@ -1616,7 +1616,7 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs) /* * _populate_mpu_rt_base - populate the virtual address for a hwmod * - * Must be called only from omap_hwmod_setup_all() so ioremap works properly. + * Must be called only from omap_hwmod_setup_*() so ioremap works properly. * Assumes the caller takes care of locking if needed. */ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) @@ -1635,12 +1635,60 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) return 0; } +/** + * omap_hwmod_setup_one - set up a single hwmod + * @oh_name: const char * name of the already-registered hwmod to set up + * + * Must be called after omap2_clk_init(). Resolves the struct clk + * names to struct clk pointers for each registered omap_hwmod. Also + * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon + * success. + */ +int __init omap_hwmod_setup_one(const char *oh_name) +{ + struct omap_hwmod *oh; + int r; + + pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); + + if (!mpu_oh) { + pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", + oh_name, MPU_INITIATOR_NAME); + return -EINVAL; + } + + oh = _lookup(oh_name); + if (!oh) { + WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); + return -EINVAL; + } + + if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) + omap_hwmod_setup_one(MPU_INITIATOR_NAME); + + r = _populate_mpu_rt_base(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); + return -EINVAL; + } + + r = _init_clocks(oh, NULL); + if (IS_ERR_VALUE(r)) { + WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); + return -EINVAL; + } + + _setup(oh, NULL); + + return 0; +} + /** * omap_hwmod_setup - do some post-clock framework initialization * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls - * _setup() on each hwmod. Returns 0 upon success or -EINVAL upon error. + * _setup() on each hwmod. Returns 0 upon success. */ static int __init omap_hwmod_setup_all(void) { @@ -1654,9 +1702,9 @@ static int __init omap_hwmod_setup_all(void) r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); - /* XXX check return value */ r = omap_hwmod_for_each(_init_clocks, NULL); - WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__); + WARN(IS_ERR_VALUE(r), + "omap_hwmod: %s: _init_clocks failed\n", __func__); omap_hwmod_for_each(_setup, NULL); @@ -2182,8 +2230,8 @@ int omap_hwmod_for_each_by_class(const char *classname, * @state: state that _setup() should leave the hwmod in * * Sets the hwmod state that @oh will enter at the end of _setup() - * (called by omap_hwmod_setup_all()). Only valid to call between - * calling omap_hwmod_register() and omap_hwmod_setup_all(). Returns + * (called by omap_hwmod_setup_*()). Only valid to call between + * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns * 0 upon success or -EINVAL if there is a problem with the arguments * or if the hwmod is in the wrong state. */ diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index afdf1971c51..f96e72ed4db 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -30,6 +30,7 @@ #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H #include +#include #include #include #include @@ -542,6 +543,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); +int __init omap_hwmod_setup_one(const char *name); + int omap_hwmod_enable(struct omap_hwmod *oh); int _omap_hwmod_enable(struct omap_hwmod *oh); int omap_hwmod_idle(struct omap_hwmod *oh); -- cgit v1.2.3-70-g09d2 From d6b5d01b3f7c10edb50b9092d8dcac9cab680ea3 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 17:38:25 -0700 Subject: OMAP2+: sdrc: fix compile break on OMAP4-only config on current omap-for-linus On non-OMAP2 and non-OMAP3 kernel configs, turn omap2_sdrc_init() into a no-op. Otherwise, compilation breaks on an OMAP4-only config with the current omap-for-linus branch: arch/arm/mach-omap2/built-in.o: In function `omap2_init_common_devices': ../mach-omap2/io.c:421: undefined reference to `omap2_sdrc_init' Thanks to Sergei Shtylyov for suggesting the use of a empty static inline function rather than a macro. Signed-off-by: Paul Walmsley Cc: Tony Lindgren Cc: Sergei Shtylyov [tony@atomide.com: updated not to use __init for inline omap2_sdrc_init] Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/sdrc.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h index efd87c8dda6..925b12b500d 100644 --- a/arch/arm/plat-omap/include/plat/sdrc.h +++ b/arch/arm/plat-omap/include/plat/sdrc.h @@ -124,8 +124,14 @@ struct omap_sdrc_params { u32 mr; }; -void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); +#else +static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1) {}; +#endif + int omap2_sdrc_get_params(unsigned long r, struct omap_sdrc_params **sdrc_cs0, struct omap_sdrc_params **sdrc_cs1); -- cgit v1.2.3-70-g09d2 From 181b250cf53233a7a7c6d7e1e9df402506712e93 Mon Sep 17 00:00:00 2001 From: Keshava Munegowda Date: Tue, 1 Mar 2011 20:08:16 +0530 Subject: arm: omap: usb: create common enums and structures for ehci and ohci Create the ehci and ohci specific platform data structures. The port enum values are made common for both ehci and ohci. Signed-off-by: Keshava Munegowda Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/board-3430sdp.c | 10 +++--- arch/arm/mach-omap2/board-3630sdp.c | 10 +++--- arch/arm/mach-omap2/board-4430sdp.c | 10 +++--- arch/arm/mach-omap2/board-am3517crane.c | 10 +++--- arch/arm/mach-omap2/board-am3517evm.c | 12 +++---- arch/arm/mach-omap2/board-cm-t35.c | 10 +++--- arch/arm/mach-omap2/board-cm-t3517.c | 8 ++--- arch/arm/mach-omap2/board-devkit8000.c | 10 +++--- arch/arm/mach-omap2/board-igep0020.c | 10 +++--- arch/arm/mach-omap2/board-igep0030.c | 10 +++--- arch/arm/mach-omap2/board-omap3beagle.c | 10 +++--- arch/arm/mach-omap2/board-omap3evm.c | 14 ++++---- arch/arm/mach-omap2/board-omap3pandora.c | 10 +++--- arch/arm/mach-omap2/board-omap3stalker.c | 10 +++--- arch/arm/mach-omap2/board-omap3touchbook.c | 10 +++--- arch/arm/mach-omap2/board-omap4panda.c | 10 +++--- arch/arm/mach-omap2/board-overo.c | 10 +++--- arch/arm/mach-omap2/board-zoom.c | 10 +++--- arch/arm/mach-omap2/usb-host.c | 50 +++++++++++++-------------- arch/arm/plat-omap/include/plat/usb.h | 54 +++++++++++++++++++----------- drivers/usb/host/ehci-omap.c | 42 +++++++++++------------ drivers/usb/host/ohci-omap3.c | 22 ++++++------ 22 files changed, 184 insertions(+), 168 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index d4e41ef86aa..a991aeb5609 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -653,11 +653,11 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 57, @@ -816,7 +816,7 @@ static void __init omap_3430sdp_init(void) board_flash_init(sdp_flash_partitions, chip_sel_3430); sdp3430_display_init(); enable_board_wakeup_source(); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); } MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 62645640f5e..03fd8aca3cc 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -54,11 +54,11 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 126, @@ -211,7 +211,7 @@ static void __init omap_sdp_init(void) board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp); enable_board_wakeup_source(); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); } MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 9cf8e333255..0e1609d3fa8 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -251,10 +251,10 @@ static void __init omap_4430sdp_init_irq(void) gic_init_irq(); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = false, .reset_gpio_port[0] = -EINVAL, .reset_gpio_port[1] = -EINVAL, @@ -584,7 +584,7 @@ static void __init omap_4430sdp_init(void) else gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); usb_musb_init(&musb_board_data); status = omap_ethernet_init(); diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 71acb5ab281..1b825a00c5b 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -59,10 +59,10 @@ static void __init am3517_crane_init_irq(void) omap_init_irq(); } -static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = GPIO_USB_NRESET, @@ -103,7 +103,7 @@ static void __init am3517_crane_init(void) return; } - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); } MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 10d60b7743c..f5bc1c6ccf5 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -430,15 +430,15 @@ static __init void am3517_evm_musb_init(void) usb_musb_init(&musb_board_data); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE) - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, #else - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, #endif - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 57, @@ -502,7 +502,7 @@ static void __init am3517_evm_init(void) /* Configure GPIO for EHCI port */ omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); am3517_evm_hecc_init(&am3517_evm_hecc_pdata); /* DSS */ am3517_evm_display_init(); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index dac14161066..c79aa9be72f 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -605,10 +605,10 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, @@ -810,7 +810,7 @@ static void __init cm_t35_init(void) cm_t35_init_display(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); } MACHINE_START(CM_T35, "Compulab CM-T35") diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 8f9a64d650e..8288a0b9159 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -167,10 +167,10 @@ static inline void cm_t3517_init_rtc(void) {} #define HSUSB2_RESET_GPIO (147) #define USB_HUB_RESET_GPIO (152) -static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data cm_t3517_ehci_pdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = HSUSB1_RESET_GPIO, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 9a2a31e011c..e0131dda579 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -620,11 +620,11 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -803,7 +803,7 @@ static void __init devkit8000_init(void) devkit8000_ads7846_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); devkit8000_flash_init(); /* Ensure SDRC pins are mux'd for self-refresh */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 3be85a1f55f..a9d7d1dc63a 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -627,10 +627,10 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET, @@ -699,7 +699,7 @@ static void __init igep2_init(void) platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); omap_serial_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); igep2_flash_init(); igep2_leds_init(); diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index 4dc62a9b9cb..1b441eafdba 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -408,10 +408,10 @@ static void __init igep3_wifi_bt_init(void) void __init igep3_wifi_bt_init(void) {} #endif -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -435,7 +435,7 @@ static void __init igep3_init(void) platform_add_devices(igep3_devices, ARRAY_SIZE(igep3_devices)); omap_serial_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); igep3_flash_init(); igep3_leds_init(); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 46d814ab565..b84a6418ec1 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -586,11 +586,11 @@ static void __init omap3beagle_flash_init(void) } } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -625,7 +625,7 @@ static void __init omap3_beagle_init(void) gpio_direction_output(170, true); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); omap3beagle_flash_init(); /* Ensure SDRC pins are mux'd for self-refresh */ diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 323c3809ce3..ed5e4118147 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -638,11 +638,11 @@ static struct platform_device *omap3_evm_devices[] __initdata = { &omap3_evm_dss_device, }; -static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { +static struct usbhs_omap_board_data usbhs_bdata __initdata = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, /* PHY reset GPIO will be runtime programmed based on EVM version */ @@ -700,7 +700,7 @@ static void __init omap3_evm_init(void) /* setup EHCI phy reset config */ omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); - ehci_pdata.reset_gpio_port[1] = 21; + usbhs_bdata.reset_gpio_port[1] = 21; /* EVM REV >= E can supply 500mA with EXTVBUS programming */ musb_board_data.power = 500; @@ -708,10 +708,10 @@ static void __init omap3_evm_init(void) } else { /* setup EHCI phy reset on MDC */ omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); - ehci_pdata.reset_gpio_port[1] = 135; + usbhs_bdata.reset_gpio_port[1] = 135; } usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); ads7846_dev_init(); omap3evm_init_smsc911x(); omap3_evm_display_init(); diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 0b34beded11..241e632a466 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -681,11 +681,11 @@ static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_vwlan_device, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = 16, @@ -716,7 +716,7 @@ static void __init omap3pandora_init(void) spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); omap3pandora_ads7846_init(); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); usb_musb_init(&musb_board_data); gpmc_nand_init(&pandora_nand_data); diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 2a2dad447e8..eaad924b624 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -608,10 +608,10 @@ static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, }; -static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -649,7 +649,7 @@ static void __init omap3_stalker_init(void) omap_serial_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); ads7846_dev_init(); omap_mux_init_gpio(21, OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index db1f74fe6c4..4e3a1ae2ac9 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -468,11 +468,11 @@ static void __init omap3touchbook_flash_init(void) } } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -527,7 +527,7 @@ static void __init omap3_touchbook_init(void) ARRAY_SIZE(omap3_ads7846_spi_board_info)); omap3_ads7846_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); omap3touchbook_flash_init(); /* Ensure SDRC pins are mux'd for self-refresh */ diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 77748f81366..b88c1909434 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -83,10 +83,10 @@ static void __init omap4_panda_init_irq(void) gic_init_irq(); } -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = false, .reset_gpio_port[0] = -EINVAL, .reset_gpio_port[1] = -EINVAL, @@ -128,7 +128,7 @@ static void __init omap4_ehci_init(void) gpio_set_value(GPIO_HUB_NRESET, 0); gpio_set_value(GPIO_HUB_NRESET, 1); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); /* enable power to hub */ gpio_set_value(GPIO_HUB_POWER, 1); diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index cb26e5d8268..f78b74c369d 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -423,10 +423,10 @@ static struct platform_device *overo_devices[] __initdata = { &overo_lcd_device, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, @@ -454,7 +454,7 @@ static void __init overo_init(void) omap_serial_init(); overo_flash_init(); usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); overo_ads7846_init(); overo_init_smsc911x(); diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index e26754c24ee..19b99128df7 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -106,10 +106,10 @@ static struct mtd_partition zoom_nand_partitions[] = { }, }; -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, +static const struct usbhs_omap_board_data usbhs_bdata __initconst = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO, @@ -123,7 +123,7 @@ static void __init omap_zoom_init(void) } else if (machine_is_omap_zoom3()) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); - usb_ehci_init(&ehci_pdata); + usb_ehci_init(&usbhs_bdata); } board_nand_init(zoom_nand_partitions, diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 45f9b80b6d2..b04ce6f8f01 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -64,10 +64,10 @@ static struct platform_device ehci_device = { /* * setup_ehci_io_mux - initialize IO pad mux for USBHOST */ -static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) +static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN); @@ -81,7 +81,7 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN); omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("hsusb1_tll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hsusb1_tll_clk", @@ -107,14 +107,14 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb1_tll_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; } switch (port_mode[1]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT); omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN); @@ -136,7 +136,7 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb2_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("hsusb2_tll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hsusb2_tll_clk", @@ -162,17 +162,17 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb2_tll_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; } switch (port_mode[2]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: printk(KERN_WARNING "Port3 can't be used in PHY mode\n"); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("hsusb3_tll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("hsusb3_tll_clk", @@ -198,7 +198,7 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("hsusb3_tll_data7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; @@ -207,10 +207,10 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) return; } -static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) +static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("usbb1_ulpiphy_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("usbb1_ulpiphy_clk", @@ -236,7 +236,7 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb1_ulpiphy_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("usbb1_ulpitll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("usbb1_ulpitll_clk", @@ -262,12 +262,12 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb1_ulpitll_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: default: break; } switch (port_mode[1]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap_mux_init_signal("usbb2_ulpiphy_stp", OMAP_PIN_OUTPUT); omap_mux_init_signal("usbb2_ulpiphy_clk", @@ -293,7 +293,7 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb2_ulpiphy_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap_mux_init_signal("usbb2_ulpitll_stp", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("usbb2_ulpitll_clk", @@ -319,13 +319,13 @@ static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) omap_mux_init_signal("usbb2_ulpitll_dat7", OMAP_PIN_INPUT_PULLDOWN); break; - case EHCI_HCD_OMAP_MODE_UNKNOWN: + case OMAP_USBHS_PORT_MODE_UNUSED: default: break; } } -void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) +void __init usb_ehci_init(const struct usbhs_omap_board_data *pdata) { platform_device_add_data(&ehci_device, pdata, sizeof(*pdata)); @@ -363,7 +363,7 @@ void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) #else -void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) +void __init usb_ehci_init(const struct usbhs_omap_board_data *pdata) { } @@ -411,7 +411,7 @@ static struct platform_device ohci_device = { .resource = ohci_resources, }; -static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) +static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: @@ -439,7 +439,7 @@ static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) omap_mux_init_signal("mm1_txdat", OMAP_PIN_INPUT_PULLDOWN); break; - case OMAP_OHCI_PORT_MODE_UNUSED: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; @@ -470,7 +470,7 @@ static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) omap_mux_init_signal("mm2_txdat", OMAP_PIN_INPUT_PULLDOWN); break; - case OMAP_OHCI_PORT_MODE_UNUSED: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; @@ -501,14 +501,14 @@ static void setup_ohci_io_mux(const enum ohci_omap3_port_mode *port_mode) omap_mux_init_signal("mm3_txdat", OMAP_PIN_INPUT_PULLDOWN); break; - case OMAP_OHCI_PORT_MODE_UNUSED: + case OMAP_USBHS_PORT_MODE_UNUSED: /* FALLTHROUGH */ default: break; } } -void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata) +void __init usb_ohci_init(const struct usbhs_omap_board_data *pdata) { platform_device_add_data(&ohci_device, pdata, sizeof(*pdata)); @@ -524,7 +524,7 @@ void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata) #else -void __init usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata) +void __init usb_ohci_init(const struct usbhs_omap_board_data *pdata) { } diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index f888e0e57dc..32dfe08023a 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -7,15 +7,12 @@ #include #define OMAP3_HS_USB_PORTS 3 -enum ehci_hcd_omap_mode { - EHCI_HCD_OMAP_MODE_UNKNOWN, - EHCI_HCD_OMAP_MODE_PHY, - EHCI_HCD_OMAP_MODE_TLL, - EHCI_HCD_OMAP_MODE_HSIC, -}; -enum ohci_omap3_port_mode { - OMAP_OHCI_PORT_MODE_UNUSED, +enum usbhs_omap_port_mode { + OMAP_USBHS_PORT_MODE_UNUSED, + OMAP_EHCI_PORT_MODE_PHY, + OMAP_EHCI_PORT_MODE_TLL, + OMAP_EHCI_PORT_MODE_HSIC, OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0, OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM, OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0, @@ -25,24 +22,45 @@ enum ohci_omap3_port_mode { OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0, OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM, OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0, - OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM, + OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM }; -struct ehci_hcd_omap_platform_data { - enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; - unsigned phy_reset:1; +struct usbhs_omap_board_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; /* have to be valid if phy_reset is true and portx is in phy mode */ int reset_gpio_port[OMAP3_HS_USB_PORTS]; + + /* Set this to true for ES2.x silicon */ + unsigned es2_compatibility:1; + + unsigned phy_reset:1; + + /* + * Regulators for USB PHYs. + * Each PHY can have a separate regulator. + */ + struct regulator *regulator[OMAP3_HS_USB_PORTS]; }; -struct ohci_hcd_omap_platform_data { - enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS]; +struct ehci_hcd_omap_platform_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; + int reset_gpio_port[OMAP3_HS_USB_PORTS]; + struct regulator *regulator[OMAP3_HS_USB_PORTS]; + unsigned phy_reset:1; +}; - /* Set this to true for ES2.x silicon */ +struct ohci_hcd_omap_platform_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; unsigned es2_compatibility:1; }; +struct usbhs_omap_platform_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; + + struct ehci_hcd_omap_platform_data *ehci_data; + struct ohci_hcd_omap_platform_data *ohci_data; +}; /*-------------------------------------------------------------------------*/ #define OMAP1_OTG_BASE 0xfffb0400 @@ -80,19 +98,17 @@ enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; extern void usb_musb_init(struct omap_musb_board_data *board_data); -extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata); +extern void usb_ehci_init(const struct usbhs_omap_board_data *pdata); -extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); +extern void usb_ohci_init(const struct usbhs_omap_board_data *pdata); extern int omap4430_phy_power(struct device *dev, int ID, int on); extern int omap4430_phy_set_clk(struct device *dev, int on); extern int omap4430_phy_init(struct device *dev); extern int omap4430_phy_exit(struct device *dev); extern int omap4430_phy_suspend(struct device *dev, int suspend); - #endif - /* * FIXME correct answer depends on hmc_mode, * as does (on omap1) any nonzero value for config->otg port number diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 15277213f92..18df6c6a580 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -155,9 +155,9 @@ #define is_omap_ehci_rev1(x) (x->omap_ehci_rev == OMAP_EHCI_REV1) #define is_omap_ehci_rev2(x) (x->omap_ehci_rev == OMAP_EHCI_REV2) -#define is_ehci_phy_mode(x) (x == EHCI_HCD_OMAP_MODE_PHY) -#define is_ehci_tll_mode(x) (x == EHCI_HCD_OMAP_MODE_TLL) -#define is_ehci_hsic_mode(x) (x == EHCI_HCD_OMAP_MODE_HSIC) +#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY) +#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL) +#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC) /*-------------------------------------------------------------------------*/ @@ -220,7 +220,7 @@ struct ehci_hcd_omap { u32 omap_ehci_rev; /* desired phy_mode: TLL, PHY */ - enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; void __iomem *uhh_base; void __iomem *tll_base; @@ -389,7 +389,7 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) */ if (is_omap_ehci_rev2(omap)) { switch (omap->port_mode[0]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap->xclk60mhsp1_ck = clk_get(omap->dev, "xclk60mhsp1_ck"); if (IS_ERR(omap->xclk60mhsp1_ck)) { @@ -413,7 +413,7 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) "Unable to set P1 f-clock\n"); } break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap->xclk60mhsp1_ck = clk_get(omap->dev, "init_60m_fclk"); if (IS_ERR(omap->xclk60mhsp1_ck)) { @@ -463,7 +463,7 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) break; } switch (omap->port_mode[1]) { - case EHCI_HCD_OMAP_MODE_PHY: + case OMAP_EHCI_PORT_MODE_PHY: omap->xclk60mhsp2_ck = clk_get(omap->dev, "xclk60mhsp2_ck"); if (IS_ERR(omap->xclk60mhsp2_ck)) { @@ -487,7 +487,7 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) "Unable to set P2 f-clock\n"); } break; - case EHCI_HCD_OMAP_MODE_TLL: + case OMAP_EHCI_PORT_MODE_TLL: omap->xclk60mhsp2_ck = clk_get(omap->dev, "init_60m_fclk"); if (IS_ERR(omap->xclk60mhsp2_ck)) { @@ -591,11 +591,11 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; if (is_omap_ehci_rev1(omap)) { - if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN) + if (omap->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; - if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN) + if (omap->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; - if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN) + if (omap->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; /* Bypass the TLL module for PHY mode operation */ @@ -656,15 +656,15 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04, EHCI_INSNREG04_DISABLE_UNSUSPEND); - if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) || - (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) || - (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) { + if ((omap->port_mode[0] == OMAP_EHCI_PORT_MODE_TLL) || + (omap->port_mode[1] == OMAP_EHCI_PORT_MODE_TLL) || + (omap->port_mode[2] == OMAP_EHCI_PORT_MODE_TLL)) { - if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) + if (omap->port_mode[0] == OMAP_EHCI_PORT_MODE_TLL) tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK; - if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) + if (omap->port_mode[1] == OMAP_EHCI_PORT_MODE_TLL) tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK; - if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) + if (omap->port_mode[2] == OMAP_EHCI_PORT_MODE_TLL) tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK; /* Enable UTMI mode for required TLL channels */ @@ -686,9 +686,9 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) } /* Soft reset the PHY using PHY reset command over ULPI */ - if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) + if (omap->port_mode[0] == OMAP_EHCI_PORT_MODE_PHY) omap_ehci_soft_phy_reset(omap, 0); - if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) + if (omap->port_mode[1] == OMAP_EHCI_PORT_MODE_PHY) omap_ehci_soft_phy_reset(omap, 1); return 0; @@ -903,7 +903,7 @@ static const struct hc_driver ehci_omap_hc_driver; */ static int ehci_hcd_omap_probe(struct platform_device *pdev) { - struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; + struct usbhs_omap_board_data *pdata = pdev->dev.platform_data; struct ehci_hcd_omap *omap; struct resource *res; struct usb_hcd *hcd; @@ -981,7 +981,7 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev) /* get ehci regulator and enable */ for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) { - if (omap->port_mode[i] != EHCI_HCD_OMAP_MODE_PHY) { + if (omap->port_mode[i] != OMAP_EHCI_PORT_MODE_PHY) { omap->regulator[i] = NULL; continue; } diff --git a/drivers/usb/host/ohci-omap3.c b/drivers/usb/host/ohci-omap3.c index 32f56bbec21..3f9db87fe52 100644 --- a/drivers/usb/host/ohci-omap3.c +++ b/drivers/usb/host/ohci-omap3.c @@ -141,7 +141,7 @@ struct ohci_hcd_omap3 { struct clk *usbtll_ick; /* port_mode: TLL/PHY, 2/3/4/6-PIN, DP-DM/DAT-SE0 */ - enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS]; + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; void __iomem *uhh_base; void __iomem *tll_base; void __iomem *ohci_base; @@ -206,10 +206,10 @@ static int ohci_omap3_start(struct usb_hcd *hcd) * convert the port-mode enum to a value we can use in the FSLSMODE * field of USBTLL_CHANNEL_CONF */ -static unsigned ohci_omap3_fslsmode(enum ohci_omap3_port_mode mode) +static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode) { switch (mode) { - case OMAP_OHCI_PORT_MODE_UNUSED: + case OMAP_USBHS_PORT_MODE_UNUSED: case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: return 0x0; @@ -266,7 +266,7 @@ static void ohci_omap3_tll_config(struct ohci_hcd_omap3 *omap) for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { /* Enable only those channels that are actually used */ - if (omap->port_mode[i] == OMAP_OHCI_PORT_MODE_UNUSED) + if (omap->port_mode[i] == OMAP_USBHS_PORT_MODE_UNUSED) continue; reg = ohci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); @@ -382,11 +382,11 @@ static int omap3_start_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd) * * For now, turn off all the Pi_CONNECT_STATUS bits * - if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED) + if (omap->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; - if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED) + if (omap->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; - if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED) + if (omap->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; */ reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; @@ -403,17 +403,17 @@ static int omap3_start_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd) reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; } else { dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n"); - if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED) + if (omap->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; - if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED) + if (omap->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; - if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED) + if (omap->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; @@ -580,7 +580,7 @@ static const struct hc_driver ohci_omap3_hc_driver = { */ static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev) { - struct ohci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; + struct usbhs_omap_board_data *pdata = pdev->dev.platform_data; struct ohci_hcd_omap3 *omap; struct resource *res; struct usb_hcd *hcd; -- cgit v1.2.3-70-g09d2 From 17cdd29d6e1ab4164c792d78c6f096fbafb94e3f Mon Sep 17 00:00:00 2001 From: Keshava Munegowda Date: Tue, 1 Mar 2011 20:08:17 +0530 Subject: usb: host: omap: common usb host core driver enabling and disabling the common clocks for ehci and ohci is implemented. usbhs is a common parent platform driver for EHCI and OHCI driver. This driver receives the clock enable and disable requests from ehci and ohci drivers.The UHH and TLL initialization is also performed. Signed-off-by: Keshava Munegowda Signed-off-by: Felipe Balbi --- arch/arm/plat-omap/include/plat/usb.h | 3 + drivers/mfd/Kconfig | 9 + drivers/mfd/Makefile | 1 + drivers/mfd/omap-usb-host.c | 1061 +++++++++++++++++++++++++++++++++ 4 files changed, 1074 insertions(+) create mode 100644 drivers/mfd/omap-usb-host.c (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 32dfe08023a..5dd27764eb6 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -102,6 +102,9 @@ extern void usb_ehci_init(const struct usbhs_omap_board_data *pdata); extern void usb_ohci_init(const struct usbhs_omap_board_data *pdata); +extern int omap_usbhs_enable(struct device *dev); +extern void omap_usbhs_disable(struct device *dev); + extern int omap4430_phy_power(struct device *dev, int ID, int on); extern int omap4430_phy_set_clk(struct device *dev, int on); extern int omap4430_phy_init(struct device *dev); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index fd018366d67..a6dfa37a674 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -624,6 +624,15 @@ config MFD_WL1273_CORE driver connects the radio-wl1273 V4L2 module and the wl1273 audio codec. +config MFD_OMAP_USB_HOST + bool "Support OMAP USBHS core driver" + depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3 + default y + help + This is the core driver for the OAMP EHCI and OHCI drivers. + This MFD driver does the required setup functionalities for + OMAP USB Host drivers. + endif # MFD_SUPPORT menu "Multimedia Capabilities Port drivers" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index a54e2c7c6a1..91fe384459a 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -83,3 +83,4 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o obj-$(CONFIG_MFD_VX855) += vx855.o obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o +obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c new file mode 100644 index 00000000000..cb01209754e --- /dev/null +++ b/drivers/mfd/omap-usb-host.c @@ -0,0 +1,1061 @@ +/** + * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com + * Author: Keshava Munegowda + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USBHS_DRIVER_NAME "usbhs-omap" +#define OMAP_EHCI_DEVICE "ehci-omap" +#define OMAP_OHCI_DEVICE "ohci-omap3" + +/* OMAP USBHOST Register addresses */ + +/* TLL Register Set */ +#define OMAP_USBTLL_REVISION (0x00) +#define OMAP_USBTLL_SYSCONFIG (0x10) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) + +#define OMAP_USBTLL_SYSSTATUS (0x14) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) + +#define OMAP_USBTLL_IRQSTATUS (0x18) +#define OMAP_USBTLL_IRQENABLE (0x1C) + +#define OMAP_TLL_SHARED_CONF (0x30) +#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) +#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) +#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) +#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) +#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) + +#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) +#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 +#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) +#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) +#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) +#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) +#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1) +#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) + +#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0 +#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1 +#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2 +#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3 +#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4 +#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5 +#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6 +#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7 +#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA +#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB + +#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) +#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) +#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) +#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) +#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) +#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) +#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) +#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) +#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) + +#define OMAP_TLL_CHANNEL_COUNT 3 +#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0) +#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1) +#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2) + +/* UHH Register Set */ +#define OMAP_UHH_REVISION (0x00) +#define OMAP_UHH_SYSCONFIG (0x10) +#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) +#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) + +#define OMAP_UHH_SYSSTATUS (0x14) +#define OMAP_UHH_HOSTCONFIG (0x40) +#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) +#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) +#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) +#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) +#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) +#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) +#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) +#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) +#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) +#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) +#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) +#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) + +/* OMAP4-specific defines */ +#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2) +#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2) +#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4) +#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4) +#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0) + +#define OMAP4_P1_MODE_CLEAR (3 << 16) +#define OMAP4_P1_MODE_TLL (1 << 16) +#define OMAP4_P1_MODE_HSIC (3 << 16) +#define OMAP4_P2_MODE_CLEAR (3 << 18) +#define OMAP4_P2_MODE_TLL (1 << 18) +#define OMAP4_P2_MODE_HSIC (3 << 18) + +#define OMAP_REV2_TLL_CHANNEL_COUNT 2 + +#define OMAP_UHH_DEBUG_CSR (0x44) + +/* Values of UHH_REVISION - Note: these are not given in the TRM */ +#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ +#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ + +#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1) +#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2) + +#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY) +#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL) +#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC) + + +struct usbhs_hcd_omap { + struct clk *usbhost_ick; + struct clk *usbhost_hs_fck; + struct clk *usbhost_fs_fck; + struct clk *xclk60mhsp1_ck; + struct clk *xclk60mhsp2_ck; + struct clk *utmi_p1_fck; + struct clk *usbhost_p1_fck; + struct clk *usbtll_p1_fck; + struct clk *utmi_p2_fck; + struct clk *usbhost_p2_fck; + struct clk *usbtll_p2_fck; + struct clk *init_60m_fclk; + struct clk *usbtll_fck; + struct clk *usbtll_ick; + + void __iomem *uhh_base; + void __iomem *tll_base; + + struct usbhs_omap_platform_data platdata; + + u32 usbhs_rev; + spinlock_t lock; + int count; +}; +/*-------------------------------------------------------------------------*/ + +const char usbhs_driver_name[] = USBHS_DRIVER_NAME; +static u64 usbhs_dmamask = ~(u32)0; + +/*-------------------------------------------------------------------------*/ + +static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) +{ + __raw_writel(val, base + reg); +} + +static inline u32 usbhs_read(void __iomem *base, u32 reg) +{ + return __raw_readl(base + reg); +} + +static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val) +{ + __raw_writeb(val, base + reg); +} + +static inline u8 usbhs_readb(void __iomem *base, u8 reg) +{ + return __raw_readb(base + reg); +} + +/*-------------------------------------------------------------------------*/ + +static struct platform_device *omap_usbhs_alloc_child(const char *name, + struct resource *res, int num_resources, void *pdata, + size_t pdata_size, struct device *dev) +{ + struct platform_device *child; + int ret; + + child = platform_device_alloc(name, 0); + + if (!child) { + dev_err(dev, "platform_device_alloc %s failed\n", name); + goto err_end; + } + + ret = platform_device_add_resources(child, res, num_resources); + if (ret) { + dev_err(dev, "platform_device_add_resources failed\n"); + goto err_alloc; + } + + ret = platform_device_add_data(child, pdata, pdata_size); + if (ret) { + dev_err(dev, "platform_device_add_data failed\n"); + goto err_alloc; + } + + child->dev.dma_mask = &usbhs_dmamask; + child->dev.coherent_dma_mask = 0xffffffff; + child->dev.parent = dev; + + ret = platform_device_add(child); + if (ret) { + dev_err(dev, "platform_device_add failed\n"); + goto err_alloc; + } + + return child; + +err_alloc: + platform_device_put(child); + +err_end: + return NULL; +} + +static int omap_usbhs_alloc_children(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct usbhs_hcd_omap *omap; + struct ehci_hcd_omap_platform_data *ehci_data; + struct ohci_hcd_omap_platform_data *ohci_data; + struct platform_device *ehci; + struct platform_device *ohci; + struct resource *res; + struct resource resources[2]; + int ret; + + omap = platform_get_drvdata(pdev); + ehci_data = omap->platdata.ehci_data; + ohci_data = omap->platdata.ohci_data; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci"); + if (!res) { + dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n"); + ret = -ENODEV; + goto err_end; + } + resources[0] = *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq"); + if (!res) { + dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n"); + ret = -ENODEV; + goto err_end; + } + resources[1] = *res; + + ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data, + sizeof(*ehci_data), dev); + + if (!ehci) { + dev_err(dev, "omap_usbhs_alloc_child failed\n"); + goto err_end; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci"); + if (!res) { + dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n"); + ret = -ENODEV; + goto err_ehci; + } + resources[0] = *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq"); + if (!res) { + dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n"); + ret = -ENODEV; + goto err_ehci; + } + resources[1] = *res; + + ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data, + sizeof(*ohci_data), dev); + if (!ohci) { + dev_err(dev, "omap_usbhs_alloc_child failed\n"); + goto err_ehci; + } + + return 0; + +err_ehci: + platform_device_put(ehci); + +err_end: + return ret; +} + +/** + * usbhs_omap_probe - initialize TI-based HCDs + * + * Allocates basic resources for this USB host controller. + */ +static int __devinit usbhs_omap_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct usbhs_omap_platform_data *pdata = dev->platform_data; + struct usbhs_hcd_omap *omap; + struct resource *res; + int ret = 0; + int i; + + if (!pdata) { + dev_err(dev, "Missing platfrom data\n"); + ret = -ENOMEM; + goto end_probe; + } + + omap = kzalloc(sizeof(*omap), GFP_KERNEL); + if (!omap) { + dev_err(dev, "Memory allocation failed\n"); + ret = -ENOMEM; + goto end_probe; + } + + spin_lock_init(&omap->lock); + + for (i = 0; i < OMAP3_HS_USB_PORTS; i++) + omap->platdata.port_mode[i] = pdata->port_mode[i]; + + omap->platdata.ehci_data = pdata->ehci_data; + omap->platdata.ohci_data = pdata->ohci_data; + + omap->usbhost_ick = clk_get(dev, "usbhost_ick"); + if (IS_ERR(omap->usbhost_ick)) { + ret = PTR_ERR(omap->usbhost_ick); + dev_err(dev, "usbhost_ick failed error:%d\n", ret); + goto err_end; + } + + omap->usbhost_hs_fck = clk_get(dev, "hs_fck"); + if (IS_ERR(omap->usbhost_hs_fck)) { + ret = PTR_ERR(omap->usbhost_hs_fck); + dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret); + goto err_usbhost_ick; + } + + omap->usbhost_fs_fck = clk_get(dev, "fs_fck"); + if (IS_ERR(omap->usbhost_fs_fck)) { + ret = PTR_ERR(omap->usbhost_fs_fck); + dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret); + goto err_usbhost_hs_fck; + } + + omap->usbtll_fck = clk_get(dev, "usbtll_fck"); + if (IS_ERR(omap->usbtll_fck)) { + ret = PTR_ERR(omap->usbtll_fck); + dev_err(dev, "usbtll_fck failed error:%d\n", ret); + goto err_usbhost_fs_fck; + } + + omap->usbtll_ick = clk_get(dev, "usbtll_ick"); + if (IS_ERR(omap->usbtll_ick)) { + ret = PTR_ERR(omap->usbtll_ick); + dev_err(dev, "usbtll_ick failed error:%d\n", ret); + goto err_usbtll_fck; + } + + omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk"); + if (IS_ERR(omap->utmi_p1_fck)) { + ret = PTR_ERR(omap->utmi_p1_fck); + dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret); + goto err_usbtll_ick; + } + + omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck"); + if (IS_ERR(omap->xclk60mhsp1_ck)) { + ret = PTR_ERR(omap->xclk60mhsp1_ck); + dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret); + goto err_utmi_p1_fck; + } + + omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk"); + if (IS_ERR(omap->utmi_p2_fck)) { + ret = PTR_ERR(omap->utmi_p2_fck); + dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret); + goto err_xclk60mhsp1_ck; + } + + omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck"); + if (IS_ERR(omap->xclk60mhsp2_ck)) { + ret = PTR_ERR(omap->xclk60mhsp2_ck); + dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret); + goto err_utmi_p2_fck; + } + + omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk"); + if (IS_ERR(omap->usbhost_p1_fck)) { + ret = PTR_ERR(omap->usbhost_p1_fck); + dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret); + goto err_xclk60mhsp2_ck; + } + + omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk"); + if (IS_ERR(omap->usbtll_p1_fck)) { + ret = PTR_ERR(omap->usbtll_p1_fck); + dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret); + goto err_usbhost_p1_fck; + } + + omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk"); + if (IS_ERR(omap->usbhost_p2_fck)) { + ret = PTR_ERR(omap->usbhost_p2_fck); + dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret); + goto err_usbtll_p1_fck; + } + + omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk"); + if (IS_ERR(omap->usbtll_p2_fck)) { + ret = PTR_ERR(omap->usbtll_p2_fck); + dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret); + goto err_usbhost_p2_fck; + } + + omap->init_60m_fclk = clk_get(dev, "init_60m_fclk"); + if (IS_ERR(omap->init_60m_fclk)) { + ret = PTR_ERR(omap->init_60m_fclk); + dev_err(dev, "init_60m_fclk failed error:%d\n", ret); + goto err_usbtll_p2_fck; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh"); + if (!res) { + dev_err(dev, "UHH EHCI get resource failed\n"); + ret = -ENODEV; + goto err_init_60m_fclk; + } + + omap->uhh_base = ioremap(res->start, resource_size(res)); + if (!omap->uhh_base) { + dev_err(dev, "UHH ioremap failed\n"); + ret = -ENOMEM; + goto err_init_60m_fclk; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll"); + if (!res) { + dev_err(dev, "UHH EHCI get resource failed\n"); + ret = -ENODEV; + goto err_tll; + } + + omap->tll_base = ioremap(res->start, resource_size(res)); + if (!omap->tll_base) { + dev_err(dev, "TLL ioremap failed\n"); + ret = -ENOMEM; + goto err_tll; + } + + platform_set_drvdata(pdev, omap); + + ret = omap_usbhs_alloc_children(pdev); + if (ret) { + dev_err(dev, "omap_usbhs_alloc_children failed\n"); + goto err_alloc; + } + + goto end_probe; + +err_alloc: + iounmap(omap->tll_base); + +err_tll: + iounmap(omap->uhh_base); + +err_init_60m_fclk: + clk_put(omap->init_60m_fclk); + +err_usbtll_p2_fck: + clk_put(omap->usbtll_p2_fck); + +err_usbhost_p2_fck: + clk_put(omap->usbhost_p2_fck); + +err_usbtll_p1_fck: + clk_put(omap->usbtll_p1_fck); + +err_usbhost_p1_fck: + clk_put(omap->usbhost_p1_fck); + +err_xclk60mhsp2_ck: + clk_put(omap->xclk60mhsp2_ck); + +err_utmi_p2_fck: + clk_put(omap->utmi_p2_fck); + +err_xclk60mhsp1_ck: + clk_put(omap->xclk60mhsp1_ck); + +err_utmi_p1_fck: + clk_put(omap->utmi_p1_fck); + +err_usbtll_ick: + clk_put(omap->usbtll_ick); + +err_usbtll_fck: + clk_put(omap->usbtll_fck); + +err_usbhost_fs_fck: + clk_put(omap->usbhost_fs_fck); + +err_usbhost_hs_fck: + clk_put(omap->usbhost_hs_fck); + +err_usbhost_ick: + clk_put(omap->usbhost_ick); + +err_end: + kfree(omap); + +end_probe: + return ret; +} + +/** + * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs + * @pdev: USB Host Controller being removed + * + * Reverses the effect of usbhs_omap_probe(). + */ +static int __devexit usbhs_omap_remove(struct platform_device *pdev) +{ + struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); + + if (omap->count != 0) { + dev_err(&pdev->dev, + "Either EHCI or OHCI is still using usbhs core\n"); + return -EBUSY; + } + + iounmap(omap->tll_base); + iounmap(omap->uhh_base); + clk_put(omap->init_60m_fclk); + clk_put(omap->usbtll_p2_fck); + clk_put(omap->usbhost_p2_fck); + clk_put(omap->usbtll_p1_fck); + clk_put(omap->usbhost_p1_fck); + clk_put(omap->xclk60mhsp2_ck); + clk_put(omap->utmi_p2_fck); + clk_put(omap->xclk60mhsp1_ck); + clk_put(omap->utmi_p1_fck); + clk_put(omap->usbtll_ick); + clk_put(omap->usbtll_fck); + clk_put(omap->usbhost_fs_fck); + clk_put(omap->usbhost_hs_fck); + clk_put(omap->usbhost_ick); + kfree(omap); + + return 0; +} + +static bool is_ohci_port(enum usbhs_omap_port_mode pmode) +{ + switch (pmode) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + return true; + + default: + return false; + } +} + +/* + * convert the port-mode enum to a value we can use in the FSLSMODE + * field of USBTLL_CHANNEL_CONF + */ +static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode) +{ + switch (mode) { + case OMAP_USBHS_PORT_MODE_UNUSED: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; + + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM; + + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + return OMAP_TLL_FSLSMODE_3PIN_PHY; + + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + return OMAP_TLL_FSLSMODE_4PIN_PHY; + + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0; + + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM; + + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + return OMAP_TLL_FSLSMODE_3PIN_TLL; + + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + return OMAP_TLL_FSLSMODE_4PIN_TLL; + + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0; + + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM; + default: + pr_warning("Invalid port mode, using default\n"); + return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; + } +} + +static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count) +{ + struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); + struct usbhs_omap_platform_data *pdata = dev->platform_data; + unsigned reg; + int i; + + /* Program Common TLL register */ + reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF); + reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON + | OMAP_TLL_SHARED_CONF_USB_DIVRATION); + reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; + reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; + + usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); + + /* Enable channels now */ + for (i = 0; i < tll_channel_count; i++) { + reg = usbhs_read(omap->tll_base, + OMAP_TLL_CHANNEL_CONF(i)); + + if (is_ohci_port(pdata->port_mode[i])) { + reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) + << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; + reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; + } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) { + + /* Disable AutoIdle, BitStuffing and use SDR Mode */ + reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE + | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF + | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); + + reg |= (1 << (i + 1)); + } else + continue; + + reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; + usbhs_write(omap->tll_base, + OMAP_TLL_CHANNEL_CONF(i), reg); + + usbhs_writeb(omap->tll_base, + OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); + } +} + +static int usbhs_enable(struct device *dev) +{ + struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); + struct usbhs_omap_platform_data *pdata = &omap->platdata; + unsigned long flags = 0; + int ret = 0; + unsigned long timeout; + unsigned reg; + + dev_dbg(dev, "starting TI HSUSB Controller\n"); + if (!pdata) { + dev_dbg(dev, "missing platform_data\n"); + ret = -ENODEV; + goto end_enable; + } + + spin_lock_irqsave(&omap->lock, flags); + if (omap->count > 0) + goto end_count; + + clk_enable(omap->usbhost_ick); + clk_enable(omap->usbhost_hs_fck); + clk_enable(omap->usbhost_fs_fck); + clk_enable(omap->usbtll_fck); + clk_enable(omap->usbtll_ick); + + if (pdata->ehci_data->phy_reset) { + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) { + gpio_request(pdata->ehci_data->reset_gpio_port[0], + "USB1 PHY reset"); + gpio_direction_output + (pdata->ehci_data->reset_gpio_port[0], 1); + } + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) { + gpio_request(pdata->ehci_data->reset_gpio_port[1], + "USB2 PHY reset"); + gpio_direction_output + (pdata->ehci_data->reset_gpio_port[1], 1); + } + + /* Hold the PHY in RESET for enough time till DIR is high */ + udelay(10); + } + + omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); + dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); + + /* perform TLL soft reset, and wait until reset is complete */ + usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, + OMAP_USBTLL_SYSCONFIG_SOFTRESET); + + /* Wait for TLL reset to complete */ + timeout = jiffies + msecs_to_jiffies(1000); + while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) + & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { + cpu_relax(); + + if (time_after(jiffies, timeout)) { + dev_dbg(dev, "operation timed out\n"); + ret = -EINVAL; + goto err_tll; + } + } + + dev_dbg(dev, "TLL RESET DONE\n"); + + /* (1<<3) = no idle mode only for initial debugging */ + usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, + OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | + OMAP_USBTLL_SYSCONFIG_SIDLEMODE | + OMAP_USBTLL_SYSCONFIG_AUTOIDLE); + + /* Put UHH in NoIdle/NoStandby mode */ + reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG); + if (is_omap_usbhs_rev1(omap)) { + reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP + | OMAP_UHH_SYSCONFIG_SIDLEMODE + | OMAP_UHH_SYSCONFIG_CACTIVITY + | OMAP_UHH_SYSCONFIG_MIDLEMODE); + reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; + + + } else if (is_omap_usbhs_rev2(omap)) { + reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR; + reg |= OMAP4_UHH_SYSCONFIG_NOIDLE; + reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR; + reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY; + } + + usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); + + reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); + /* setup ULPI bypass and burst configurations */ + reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN + | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN + | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); + reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; + reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; + + if (is_omap_usbhs_rev1(omap)) { + if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) + reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; + if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) + reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; + if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) + reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; + + /* Bypass the TLL module for PHY mode operation */ + if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { + dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); + if (is_ehci_phy_mode(pdata->port_mode[0]) || + is_ehci_phy_mode(pdata->port_mode[1]) || + is_ehci_phy_mode(pdata->port_mode[2])) + reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; + else + reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; + } else { + dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); + if (is_ehci_phy_mode(pdata->port_mode[0])) + reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; + else + reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; + if (is_ehci_phy_mode(pdata->port_mode[1])) + reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; + else + reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; + if (is_ehci_phy_mode(pdata->port_mode[2])) + reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; + else + reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; + } + } else if (is_omap_usbhs_rev2(omap)) { + /* Clear port mode fields for PHY mode*/ + reg &= ~OMAP4_P1_MODE_CLEAR; + reg &= ~OMAP4_P2_MODE_CLEAR; + + if (is_ehci_phy_mode(pdata->port_mode[0])) { + ret = clk_set_parent(omap->utmi_p1_fck, + omap->xclk60mhsp1_ck); + if (ret != 0) { + dev_err(dev, "xclk60mhsp1_ck set parent" + "failed error:%d\n", ret); + goto err_tll; + } + } else if (is_ehci_tll_mode(pdata->port_mode[0])) { + ret = clk_set_parent(omap->utmi_p1_fck, + omap->init_60m_fclk); + if (ret != 0) { + dev_err(dev, "init_60m_fclk set parent" + "failed error:%d\n", ret); + goto err_tll; + } + clk_enable(omap->usbhost_p1_fck); + clk_enable(omap->usbtll_p1_fck); + } + + if (is_ehci_phy_mode(pdata->port_mode[1])) { + ret = clk_set_parent(omap->utmi_p2_fck, + omap->xclk60mhsp2_ck); + if (ret != 0) { + dev_err(dev, "xclk60mhsp1_ck set parent" + "failed error:%d\n", ret); + goto err_tll; + } + } else if (is_ehci_tll_mode(pdata->port_mode[1])) { + ret = clk_set_parent(omap->utmi_p2_fck, + omap->init_60m_fclk); + if (ret != 0) { + dev_err(dev, "init_60m_fclk set parent" + "failed error:%d\n", ret); + goto err_tll; + } + clk_enable(omap->usbhost_p2_fck); + clk_enable(omap->usbtll_p2_fck); + } + + clk_enable(omap->utmi_p1_fck); + clk_enable(omap->utmi_p2_fck); + + if (is_ehci_tll_mode(pdata->port_mode[0]) || + (is_ohci_port(pdata->port_mode[0]))) + reg |= OMAP4_P1_MODE_TLL; + else if (is_ehci_hsic_mode(pdata->port_mode[0])) + reg |= OMAP4_P1_MODE_HSIC; + + if (is_ehci_tll_mode(pdata->port_mode[1]) || + (is_ohci_port(pdata->port_mode[1]))) + reg |= OMAP4_P2_MODE_TLL; + else if (is_ehci_hsic_mode(pdata->port_mode[1])) + reg |= OMAP4_P2_MODE_HSIC; + } + + usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); + dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); + + if (is_ehci_tll_mode(pdata->port_mode[0]) || + is_ehci_tll_mode(pdata->port_mode[1]) || + is_ehci_tll_mode(pdata->port_mode[2]) || + (is_ohci_port(pdata->port_mode[0])) || + (is_ohci_port(pdata->port_mode[1])) || + (is_ohci_port(pdata->port_mode[2]))) { + + /* Enable UTMI mode for required TLL channels */ + if (is_omap_usbhs_rev2(omap)) + usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); + else + usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); + } + + if (pdata->ehci_data->phy_reset) { + /* Hold the PHY in RESET for enough time till + * PHY is settled and ready + */ + udelay(10); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) + gpio_set_value + (pdata->ehci_data->reset_gpio_port[0], 0); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) + gpio_set_value + (pdata->ehci_data->reset_gpio_port[1], 0); + } + +end_count: + omap->count++; + goto end_enable; + +err_tll: + if (pdata->ehci_data->phy_reset) { + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) + gpio_free(pdata->ehci_data->reset_gpio_port[0]); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) + gpio_free(pdata->ehci_data->reset_gpio_port[1]); + } + + clk_disable(omap->usbtll_ick); + clk_disable(omap->usbtll_fck); + clk_disable(omap->usbhost_fs_fck); + clk_disable(omap->usbhost_hs_fck); + clk_disable(omap->usbhost_ick); + +end_enable: + spin_unlock_irqrestore(&omap->lock, flags); + return ret; +} + +static void usbhs_disable(struct device *dev) +{ + struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); + struct usbhs_omap_platform_data *pdata = &omap->platdata; + unsigned long flags = 0; + unsigned long timeout; + + dev_dbg(dev, "stopping TI HSUSB Controller\n"); + + spin_lock_irqsave(&omap->lock, flags); + + if (omap->count == 0) + goto end_disble; + + omap->count--; + + if (omap->count != 0) + goto end_disble; + + /* Reset OMAP modules for insmod/rmmod to work */ + usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, + is_omap_usbhs_rev2(omap) ? + OMAP4_UHH_SYSCONFIG_SOFTRESET : + OMAP_UHH_SYSCONFIG_SOFTRESET); + + timeout = jiffies + msecs_to_jiffies(100); + while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) + & (1 << 0))) { + cpu_relax(); + + if (time_after(jiffies, timeout)) + dev_dbg(dev, "operation timed out\n"); + } + + while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) + & (1 << 1))) { + cpu_relax(); + + if (time_after(jiffies, timeout)) + dev_dbg(dev, "operation timed out\n"); + } + + while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) + & (1 << 2))) { + cpu_relax(); + + if (time_after(jiffies, timeout)) + dev_dbg(dev, "operation timed out\n"); + } + + usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); + + while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) + & (1 << 0))) { + cpu_relax(); + + if (time_after(jiffies, timeout)) + dev_dbg(dev, "operation timed out\n"); + } + + if (pdata->ehci_data->phy_reset) { + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) + gpio_free(pdata->ehci_data->reset_gpio_port[0]); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) + gpio_free(pdata->ehci_data->reset_gpio_port[1]); + } + + clk_disable(omap->utmi_p2_fck); + clk_disable(omap->utmi_p1_fck); + clk_disable(omap->usbtll_ick); + clk_disable(omap->usbtll_fck); + clk_disable(omap->usbhost_fs_fck); + clk_disable(omap->usbhost_hs_fck); + clk_disable(omap->usbhost_ick); + +end_disble: + spin_unlock_irqrestore(&omap->lock, flags); +} + +int omap_usbhs_enable(struct device *dev) +{ + return usbhs_enable(dev->parent); +} +EXPORT_SYMBOL_GPL(omap_usbhs_enable); + +void omap_usbhs_disable(struct device *dev) +{ + usbhs_disable(dev->parent); +} +EXPORT_SYMBOL_GPL(omap_usbhs_disable); + +static struct platform_driver usbhs_omap_driver = { + .driver = { + .name = (char *)usbhs_driver_name, + .owner = THIS_MODULE, + }, + .remove = __exit_p(usbhs_omap_remove), +}; + +MODULE_AUTHOR("Keshava Munegowda "); +MODULE_ALIAS("platform:" USBHS_DRIVER_NAME); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI"); + +static int __init omap_usbhs_drvinit(void) +{ + return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe); +} + +/* + * init before ehci and ohci drivers; + * The usbhs core driver should be initialized much before + * the omap ehci and ohci probe functions are called. + */ +fs_initcall(omap_usbhs_drvinit); + +static void __exit omap_usbhs_drvexit(void) +{ + platform_driver_unregister(&usbhs_omap_driver); +} +module_exit(omap_usbhs_drvexit); -- cgit v1.2.3-70-g09d2 From 2236396d4d23828a0875a4d447103d0ab48aed0b Mon Sep 17 00:00:00 2001 From: Keshava Munegowda Date: Tue, 1 Mar 2011 20:08:18 +0530 Subject: arm: omap: usb: usbhs core device initialization A new usbhs platform device is defined; this device will be the parent device of ehci and ohci platform devices. the usbhs_init function is defined which does the usbhs device initialization and I/O mux of ehci and ohci. Signed-off-by: Keshava Munegowda Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/usb-host.c | 195 +++++++++++++++++++++++++++++++--- arch/arm/plat-omap/include/plat/usb.h | 2 + 2 files changed, 183 insertions(+), 14 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index b04ce6f8f01..ab063820874 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -6,6 +6,7 @@ * * Copyright (C) 2007-2011 Texas Instruments * Author: Vikram Pandita + * Author: Keshava Munegowda * * Generalization by: * Felipe Balbi @@ -19,7 +20,7 @@ #include #include #include -#include +#include #include #include @@ -30,7 +31,7 @@ #include "mux.h" -#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) +#ifdef CONFIG_MFD_OMAP_USB_HOST static struct resource ehci_resources[] = { { @@ -361,17 +362,6 @@ void __init usb_ehci_init(const struct usbhs_omap_board_data *pdata) } } -#else - -void __init usb_ehci_init(const struct usbhs_omap_board_data *pdata) - -{ -} - -#endif /* CONFIG_USB_EHCI_HCD */ - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - static struct resource ohci_resources[] = { { .name = "ohci", @@ -508,6 +498,77 @@ static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) } } +static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) +{ + switch (port_mode[0]) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + omap_mux_init_signal("usbb1_mm_rxdp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_mm_rxdm", + OMAP_PIN_INPUT_PULLDOWN); + + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + omap_mux_init_signal("usbb1_mm_rxrcv", + OMAP_PIN_INPUT_PULLDOWN); + + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + omap_mux_init_signal("usbb1_mm_txen", + OMAP_PIN_INPUT_PULLDOWN); + + + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + omap_mux_init_signal("usbb1_mm_txdat", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb1_mm_txse0", + OMAP_PIN_INPUT_PULLDOWN); + break; + + case OMAP_USBHS_PORT_MODE_UNUSED: + default: + break; + } + + switch (port_mode[1]) { + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: + omap_mux_init_signal("usbb2_mm_rxdp", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_mm_rxdm", + OMAP_PIN_INPUT_PULLDOWN); + + case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: + case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: + omap_mux_init_signal("usbb2_mm_rxrcv", + OMAP_PIN_INPUT_PULLDOWN); + + case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: + omap_mux_init_signal("usbb2_mm_txen", + OMAP_PIN_INPUT_PULLDOWN); + + + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: + case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: + omap_mux_init_signal("usbb2_mm_txdat", + OMAP_PIN_INPUT_PULLDOWN); + omap_mux_init_signal("usbb2_mm_txse0", + OMAP_PIN_INPUT_PULLDOWN); + break; + + case OMAP_USBHS_PORT_MODE_UNUSED: + default: + break; + } +} + void __init usb_ohci_init(const struct usbhs_omap_board_data *pdata) { platform_device_add_data(&ohci_device, pdata, sizeof(*pdata)); @@ -522,10 +583,116 @@ void __init usb_ohci_init(const struct usbhs_omap_board_data *pdata) } } +#define OMAP_USBHS_DEVICE "usbhs-omap" + +static struct resource usbhs_resources[] = { + { + .name = "uhh", + .flags = IORESOURCE_MEM, + }, + { + .name = "tll", + .flags = IORESOURCE_MEM, + }, + { + .name = "ehci", + .flags = IORESOURCE_MEM, + }, + { + .name = "ehci-irq", + .flags = IORESOURCE_IRQ, + }, + { + .name = "ohci", + .flags = IORESOURCE_MEM, + }, + { + .name = "ohci-irq", + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device usbhs_device = { + .name = OMAP_USBHS_DEVICE, + .id = 0, + .num_resources = ARRAY_SIZE(usbhs_resources), + .resource = usbhs_resources, +}; + +static struct usbhs_omap_platform_data usbhs_data; +static struct ehci_hcd_omap_platform_data ehci_data; +static struct ohci_hcd_omap_platform_data ohci_data; + +void __init usbhs_init(const struct usbhs_omap_board_data *pdata) +{ + int i; + + for (i = 0; i < OMAP3_HS_USB_PORTS; i++) { + usbhs_data.port_mode[i] = pdata->port_mode[i]; + ohci_data.port_mode[i] = pdata->port_mode[i]; + ehci_data.port_mode[i] = pdata->port_mode[i]; + ehci_data.reset_gpio_port[i] = pdata->reset_gpio_port[i]; + ehci_data.regulator[i] = pdata->regulator[i]; + } + ehci_data.phy_reset = pdata->phy_reset; + ohci_data.es2_compatibility = pdata->es2_compatibility; + usbhs_data.ehci_data = &ehci_data; + usbhs_data.ohci_data = &ohci_data; + + if (cpu_is_omap34xx()) { + usbhs_resources[0].start = OMAP34XX_UHH_CONFIG_BASE; + usbhs_resources[0].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1; + usbhs_resources[1].start = OMAP34XX_USBTLL_BASE; + usbhs_resources[1].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1; + usbhs_resources[2].start = OMAP34XX_EHCI_BASE; + usbhs_resources[2].end = OMAP34XX_EHCI_BASE + SZ_1K - 1; + usbhs_resources[3].start = INT_34XX_EHCI_IRQ; + usbhs_resources[4].start = OMAP34XX_OHCI_BASE; + usbhs_resources[4].end = OMAP34XX_OHCI_BASE + SZ_1K - 1; + usbhs_resources[5].start = INT_34XX_OHCI_IRQ; + setup_ehci_io_mux(pdata->port_mode); + setup_ohci_io_mux(pdata->port_mode); + } else if (cpu_is_omap44xx()) { + usbhs_resources[0].start = OMAP44XX_UHH_CONFIG_BASE; + usbhs_resources[0].end = OMAP44XX_UHH_CONFIG_BASE + SZ_1K - 1; + usbhs_resources[1].start = OMAP44XX_USBTLL_BASE; + usbhs_resources[1].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1; + usbhs_resources[2].start = OMAP44XX_HSUSB_EHCI_BASE; + usbhs_resources[2].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1; + usbhs_resources[3].start = OMAP44XX_IRQ_EHCI; + usbhs_resources[4].start = OMAP44XX_HSUSB_OHCI_BASE; + usbhs_resources[4].end = OMAP44XX_HSUSB_OHCI_BASE + SZ_1K - 1; + usbhs_resources[5].start = OMAP44XX_IRQ_OHCI; + setup_4430ehci_io_mux(pdata->port_mode); + setup_4430ohci_io_mux(pdata->port_mode); + } + + if (platform_device_add_data(&usbhs_device, + &usbhs_data, sizeof(usbhs_data)) < 0) { + printk(KERN_ERR "USBHS platform_device_add_data failed\n"); + goto init_end; + } + + if (platform_device_register(&usbhs_device) < 0) + printk(KERN_ERR "USBHS platform_device_register failed\n"); + +init_end: + return; +} + #else +void __init usbhs_init(const struct usbhs_omap_board_data *pdata) +{ +} + void __init usb_ohci_init(const struct usbhs_omap_board_data *pdata) { } -#endif /* CONFIG_USB_OHCI_HCD */ +void __init usb_ehci_init(const struct usbhs_omap_board_data *pdata) +{ +} +#endif + + diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 5dd27764eb6..4c8bdb835fa 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -102,6 +102,8 @@ extern void usb_ehci_init(const struct usbhs_omap_board_data *pdata); extern void usb_ohci_init(const struct usbhs_omap_board_data *pdata); +extern void usbhs_init(const struct usbhs_omap_board_data *pdata); + extern int omap_usbhs_enable(struct device *dev); extern void omap_usbhs_disable(struct device *dev); -- cgit v1.2.3-70-g09d2 From 3b68ae73d8afa925807ebaae7eb14e2afd43f5b5 Mon Sep 17 00:00:00 2001 From: Keshava Munegowda Date: Tue, 1 Mar 2011 20:08:20 +0530 Subject: arm: omap: usb: cleanup ehci and ohci resources and devices The prototype and defination of functions usb_ehci_init and usb_ohci_init are removed. The ehci and ohci devices are removed since usbhs device contains both ehci and ohci details. Signed-off-by: Keshava Munegowda Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/usb-host.c | 176 +++++----------------------------- arch/arm/plat-omap/include/plat/usb.h | 4 - 2 files changed, 26 insertions(+), 154 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index ab063820874..89ae29847c5 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -33,34 +33,46 @@ #ifdef CONFIG_MFD_OMAP_USB_HOST -static struct resource ehci_resources[] = { +#define OMAP_USBHS_DEVICE "usbhs-omap" + +static struct resource usbhs_resources[] = { + { + .name = "uhh", + .flags = IORESOURCE_MEM, + }, { + .name = "tll", .flags = IORESOURCE_MEM, }, { + .name = "ehci", .flags = IORESOURCE_MEM, }, { + .name = "ehci-irq", + .flags = IORESOURCE_IRQ, + }, + { + .name = "ohci", .flags = IORESOURCE_MEM, }, - { /* general IRQ */ - .flags = IORESOURCE_IRQ, + { + .name = "ohci-irq", + .flags = IORESOURCE_IRQ, } }; -static u64 ehci_dmamask = ~(u32)0; -static struct platform_device ehci_device = { - .name = "ehci-omap", - .id = 0, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = 0xffffffff, - .platform_data = NULL, - }, - .num_resources = ARRAY_SIZE(ehci_resources), - .resource = ehci_resources, +static struct platform_device usbhs_device = { + .name = OMAP_USBHS_DEVICE, + .id = 0, + .num_resources = ARRAY_SIZE(usbhs_resources), + .resource = usbhs_resources, }; +static struct usbhs_omap_platform_data usbhs_data; +static struct ehci_hcd_omap_platform_data ehci_data; +static struct ohci_hcd_omap_platform_data ohci_data; + /* MUX settings for EHCI pins */ /* * setup_ehci_io_mux - initialize IO pad mux for USBHOST @@ -326,81 +338,6 @@ static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode) } } -void __init usb_ehci_init(const struct usbhs_omap_board_data *pdata) -{ - platform_device_add_data(&ehci_device, pdata, sizeof(*pdata)); - - /* Setup Pin IO MUX for EHCI */ - if (cpu_is_omap34xx()) { - ehci_resources[0].start = OMAP34XX_EHCI_BASE; - ehci_resources[0].end = OMAP34XX_EHCI_BASE + SZ_1K - 1; - ehci_resources[1].start = OMAP34XX_UHH_CONFIG_BASE; - ehci_resources[1].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1; - ehci_resources[2].start = OMAP34XX_USBTLL_BASE; - ehci_resources[2].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1; - ehci_resources[3].start = INT_34XX_EHCI_IRQ; - setup_ehci_io_mux(pdata->port_mode); - } else if (cpu_is_omap44xx()) { - ehci_resources[0].start = OMAP44XX_HSUSB_EHCI_BASE; - ehci_resources[0].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1; - ehci_resources[1].start = OMAP44XX_UHH_CONFIG_BASE; - ehci_resources[1].end = OMAP44XX_UHH_CONFIG_BASE + SZ_2K - 1; - ehci_resources[2].start = OMAP44XX_USBTLL_BASE; - ehci_resources[2].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1; - ehci_resources[3].start = OMAP44XX_IRQ_EHCI; - setup_4430ehci_io_mux(pdata->port_mode); - } - - ehci_resources[0].name = "ehci"; - ehci_resources[1].name = "uhh"; - ehci_resources[2].name = "tll"; - ehci_resources[3].name = "irq"; - - if (platform_device_register(&ehci_device) < 0) { - printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n"); - return; - } -} - -static struct resource ohci_resources[] = { - { - .name = "ohci", - .start = OMAP34XX_OHCI_BASE, - .end = OMAP34XX_OHCI_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "uhh", - .start = OMAP34XX_UHH_CONFIG_BASE, - .end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "tll", - .start = OMAP34XX_USBTLL_BASE, - .end = OMAP34XX_USBTLL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { /* general IRQ */ - .name = "irq", - .start = INT_34XX_OHCI_IRQ, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 ohci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ohci_device = { - .name = "ohci-omap3", - .id = 0, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(ohci_resources), - .resource = ohci_resources, -}; - static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) { switch (port_mode[0]) { @@ -569,60 +506,6 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode) } } -void __init usb_ohci_init(const struct usbhs_omap_board_data *pdata) -{ - platform_device_add_data(&ohci_device, pdata, sizeof(*pdata)); - - /* Setup Pin IO MUX for OHCI */ - if (cpu_is_omap34xx()) - setup_ohci_io_mux(pdata->port_mode); - - if (platform_device_register(&ohci_device) < 0) { - pr_err("Unable to register FS-USB (OHCI) device\n"); - return; - } -} - -#define OMAP_USBHS_DEVICE "usbhs-omap" - -static struct resource usbhs_resources[] = { - { - .name = "uhh", - .flags = IORESOURCE_MEM, - }, - { - .name = "tll", - .flags = IORESOURCE_MEM, - }, - { - .name = "ehci", - .flags = IORESOURCE_MEM, - }, - { - .name = "ehci-irq", - .flags = IORESOURCE_IRQ, - }, - { - .name = "ohci", - .flags = IORESOURCE_MEM, - }, - { - .name = "ohci-irq", - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device usbhs_device = { - .name = OMAP_USBHS_DEVICE, - .id = 0, - .num_resources = ARRAY_SIZE(usbhs_resources), - .resource = usbhs_resources, -}; - -static struct usbhs_omap_platform_data usbhs_data; -static struct ehci_hcd_omap_platform_data ehci_data; -static struct ohci_hcd_omap_platform_data ohci_data; - void __init usbhs_init(const struct usbhs_omap_board_data *pdata) { int i; @@ -686,13 +569,6 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata) { } -void __init usb_ohci_init(const struct usbhs_omap_board_data *pdata) -{ -} - -void __init usb_ehci_init(const struct usbhs_omap_board_data *pdata) -{ -} #endif diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 4c8bdb835fa..fe449f1a1c1 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -98,10 +98,6 @@ enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; extern void usb_musb_init(struct omap_musb_board_data *board_data); -extern void usb_ehci_init(const struct usbhs_omap_board_data *pdata); - -extern void usb_ohci_init(const struct usbhs_omap_board_data *pdata); - extern void usbhs_init(const struct usbhs_omap_board_data *pdata); extern int omap_usbhs_enable(struct device *dev); -- cgit v1.2.3-70-g09d2 From e08016d0f4fcfe038a402071ada3073c6ca8d62d Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Tue, 1 Mar 2011 13:12:55 -0800 Subject: omap: mmc: split out init for 2420 The MMC controller on the OMAP2420 is different from those on the OMAP2430, OMAP3 and OMAP4 families - all of the latter are identical. The one on the OMAP2420 is closer to that on OMAP1 chips. Currently, the n8x0 is the only OMAP2420 platform supported in mainline which registers the MMC controller. Upcoming changes to register the controllers using hwmod data are potentially invasive. To reduce the risk, separate out the 2420 controller registration from the common init function and update its only user. Also seperating out mux settings for OMAP2420. Signed-off-by: Anand Gadiyar Signed-off-by: Kishore Kadiyala Cc: Tony Lindgren Cc: Madhusudhan Chikkature Cc: Chris Ball Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 2 +- arch/arm/mach-omap2/devices.c | 88 ++++++++++++++++++++++------------- arch/arm/plat-omap/include/plat/mmc.h | 4 ++ 3 files changed, 61 insertions(+), 33 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index b36cbd21e2d..e710cd9e079 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -536,7 +536,7 @@ static void __init n8x0_mmc_init(void) } mmc_data[0] = &mmc1_data; - omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC); + omap242x_init_mmc(mmc_data); } #else diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 9ee876fd367..100bb425e9c 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -650,11 +650,10 @@ err1: static inline void omap_hsmmc_reset(void) {} #endif -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ - defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, - int controller_nr) +static inline void omap242x_mmc_mux(struct omap_mmc_platform_data + *mmc_controller) { if ((mmc_controller->slots[0].switch_pin > 0) && \ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) @@ -665,33 +664,61 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, OMAP_PIN_INPUT_PULLUP); - if (cpu_is_omap2420() && controller_nr == 0) { - omap_mux_init_signal("sdmmc_cmd", 0); - omap_mux_init_signal("sdmmc_clki", 0); - omap_mux_init_signal("sdmmc_clko", 0); - omap_mux_init_signal("sdmmc_dat0", 0); - omap_mux_init_signal("sdmmc_dat_dir0", 0); - omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { - omap_mux_init_signal("sdmmc_dat1", 0); - omap_mux_init_signal("sdmmc_dat2", 0); - omap_mux_init_signal("sdmmc_dat3", 0); - omap_mux_init_signal("sdmmc_dat_dir1", 0); - omap_mux_init_signal("sdmmc_dat_dir2", 0); - omap_mux_init_signal("sdmmc_dat_dir3", 0); - } + omap_mux_init_signal("sdmmc_cmd", 0); + omap_mux_init_signal("sdmmc_clki", 0); + omap_mux_init_signal("sdmmc_clko", 0); + omap_mux_init_signal("sdmmc_dat0", 0); + omap_mux_init_signal("sdmmc_dat_dir0", 0); + omap_mux_init_signal("sdmmc_cmd_dir", 0); + if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { + omap_mux_init_signal("sdmmc_dat1", 0); + omap_mux_init_signal("sdmmc_dat2", 0); + omap_mux_init_signal("sdmmc_dat3", 0); + omap_mux_init_signal("sdmmc_dat_dir1", 0); + omap_mux_init_signal("sdmmc_dat_dir2", 0); + omap_mux_init_signal("sdmmc_dat_dir3", 0); + } - /* - * Use internal loop-back in MMC/SDIO Module Input Clock - * selection - */ - if (mmc_controller->slots[0].internal_clock) { - u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); - v |= (1 << 24); - omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); - } + /* + * Use internal loop-back in MMC/SDIO Module Input Clock + * selection + */ + if (mmc_controller->slots[0].internal_clock) { + u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + v |= (1 << 24); + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + } +} + +void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) +{ + char *name = "mmci-omap"; + + if (!mmc_data[0]) { + pr_err("%s fails: Incomplete platform data\n", __func__); + return; } + omap242x_mmc_mux(mmc_data[0]); + omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, + INT_24XX_MMC_IRQ, mmc_data[0]); +} + +#endif + +#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) + +static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, + int controller_nr) +{ + if ((mmc_controller->slots[0].switch_pin > 0) && \ + (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, + OMAP_PIN_INPUT_PULLUP); + if ((mmc_controller->slots[0].gpio_wp > 0) && \ + (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) + omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, + OMAP_PIN_INPUT_PULLUP); if (cpu_is_omap34xx()) { if (controller_nr == 0) { omap_mux_init_signal("sdmmc1_clk", @@ -808,10 +835,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, continue; } - if (cpu_is_omap2420()) { - size = OMAP2420_MMC_SIZE; - name = "mmci-omap"; - } else if (cpu_is_omap44xx()) { + if (cpu_is_omap44xx()) { if (i < 3) irq += OMAP44XX_IRQ_GIC_START; size = OMAP4_HSMMC_SIZE; diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index f57f36abb07..e5de5d452b3 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -159,6 +159,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot, defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers); +void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers); int omap_mmc_add(const char *name, int id, unsigned long base, @@ -169,6 +170,9 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers) { } +static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) +{ +} static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers) { -- cgit v1.2.3-70-g09d2 From 6ab8946f672497a55625d2106250d2923125fdfb Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Tue, 1 Mar 2011 13:12:56 -0800 Subject: OMAP: hwmod data: Add dev_attr and use in the host driver Add a device attribute to hwmod data of omap2430, omap3, omap4. Currently the device attribute holds information regarding dual volt MMC card support by the controller which will be later passed to the host driver via platform data. Signed-off-by: Kevin Hilman Signed-off-by: Kishore Kadiyala Acked-by: Benoit Cousson Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 6 ++++++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 6 ++++++ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 ++++++++ arch/arm/plat-omap/include/plat/mmc.h | 9 +++++++++ 4 files changed, 29 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 0d239e3a980..ca25fa2af78 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include "omap_hwmod_common_data.h" @@ -2204,6 +2205,10 @@ static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { &omap2430_l4_core__mmc1, }; +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + static struct omap_hwmod omap2430_mmc1_hwmod = { .name = "mmc1", .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, @@ -2223,6 +2228,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = { .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, }, }, + .dev_attr = &mmc1_dev_attr, .slaves = omap2430_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), .class = &omap2430_mmc_class, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 207ccfbac2e..5fdcc1e9d4a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -2944,6 +2945,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { &omap3xxx_l4_core__mmc1, }; +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + static struct omap_hwmod omap3xxx_mmc1_hwmod = { .name = "mmc1", .mpu_irqs = omap34xx_mmc1_mpu_irqs, @@ -2962,6 +2967,7 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = { .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, }, }, + .dev_attr = &mmc1_dev_attr, .slaves = omap3xxx_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), .class = &omap34xx_mmc_class, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 12fcd0a0820..9398c2db725 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -3383,6 +3384,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { }; /* mmc1 */ + static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { { .irq = 83 + OMAP44XX_IRQ_GIC_START }, }; @@ -3420,6 +3422,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { &omap44xx_l4_per__mmc1, }; +/* mmc1 dev_attr */ +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + static struct omap_hwmod omap44xx_mmc1_hwmod = { .name = "mmc1", .class = &omap44xx_mmc_hwmod_class, @@ -3433,6 +3440,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, }, }, + .dev_attr = &mmc1_dev_attr, .slaves = omap44xx_mmc1_slaves, .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), .masters = omap44xx_mmc1_masters, diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index e5de5d452b3..a7afab09571 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -43,6 +43,12 @@ #define OMAP_MMC_MAX_SLOTS 2 +#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1) + +struct omap_mmc_dev_attr { + u8 flags; +}; + struct omap_mmc_platform_data { /* back-link to device */ struct device *dev; @@ -71,6 +77,9 @@ struct omap_mmc_platform_data { u64 dma_mask; + /* Integrating attributes from the omap_hwmod layer */ + u8 controller_flags; + /* Register offset deviation */ u16 reg_offset; -- cgit v1.2.3-70-g09d2 From 4621d5f8cb435b1ba74efe6e0a7125febb40186b Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Mon, 28 Feb 2011 20:48:04 +0530 Subject: OMAP: adapt hsmmc to hwmod framework OMAP2420 platform consists of mmc block as in omap1 and not the hsmmc block as present in omap2430, omap3, omap4 platforms. Removing all base address macro defines except keeping one for OMAP2420 and adapting only hsmmc device registration and driver to hwmod framework. Changes involves: 1) Remove controller reset in devices.c which is taken care of by hwmod framework. 2) Using omap-device layer to register device and utilizing data from hwmod data file for base address, dma channel number, Irq_number, device attribute. 3) Update the driver to use dev_attr to find whether controller supports dual volt cards Signed-off-by: Paul Walmsley Signed-off-by: Kishore Kadiyala Reviewed-by: Balaji T K Cc: Benoit Cousson CC: Kevin Hilman Cc: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 168 ----------------- arch/arm/mach-omap2/hsmmc.c | 346 +++++++++++++++++++--------------- arch/arm/plat-omap/include/plat/mmc.h | 20 +- drivers/mmc/host/omap_hsmmc.c | 4 +- 4 files changed, 200 insertions(+), 338 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2f4a598ba67..31632ac1ca7 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -544,112 +544,6 @@ static inline void omap_init_aes(void) { } /*-------------------------------------------------------------------------*/ -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - -#define MMCHS_SYSCONFIG 0x0010 -#define MMCHS_SYSCONFIG_SWRESET (1 << 1) -#define MMCHS_SYSSTATUS 0x0014 -#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) - -static struct platform_device dummy_pdev = { - .dev = { - .bus = &platform_bus_type, - }, -}; - -/** - * omap_hsmmc_reset() - Full reset of each HS-MMC controller - * - * Ensure that each MMC controller is fully reset. Controllers - * left in an unknown state (by bootloader) may prevent retention - * or OFF-mode. This is especially important in cases where the - * MMC driver is not enabled, _or_ built as a module. - * - * In order for reset to work, interface, functional and debounce - * clocks must be enabled. The debounce clock comes from func_32k_clk - * and is not under SW control, so we only enable i- and f-clocks. - **/ -static void __init omap_hsmmc_reset(void) -{ - u32 i, nr_controllers; - struct clk *iclk, *fclk; - - if (cpu_is_omap242x()) - return; - - nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : - (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); - - for (i = 0; i < nr_controllers; i++) { - u32 v, base = 0; - struct device *dev = &dummy_pdev.dev; - - switch (i) { - case 0: - base = OMAP2_MMC1_BASE; - break; - case 1: - base = OMAP2_MMC2_BASE; - break; - case 2: - base = OMAP3_MMC3_BASE; - break; - case 3: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC4_BASE; - break; - case 4: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC5_BASE; - break; - } - - if (cpu_is_omap44xx()) - base += OMAP4_MMC_REG_OFFSET; - - dummy_pdev.id = i; - dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); - iclk = clk_get(dev, "ick"); - if (IS_ERR(iclk)) - goto err1; - if (clk_enable(iclk)) - goto err2; - - fclk = clk_get(dev, "fck"); - if (IS_ERR(fclk)) - goto err3; - if (clk_enable(fclk)) - goto err4; - - omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); - v = omap_readl(base + MMCHS_SYSSTATUS); - while (!(omap_readl(base + MMCHS_SYSSTATUS) & - MMCHS_SYSSTATUS_RESETDONE)) - cpu_relax(); - - clk_disable(fclk); - clk_put(fclk); - clk_disable(iclk); - clk_put(iclk); - } - return; - -err4: - clk_put(fclk); -err3: - clk_disable(iclk); -err2: - clk_put(iclk); -err1: - printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " - "cannot reset.\n", __func__, i); -} -#else -static inline void omap_hsmmc_reset(void) {} -#endif - #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) static inline void omap242x_mmc_mux(struct omap_mmc_platform_data @@ -706,67 +600,6 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) #endif -#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) - -void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers) -{ - int i; - char *name; - - for (i = 0; i < nr_controllers; i++) { - unsigned long base, size; - unsigned int irq = 0; - - if (!mmc_data[i]) - continue; - - switch (i) { - case 0: - base = OMAP2_MMC1_BASE; - irq = INT_24XX_MMC_IRQ; - break; - case 1: - base = OMAP2_MMC2_BASE; - irq = INT_24XX_MMC2_IRQ; - break; - case 2: - if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) - return; - base = OMAP3_MMC3_BASE; - irq = INT_34XX_MMC3_IRQ; - break; - case 3: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC4_BASE; - irq = OMAP44XX_IRQ_MMC4; - break; - case 4: - if (!cpu_is_omap44xx()) - return; - base = OMAP4_MMC5_BASE; - irq = OMAP44XX_IRQ_MMC5; - break; - default: - continue; - } - - if (cpu_is_omap44xx()) { - if (i < 3) - irq += OMAP44XX_IRQ_GIC_START; - size = OMAP4_HSMMC_SIZE; - name = "mmci-omap-hs"; - } else { - size = OMAP3_HSMMC_SIZE; - name = "mmci-omap-hs"; - } - omap_mmc_add(name, i, base, size, irq, mmc_data[i]); - }; -} - -#endif - /*-------------------------------------------------------------------------*/ #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) @@ -836,7 +669,6 @@ static int __init omap2_init_devices(void) * please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - omap_hsmmc_reset(); omap_init_audio(); omap_init_camera(); omap_init_mbox(); diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 1348ac3d60e..d492bc4d342 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "mux.h" #include "hsmmc.h" @@ -30,10 +31,6 @@ static u16 control_mmc1; #define HSMMC_NAME_LEN 9 -static struct hsmmc_controller { - char name[HSMMC_NAME_LEN + 1]; -} hsmmc[OMAP34XX_NR_MMC]; - #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) static int hsmmc_get_context_loss(struct device *dev) @@ -287,13 +284,203 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, } } -static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; +static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, + struct omap_mmc_platform_data *mmc) +{ + char *hc_name; + + hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); + if (!hc_name) { + pr_err("Cannot allocate memory for controller slot name\n"); + kfree(hc_name); + return -ENOMEM; + } + + if (c->name) + strncpy(hc_name, c->name, HSMMC_NAME_LEN); + else + snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", + c->mmc, 1); + mmc->slots[0].name = hc_name; + mmc->nr_slots = 1; + mmc->slots[0].caps = c->caps; + mmc->slots[0].internal_clock = !c->ext_clock; + mmc->dma_mask = 0xffffffff; + if (cpu_is_omap44xx()) + mmc->reg_offset = OMAP4_MMC_REG_OFFSET; + else + mmc->reg_offset = 0; + + mmc->get_context_loss_count = hsmmc_get_context_loss; + + mmc->slots[0].switch_pin = c->gpio_cd; + mmc->slots[0].gpio_wp = c->gpio_wp; + + mmc->slots[0].remux = c->remux; + mmc->slots[0].init_card = c->init_card; + + if (c->cover_only) + mmc->slots[0].cover = 1; + + if (c->nonremovable) + mmc->slots[0].nonremovable = 1; + + if (c->power_saving) + mmc->slots[0].power_saving = 1; + + if (c->no_off) + mmc->slots[0].no_off = 1; + + if (c->vcc_aux_disable_is_sleep) + mmc->slots[0].vcc_aux_disable_is_sleep = 1; + + /* + * NOTE: MMC slots should have a Vcc regulator set up. + * This may be from a TWL4030-family chip, another + * controllable regulator, or a fixed supply. + * + * temporary HACK: ocr_mask instead of fixed supply + */ + mmc->slots[0].ocr_mask = c->ocr_mask; + + if (cpu_is_omap3517() || cpu_is_omap3505()) + mmc->slots[0].set_power = nop_mmc_set_power; + else + mmc->slots[0].features |= HSMMC_HAS_PBIAS; + + if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) + mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; + + switch (c->mmc) { + case 1: + if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { + /* on-chip level shifting via PBIAS0/PBIAS1 */ + if (cpu_is_omap44xx()) { + mmc->slots[0].before_set_reg = + omap4_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap4_hsmmc1_after_set_reg; + } else { + mmc->slots[0].before_set_reg = + omap_hsmmc1_before_set_reg; + mmc->slots[0].after_set_reg = + omap_hsmmc1_after_set_reg; + } + } + + /* OMAP3630 HSMMC1 supports only 4-bit */ + if (cpu_is_omap3630() && + (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + mmc->slots[0].caps = c->caps; + } + break; + case 2: + if (c->ext_clock) + c->transceiver = 1; + if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + } + /* FALLTHROUGH */ + case 3: + if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { + /* off-chip level shifting, or none */ + mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; + mmc->slots[0].after_set_reg = NULL; + } + break; + case 4: + case 5: + mmc->slots[0].before_set_reg = NULL; + mmc->slots[0].after_set_reg = NULL; + break; + default: + pr_err("MMC%d configuration not supported!\n", c->mmc); + kfree(hc_name); + return -ENODEV; + } + return 0; +} + +static struct omap_device_pm_latency omap_hsmmc_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, + /* + * XXX There should also be an entry here to power off/on the + * MMC regulators/PBIAS cells, etc. + */ +}; + +#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 + +void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) +{ + struct omap_hwmod *oh; + struct omap_device *od; + struct omap_device_pm_latency *ohl; + char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; + struct omap_mmc_platform_data *mmc_data; + struct omap_mmc_dev_attr *mmc_dev_attr; + char *name; + int l; + int ohl_cnt = 0; + + mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); + if (!mmc_data) { + pr_err("Cannot allocate memory for mmc device!\n"); + goto done; + } + + if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) { + pr_err("%s fails!\n", __func__); + goto done; + } + omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); + + name = "mmci-omap-hs"; + ohl = omap_hsmmc_latency; + ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency); + + l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, + "mmc%d", ctrl_nr); + WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN, + "String buffer overflow in MMC%d device setup\n", ctrl_nr); + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + kfree(mmc_data->slots[0].name); + goto done; + } + + if (oh->dev_attr != NULL) { + mmc_dev_attr = oh->dev_attr; + mmc_data->controller_flags = mmc_dev_attr->flags; + } + + od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, + sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); + if (IS_ERR(od)) { + WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name); + kfree(mmc_data->slots[0].name); + goto done; + } + /* + * return device handle to board setup code + * required to populate for regulator framework structure + */ + hsmmcinfo->dev = &od->pdev.dev; + +done: + kfree(mmc_data); +} void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) { - struct omap2_hsmmc_info *c; - int nr_hsmmc = ARRAY_SIZE(hsmmc_data); - int i; u32 reg; if (!cpu_is_omap44xx()) { @@ -319,148 +506,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) omap4_ctrl_pad_writel(reg, control_mmc1); } - for (c = controllers; c->mmc; c++) { - struct hsmmc_controller *hc = hsmmc + c->mmc - 1; - struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; - - if (!c->mmc || c->mmc > nr_hsmmc) { - pr_debug("MMC%d: no such controller\n", c->mmc); - continue; - } - if (mmc) { - pr_debug("MMC%d: already configured\n", c->mmc); - continue; - } - - mmc = kzalloc(sizeof(struct omap_mmc_platform_data), - GFP_KERNEL); - if (!mmc) { - pr_err("Cannot allocate memory for mmc device!\n"); - goto done; - } - - if (c->name) - strncpy(hc->name, c->name, HSMMC_NAME_LEN); - else - snprintf(hc->name, ARRAY_SIZE(hc->name), - "mmc%islot%i", c->mmc, 1); - mmc->slots[0].name = hc->name; - mmc->nr_slots = 1; - mmc->slots[0].caps = c->caps; - mmc->slots[0].internal_clock = !c->ext_clock; - mmc->dma_mask = 0xffffffff; - if (cpu_is_omap44xx()) - mmc->reg_offset = OMAP4_MMC_REG_OFFSET; - else - mmc->reg_offset = 0; - - mmc->get_context_loss_count = hsmmc_get_context_loss; - - mmc->slots[0].switch_pin = c->gpio_cd; - mmc->slots[0].gpio_wp = c->gpio_wp; - - mmc->slots[0].remux = c->remux; - mmc->slots[0].init_card = c->init_card; - - if (c->cover_only) - mmc->slots[0].cover = 1; - - if (c->nonremovable) - mmc->slots[0].nonremovable = 1; - - if (c->power_saving) - mmc->slots[0].power_saving = 1; - - if (c->no_off) - mmc->slots[0].no_off = 1; - - if (c->vcc_aux_disable_is_sleep) - mmc->slots[0].vcc_aux_disable_is_sleep = 1; - - /* NOTE: MMC slots should have a Vcc regulator set up. - * This may be from a TWL4030-family chip, another - * controllable regulator, or a fixed supply. - * - * temporary HACK: ocr_mask instead of fixed supply - */ - mmc->slots[0].ocr_mask = c->ocr_mask; - - if (cpu_is_omap3517() || cpu_is_omap3505()) - mmc->slots[0].set_power = nop_mmc_set_power; - else - mmc->slots[0].features |= HSMMC_HAS_PBIAS; - - if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) - mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; - - switch (c->mmc) { - case 1: - if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { - /* on-chip level shifting via PBIAS0/PBIAS1 */ - if (cpu_is_omap44xx()) { - mmc->slots[0].before_set_reg = - omap4_hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = - omap4_hsmmc1_after_set_reg; - } else { - mmc->slots[0].before_set_reg = - omap_hsmmc1_before_set_reg; - mmc->slots[0].after_set_reg = - omap_hsmmc1_after_set_reg; - } - } - - /* Omap3630 HSMMC1 supports only 4-bit */ - if (cpu_is_omap3630() && - (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - mmc->slots[0].caps = c->caps; - } - break; - case 2: - if (c->ext_clock) - c->transceiver = 1; - if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { - c->caps &= ~MMC_CAP_8_BIT_DATA; - c->caps |= MMC_CAP_4_BIT_DATA; - } - /* FALLTHROUGH */ - case 3: - if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { - /* off-chip level shifting, or none */ - mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; - mmc->slots[0].after_set_reg = NULL; - } - break; - case 4: - case 5: - mmc->slots[0].before_set_reg = NULL; - mmc->slots[0].after_set_reg = NULL; - break; - default: - pr_err("MMC%d configuration not supported!\n", c->mmc); - kfree(mmc); - continue; - } - hsmmc_data[c->mmc - 1] = mmc; - omap_hsmmc_mux(hsmmc_data[c->mmc - 1], (c->mmc - 1)); - } - - omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); - - /* pass the device nodes back to board setup code */ - for (c = controllers; c->mmc; c++) { - struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; + for (; controllers->mmc; controllers++) + omap_init_hsmmc(controllers, controllers->mmc); - if (!c->mmc || c->mmc > nr_hsmmc) - continue; - c->dev = mmc->dev; - } - -done: - for (i = 0; i < nr_hsmmc; i++) - kfree(hsmmc_data[i]); } #endif diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index a7afab09571..f38fef9f131 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -24,22 +24,10 @@ #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ #define OMAP24XX_NR_MMC 2 -#define OMAP34XX_NR_MMC 3 -#define OMAP44XX_NR_MMC 5 #define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE -#define OMAP3_HSMMC_SIZE 0x200 -#define OMAP4_HSMMC_SIZE 0x1000 #define OMAP2_MMC1_BASE 0x4809c000 -#define OMAP2_MMC2_BASE 0x480b4000 -#define OMAP3_MMC3_BASE 0x480ad000 -#define OMAP4_MMC4_BASE 0x480d1000 -#define OMAP4_MMC5_BASE 0x480d5000 + #define OMAP4_MMC_REG_OFFSET 0x100 -#define HSMMC5 (1 << 4) -#define HSMMC4 (1 << 3) -#define HSMMC3 (1 << 2) -#define HSMMC2 (1 << 1) -#define HSMMC1 (1 << 0) #define OMAP_MMC_MAX_SLOTS 2 @@ -169,8 +157,6 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot, void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, int nr_controllers); void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); -void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers); int omap_mmc_add(const char *name, int id, unsigned long base, unsigned long size, unsigned int irq, struct omap_mmc_platform_data *data); @@ -182,10 +168,6 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) { } -static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers) -{ -} static inline int omap_mmc_add(const char *name, int id, unsigned long base, unsigned long size, unsigned int irq, struct omap_mmc_platform_data *data) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 8c42573f42e..d0bd2b43393 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -1571,7 +1571,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) break; } - if (host->id == OMAP_MMC1_DEVID) { + if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { /* Only MMC1 can interface at 3V without some flavor * of external transceiver; but they all handle 1.8V. */ @@ -1663,7 +1663,7 @@ static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) u32 hctl, capa, value; /* Only MMC1 supports 3.0V */ - if (host->id == OMAP_MMC1_DEVID) { + if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { hctl = SDVS30; capa = VS30 | VS18; } else { -- cgit v1.2.3-70-g09d2 From 7328ff4d72401835fa1aadfb9e574a2133bd952b Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:54:33 -0700 Subject: OMAP: smartreflex: move plat/smartreflex.h to mach-omap2/smartreflex.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no reason for this header file to be in plat-omap/include/plat/smartreflex.h. The hardware devices are in OMAP2+ SoCs only. Leaving this header file in plat-omap causes problems due to cross-dependencies with other header files that should live in mach-omap2/. Thanks to Benoît Cousson for suggesting the removal of the smartreflex.h include from the OMAP3xxx hwmod data. Signed-off-by: Paul Walmsley Cc: Benoît Cousson --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 1 - arch/arm/mach-omap2/smartreflex-class3.c | 2 +- arch/arm/mach-omap2/smartreflex.c | 2 +- arch/arm/mach-omap2/smartreflex.h | 245 ++++++++++++++++++++++++++ arch/arm/mach-omap2/sr_device.c | 2 +- arch/arm/plat-omap/include/plat/smartreflex.h | 245 -------------------------- 6 files changed, 248 insertions(+), 249 deletions(-) create mode 100644 arch/arm/mach-omap2/smartreflex.h delete mode 100644 arch/arm/plat-omap/include/plat/smartreflex.h (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e9d00122856..8de2de97c2a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include "omap_hwmod_common_data.h" diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c index 60e70552b4c..f438cf4d847 100644 --- a/arch/arm/mach-omap2/smartreflex-class3.c +++ b/arch/arm/mach-omap2/smartreflex-class3.c @@ -11,7 +11,7 @@ * published by the Free Software Foundation. */ -#include +#include "smartreflex.h" static int sr_class3_enable(struct voltagedomain *voltdm) { diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index c37e823266d..077dfb6fd8f 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -26,9 +26,9 @@ #include #include -#include #include "pm.h" +#include "smartreflex.h" #define SMARTREFLEX_NAME_LEN 16 #define NVALUE_NAME_LEN 40 diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h new file mode 100644 index 00000000000..6568c885f37 --- /dev/null +++ b/arch/arm/mach-omap2/smartreflex.h @@ -0,0 +1,245 @@ +/* + * OMAP Smartreflex Defines and Routines + * + * Author: Thara Gopinath + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Thara Gopinath + * + * Copyright (C) 2008 Nokia Corporation + * Kalle Jokiniemi + * + * Copyright (C) 2007 Texas Instruments, Inc. + * Lesly A M + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H +#define __ASM_ARM_OMAP_SMARTREFLEX_H + +#include +#include + +/* + * Different Smartreflex IPs version. The v1 is the 65nm version used in + * OMAP3430. The v2 is the update for the 45nm version of the IP + * used in OMAP3630 and OMAP4430 + */ +#define SR_TYPE_V1 1 +#define SR_TYPE_V2 2 + +/* SMART REFLEX REG ADDRESS OFFSET */ +#define SRCONFIG 0x00 +#define SRSTATUS 0x04 +#define SENVAL 0x08 +#define SENMIN 0x0C +#define SENMAX 0x10 +#define SENAVG 0x14 +#define AVGWEIGHT 0x18 +#define NVALUERECIPROCAL 0x1c +#define SENERROR_V1 0x20 +#define ERRCONFIG_V1 0x24 +#define IRQ_EOI 0x20 +#define IRQSTATUS_RAW 0x24 +#define IRQSTATUS 0x28 +#define IRQENABLE_SET 0x2C +#define IRQENABLE_CLR 0x30 +#define SENERROR_V2 0x34 +#define ERRCONFIG_V2 0x38 + +/* Bit/Shift Positions */ + +/* SRCONFIG */ +#define SRCONFIG_ACCUMDATA_SHIFT 22 +#define SRCONFIG_SRCLKLENGTH_SHIFT 12 +#define SRCONFIG_SENNENABLE_V1_SHIFT 5 +#define SRCONFIG_SENPENABLE_V1_SHIFT 3 +#define SRCONFIG_SENNENABLE_V2_SHIFT 1 +#define SRCONFIG_SENPENABLE_V2_SHIFT 0 +#define SRCONFIG_CLKCTRL_SHIFT 0 + +#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22) + +#define SRCONFIG_SRENABLE BIT(11) +#define SRCONFIG_SENENABLE BIT(10) +#define SRCONFIG_ERRGEN_EN BIT(9) +#define SRCONFIG_MINMAXAVG_EN BIT(8) +#define SRCONFIG_DELAYCTRL BIT(2) + +/* AVGWEIGHT */ +#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2 +#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0 + +/* NVALUERECIPROCAL */ +#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 +#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 +#define NVALUERECIPROCAL_RNSENP_SHIFT 8 +#define NVALUERECIPROCAL_RNSENN_SHIFT 0 + +/* ERRCONFIG */ +#define ERRCONFIG_ERRWEIGHT_SHIFT 16 +#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8 +#define ERRCONFIG_ERRMINLIMIT_SHIFT 0 + +#define SR_ERRWEIGHT_MASK (0x07 << 16) +#define SR_ERRMAXLIMIT_MASK (0xff << 8) +#define SR_ERRMINLIMIT_MASK (0xff << 0) + +#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31) +#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30) +#define ERRCONFIG_MCUACCUMINTEN BIT(29) +#define ERRCONFIG_MCUACCUMINTST BIT(28) +#define ERRCONFIG_MCUVALIDINTEN BIT(27) +#define ERRCONFIG_MCUVALIDINTST BIT(26) +#define ERRCONFIG_MCUBOUNDINTEN BIT(25) +#define ERRCONFIG_MCUBOUNDINTST BIT(24) +#define ERRCONFIG_MCUDISACKINTEN BIT(23) +#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23) +#define ERRCONFIG_MCUDISACKINTST BIT(22) +#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22) + +#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \ + ERRCONFIG_MCUACCUMINTST | \ + ERRCONFIG_MCUVALIDINTST | \ + ERRCONFIG_MCUBOUNDINTST | \ + ERRCONFIG_MCUDISACKINTST) +/* IRQSTATUS */ +#define IRQSTATUS_MCUACCUMINT BIT(3) +#define IRQSTATUS_MCVALIDINT BIT(2) +#define IRQSTATUS_MCBOUNDSINT BIT(1) +#define IRQSTATUS_MCUDISABLEACKINT BIT(0) + +/* IRQENABLE_SET and IRQENABLE_CLEAR */ +#define IRQENABLE_MCUACCUMINT BIT(3) +#define IRQENABLE_MCUVALIDINT BIT(2) +#define IRQENABLE_MCUBOUNDSINT BIT(1) +#define IRQENABLE_MCUDISABLEACKINT BIT(0) + +/* Common Bit values */ + +#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c +#define SRCLKLENGTH_13MHZ_SYSCLK 0x41 +#define SRCLKLENGTH_19MHZ_SYSCLK 0x60 +#define SRCLKLENGTH_26MHZ_SYSCLK 0x82 +#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 + +/* + * 3430 specific values. Maybe these should be passed from board file or + * pmic structures. + */ +#define OMAP3430_SR_ACCUMDATA 0x1f4 + +#define OMAP3430_SR1_SENPAVGWEIGHT 0x03 +#define OMAP3430_SR1_SENNAVGWEIGHT 0x03 + +#define OMAP3430_SR2_SENPAVGWEIGHT 0x01 +#define OMAP3430_SR2_SENNAVGWEIGHT 0x01 + +#define OMAP3430_SR_ERRWEIGHT 0x04 +#define OMAP3430_SR_ERRMAXLIMIT 0x02 + +/** + * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass + * pmic specific info to smartreflex driver + * + * @sr_pmic_init: API to initialize smartreflex on the PMIC side. + */ +struct omap_sr_pmic_data { + void (*sr_pmic_init) (void); +}; + +#ifdef CONFIG_OMAP_SMARTREFLEX +/* + * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR. + * The smartreflex class driver should pass the class type. + * Should be used to populate the class_type field of the + * omap_smartreflex_class_data structure. + */ +#define SR_CLASS1 0x1 +#define SR_CLASS2 0x2 +#define SR_CLASS3 0x3 + +/** + * struct omap_sr_class_data - Smartreflex class driver info + * + * @enable: API to enable a particular class smaartreflex. + * @disable: API to disable a particular class smartreflex. + * @configure: API to configure a particular class smartreflex. + * @notify: API to notify the class driver about an event in SR. + * Not needed for class3. + * @notify_flags: specify the events to be notified to the class driver + * @class_type: specify which smartreflex class. + * Can be used by the SR driver to take any class + * based decisions. + */ +struct omap_sr_class_data { + int (*enable)(struct voltagedomain *voltdm); + int (*disable)(struct voltagedomain *voltdm, int is_volt_reset); + int (*configure)(struct voltagedomain *voltdm); + int (*notify)(struct voltagedomain *voltdm, u32 status); + u8 notify_flags; + u8 class_type; +}; + +/** + * struct omap_sr_nvalue_table - Smartreflex n-target value info + * + * @efuse_offs: The offset of the efuse where n-target values are stored. + * @nvalue: The n-target value. + */ +struct omap_sr_nvalue_table { + u32 efuse_offs; + u32 nvalue; +}; + +/** + * struct omap_sr_data - Smartreflex platform data. + * + * @ip_type: Smartreflex IP type. + * @senp_mod: SENPENABLE value for the sr + * @senn_mod: SENNENABLE value for sr + * @nvalue_count: Number of distinct nvalues in the nvalue table + * @enable_on_init: whether this sr module needs to enabled at + * boot up or not. + * @nvalue_table: table containing the efuse offsets and nvalues + * corresponding to them. + * @voltdm: Pointer to the voltage domain associated with the SR + */ +struct omap_sr_data { + int ip_type; + u32 senp_mod; + u32 senn_mod; + int nvalue_count; + bool enable_on_init; + struct omap_sr_nvalue_table *nvalue_table; + struct voltagedomain *voltdm; +}; + +/* Smartreflex module enable/disable interface */ +void omap_sr_enable(struct voltagedomain *voltdm); +void omap_sr_disable(struct voltagedomain *voltdm); +void omap_sr_disable_reset_volt(struct voltagedomain *voltdm); + +/* API to register the pmic specific data with the smartreflex driver. */ +void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data); + +/* Smartreflex driver hooks to be called from Smartreflex class driver */ +int sr_enable(struct voltagedomain *voltdm, unsigned long volt); +void sr_disable(struct voltagedomain *voltdm); +int sr_configure_errgen(struct voltagedomain *voltdm); +int sr_configure_minmax(struct voltagedomain *voltdm); + +/* API to register the smartreflex class driver with the smartreflex driver */ +int sr_register_class(struct omap_sr_class_data *class_data); +#else +static inline void omap_sr_enable(struct voltagedomain *voltdm) {} +static inline void omap_sr_disable(struct voltagedomain *voltdm) {} +static inline void omap_sr_disable_reset_volt( + struct voltagedomain *voltdm) {} +static inline void omap_sr_register_pmic( + struct omap_sr_pmic_data *pmic_data) {} +#endif +#endif diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index b1e0af18a26..a636604961b 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -23,9 +23,9 @@ #include #include -#include #include +#include "smartreflex.h" #include "control.h" #include "pm.h" diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h deleted file mode 100644 index 6568c885f37..00000000000 --- a/arch/arm/plat-omap/include/plat/smartreflex.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * OMAP Smartreflex Defines and Routines - * - * Author: Thara Gopinath - * - * Copyright (C) 2010 Texas Instruments, Inc. - * Thara Gopinath - * - * Copyright (C) 2008 Nokia Corporation - * Kalle Jokiniemi - * - * Copyright (C) 2007 Texas Instruments, Inc. - * Lesly A M - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H -#define __ASM_ARM_OMAP_SMARTREFLEX_H - -#include -#include - -/* - * Different Smartreflex IPs version. The v1 is the 65nm version used in - * OMAP3430. The v2 is the update for the 45nm version of the IP - * used in OMAP3630 and OMAP4430 - */ -#define SR_TYPE_V1 1 -#define SR_TYPE_V2 2 - -/* SMART REFLEX REG ADDRESS OFFSET */ -#define SRCONFIG 0x00 -#define SRSTATUS 0x04 -#define SENVAL 0x08 -#define SENMIN 0x0C -#define SENMAX 0x10 -#define SENAVG 0x14 -#define AVGWEIGHT 0x18 -#define NVALUERECIPROCAL 0x1c -#define SENERROR_V1 0x20 -#define ERRCONFIG_V1 0x24 -#define IRQ_EOI 0x20 -#define IRQSTATUS_RAW 0x24 -#define IRQSTATUS 0x28 -#define IRQENABLE_SET 0x2C -#define IRQENABLE_CLR 0x30 -#define SENERROR_V2 0x34 -#define ERRCONFIG_V2 0x38 - -/* Bit/Shift Positions */ - -/* SRCONFIG */ -#define SRCONFIG_ACCUMDATA_SHIFT 22 -#define SRCONFIG_SRCLKLENGTH_SHIFT 12 -#define SRCONFIG_SENNENABLE_V1_SHIFT 5 -#define SRCONFIG_SENPENABLE_V1_SHIFT 3 -#define SRCONFIG_SENNENABLE_V2_SHIFT 1 -#define SRCONFIG_SENPENABLE_V2_SHIFT 0 -#define SRCONFIG_CLKCTRL_SHIFT 0 - -#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22) - -#define SRCONFIG_SRENABLE BIT(11) -#define SRCONFIG_SENENABLE BIT(10) -#define SRCONFIG_ERRGEN_EN BIT(9) -#define SRCONFIG_MINMAXAVG_EN BIT(8) -#define SRCONFIG_DELAYCTRL BIT(2) - -/* AVGWEIGHT */ -#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2 -#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0 - -/* NVALUERECIPROCAL */ -#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 -#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 -#define NVALUERECIPROCAL_RNSENP_SHIFT 8 -#define NVALUERECIPROCAL_RNSENN_SHIFT 0 - -/* ERRCONFIG */ -#define ERRCONFIG_ERRWEIGHT_SHIFT 16 -#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8 -#define ERRCONFIG_ERRMINLIMIT_SHIFT 0 - -#define SR_ERRWEIGHT_MASK (0x07 << 16) -#define SR_ERRMAXLIMIT_MASK (0xff << 8) -#define SR_ERRMINLIMIT_MASK (0xff << 0) - -#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31) -#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30) -#define ERRCONFIG_MCUACCUMINTEN BIT(29) -#define ERRCONFIG_MCUACCUMINTST BIT(28) -#define ERRCONFIG_MCUVALIDINTEN BIT(27) -#define ERRCONFIG_MCUVALIDINTST BIT(26) -#define ERRCONFIG_MCUBOUNDINTEN BIT(25) -#define ERRCONFIG_MCUBOUNDINTST BIT(24) -#define ERRCONFIG_MCUDISACKINTEN BIT(23) -#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23) -#define ERRCONFIG_MCUDISACKINTST BIT(22) -#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22) - -#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \ - ERRCONFIG_MCUACCUMINTST | \ - ERRCONFIG_MCUVALIDINTST | \ - ERRCONFIG_MCUBOUNDINTST | \ - ERRCONFIG_MCUDISACKINTST) -/* IRQSTATUS */ -#define IRQSTATUS_MCUACCUMINT BIT(3) -#define IRQSTATUS_MCVALIDINT BIT(2) -#define IRQSTATUS_MCBOUNDSINT BIT(1) -#define IRQSTATUS_MCUDISABLEACKINT BIT(0) - -/* IRQENABLE_SET and IRQENABLE_CLEAR */ -#define IRQENABLE_MCUACCUMINT BIT(3) -#define IRQENABLE_MCUVALIDINT BIT(2) -#define IRQENABLE_MCUBOUNDSINT BIT(1) -#define IRQENABLE_MCUDISABLEACKINT BIT(0) - -/* Common Bit values */ - -#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c -#define SRCLKLENGTH_13MHZ_SYSCLK 0x41 -#define SRCLKLENGTH_19MHZ_SYSCLK 0x60 -#define SRCLKLENGTH_26MHZ_SYSCLK 0x82 -#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 - -/* - * 3430 specific values. Maybe these should be passed from board file or - * pmic structures. - */ -#define OMAP3430_SR_ACCUMDATA 0x1f4 - -#define OMAP3430_SR1_SENPAVGWEIGHT 0x03 -#define OMAP3430_SR1_SENNAVGWEIGHT 0x03 - -#define OMAP3430_SR2_SENPAVGWEIGHT 0x01 -#define OMAP3430_SR2_SENNAVGWEIGHT 0x01 - -#define OMAP3430_SR_ERRWEIGHT 0x04 -#define OMAP3430_SR_ERRMAXLIMIT 0x02 - -/** - * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass - * pmic specific info to smartreflex driver - * - * @sr_pmic_init: API to initialize smartreflex on the PMIC side. - */ -struct omap_sr_pmic_data { - void (*sr_pmic_init) (void); -}; - -#ifdef CONFIG_OMAP_SMARTREFLEX -/* - * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR. - * The smartreflex class driver should pass the class type. - * Should be used to populate the class_type field of the - * omap_smartreflex_class_data structure. - */ -#define SR_CLASS1 0x1 -#define SR_CLASS2 0x2 -#define SR_CLASS3 0x3 - -/** - * struct omap_sr_class_data - Smartreflex class driver info - * - * @enable: API to enable a particular class smaartreflex. - * @disable: API to disable a particular class smartreflex. - * @configure: API to configure a particular class smartreflex. - * @notify: API to notify the class driver about an event in SR. - * Not needed for class3. - * @notify_flags: specify the events to be notified to the class driver - * @class_type: specify which smartreflex class. - * Can be used by the SR driver to take any class - * based decisions. - */ -struct omap_sr_class_data { - int (*enable)(struct voltagedomain *voltdm); - int (*disable)(struct voltagedomain *voltdm, int is_volt_reset); - int (*configure)(struct voltagedomain *voltdm); - int (*notify)(struct voltagedomain *voltdm, u32 status); - u8 notify_flags; - u8 class_type; -}; - -/** - * struct omap_sr_nvalue_table - Smartreflex n-target value info - * - * @efuse_offs: The offset of the efuse where n-target values are stored. - * @nvalue: The n-target value. - */ -struct omap_sr_nvalue_table { - u32 efuse_offs; - u32 nvalue; -}; - -/** - * struct omap_sr_data - Smartreflex platform data. - * - * @ip_type: Smartreflex IP type. - * @senp_mod: SENPENABLE value for the sr - * @senn_mod: SENNENABLE value for sr - * @nvalue_count: Number of distinct nvalues in the nvalue table - * @enable_on_init: whether this sr module needs to enabled at - * boot up or not. - * @nvalue_table: table containing the efuse offsets and nvalues - * corresponding to them. - * @voltdm: Pointer to the voltage domain associated with the SR - */ -struct omap_sr_data { - int ip_type; - u32 senp_mod; - u32 senn_mod; - int nvalue_count; - bool enable_on_init; - struct omap_sr_nvalue_table *nvalue_table; - struct voltagedomain *voltdm; -}; - -/* Smartreflex module enable/disable interface */ -void omap_sr_enable(struct voltagedomain *voltdm); -void omap_sr_disable(struct voltagedomain *voltdm); -void omap_sr_disable_reset_volt(struct voltagedomain *voltdm); - -/* API to register the pmic specific data with the smartreflex driver. */ -void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data); - -/* Smartreflex driver hooks to be called from Smartreflex class driver */ -int sr_enable(struct voltagedomain *voltdm, unsigned long volt); -void sr_disable(struct voltagedomain *voltdm); -int sr_configure_errgen(struct voltagedomain *voltdm); -int sr_configure_minmax(struct voltagedomain *voltdm); - -/* API to register the smartreflex class driver with the smartreflex driver */ -int sr_register_class(struct omap_sr_class_data *class_data); -#else -static inline void omap_sr_enable(struct voltagedomain *voltdm) {} -static inline void omap_sr_disable(struct voltagedomain *voltdm) {} -static inline void omap_sr_disable_reset_volt( - struct voltagedomain *voltdm) {} -static inline void omap_sr_register_pmic( - struct omap_sr_pmic_data *pmic_data) {} -#endif -#endif -- cgit v1.2.3-70-g09d2 From e1d6f4729e9fd46efa1029b6e806bb8b6c24e776 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Feb 2011 15:54:33 -0700 Subject: OMAP: voltage: move plat/voltage.h to mach-omap2/voltage.h At this point in time, there's no reason for this header file to be in plat-omap/include/plat/voltage.h. It should not be included by device drivers, and the code that uses it is currently all under mach-omap2/. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_twl.c | 2 +- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/mach-omap2/smartreflex.h | 3 +- arch/arm/mach-omap2/sr_device.c | 2 +- arch/arm/mach-omap2/voltage.c | 3 +- arch/arm/mach-omap2/voltage.h | 155 +++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 - arch/arm/plat-omap/include/plat/voltage.h | 155 --------------------------- 8 files changed, 162 insertions(+), 161 deletions(-) create mode 100644 arch/arm/mach-omap2/voltage.h delete mode 100644 arch/arm/plat-omap/include/plat/voltage.h (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 00e1d2b5368..ad8c18a45ce 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -18,7 +18,7 @@ #include #include -#include +#include "voltage.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 7bb64d8121a..2c3a2531e67 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -18,8 +18,8 @@ #include #include #include -#include +#include "voltage.h" #include "powerdomain.h" #include "clockdomain.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h index 6568c885f37..5f35b9e2555 100644 --- a/arch/arm/mach-omap2/smartreflex.h +++ b/arch/arm/mach-omap2/smartreflex.h @@ -21,7 +21,8 @@ #define __ASM_ARM_OMAP_SMARTREFLEX_H #include -#include + +#include "voltage.h" /* * Different Smartreflex IPs version. The v1 is the 65nm version used in diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index a636604961b..10d3c5ee801 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -23,9 +23,9 @@ #include #include -#include #include "smartreflex.h" +#include "voltage.h" #include "control.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 12be525b8df..3c9bcdce612 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -26,7 +26,6 @@ #include #include -#include #include "prm-regbits-34xx.h" #include "prm-regbits-44xx.h" @@ -35,6 +34,8 @@ #include "prminst44xx.h" #include "control.h" +#include "voltage.h" + #define VP_IDLE_TIMEOUT 200 #define VP_TRANXDONE_TIMEOUT 300 #define VOLTAGE_DIR_SIZE 16 diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h new file mode 100644 index 00000000000..5bd204e55c3 --- /dev/null +++ b/arch/arm/mach-omap2/voltage.h @@ -0,0 +1,155 @@ +/* + * OMAP Voltage Management Routines + * + * Author: Thara Gopinath + * + * Copyright (C) 2009 Texas Instruments, Inc. + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H +#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H + +#include + +#define VOLTSCALE_VPFORCEUPDATE 1 +#define VOLTSCALE_VCBYPASS 2 + +/* + * OMAP3 GENERIC setup times. Revisit to see if these needs to be + * passed from board or PMIC file + */ +#define OMAP3_CLKSETUP 0xff +#define OMAP3_VOLTOFFSET 0xff +#define OMAP3_VOLTSETUP2 0xff + +/* Voltage value defines */ +#define OMAP3430_VDD_MPU_OPP1_UV 975000 +#define OMAP3430_VDD_MPU_OPP2_UV 1075000 +#define OMAP3430_VDD_MPU_OPP3_UV 1200000 +#define OMAP3430_VDD_MPU_OPP4_UV 1270000 +#define OMAP3430_VDD_MPU_OPP5_UV 1350000 + +#define OMAP3430_VDD_CORE_OPP1_UV 975000 +#define OMAP3430_VDD_CORE_OPP2_UV 1050000 +#define OMAP3430_VDD_CORE_OPP3_UV 1150000 + +#define OMAP3630_VDD_MPU_OPP50_UV 1012500 +#define OMAP3630_VDD_MPU_OPP100_UV 1200000 +#define OMAP3630_VDD_MPU_OPP120_UV 1325000 +#define OMAP3630_VDD_MPU_OPP1G_UV 1375000 + +#define OMAP3630_VDD_CORE_OPP50_UV 1000000 +#define OMAP3630_VDD_CORE_OPP100_UV 1200000 + +#define OMAP4430_VDD_MPU_OPP50_UV 930000 +#define OMAP4430_VDD_MPU_OPP100_UV 1100000 +#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000 +#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000 + +#define OMAP4430_VDD_IVA_OPP50_UV 930000 +#define OMAP4430_VDD_IVA_OPP100_UV 1100000 +#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000 + +#define OMAP4430_VDD_CORE_OPP50_UV 930000 +#define OMAP4430_VDD_CORE_OPP100_UV 1100000 + +/** + * struct voltagedomain - omap voltage domain global structure. + * @name: Name of the voltage domain which can be used as a unique + * identifier. + */ +struct voltagedomain { + char *name; +}; + +/** + * struct omap_volt_data - Omap voltage specific data. + * @voltage_nominal: The possible voltage value in uV + * @sr_efuse_offs: The offset of the efuse register(from system + * control module base address) from where to read + * the n-target value for the smartreflex module. + * @sr_errminlimit: Error min limit value for smartreflex. This value + * differs at differnet opp and thus is linked + * with voltage. + * @vp_errorgain: Error gain value for the voltage processor. This + * field also differs according to the voltage/opp. + */ +struct omap_volt_data { + u32 volt_nominal; + u32 sr_efuse_offs; + u8 sr_errminlimit; + u8 vp_errgain; +}; + +/** + * struct omap_volt_pmic_info - PMIC specific data required by voltage driver. + * @slew_rate: PMIC slew rate (in uv/us) + * @step_size: PMIC voltage step size (in uv) + * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV. + * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value. + */ +struct omap_volt_pmic_info { + int slew_rate; + int step_size; + u32 on_volt; + u32 onlp_volt; + u32 ret_volt; + u32 off_volt; + u16 volt_setup_time; + u8 vp_erroroffset; + u8 vp_vstepmin; + u8 vp_vstepmax; + u8 vp_vddmin; + u8 vp_vddmax; + u8 vp_timeout_us; + u8 i2c_slave_addr; + u8 pmic_reg; + unsigned long (*vsel_to_uv) (const u8 vsel); + u8 (*uv_to_vsel) (unsigned long uV); +}; + +unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm); +void omap_vp_enable(struct voltagedomain *voltdm); +void omap_vp_disable(struct voltagedomain *voltdm); +int omap_voltage_scale_vdd(struct voltagedomain *voltdm, + unsigned long target_volt); +void omap_voltage_reset(struct voltagedomain *voltdm); +void omap_voltage_get_volttable(struct voltagedomain *voltdm, + struct omap_volt_data **volt_data); +struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, + unsigned long volt); +unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm); +struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm); +#ifdef CONFIG_PM +int omap_voltage_register_pmic(struct voltagedomain *voltdm, + struct omap_volt_pmic_info *pmic_info); +void omap_change_voltscale_method(struct voltagedomain *voltdm, + int voltscale_method); +/* API to get the voltagedomain pointer */ +struct voltagedomain *omap_voltage_domain_lookup(char *name); + +int omap_voltage_late_init(void); +#else +static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm, + struct omap_volt_pmic_info *pmic_info) +{ + return -EINVAL; +} +static inline void omap_change_voltscale_method(struct voltagedomain *voltdm, + int voltscale_method) {} +static inline int omap_voltage_late_init(void) +{ + return -EINVAL; +} +static inline struct voltagedomain *omap_voltage_domain_lookup(char *name) +{ + return ERR_PTR(-EINVAL); +} +#endif + +#endif diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index fedd82971c9..82d79f011dc 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -34,7 +34,6 @@ #include #include #include -#include struct omap_device; diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h deleted file mode 100644 index 5bd204e55c3..00000000000 --- a/arch/arm/plat-omap/include/plat/voltage.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * OMAP Voltage Management Routines - * - * Author: Thara Gopinath - * - * Copyright (C) 2009 Texas Instruments, Inc. - * Thara Gopinath - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H -#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H - -#include - -#define VOLTSCALE_VPFORCEUPDATE 1 -#define VOLTSCALE_VCBYPASS 2 - -/* - * OMAP3 GENERIC setup times. Revisit to see if these needs to be - * passed from board or PMIC file - */ -#define OMAP3_CLKSETUP 0xff -#define OMAP3_VOLTOFFSET 0xff -#define OMAP3_VOLTSETUP2 0xff - -/* Voltage value defines */ -#define OMAP3430_VDD_MPU_OPP1_UV 975000 -#define OMAP3430_VDD_MPU_OPP2_UV 1075000 -#define OMAP3430_VDD_MPU_OPP3_UV 1200000 -#define OMAP3430_VDD_MPU_OPP4_UV 1270000 -#define OMAP3430_VDD_MPU_OPP5_UV 1350000 - -#define OMAP3430_VDD_CORE_OPP1_UV 975000 -#define OMAP3430_VDD_CORE_OPP2_UV 1050000 -#define OMAP3430_VDD_CORE_OPP3_UV 1150000 - -#define OMAP3630_VDD_MPU_OPP50_UV 1012500 -#define OMAP3630_VDD_MPU_OPP100_UV 1200000 -#define OMAP3630_VDD_MPU_OPP120_UV 1325000 -#define OMAP3630_VDD_MPU_OPP1G_UV 1375000 - -#define OMAP3630_VDD_CORE_OPP50_UV 1000000 -#define OMAP3630_VDD_CORE_OPP100_UV 1200000 - -#define OMAP4430_VDD_MPU_OPP50_UV 930000 -#define OMAP4430_VDD_MPU_OPP100_UV 1100000 -#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000 -#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000 - -#define OMAP4430_VDD_IVA_OPP50_UV 930000 -#define OMAP4430_VDD_IVA_OPP100_UV 1100000 -#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000 - -#define OMAP4430_VDD_CORE_OPP50_UV 930000 -#define OMAP4430_VDD_CORE_OPP100_UV 1100000 - -/** - * struct voltagedomain - omap voltage domain global structure. - * @name: Name of the voltage domain which can be used as a unique - * identifier. - */ -struct voltagedomain { - char *name; -}; - -/** - * struct omap_volt_data - Omap voltage specific data. - * @voltage_nominal: The possible voltage value in uV - * @sr_efuse_offs: The offset of the efuse register(from system - * control module base address) from where to read - * the n-target value for the smartreflex module. - * @sr_errminlimit: Error min limit value for smartreflex. This value - * differs at differnet opp and thus is linked - * with voltage. - * @vp_errorgain: Error gain value for the voltage processor. This - * field also differs according to the voltage/opp. - */ -struct omap_volt_data { - u32 volt_nominal; - u32 sr_efuse_offs; - u8 sr_errminlimit; - u8 vp_errgain; -}; - -/** - * struct omap_volt_pmic_info - PMIC specific data required by voltage driver. - * @slew_rate: PMIC slew rate (in uv/us) - * @step_size: PMIC voltage step size (in uv) - * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV. - * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value. - */ -struct omap_volt_pmic_info { - int slew_rate; - int step_size; - u32 on_volt; - u32 onlp_volt; - u32 ret_volt; - u32 off_volt; - u16 volt_setup_time; - u8 vp_erroroffset; - u8 vp_vstepmin; - u8 vp_vstepmax; - u8 vp_vddmin; - u8 vp_vddmax; - u8 vp_timeout_us; - u8 i2c_slave_addr; - u8 pmic_reg; - unsigned long (*vsel_to_uv) (const u8 vsel); - u8 (*uv_to_vsel) (unsigned long uV); -}; - -unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm); -void omap_vp_enable(struct voltagedomain *voltdm); -void omap_vp_disable(struct voltagedomain *voltdm); -int omap_voltage_scale_vdd(struct voltagedomain *voltdm, - unsigned long target_volt); -void omap_voltage_reset(struct voltagedomain *voltdm); -void omap_voltage_get_volttable(struct voltagedomain *voltdm, - struct omap_volt_data **volt_data); -struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, - unsigned long volt); -unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm); -struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm); -#ifdef CONFIG_PM -int omap_voltage_register_pmic(struct voltagedomain *voltdm, - struct omap_volt_pmic_info *pmic_info); -void omap_change_voltscale_method(struct voltagedomain *voltdm, - int voltscale_method); -/* API to get the voltagedomain pointer */ -struct voltagedomain *omap_voltage_domain_lookup(char *name); - -int omap_voltage_late_init(void); -#else -static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm, - struct omap_volt_pmic_info *pmic_info) -{ - return -EINVAL; -} -static inline void omap_change_voltscale_method(struct voltagedomain *voltdm, - int voltscale_method) {} -static inline int omap_voltage_late_init(void) -{ - return -EINVAL; -} -static inline struct voltagedomain *omap_voltage_domain_lookup(char *name) -{ - return ERR_PTR(-EINVAL); -} -#endif - -#endif -- cgit v1.2.3-70-g09d2 From 241d3a8dca239610d3d991bf58d4fe38c2d86fd5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 16 Feb 2011 15:38:39 -0700 Subject: OMAP2+: clock: remove the DPLL rate tolerance code Remove the DPLL rate tolerance code that is called during rate rounding. As far as I know, this code is never used, since it's been more important for callers of the DPLL round_rate()/set_rate() functions to obtain an exact rate than it is to save a relatively small amount of power. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_dpll.c | 91 +++++++++------------------------ arch/arm/mach-omap2/clock.h | 4 -- arch/arm/mach-omap2/clock2420_data.c | 1 - arch/arm/mach-omap2/clock2430_data.c | 1 - arch/arm/mach-omap2/clock3xxx_data.c | 6 --- arch/arm/plat-omap/include/plat/clock.h | 7 +-- 6 files changed, 24 insertions(+), 86 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 337392c3f54..17735e7f47b 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk) if (!dd) return; - /* Return bypass rate if DPLL is bypassed */ v = __raw_readl(dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - /* Reparent in case the dpll is in bypass */ + /* Reparent the struct clk in case the dpll is in bypass */ if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) @@ -259,51 +258,23 @@ u32 omap2_get_dpll_rate(struct clk *clk) /* DPLL rate rounding code */ -/** - * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding - * @clk: struct clk * of the DPLL - * @tolerance: maximum rate error tolerance - * - * Set the maximum DPLL rate error tolerance for the rate rounding - * algorithm. The rate tolerance is an attempt to balance DPLL power - * saving (the least divider value "n") vs. rate fidelity (the least - * difference between the desired DPLL target rate and the rounded - * rate out of the algorithm). So, increasing the tolerance is likely - * to decrease DPLL power consumption and increase DPLL rate error. - * Returns -EINVAL if provided a null clock ptr or a clk that is not a - * DPLL; or 0 upon success. - */ -int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) -{ - if (!clk || !clk->dpll_data) - return -EINVAL; - - clk->dpll_data->rate_tolerance = tolerance; - - return 0; -} - /** * omap2_dpll_round_rate - round a target rate for an OMAP DPLL * @clk: struct clk * for a DPLL * @target_rate: desired DPLL clock rate * - * Given a DPLL, a desired target rate, and a rate tolerance, round - * the target rate to a possible, programmable rate for this DPLL. - * Rate tolerance is assumed to be set by the caller before this - * function is called. Attempts to select the minimum possible n - * within the tolerance to reduce power consumption. Stores the - * computed (m, n) in the DPLL's dpll_data structure so set_rate() - * will not need to call this (expensive) function again. Returns ~0 - * if the target rate cannot be rounded, either because the rate is - * too low or because the rate tolerance is set too tightly; or the - * rounded rate upon success. + * Given a DPLL and a desired target rate, round the target rate to a + * possible, programmable rate for this DPLL. Attempts to select the + * minimum possible n. Stores the computed (m, n) in the DPLL's + * dpll_data structure so set_rate() will not need to call this + * (expensive) function again. Returns ~0 if the target rate cannot + * be rounded, or the rounded rate upon success. */ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) { - int m, n, r, e, scaled_max_m; - unsigned long scaled_rt_rp, new_rate; - int min_e = -1, min_e_m = -1, min_e_n = -1; + int m, n, r, scaled_max_m; + unsigned long scaled_rt_rp; + unsigned long new_rate = 0; struct dpll_data *dd; if (!clk || !clk->dpll_data) @@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; - pr_debug("clock: starting DPLL round_rate for clock %s, target rate " - "%ld\n", clk->name, target_rate); + pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", + clk->name, target_rate); scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; @@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) if (r == DPLL_MULT_UNDERFLOW) continue; - e = target_rate - new_rate; - pr_debug("clock: n = %d: m = %d: rate error is %d " - "(new_rate = %ld)\n", n, m, e, new_rate); - - if (min_e == -1 || - min_e >= (int)(abs(e) - dd->rate_tolerance)) { - min_e = e; - min_e_m = m; - min_e_n = n; - - pr_debug("clock: found new least error %d\n", min_e); + pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", + clk->name, m, n, new_rate); - /* We found good settings -- bail out now */ - if (min_e <= dd->rate_tolerance) - break; + if (target_rate == new_rate) { + dd->last_rounded_m = m; + dd->last_rounded_n = n; + dd->last_rounded_rate = target_rate; + break; } } - if (min_e < 0) { - pr_debug("clock: error: target rate or tolerance too low\n"); + if (target_rate != new_rate) { + pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, + target_rate); return ~0; } - dd->last_rounded_m = min_e_m; - dd->last_rounded_n = min_e_n; - dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, - min_e_m, min_e_n); - - pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", - min_e, min_e_m, min_e_n); - pr_debug("clock: final rate: %ld (target rate: %ld)\n", - dd->last_rounded_rate, target_rate); - - return dd->last_rounded_rate; + return target_rate; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 70f8b073e69..62cfd6cc746 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -18,9 +18,6 @@ #include -/* The maximum error between a target DPLL rate and the rounded rate in Hz */ -#define DEFAULT_DPLL_RATE_TOLERANCE 50000 - /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 #define CORE_CLK_SRC_DPLL 0x1 @@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); unsigned long omap3_dpll_recalc(struct clk *clk); unsigned long omap3_clkoutx2_recalc(struct clk *clk); diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 6e9d20dc864..22eeafc89b9 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = { .max_multiplier = 1023, .min_divider = 1, .max_divider = 16, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; /* diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 3378dbf8bac..df4cac5fef0 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = { .max_multiplier = 1023, .min_divider = 1, .max_divider = 16, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; /* diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 305b5f75c44..3dbeb3a5813 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -291,7 +291,6 @@ static struct dpll_data dpll1_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll1_ck = { @@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll2_ck = { @@ -424,7 +422,6 @@ static struct dpll_data dpll3_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll3_ck = { @@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct dpll_data dpll4_dd_3630 __initdata = { @@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = { .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE, .flags = DPLL_J_TYPE }; @@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = { .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, - .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; static struct clk dpll5_ck = { diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index dcd7bb81420..006e599c661 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -109,7 +109,6 @@ struct clksel { * @clk_ref: struct clk pointer to the clock's reference clock input * @control_reg: register containing the DPLL mode bitfield * @enable_mask: mask of the DPLL mode bitfield in @control_reg - * @rate_tolerance: maximum variance allowed from target rate (in Hz) * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() * @max_multiplier: maximum valid non-bypass multiplier value (actual) @@ -135,12 +134,9 @@ struct clksel { * XXX Some DPLLs have multiple bypass inputs, so it's not technically * correct to only have one @clk_bypass pointer. * - * XXX @rate_tolerance should probably be deprecated - currently there - * don't seem to be any usecases for DPLL rounding that is not exact. - * * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, * @last_rounded_n) should be separated from the runtime-fixed fields - * and placed into a differenct structure, so that the runtime-fixed data + * and placed into a different structure, so that the runtime-fixed data * can be placed into read-only space. */ struct dpll_data { @@ -151,7 +147,6 @@ struct dpll_data { struct clk *clk_ref; void __iomem *control_reg; u32 enable_mask; - unsigned int rate_tolerance; unsigned long last_rounded_rate; u16 last_rounded_m; u16 max_multiplier; -- cgit v1.2.3-70-g09d2 From 4bb194dc9471c79caa1952ecdb31148074ac1abf Mon Sep 17 00:00:00 2001 From: sricharan Date: Tue, 8 Feb 2011 22:13:37 +0530 Subject: OMAP3: hwmod_data: Add address space and irq in L3 hwmod. Add the address spaces, irqs of the l3 interconnect to the hwmod data. The hwmod changes are aligned with Benoit Cousson. Signed-off-by: sricharan Signed-off-by: Santosh Shilimkar Acked-by: Benoit Cousson --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 22 ++++++++++++++++++++-- arch/arm/plat-omap/include/plat/irqs.h | 2 ++ 2 files changed, 22 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index e2792cf9c54..2539e469c1e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -100,10 +100,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L3 taret configuration and error log registers */ +static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { + { .irq = INT_34XX_L3_DBG_IRQ }, + { .irq = INT_34XX_L3_APP_IRQ }, +}; + +static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { + { + .pa_start = 0x68000000, + .pa_end = 0x6800ffff, + .flags = ADDR_TYPE_RT, + }, +}; + /* MPU -> L3 interface */ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { - .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_main_hwmod, + .master = &omap3xxx_mpu_hwmod, + .slave = &omap3xxx_l3_main_hwmod, + .addr = omap3xxx_l3_main_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs), .user = OCP_USER_MPU, }; @@ -135,6 +151,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { static struct omap_hwmod omap3xxx_l3_main_hwmod = { .name = "l3_main", .class = &l3_hwmod_class, + .mpu_irqs = omap3xxx_l3_main_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs), .masters = omap3xxx_l3_main_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), .slaves = omap3xxx_l3_main_slaves, diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 1b911681e91..d7792837046 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -315,6 +315,8 @@ #define INT_34XX_SSM_ABORT_IRQ 6 #define INT_34XX_SYS_NIRQ 7 #define INT_34XX_D2D_FW_IRQ 8 +#define INT_34XX_L3_DBG_IRQ 9 +#define INT_34XX_L3_APP_IRQ 10 #define INT_34XX_PRCM_MPU_IRQ 11 #define INT_34XX_MCBSP1_IRQ 16 #define INT_34XX_MCBSP2_IRQ 17 -- cgit v1.2.3-70-g09d2 From df93bd76b61639fe9093ccbfc5d1a4bfb744ec47 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 21 Jan 2011 14:30:15 -0800 Subject: OMAP2+: remove unused UART base addresses from omap_globals Now that omap_hwmod + omap_device is used for OMAP UART device and driver code, we no longer need the UART physical addresses in omap_globals. Note that the #defines for the base addresses are still left in since they are used by DEBUG_LL and uncompress code. Build tested for OMAP1 (omap1_defconfig) and OMAP2+ (omap2plus_defconfig) Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/common.c | 14 -------------- arch/arm/plat-omap/include/plat/common.h | 4 ---- 2 files changed, 18 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 778929f7e92..994f0f00c70 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -50,9 +50,6 @@ static struct omap_globals omap242x_globals = { .ctrl = OMAP242X_CTRL_BASE, .prm = OMAP2420_PRM_BASE, .cm = OMAP2420_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, }; void __init omap2_set_globals_242x(void) @@ -71,9 +68,6 @@ static struct omap_globals omap243x_globals = { .ctrl = OMAP243X_CTRL_BASE, .prm = OMAP2430_PRM_BASE, .cm = OMAP2430_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, }; void __init omap2_set_globals_243x(void) @@ -92,10 +86,6 @@ static struct omap_globals omap3_globals = { .ctrl = OMAP343X_CTRL_BASE, .prm = OMAP3430_PRM_BASE, .cm = OMAP3430_CM_BASE, - .uart1_phys = OMAP3_UART1_BASE, - .uart2_phys = OMAP3_UART2_BASE, - .uart3_phys = OMAP3_UART3_BASE, - .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ }; void __init omap2_set_globals_3xxx(void) @@ -119,10 +109,6 @@ static struct omap_globals omap4_globals = { .prm = OMAP4430_PRM_BASE, .cm = OMAP4430_CM_BASE, .cm2 = OMAP4430_CM2_BASE, - .uart1_phys = OMAP4_UART1_BASE, - .uart2_phys = OMAP4_UART2_BASE, - .uart3_phys = OMAP4_UART3_BASE, - .uart4_phys = OMAP4_UART4_BASE, }; void __init omap2_set_globals_443x(void) diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 29b2afb4288..1b8095bb8d0 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -56,10 +56,6 @@ struct omap_globals { unsigned long prm; /* Power and Reset Management */ unsigned long cm; /* Clock Management */ unsigned long cm2; - unsigned long uart1_phys; - unsigned long uart2_phys; - unsigned long uart3_phys; - unsigned long uart4_phys; }; void omap2_set_globals_242x(void); -- cgit v1.2.3-70-g09d2 From 4d2274c543e78a267989da5f9b12e223cd87839f Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 3 Mar 2011 15:22:42 -0700 Subject: OMAP2+: hwmod: fix a documentation bug with HWMOD_NO_OCP_AUTOIDLE The documented name of the HWMOD_NO_OCP_AUTOIDLE flag was incorrect; fix it. Signed-off-by: Paul Walmsley --- arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 1eee85a8abb..5924ecdfb95 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -372,7 +372,7 @@ struct omap_hwmod_omap4_prcm { * SDRAM controller, etc. XXX probably belongs outside the main hwmod file * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM * controller, etc. XXX probably belongs outside the main hwmod file - * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) + * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) * when module is enabled, rather than the default, which is to * enable autoidle * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup -- cgit v1.2.3-70-g09d2 From cc1226e7635011c7dd1e786770ed51ee751800f2 Mon Sep 17 00:00:00 2001 From: omar ramirez Date: Fri, 4 Mar 2011 13:32:44 -0700 Subject: OMAP2+: hwmod: use status bit info for reset line On OMAP2 and OMAP3 the reset ctrl shift doesn't match the status bit, as it does on OMAP4, when handling the reset lines. This patch adds a new member in the reset info structure, so now it can be added as part of hwmod data, and checked accordingly for OMAP2 or 3; otherwise, there could be cases when the shift masks doesn't match both of the registers, and a successful reset might throw an error message or vice versa. Signed-off-by: Omar Ramirez Luna [paul@pwsan.com: added a warning if st_shift used on OMAP4; renamed 'r' variable; improved some documentation] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 75 ++++++++++++++++------------ arch/arm/mach-omap2/prm2xxx_3xxx.c | 18 ++++--- arch/arm/mach-omap2/prm2xxx_3xxx.h | 5 +- arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 + 4 files changed, 58 insertions(+), 42 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2146d9aa507..005264779f8 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -972,25 +972,29 @@ static int _wait_target_ready(struct omap_hwmod *oh) } /** - * _lookup_hardreset - return the register bit shift for this hwmod/reset line + * _lookup_hardreset - fill register bit info for this hwmod/reset line * @oh: struct omap_hwmod * * @name: name of the reset line in the context of this hwmod + * @ohri: struct omap_hwmod_rst_info * that this function will fill in * * Return the bit position of the reset line that match the * input name. Return -ENOENT if not found. */ -static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) +static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, + struct omap_hwmod_rst_info *ohri) { int i; for (i = 0; i < oh->rst_lines_cnt; i++) { const char *rst_line = oh->rst_lines[i].name; if (!strcmp(rst_line, name)) { - u8 shift = oh->rst_lines[i].rst_shift; - pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", - oh->name, rst_line, shift); + ohri->rst_shift = oh->rst_lines[i].rst_shift; + ohri->st_shift = oh->rst_lines[i].st_shift; + pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", + oh->name, __func__, rst_line, ohri->rst_shift, + ohri->st_shift); - return shift; + return 0; } } @@ -1009,21 +1013,22 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) */ static int _assert_hardreset(struct omap_hwmod *oh, const char *name) { - u8 shift; + struct omap_hwmod_rst_info ohri; + u8 ret; if (!oh) return -EINVAL; - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; + ret = _lookup_hardreset(oh, name, &ohri); + if (IS_ERR_VALUE(ret)) + return ret; if (cpu_is_omap24xx() || cpu_is_omap34xx()) return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, - shift); + ohri.rst_shift); else if (cpu_is_omap44xx()) return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, - shift); + ohri.rst_shift); else return -EINVAL; } @@ -1040,29 +1045,34 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name) */ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) { - u8 shift; - int r; + struct omap_hwmod_rst_info ohri; + int ret; if (!oh) return -EINVAL; - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; + ret = _lookup_hardreset(oh, name, &ohri); + if (IS_ERR_VALUE(ret)) + return ret; - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, - shift); - else if (cpu_is_omap44xx()) - r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, - shift); - else + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, + ohri.rst_shift, + ohri.st_shift); + } else if (cpu_is_omap44xx()) { + if (ohri.st_shift) + pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", + oh->name, name); + ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, + ohri.rst_shift); + } else { return -EINVAL; + } - if (r == -EBUSY) + if (ret == -EBUSY) pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); - return r; + return ret; } /** @@ -1075,21 +1085,22 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) */ static int _read_hardreset(struct omap_hwmod *oh, const char *name) { - u8 shift; + struct omap_hwmod_rst_info ohri; + u8 ret; if (!oh) return -EINVAL; - shift = _lookup_hardreset(oh, name); - if (IS_ERR_VALUE(shift)) - return shift; + ret = _lookup_hardreset(oh, name, &ohri); + if (IS_ERR_VALUE(ret)) + return ret; if (cpu_is_omap24xx() || cpu_is_omap34xx()) { return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, - shift); + ohri.st_shift); } else if (cpu_is_omap44xx()) { return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, - shift); + ohri.rst_shift); } else { return -EINVAL; } diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index ec0362574b5..051213fbc34 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -118,7 +118,8 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) /** * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait * @prm_mod: PRM submodule base (e.g. CORE_MOD) - * @shift: register bit shift corresponding to the reset line to deassert + * @rst_shift: register bit shift corresponding to the reset line to deassert + * @st_shift: register bit shift for the status of the deasserted submodule * * Some IPs like dsp or iva contain processors that require an HW * reset line to be asserted / deasserted in order to fully enable the @@ -129,27 +130,28 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) * -EINVAL upon an argument error, -EEXIST if the submodule was already out * of reset, or -EBUSY if the submodule did not exit reset promptly. */ -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) +int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) { - u32 mask; + u32 rst, st; int c; if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) return -EINVAL; - mask = 1 << shift; + rst = 1 << rst_shift; + st = 1 << st_shift; /* Check the current status to avoid de-asserting the line twice */ - if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) + if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0) return -EEXIST; /* Clear the reset status by writing 1 to the status bit */ - omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); + omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST); /* de-assert the reset control line */ - omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); + omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL); /* wait the status to be set */ omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, - mask), + st), MAX_MODULE_HARDRESET_WAIT, c); return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index 49654c8d18f..a1fc62a39db 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -282,7 +282,8 @@ static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) "not suppose to be used on omap4\n"); return 0; } -static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) +static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, + u8 st_shift) { WARN(1, "prm: omap2xxx/omap3xxx specific function and " "not suppose to be used on omap4\n"); @@ -300,7 +301,7 @@ extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); /* These omap2_ PRM functions apply to both OMAP2 and 3 */ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); -extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); +extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); #endif /* CONFIG_ARCH_OMAP4 */ #endif diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 5924ecdfb95..78f1cc88ff0 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -124,6 +124,7 @@ struct omap_hwmod_dma_info { * struct omap_hwmod_rst_info - IPs reset lines use by hwmod * @name: name of the reset line (module local name) * @rst_shift: Offset of the reset bit + * @st_shift: Offset of the reset status bit (OMAP2/3 only) * * @name should be something short, e.g., "cpu0" or "rst". It is defined * locally to the hwmod. @@ -131,6 +132,7 @@ struct omap_hwmod_dma_info { struct omap_hwmod_rst_info { const char *name; u8 rst_shift; + u8 st_shift; }; /** -- cgit v1.2.3-70-g09d2 From 43b01643355672a266b95c4719f47cd1abac4680 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 10 Mar 2011 03:50:07 -0700 Subject: OMAP2+: hwmod: allow board files to prevent devices from being reset upon init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some boards can't tolerate IP blocks being reset when they are initialized. Michael Büsch cites a case with the Nokia N810: http://www.spinics.net/lists/linux-omap/msg47277.html To allow such boards to continue working normally, allow board file maintainers to mark IP blocks to prevent them from being reset upon init. This is done via a hwmod function, omap_hwmod_no_setup_reset(). Signed-off-by: Paul Walmsley Cc: Michael Buesch --- arch/arm/mach-omap2/omap_hwmod.c | 26 ++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 ++ 2 files changed, 28 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e282e35769f..816aeb97ba2 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2218,3 +2218,29 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) return ret; } + +/** + * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup + * @oh: struct omap_hwmod * + * + * Prevent the hwmod @oh from being reset during the setup process. + * Intended for use by board-*.c files on boards with devices that + * cannot tolerate being reset. Must be called before the hwmod has + * been set up. Returns 0 upon success or negative error code upon + * failure. + */ +int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + if (oh->_state != _HWMOD_STATE_REGISTERED) { + pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", + oh->name); + return -EINVAL; + } + + oh->flags |= HWMOD_INIT_NO_RESET; + + return 0; +} diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 1eee85a8abb..bba234337d0 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -589,6 +589,8 @@ int omap_hwmod_for_each_by_class(const char *classname, int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); +int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); + /* * Chip variant-specific hwmod init routines - XXX should be converted * to use initcalls once the initial boot ordering is straightened out -- cgit v1.2.3-70-g09d2 From 9599217a06da5f5a95794ca9192c14317d441187 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 10 Mar 2011 03:50:08 -0700 Subject: OMAP2+: hwmod: add API to handle autoidle mode Create a new API that forms a wrapper to _set_module_autoidle() to modify the AUTOIDLE bit. This API is intended to be used by drivers that requires direct manipulation of the AUTOIDLE bits in SYSCONFIG register. McBSP driver requires autoidle bit to be enabled/disabled while using sidetone feature. Signed-off-by: Kishon Vijay Abraham I Cc: Paul Walmsley Cc: Benoit Cousson [paul@pwsan.com: restrict the hwmod states that the autoidle bit can be changed in; changed function name; dropped "int" from "unsigned int long"] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 36 ++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 + 2 files changed, 37 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 816aeb97ba2..a68a2cf1be3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1287,6 +1287,42 @@ static int _idle(struct omap_hwmod *oh) return 0; } +/** + * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit + * @oh: struct omap_hwmod * + * @autoidle: desired AUTOIDLE bitfield value (0 or 1) + * + * Sets the IP block's OCP autoidle bit in hardware, and updates our + * local copy. Intended to be used by drivers that require + * direct manipulation of the AUTOIDLE bits. + * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes + * along the return value from _set_module_autoidle(). + * + * Any users of this function should be scrutinized carefully. + */ +int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) +{ + u32 v; + int retval = 0; + unsigned long flags; + + if (!oh || oh->_state != _HWMOD_STATE_ENABLED) + return -EINVAL; + + spin_lock_irqsave(&oh->_lock, flags); + + v = oh->_sysc_cache; + + retval = _set_module_autoidle(oh, autoidle, &v); + + if (!retval) + _write_sysconfig(v, oh); + + spin_unlock_irqrestore(&oh->_lock, flags); + + return retval; +} + /** * _shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index bba234337d0..98f7f618a91 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -555,6 +555,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); +int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle); int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); -- cgit v1.2.3-70-g09d2 From 029268e4c124a38b11ae965849ea2dfef724a568 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 11 Mar 2011 11:32:25 -0800 Subject: omap2+: Add separate list for dynamic pads to mux This avoids going through the list unnecessarily when idling devices for runtime PM. Based on an earlier patch by sricharan . Signed-off-by: sricharan Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mux.c | 88 ++++++++++++++++++++++++---- arch/arm/mach-omap2/mux.h | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 6 +- arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 + 4 files changed, 83 insertions(+), 16 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 6c84659cf84..8717370c91b 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -258,7 +258,7 @@ struct omap_hwmod_mux_info * __init omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) { struct omap_hwmod_mux_info *hmux; - int i; + int i, nr_pads_dynamic = 0; if (!bpads || nr_pads < 1) return NULL; @@ -302,9 +302,40 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) pad->enable = bpad->enable; pad->idle = bpad->idle; pad->off = bpad->off; + + if (pad->flags & OMAP_DEVICE_PAD_REMUX) + nr_pads_dynamic++; + pr_debug("%s: Initialized %s\n", __func__, pad->name); } + if (!nr_pads_dynamic) + return hmux; + + /* + * Add pads that need dynamic muxing into a separate list + */ + + hmux->nr_pads_dynamic = nr_pads_dynamic; + hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) * + nr_pads_dynamic, GFP_KERNEL); + if (!hmux->pads_dynamic) { + pr_err("%s: Could not allocate dynamic pads\n", __func__); + return hmux; + } + + nr_pads_dynamic = 0; + for (i = 0; i < hmux->nr_pads; i++) { + struct omap_device_pad *pad = &hmux->pads[i]; + + if (pad->flags & OMAP_DEVICE_PAD_REMUX) { + pr_debug("%s: pad %s tagged dynamic\n", + __func__, pad->name); + hmux->pads_dynamic[nr_pads_dynamic] = pad; + nr_pads_dynamic++; + } + } + return hmux; err3: @@ -322,6 +353,44 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) { int i; + /* Runtime idling of dynamic pads */ + if (state == _HWMOD_STATE_IDLE && hmux->enabled) { + for (i = 0; i < hmux->nr_pads_dynamic; i++) { + struct omap_device_pad *pad = hmux->pads_dynamic[i]; + int val = -EINVAL; + + pad->flags |= OMAP_DEVICE_PAD_IDLE; + val = pad->idle; + omap_mux_write(pad->partition, val, + pad->mux->reg_offset); + } + + return; + } + + /* Runtime enabling of dynamic pads */ + if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic) { + int idled = 0; + + for (i = 0; i < hmux->nr_pads_dynamic; i++) { + struct omap_device_pad *pad = hmux->pads_dynamic[i]; + int val = -EINVAL; + + if (!(pad->flags & OMAP_DEVICE_PAD_IDLE)) + continue; + + pad->flags &= ~OMAP_DEVICE_PAD_IDLE; + val = pad->enable; + omap_mux_write(pad->partition, val, + pad->mux->reg_offset); + idled++; + } + + if (idled) + return; + } + + /* Enabling or disabling of all pads */ for (i = 0; i < hmux->nr_pads; i++) { struct omap_device_pad *pad = &hmux->pads[i]; int flags, val = -EINVAL; @@ -330,21 +399,10 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) switch (state) { case _HWMOD_STATE_ENABLED: - if (flags & OMAP_DEVICE_PAD_ENABLED) - break; - flags |= OMAP_DEVICE_PAD_ENABLED; val = pad->enable; pr_debug("%s: Enabling %s %x\n", __func__, pad->name, val); break; - case _HWMOD_STATE_IDLE: - if (!(flags & OMAP_DEVICE_PAD_REMUX)) - break; - flags &= ~OMAP_DEVICE_PAD_ENABLED; - val = pad->idle; - pr_debug("%s: Idling %s %x\n", __func__, - pad->name, val); - break; case _HWMOD_STATE_DISABLED: default: /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */ @@ -352,7 +410,6 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) val = pad->off; else val = OMAP_MUX_MODE7; - flags &= ~OMAP_DEVICE_PAD_ENABLED; pr_debug("%s: Disabling %s %x\n", __func__, pad->name, val); }; @@ -363,6 +420,11 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) pad->flags = flags; } } + + if (state == _HWMOD_STATE_ENABLED) + hmux->enabled = true; + else + hmux->enabled = false; } #ifdef CONFIG_DEBUG_FS diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index a4ab17a737a..1d5bf4298c6 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -159,7 +159,7 @@ struct omap_board_mux { u16 value; }; -#define OMAP_DEVICE_PAD_ENABLED BIT(7) /* Not needed for board-*.c */ +#define OMAP_DEVICE_PAD_IDLE BIT(7) /* Not needed for board-*.c */ #define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad, needs enable, idle and off values */ diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 4c8329e4e6e..e03429453ce 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1244,7 +1244,9 @@ static int _enable(struct omap_hwmod *oh) _deassert_hardreset(oh, oh->rst_lines[0].name); /* Mux pins for device runtime if populated */ - if (oh->mux) + if (oh->mux && (!oh->mux->enabled || + ((oh->_state == _HWMOD_STATE_IDLE) && + oh->mux->pads_dynamic))) omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); _add_initiator_dep(oh, mpu_oh); @@ -1293,7 +1295,7 @@ static int _idle(struct omap_hwmod *oh) _disable_clocks(oh); /* Mux pins for device idle if populated */ - if (oh->mux) + if (oh->mux && oh->mux->pads_dynamic) omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); oh->_state = _HWMOD_STATE_IDLE; diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 23c77cd4abe..1adea9c6298 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -90,6 +90,9 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; struct omap_hwmod_mux_info { int nr_pads; struct omap_device_pad *pads; + int nr_pads_dynamic; + struct omap_device_pad **pads_dynamic; + bool enabled; }; /** -- cgit v1.2.3-70-g09d2 From d038aee24dcd5a2a0d8547f5396f67ae9698ac8e Mon Sep 17 00:00:00 2001 From: David Cohen Date: Wed, 9 Mar 2011 09:17:33 +0000 Subject: omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag Currently IOVMM driver sets IOVMF_DA_FIXED/IOVMF_DA_ANON flags according to input 'da' address when mapping memory: da == 0: IOVMF_DA_ANON da != 0: IOVMF_DA_FIXED It prevents IOMMU to map first page with fixed 'da'. To avoid such issue, IOVMM will not automatically set IOVMF_DA_FIXED. It should now come from the user throught 'flags' parameter when mapping memory. As IOVMF_DA_ANON and IOVMF_DA_FIXED are mutually exclusive, IOVMF_DA_ANON can be removed. The driver will now check internally if IOVMF_DA_FIXED is set or not. Signed-off-by: David Cohen Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/iovmm.h | 2 -- arch/arm/plat-omap/iovmm.c | 14 +++++--------- 2 files changed, 5 insertions(+), 11 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h index bdc7ce5d7a4..32a2f6c4d39 100644 --- a/arch/arm/plat-omap/include/plat/iovmm.h +++ b/arch/arm/plat-omap/include/plat/iovmm.h @@ -71,8 +71,6 @@ struct iovm_struct { #define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT)) #define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) -#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT)) -#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT)) extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c index ea7eab98a73..51ef43e8def 100644 --- a/arch/arm/plat-omap/iovmm.c +++ b/arch/arm/plat-omap/iovmm.c @@ -279,7 +279,7 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, start = da; alignment = PAGE_SIZE; - if (flags & IOVMF_DA_ANON) { + if (~flags & IOVMF_DA_FIXED) { /* Don't map address 0 */ start = obj->da_start ? obj->da_start : alignment; @@ -304,7 +304,7 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, if (tmp->da_start > start && (tmp->da_start - start) >= bytes) goto found; - if (tmp->da_end >= start && flags & IOVMF_DA_ANON) + if (tmp->da_end >= start && ~flags & IOVMF_DA_FIXED) start = roundup(tmp->da_end + 1, alignment); prev_end = tmp->da_end; @@ -651,7 +651,6 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt, flags &= IOVMF_HW_MASK; flags |= IOVMF_DISCONT; flags |= IOVMF_MMIO; - flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); da = __iommu_vmap(obj, da, sgt, va, bytes, flags); if (IS_ERR_VALUE(da)) @@ -691,7 +690,7 @@ EXPORT_SYMBOL_GPL(iommu_vunmap); * @flags: iovma and page property * * Allocate @bytes linearly and creates 1-n-1 mapping and returns - * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. + * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set. */ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) { @@ -710,7 +709,6 @@ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) flags &= IOVMF_HW_MASK; flags |= IOVMF_DISCONT; flags |= IOVMF_ALLOC; - flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); sgt = sgtable_alloc(bytes, flags, da, 0); if (IS_ERR(sgt)) { @@ -781,7 +779,7 @@ static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va, * @flags: iovma and page property * * Creates 1-1-1 mapping and returns @da again, which can be - * adjusted if 'IOVMF_DA_ANON' is set. + * adjusted if 'IOVMF_DA_FIXED' is not set. */ u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, u32 flags) @@ -800,7 +798,6 @@ u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, flags &= IOVMF_HW_MASK; flags |= IOVMF_LINEAR; flags |= IOVMF_MMIO; - flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); da = __iommu_kmap(obj, da, pa, va, bytes, flags); if (IS_ERR_VALUE(da)) @@ -839,7 +836,7 @@ EXPORT_SYMBOL_GPL(iommu_kunmap); * @flags: iovma and page property * * Allocate @bytes linearly and creates 1-1-1 mapping and returns - * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. + * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set. */ u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) { @@ -859,7 +856,6 @@ u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) flags &= IOVMF_HW_MASK; flags |= IOVMF_LINEAR; flags |= IOVMF_ALLOC; - flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); da = __iommu_kmap(obj, da, pa, va, bytes, flags); if (IS_ERR_VALUE(da)) -- cgit v1.2.3-70-g09d2