From fa60be6e3f9362bd841e26b9366f0db7b761a042 Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Wed, 25 Apr 2012 11:14:31 +0530 Subject: ARM: OMAP2+: Voltage: Move the omap_volt_data structure to plat Move the omap_volt_data structure from mach-omap2/ directory to arch/arm/plat-omap/include/plat/ so that it is accessible from both mach-omap2 and drivers directories. Signed-off-by: J Keerthy Reviewed-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/include/plat/voltage.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h index 0a6a482ec01..5be4d5def42 100644 --- a/arch/arm/plat-omap/include/plat/voltage.h +++ b/arch/arm/plat-omap/include/plat/voltage.h @@ -11,10 +11,29 @@ #ifndef __ARCH_ARM_OMAP_VOLTAGE_H #define __ARCH_ARM_OMAP_VOLTAGE_H +/** + * struct omap_volt_data - Omap voltage specific data. + * @voltage_nominal: The possible voltage value in uV + * @sr_efuse_offs: The offset of the efuse register(from system + * control module base address) from where to read + * the n-target value for the smartreflex module. + * @sr_errminlimit: Error min limit value for smartreflex. This value + * differs at differnet opp and thus is linked + * with voltage. + * @vp_errorgain: Error gain value for the voltage processor. This + * field also differs according to the voltage/opp. + */ +struct omap_volt_data { + u32 volt_nominal; + u32 sr_efuse_offs; + u8 sr_errminlimit; + u8 vp_errgain; +}; struct voltagedomain; struct voltagedomain *voltdm_lookup(const char *name); int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt); unsigned long voltdm_get_voltage(struct voltagedomain *voltdm); - +struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, + unsigned long volt); #endif -- cgit v1.2.3-70-g09d2 From b924b2047045844644e04b3c6e8308b2114afe7e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 4 Jun 2012 00:56:15 -0700 Subject: ARM: OMAP: Make FS USB omap1 only As the FS USB code is not being actively used for omap2+ there's no point keeping it around for omap2+. Let's make the FS USB platform init code omap1 only so we can remove the last user of omap_read/write for omap2+, and simplify things for further USB, DMA, and device tree related work. While at it, also group the mach includes for the related drivers. Cc: linux-usb@vger.kernel.org Cc: Kyungmin Park Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-ams-delta.c | 2 +- arch/arm/mach-omap1/board-generic.c | 4 +- arch/arm/mach-omap1/board-h2.c | 2 +- arch/arm/mach-omap1/board-h3.c | 2 +- arch/arm/mach-omap1/board-htcherald.c | 2 +- arch/arm/mach-omap1/board-innovator.c | 2 +- arch/arm/mach-omap1/board-nokia770.c | 2 +- arch/arm/mach-omap1/board-osk.c | 2 +- arch/arm/mach-omap1/board-palmte.c | 2 +- arch/arm/mach-omap1/board-palmtt.c | 2 +- arch/arm/mach-omap1/board-palmz71.c | 2 +- arch/arm/mach-omap1/board-sx1.c | 2 +- arch/arm/mach-omap1/board-voiceblue.c | 3 +- arch/arm/mach-omap1/clock_data.c | 3 +- arch/arm/mach-omap1/include/mach/usb.h | 165 +++++++++++++++++++++++++++ arch/arm/mach-omap1/usb.c | 116 ++++++++++++++++++- arch/arm/plat-omap/Makefile | 2 +- arch/arm/plat-omap/include/plat/board.h | 38 ------- arch/arm/plat-omap/include/plat/usb.h | 196 +------------------------------- arch/arm/plat-omap/usb.c | 145 ----------------------- drivers/usb/gadget/Kconfig | 2 +- drivers/usb/gadget/omap_udc.c | 3 +- drivers/usb/host/Kconfig | 2 +- drivers/usb/host/ohci-omap.c | 7 +- drivers/usb/otg/isp1301_omap.c | 2 +- 25 files changed, 310 insertions(+), 400 deletions(-) create mode 100644 arch/arm/mach-omap1/include/mach/usb.h delete mode 100644 arch/arm/plat-omap/usb.c (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index f2f8a584701..c53469802c0 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -37,12 +37,12 @@ #include #include #include -#include #include #include #include #include +#include #include "iomap.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index e75e2d55a2d..6ec385e2b98 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -23,8 +23,10 @@ #include #include -#include #include + +#include + #include "common.h" /* assume no Mini-AB port */ diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index a28e989a63f..44a4ab195fb 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -40,11 +40,11 @@ #include #include #include -#include #include #include #include +#include #include "common.h" #include "board-h2.h" diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 108a8640fc6..86cb5a04a40 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -40,13 +40,13 @@ #include #include -#include #include #include #include #include #include +#include #include "common.h" #include "board-h3.h" diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 118a9d4a4c5..b3f6e943e66 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -44,10 +44,10 @@ #include #include #include -#include #include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 7970223a559..f21c2966daa 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -35,11 +35,11 @@ #include #include #include -#include #include #include #include +#include #include "iomap.h" #include "common.h" diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 7212ae97f44..4007a372481 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -26,7 +26,6 @@ #include #include -#include #include #include #include @@ -34,6 +33,7 @@ #include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index da8d872d3d1..8784705edb6 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -45,11 +45,11 @@ #include #include -#include #include #include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 949b62a7369..26bcb9defcd 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -35,7 +35,6 @@ #include #include -#include #include #include #include @@ -43,6 +42,7 @@ #include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 7f1e1cf2bf4..4d099446dfa 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -43,6 +42,7 @@ #include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 3c71c6bace2..cc71a26723e 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -37,7 +37,6 @@ #include #include -#include #include #include #include @@ -45,6 +44,7 @@ #include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 3b7b82b1368..8c665bd16ac 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -37,13 +37,13 @@ #include #include #include -#include #include #include #include #include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index afd67f0ec49..3497769eb35 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -35,9 +35,10 @@ #include #include #include -#include +#include #include +#include #include "common.h" diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index c6ce93f71d0..c007d80dfb6 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -25,10 +25,11 @@ #include #include #include +#include #include /* for omap_sram_reprogram_clock() */ -#include /* for OTG_BASE */ #include +#include /* for OTG_BASE */ #include "iomap.h" #include "clock.h" diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h new file mode 100644 index 00000000000..753cd5ce694 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/usb.h @@ -0,0 +1,165 @@ +/* + * FIXME correct answer depends on hmc_mode, + * as does (on omap1) any nonzero value for config->otg port number + */ +#ifdef CONFIG_USB_GADGET_OMAP +#define is_usb0_device(config) 1 +#else +#define is_usb0_device(config) 0 +#endif + +struct omap_usb_config { + /* Configure drivers according to the connectors on your board: + * - "A" connector (rectagular) + * ... for host/OHCI use, set "register_host". + * - "B" connector (squarish) or "Mini-B" + * ... for device/gadget use, set "register_dev". + * - "Mini-AB" connector (very similar to Mini-B) + * ... for OTG use as device OR host, initialize "otg" + */ + unsigned register_host:1; + unsigned register_dev:1; + u8 otg; /* port number, 1-based: usb1 == 2 */ + + u8 hmc_mode; + + /* implicitly true if otg: host supports remote wakeup? */ + u8 rwc; + + /* signaling pins used to talk to transceiver on usbN: + * 0 == usbN unused + * 2 == usb0-only, using internal transceiver + * 3 == 3 wire bidirectional + * 4 == 4 wire bidirectional + * 6 == 6 wire unidirectional (or TLL) + */ + u8 pins[3]; + + struct platform_device *udc_device; + struct platform_device *ohci_device; + struct platform_device *otg_device; + + u32 (*usb0_init)(unsigned nwires, unsigned is_device); + u32 (*usb1_init)(unsigned nwires); + u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); + + int (*ocpi_enable)(void); +}; + +void omap_otg_init(struct omap_usb_config *config); + +#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) +void omap1_usb_init(struct omap_usb_config *pdata); +#else +static inline void omap1_usb_init(struct omap_usb_config *pdata) +{ +} +#endif + +#define OMAP1_OTG_BASE 0xfffb0400 +#define OMAP1_UDC_BASE 0xfffb4000 +#define OMAP1_OHCI_BASE 0xfffba000 + +#define OMAP2_OHCI_BASE 0x4805e000 +#define OMAP2_UDC_BASE 0x4805e200 +#define OMAP2_OTG_BASE 0x4805e300 +#define OTG_BASE OMAP1_OTG_BASE +#define UDC_BASE OMAP1_UDC_BASE +#define OMAP_OHCI_BASE OMAP1_OHCI_BASE + +/* + * OTG and transceiver registers, for OMAPs starting with ARM926 + */ +#define OTG_REV (OTG_BASE + 0x00) +#define OTG_SYSCON_1 (OTG_BASE + 0x04) +# define USB2_TRX_MODE(w) (((w)>>24)&0x07) +# define USB1_TRX_MODE(w) (((w)>>20)&0x07) +# define USB0_TRX_MODE(w) (((w)>>16)&0x07) +# define OTG_IDLE_EN (1 << 15) +# define HST_IDLE_EN (1 << 14) +# define DEV_IDLE_EN (1 << 13) +# define OTG_RESET_DONE (1 << 2) +# define OTG_SOFT_RESET (1 << 1) +#define OTG_SYSCON_2 (OTG_BASE + 0x08) +# define OTG_EN (1 << 31) +# define USBX_SYNCHRO (1 << 30) +# define OTG_MST16 (1 << 29) +# define SRP_GPDATA (1 << 28) +# define SRP_GPDVBUS (1 << 27) +# define SRP_GPUVBUS(w) (((w)>>24)&0x07) +# define A_WAIT_VRISE(w) (((w)>>20)&0x07) +# define B_ASE_BRST(w) (((w)>>16)&0x07) +# define SRP_DPW (1 << 14) +# define SRP_DATA (1 << 13) +# define SRP_VBUS (1 << 12) +# define OTG_PADEN (1 << 10) +# define HMC_PADEN (1 << 9) +# define UHOST_EN (1 << 8) +# define HMC_TLLSPEED (1 << 7) +# define HMC_TLLATTACH (1 << 6) +# define OTG_HMC(w) (((w)>>0)&0x3f) +#define OTG_CTRL (OTG_BASE + 0x0c) +# define OTG_USB2_EN (1 << 29) +# define OTG_USB2_DP (1 << 28) +# define OTG_USB2_DM (1 << 27) +# define OTG_USB1_EN (1 << 26) +# define OTG_USB1_DP (1 << 25) +# define OTG_USB1_DM (1 << 24) +# define OTG_USB0_EN (1 << 23) +# define OTG_USB0_DP (1 << 22) +# define OTG_USB0_DM (1 << 21) +# define OTG_ASESSVLD (1 << 20) +# define OTG_BSESSEND (1 << 19) +# define OTG_BSESSVLD (1 << 18) +# define OTG_VBUSVLD (1 << 17) +# define OTG_ID (1 << 16) +# define OTG_DRIVER_SEL (1 << 15) +# define OTG_A_SETB_HNPEN (1 << 12) +# define OTG_A_BUSREQ (1 << 11) +# define OTG_B_HNPEN (1 << 9) +# define OTG_B_BUSREQ (1 << 8) +# define OTG_BUSDROP (1 << 7) +# define OTG_PULLDOWN (1 << 5) +# define OTG_PULLUP (1 << 4) +# define OTG_DRV_VBUS (1 << 3) +# define OTG_PD_VBUS (1 << 2) +# define OTG_PU_VBUS (1 << 1) +# define OTG_PU_ID (1 << 0) +#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ +# define DRIVER_SWITCH (1 << 15) +# define A_VBUS_ERR (1 << 13) +# define A_REQ_TMROUT (1 << 12) +# define A_SRP_DETECT (1 << 11) +# define B_HNP_FAIL (1 << 10) +# define B_SRP_TMROUT (1 << 9) +# define B_SRP_DONE (1 << 8) +# define B_SRP_STARTED (1 << 7) +# define OPRT_CHG (1 << 0) +#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ + // same bits as in IRQ_EN +#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ +# define OTGVPD (1 << 14) +# define OTGVPU (1 << 13) +# define OTGPUID (1 << 12) +# define USB2VDR (1 << 10) +# define USB2PDEN (1 << 9) +# define USB2PUEN (1 << 8) +# define USB1VDR (1 << 6) +# define USB1PDEN (1 << 5) +# define USB1PUEN (1 << 4) +# define USB0VDR (1 << 2) +# define USB0PDEN (1 << 1) +# define USB0PUEN (1 << 0) +#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ +#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ + +/*-------------------------------------------------------------------------*/ + +/* OMAP1 */ +#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) +# define CONF_USB2_UNI_R (1 << 8) +# define CONF_USB1_UNI_R (1 << 7) +# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) +# define CONF_USB0_ISOLATE_R (1 << 3) +# define CONF_USB_PWRDN_DM_R (1 << 2) +# define CONF_USB_PWRDN_DP_R (1 << 1) diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index e61afd92276..65f88176fba 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -27,7 +27,8 @@ #include #include -#include + +#include #include "common.h" @@ -55,6 +56,119 @@ #define INT_USB_IRQ_HGEN INT_USB_HHC_1 #define INT_USB_IRQ_OTG IH2_BASE + 8 +#ifdef CONFIG_ARCH_OMAP_OTG + +void __init +omap_otg_init(struct omap_usb_config *config) +{ + u32 syscon; + int alt_pingroup = 0; + + /* NOTE: no bus or clock setup (yet?) */ + + syscon = omap_readl(OTG_SYSCON_1) & 0xffff; + if (!(syscon & OTG_RESET_DONE)) + pr_debug("USB resets not complete?\n"); + + //omap_writew(0, OTG_IRQ_EN); + + /* pin muxing and transceiver pinouts */ + if (config->pins[0] > 2) /* alt pingroup 2 */ + alt_pingroup = 1; + syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); + syscon |= config->usb1_init(config->pins[1]); + syscon |= config->usb2_init(config->pins[2], alt_pingroup); + pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); + omap_writel(syscon, OTG_SYSCON_1); + + syscon = config->hmc_mode; + syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; +#ifdef CONFIG_USB_OTG + if (config->otg) + syscon |= OTG_EN; +#endif + if (cpu_class_is_omap1()) + pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", + omap_readl(USB_TRANSCEIVER_CTRL)); + pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); + omap_writel(syscon, OTG_SYSCON_2); + + printk("USB: hmc %d", config->hmc_mode); + if (!alt_pingroup) + printk(", usb2 alt %d wires", config->pins[2]); + else if (config->pins[0]) + printk(", usb0 %d wires%s", config->pins[0], + is_usb0_device(config) ? " (dev)" : ""); + if (config->pins[1]) + printk(", usb1 %d wires", config->pins[1]); + if (!alt_pingroup && config->pins[2]) + printk(", usb2 %d wires", config->pins[2]); + if (config->otg) + printk(", Mini-AB on usb%d", config->otg - 1); + printk("\n"); + + if (cpu_class_is_omap1()) { + u16 w; + + /* leave USB clocks/controllers off until needed */ + w = omap_readw(ULPD_SOFT_REQ); + w &= ~SOFT_USB_CLK_REQ; + omap_writew(w, ULPD_SOFT_REQ); + + w = omap_readw(ULPD_CLOCK_CTRL); + w &= ~USB_MCLK_EN; + w |= DIS_USB_PVCI_CLK; + omap_writew(w, ULPD_CLOCK_CTRL); + } + syscon = omap_readl(OTG_SYSCON_1); + syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; + +#ifdef CONFIG_USB_GADGET_OMAP + if (config->otg || config->register_dev) { + struct platform_device *udc_device = config->udc_device; + int status; + + syscon &= ~DEV_IDLE_EN; + udc_device->dev.platform_data = config; + status = platform_device_register(udc_device); + if (status) + pr_debug("can't register UDC device, %d\n", status); + } +#endif + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + if (config->otg || config->register_host) { + struct platform_device *ohci_device = config->ohci_device; + int status; + + syscon &= ~HST_IDLE_EN; + ohci_device->dev.platform_data = config; + status = platform_device_register(ohci_device); + if (status) + pr_debug("can't register OHCI device, %d\n", status); + } +#endif + +#ifdef CONFIG_USB_OTG + if (config->otg) { + struct platform_device *otg_device = config->otg_device; + int status; + + syscon &= ~OTG_IDLE_EN; + otg_device->dev.platform_data = config; + status = platform_device_register(otg_device); + if (status) + pr_debug("can't register OTG device, %d\n", status); + } +#endif + pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); + omap_writel(syscon, OTG_SYSCON_1); +} + +#else +void omap_otg_init(struct omap_usb_config *config) {} +#endif + #ifdef CONFIG_USB_GADGET_OMAP static struct resource udc_resources[] = { diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index ed8605f0115..6d87532871c 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ - usb.o fb.o counter_32k.o + fb.o counter_32k.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index 4814c5b6530..e62f20a5c0a 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h @@ -57,44 +57,6 @@ struct omap_camera_sensor_config { int (*power_off)(void * data); }; -struct omap_usb_config { - /* Configure drivers according to the connectors on your board: - * - "A" connector (rectagular) - * ... for host/OHCI use, set "register_host". - * - "B" connector (squarish) or "Mini-B" - * ... for device/gadget use, set "register_dev". - * - "Mini-AB" connector (very similar to Mini-B) - * ... for OTG use as device OR host, initialize "otg" - */ - unsigned register_host:1; - unsigned register_dev:1; - u8 otg; /* port number, 1-based: usb1 == 2 */ - - u8 hmc_mode; - - /* implicitly true if otg: host supports remote wakeup? */ - u8 rwc; - - /* signaling pins used to talk to transceiver on usbN: - * 0 == usbN unused - * 2 == usb0-only, using internal transceiver - * 3 == 3 wire bidirectional - * 4 == 4 wire bidirectional - * 6 == 6 wire unidirectional (or TLL) - */ - u8 pins[3]; - - struct platform_device *udc_device; - struct platform_device *ohci_device; - struct platform_device *otg_device; - - u32 (*usb0_init)(unsigned nwires, unsigned is_device); - u32 (*usb1_init)(unsigned nwires); - u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); - - int (*ocpi_enable)(void); -}; - struct omap_lcd_config { char panel_name[16]; char ctrl_name[16]; diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 762eeb0626c..548a4c8d63d 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -44,6 +44,8 @@ struct usbhs_omap_board_data { struct regulator *regulator[OMAP3_HS_USB_PORTS]; }; +#ifdef CONFIG_ARCH_OMAP2PLUS + struct ehci_hcd_omap_platform_data { enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; int reset_gpio_port[OMAP3_HS_USB_PORTS]; @@ -64,26 +66,6 @@ struct usbhs_omap_platform_data { }; /*-------------------------------------------------------------------------*/ -#define OMAP1_OTG_BASE 0xfffb0400 -#define OMAP1_UDC_BASE 0xfffb4000 -#define OMAP1_OHCI_BASE 0xfffba000 - -#define OMAP2_OHCI_BASE 0x4805e000 -#define OMAP2_UDC_BASE 0x4805e200 -#define OMAP2_OTG_BASE 0x4805e300 - -#ifdef CONFIG_ARCH_OMAP1 - -#define OTG_BASE OMAP1_OTG_BASE -#define UDC_BASE OMAP1_UDC_BASE -#define OMAP_OHCI_BASE OMAP1_OHCI_BASE - -#else - -#define OTG_BASE OMAP2_OTG_BASE -#define UDC_BASE OMAP2_UDC_BASE -#define OMAP_OHCI_BASE OMAP2_OHCI_BASE - struct omap_musb_board_data { u8 interface_type; u8 mode; @@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev); extern int omap4430_phy_exit(struct device *dev); extern int omap4430_phy_suspend(struct device *dev, int suspend); -/* - * NOTE: Please update omap USB drivers to use ioremap + read/write - */ - -#define OMAP2_L4_IO_OFFSET 0xb2000000 -#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) - -static inline u8 omap_readb(u32 pa) -{ - return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); -} - -static inline u16 omap_readw(u32 pa) -{ - return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); -} - -static inline u32 omap_readl(u32 pa) -{ - return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); -} - -static inline void omap_writeb(u8 v, u32 pa) -{ - __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); -} - - -static inline void omap_writew(u16 v, u32 pa) -{ - __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); -} - -static inline void omap_writel(u32 v, u32 pa) -{ - __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); -} - #endif extern void am35x_musb_reset(void); @@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void); extern void am35x_set_mode(u8 musb_mode); extern void ti81xx_musb_phy_power(u8 on); -/* - * FIXME correct answer depends on hmc_mode, - * as does (on omap1) any nonzero value for config->otg port number - */ -#ifdef CONFIG_USB_GADGET_OMAP -#define is_usb0_device(config) 1 -#else -#define is_usb0_device(config) 0 -#endif - -void omap_otg_init(struct omap_usb_config *config); - -#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) -void omap1_usb_init(struct omap_usb_config *pdata); -#else -static inline void omap1_usb_init(struct omap_usb_config *pdata) -{ -} -#endif - -#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) -void omap2_usbfs_init(struct omap_usb_config *pdata); -#else -static inline void omap2_usbfs_init(struct omap_usb_config *pdata) -{ -} -#endif - -/*-------------------------------------------------------------------------*/ - -/* - * OTG and transceiver registers, for OMAPs starting with ARM926 - */ -#define OTG_REV (OTG_BASE + 0x00) -#define OTG_SYSCON_1 (OTG_BASE + 0x04) -# define USB2_TRX_MODE(w) (((w)>>24)&0x07) -# define USB1_TRX_MODE(w) (((w)>>20)&0x07) -# define USB0_TRX_MODE(w) (((w)>>16)&0x07) -# define OTG_IDLE_EN (1 << 15) -# define HST_IDLE_EN (1 << 14) -# define DEV_IDLE_EN (1 << 13) -# define OTG_RESET_DONE (1 << 2) -# define OTG_SOFT_RESET (1 << 1) -#define OTG_SYSCON_2 (OTG_BASE + 0x08) -# define OTG_EN (1 << 31) -# define USBX_SYNCHRO (1 << 30) -# define OTG_MST16 (1 << 29) -# define SRP_GPDATA (1 << 28) -# define SRP_GPDVBUS (1 << 27) -# define SRP_GPUVBUS(w) (((w)>>24)&0x07) -# define A_WAIT_VRISE(w) (((w)>>20)&0x07) -# define B_ASE_BRST(w) (((w)>>16)&0x07) -# define SRP_DPW (1 << 14) -# define SRP_DATA (1 << 13) -# define SRP_VBUS (1 << 12) -# define OTG_PADEN (1 << 10) -# define HMC_PADEN (1 << 9) -# define UHOST_EN (1 << 8) -# define HMC_TLLSPEED (1 << 7) -# define HMC_TLLATTACH (1 << 6) -# define OTG_HMC(w) (((w)>>0)&0x3f) -#define OTG_CTRL (OTG_BASE + 0x0c) -# define OTG_USB2_EN (1 << 29) -# define OTG_USB2_DP (1 << 28) -# define OTG_USB2_DM (1 << 27) -# define OTG_USB1_EN (1 << 26) -# define OTG_USB1_DP (1 << 25) -# define OTG_USB1_DM (1 << 24) -# define OTG_USB0_EN (1 << 23) -# define OTG_USB0_DP (1 << 22) -# define OTG_USB0_DM (1 << 21) -# define OTG_ASESSVLD (1 << 20) -# define OTG_BSESSEND (1 << 19) -# define OTG_BSESSVLD (1 << 18) -# define OTG_VBUSVLD (1 << 17) -# define OTG_ID (1 << 16) -# define OTG_DRIVER_SEL (1 << 15) -# define OTG_A_SETB_HNPEN (1 << 12) -# define OTG_A_BUSREQ (1 << 11) -# define OTG_B_HNPEN (1 << 9) -# define OTG_B_BUSREQ (1 << 8) -# define OTG_BUSDROP (1 << 7) -# define OTG_PULLDOWN (1 << 5) -# define OTG_PULLUP (1 << 4) -# define OTG_DRV_VBUS (1 << 3) -# define OTG_PD_VBUS (1 << 2) -# define OTG_PU_VBUS (1 << 1) -# define OTG_PU_ID (1 << 0) -#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ -# define DRIVER_SWITCH (1 << 15) -# define A_VBUS_ERR (1 << 13) -# define A_REQ_TMROUT (1 << 12) -# define A_SRP_DETECT (1 << 11) -# define B_HNP_FAIL (1 << 10) -# define B_SRP_TMROUT (1 << 9) -# define B_SRP_DONE (1 << 8) -# define B_SRP_STARTED (1 << 7) -# define OPRT_CHG (1 << 0) -#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ - // same bits as in IRQ_EN -#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ -# define OTGVPD (1 << 14) -# define OTGVPU (1 << 13) -# define OTGPUID (1 << 12) -# define USB2VDR (1 << 10) -# define USB2PDEN (1 << 9) -# define USB2PUEN (1 << 8) -# define USB1VDR (1 << 6) -# define USB1PDEN (1 << 5) -# define USB1PUEN (1 << 4) -# define USB0VDR (1 << 2) -# define USB0PDEN (1 << 1) -# define USB0PUEN (1 << 0) -#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ -#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ - -/*-------------------------------------------------------------------------*/ - -/* OMAP1 */ -#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) -# define CONF_USB2_UNI_R (1 << 8) -# define CONF_USB1_UNI_R (1 << 7) -# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) -# define CONF_USB0_ISOLATE_R (1 << 3) -# define CONF_USB_PWRDN_DM_R (1 << 2) -# define CONF_USB_PWRDN_DP_R (1 << 1) - -/* OMAP2 */ -# define USB_UNIDIR 0x0 -# define USB_UNIDIR_TLL 0x1 -# define USB_BIDIR 0x2 -# define USB_BIDIR_TLL 0x3 -# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2))) -# define USBT2TLL5PI (1 << 17) -# define USB0PUENACTLOI (1 << 16) -# define USBSTANDBYCTRL (1 << 15) /* AM35x */ /* USB 2.0 PHY Control */ #define CONF2_PHY_GPIOMODE (1 << 23) diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c deleted file mode 100644 index daa0327381b..00000000000 --- a/arch/arm/plat-omap/usb.c +++ /dev/null @@ -1,145 +0,0 @@ - /* - * arch/arm/plat-omap/usb.c -- platform level USB initialization - * - * Copyright (C) 2004 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#undef DEBUG - -#include -#include -#include -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_ARCH_OMAP_OTG - -void __init -omap_otg_init(struct omap_usb_config *config) -{ - u32 syscon; - int alt_pingroup = 0; - - /* NOTE: no bus or clock setup (yet?) */ - - syscon = omap_readl(OTG_SYSCON_1) & 0xffff; - if (!(syscon & OTG_RESET_DONE)) - pr_debug("USB resets not complete?\n"); - - //omap_writew(0, OTG_IRQ_EN); - - /* pin muxing and transceiver pinouts */ - if (config->pins[0] > 2) /* alt pingroup 2 */ - alt_pingroup = 1; - syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); - syscon |= config->usb1_init(config->pins[1]); - syscon |= config->usb2_init(config->pins[2], alt_pingroup); - pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); - omap_writel(syscon, OTG_SYSCON_1); - - syscon = config->hmc_mode; - syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; -#ifdef CONFIG_USB_OTG - if (config->otg) - syscon |= OTG_EN; -#endif - if (cpu_class_is_omap1()) - pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", - omap_readl(USB_TRANSCEIVER_CTRL)); - pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); - omap_writel(syscon, OTG_SYSCON_2); - - printk("USB: hmc %d", config->hmc_mode); - if (!alt_pingroup) - printk(", usb2 alt %d wires", config->pins[2]); - else if (config->pins[0]) - printk(", usb0 %d wires%s", config->pins[0], - is_usb0_device(config) ? " (dev)" : ""); - if (config->pins[1]) - printk(", usb1 %d wires", config->pins[1]); - if (!alt_pingroup && config->pins[2]) - printk(", usb2 %d wires", config->pins[2]); - if (config->otg) - printk(", Mini-AB on usb%d", config->otg - 1); - printk("\n"); - - if (cpu_class_is_omap1()) { - u16 w; - - /* leave USB clocks/controllers off until needed */ - w = omap_readw(ULPD_SOFT_REQ); - w &= ~SOFT_USB_CLK_REQ; - omap_writew(w, ULPD_SOFT_REQ); - - w = omap_readw(ULPD_CLOCK_CTRL); - w &= ~USB_MCLK_EN; - w |= DIS_USB_PVCI_CLK; - omap_writew(w, ULPD_CLOCK_CTRL); - } - syscon = omap_readl(OTG_SYSCON_1); - syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; - -#ifdef CONFIG_USB_GADGET_OMAP - if (config->otg || config->register_dev) { - struct platform_device *udc_device = config->udc_device; - int status; - - syscon &= ~DEV_IDLE_EN; - udc_device->dev.platform_data = config; - status = platform_device_register(udc_device); - if (status) - pr_debug("can't register UDC device, %d\n", status); - } -#endif - -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - if (config->otg || config->register_host) { - struct platform_device *ohci_device = config->ohci_device; - int status; - - syscon &= ~HST_IDLE_EN; - ohci_device->dev.platform_data = config; - status = platform_device_register(ohci_device); - if (status) - pr_debug("can't register OHCI device, %d\n", status); - } -#endif - -#ifdef CONFIG_USB_OTG - if (config->otg) { - struct platform_device *otg_device = config->otg_device; - int status; - - syscon &= ~OTG_IDLE_EN; - otg_device->dev.platform_data = config; - status = platform_device_register(otg_device); - if (status) - pr_debug("can't register OTG device, %d\n", status); - } -#endif - pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); - omap_writel(syscon, OTG_SYSCON_1); -} - -#else -void omap_otg_init(struct omap_usb_config *config) {} -#endif diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index bddc8fd9a7b..271ca161d7e 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -185,7 +185,7 @@ config USB_FUSB300 config USB_OMAP tristate "OMAP USB Device Controller" - depends on ARCH_OMAP + depends on ARCH_OMAP1 select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_H4_OTG select USB_OTG_UTILS if ARCH_OMAP help diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c index 7ba32469c5b..2acf06cd922 100644 --- a/drivers/usb/gadget/omap_udc.c +++ b/drivers/usb/gadget/omap_udc.c @@ -44,7 +44,8 @@ #include #include -#include + +#include #include "omap_udc.h" diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 83e58df29fe..dcfaaa91a3f 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -308,7 +308,7 @@ config USB_OHCI_HCD config USB_OHCI_HCD_OMAP1 bool "OHCI support for OMAP1/2 chips" - depends on USB_OHCI_HCD && (ARCH_OMAP1 || ARCH_OMAP2) + depends on USB_OHCI_HCD && ARCH_OMAP1 default y ---help--- Enables support for the OHCI controller on OMAP1/2 chips. diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index 9ce35d0d9d5..b02c344e2cc 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -20,14 +20,15 @@ #include #include -#include #include #include #include -#include #include -#include + +#include +#include +#include /* OMAP-1510 OHCI has its own MMU for DMA */ diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c index 70cf5d7bca4..e0558dfcfaf 100644 --- a/drivers/usb/otg/isp1301_omap.c +++ b/drivers/usb/otg/isp1301_omap.c @@ -36,9 +36,9 @@ #include #include -#include #include +#include #ifndef DEBUG #undef VERBOSE -- cgit v1.2.3-70-g09d2 From d0a9001dce0ea24751b1f6336f2881ac906cabbb Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Thu, 10 May 2012 14:23:01 +0530 Subject: ARM: OMAP2+: am33xx: Add low level debugging support Add support for low level debugging on AM335X EVM (AM33XX family). Currently only support for UART1 console, which is used on AM335X EVM is added. Signed-off-by: Afzal Mohammed Signed-off-by: Vaibhav Hiremath Reviewed-by: Kevin Hilman Cc: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/include/mach/debug-macro.S | 17 ++++++++++++++++- arch/arm/plat-omap/include/plat/serial.h | 4 ++++ arch/arm/plat-omap/include/plat/uncompress.h | 6 ++++++ 3 files changed, 26 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index cdfc2a1f0e7..d7f844a99a7 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -72,6 +72,8 @@ omap_uart_lsr: .word 0 beq 82f @ configure UART2 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different beq 83f @ configure UART3 + cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different + beq 84f @ configure UART1 cmp \rp, #ZOOM_UART @ only on zoom2/3 beq 95f @ configure ZOOM_UART @@ -100,7 +102,9 @@ omap_uart_lsr: .word 0 b 98f 83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) b 98f - +84: ldr \rp, =AM33XX_UART1_BASE + and \rp, \rp, #0x00ffffff + b 97f 95: ldr \rp, =ZOOM_UART_BASE str \rp, [\tmp, #0] @ omap_uart_phys ldr \rp, =ZOOM_UART_VIRT @@ -109,6 +113,17 @@ omap_uart_lsr: .word 0 str \rp, [\tmp, #8] @ omap_uart_lsr b 10b + /* AM33XX: Store both phys and virt address for the uart */ +97: add \rp, \rp, #0x44000000 @ phys base + str \rp, [\tmp, #0] @ omap_uart_phys + sub \rp, \rp, #0x44000000 @ phys base + add \rp, \rp, #0xf9000000 @ virt base + str \rp, [\tmp, #4] @ omap_uart_virt + mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) + str \rp, [\tmp, #8] @ omap_uart_lsr + + b 10b + /* Store both phys and virt address for the uart */ 98: add \rp, \rp, #0x48000000 @ phys base str \rp, [\tmp, #0] @ omap_uart_phys diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index b073e5f2b19..28e2d250c2f 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -60,6 +60,9 @@ /* AM3505/3517 UART4 */ #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ +/* AM33XX serial port */ +#define AM33XX_UART1_BASE 0x44E09000 + /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 @@ -93,6 +96,7 @@ #define TI81XXUART1 81 #define TI81XXUART2 82 #define TI81XXUART3 83 +#define AM33XXUART1 84 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index cc3f11ba7a9..ac432339021 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -103,6 +103,10 @@ static inline void flush(void) _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ TI81XXUART##p) +#define DEBUG_LL_AM33XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ + AM33XXUART##p) + static inline void __arch_decomp_setup(unsigned long arch_id) { int port = 0; @@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* TI8148 base boards using UART1 */ DEBUG_LL_TI81XX(1, ti8148evm); + /* AM33XX base boards using UART1 */ + DEBUG_LL_AM33XX(1, am335xevm); } while (0); } -- cgit v1.2.3-70-g09d2 From b8fd7331208e52a0a932209584bde80fd4ec09b9 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:49 -0500 Subject: ARM: OMAP: Remove unnecessary clk structure In the plat/dmtimer.h there is a structure named "clk" declared. This structure is not used and appears to be left over from previous code. Hence, remove this unused structure. Verified that both omap1 and omap2plus kernel configurations build with this change. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/dmtimer.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 5da73562e48..5fdfaa48125 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -71,7 +71,6 @@ struct omap_timer_capability_dev_attr { }; struct omap_dm_timer; -struct clk; struct timer_regs { u32 tidr; -- cgit v1.2.3-70-g09d2 From b7b4ff764f7bf903e47eebdab661b1c38e791c6d Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:51 -0500 Subject: ARM: OMAP2+: Add dmtimer platform function to reserve systimers During early boot, one or two dmtimers are reserved by the kernel as system timers (for clocksource and clockevents). These timers are marked as reserved and the dmtimer driver is notified which timers have been reserved via the platform data information. For OMAP2+ devices the timers reserved may vary depending on device and compile flags. Therefore, it is not easy to assume which timers we be reserved for the system timers. In order to migrate the dmtimer driver to support device-tree we need a way to pass the timers reserved for system timers to the dmtimer driver. Using the platform data structure will not work in the same way as it is currently used because the platform data structure will be stored statically in the dmtimer itself and the platform data will be selected via the device-tree match device function (of_match_device). There are a couple ways to workaround this. One option is to store the system timers reserved for the kernel in the device-tree and query them on boot. The downside of this approach is that it adds some delay to parse the DT blob to search for the system timers. Secondly, for OMAP3 devices we have a dependency on compile time flags and the device-tree would not be aware of that kernel compile flags and so we would need to address that. The second option is to add a function to the dmtimer code to reserved the system timers during boot and so the dmtimer knows exactly which timers are being used for system timers. This also allows us to remove the "reserved" member from the timer platform data. This seemed like the simpler approach and so was implemented here. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 9 ++------- arch/arm/plat-omap/dmtimer.c | 18 +++++++++++++++++- arch/arm/plat-omap/include/plat/dmtimer.h | 3 +-- 3 files changed, 20 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index c030dfeee76..b0b208077c9 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -69,8 +69,6 @@ #define OMAP3_SECURE_TIMER 1 #endif -static u32 sys_timer_reserved; - /* Clockevent code */ static struct omap_dm_timer clkev; @@ -177,7 +175,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, omap_hwmod_enable(oh); - sys_timer_reserved |= (1 << (gptimer_id - 1)); + if (omap_dm_timer_reserve_systimer(gptimer_id)) + return -ENODEV; if (gptimer_id != 12) { struct clk *src; @@ -501,10 +500,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) pdata->set_timer_src = omap2_dm_timer_set_src; pdata->timer_ip_version = oh->class->rev; - /* Mark clocksource and clockevent timers as reserved */ - if ((sys_timer_reserved >> (id - 1)) & 0x1) - pdata->reserved = 1; - pwrdm = omap_hwmod_get_pwrdm(oh); pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); #ifdef CONFIG_PM diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 3b0cfeb33d0..f5b5c89ac7c 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -45,6 +45,7 @@ #include +static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); @@ -152,6 +153,21 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer) return ret; } +static inline u32 omap_dm_timer_reserved_systimer(int id) +{ + return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; +} + +int omap_dm_timer_reserve_systimer(int id) +{ + if (omap_dm_timer_reserved_systimer(id)) + return -ENODEV; + + omap_reserved_systimers |= (1 << (id - 1)); + + return 0; +} + struct omap_dm_timer *omap_dm_timer_request(void) { struct omap_dm_timer *timer = NULL, *t; @@ -674,7 +690,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->id = pdev->id; timer->irq = irq->start; - timer->reserved = pdata->reserved; + timer->reserved = omap_dm_timer_reserved_systimer(timer->id); timer->pdev = pdev; timer->loses_context = pdata->loses_context; timer->get_context_loss_count = pdata->get_context_loss_count; diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 5fdfaa48125..1e5ce5d5624 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -98,13 +98,12 @@ struct dmtimer_platform_data { int (*set_timer_src)(struct platform_device *pdev, int source); int timer_ip_version; u32 needs_manual_reset:1; - bool reserved; - bool loses_context; int (*get_context_loss_count)(struct device *dev); }; +int omap_dm_timer_reserve_systimer(int id); struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); int omap_dm_timer_free(struct omap_dm_timer *timer); -- cgit v1.2.3-70-g09d2 From d1c1691be5290bf7e5b11b63b6fda0d63a9f4937 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:52 -0500 Subject: ARM: OMAP: Add DMTIMER capability variable to represent timer features Although the OMAP timers share a common hardware design, there are some differences between the timer instances in a given device. For example, a timer maybe in a power domain that can be powered-of, so can lose its logic state and need restoring where as another may be in power domain that is always be on. Another example, is a timer may support different clock sources to drive the timer. This information is passed to the dmtimer via the following platform data structure. struct dmtimer_platform_data { int (*set_timer_src)(struct platform_device *pdev, int source); int timer_ip_version; u32 needs_manual_reset:1; bool loses_context; int (*get_context_loss_count)(struct device *dev); }; The above structure uses multiple variables to represent the timer features. HWMOD also stores the timer capabilities using a bit-mask that represents the features supported. By using the same format for representing the timer features in the platform data as used by HWMOD, we can ... 1. Use the flags defined in the plat/dmtimer.h to represent the features supported. 2. For devices using HWMOD, we can retrieve the features supported from HWMOD. 3. Eventually, simplify the platform data structure to be ... struct dmtimer_platform_data { int (*set_timer_src)(struct platform_device *pdev, int source); u32 timer_capability; } Another benefit from doing this, is that it will simplify the migration of the dmtimer driver to device-tree. For example, in the current OMAP2+ timer code the "loses_context" variable is configured at runtime by calling an architecture specific function. For device tree this creates a problem, because we would need to call the architecture specific function from within the dmtimer driver. However, such attributes do not need to be queried at runtime and we can look up the attributes via HWMOD or device-tree. This changes a new "capability" variable to the platform data and timer structure so we can start removing and simplifying the platform data structure. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 3 +++ arch/arm/plat-omap/dmtimer.c | 1 + arch/arm/plat-omap/include/plat/dmtimer.h | 2 ++ 3 files changed, 6 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b0b208077c9..d8a5dc3d695 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -500,6 +500,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) pdata->set_timer_src = omap2_dm_timer_set_src; pdata->timer_ip_version = oh->class->rev; + if (timer_dev_attr) + pdata->timer_capability = timer_dev_attr->timer_capability; + pwrdm = omap_hwmod_get_pwrdm(oh); pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); #ifdef CONFIG_PM diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index f5b5c89ac7c..30742d8e681 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -694,6 +694,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->pdev = pdev; timer->loses_context = pdata->loses_context; timer->get_context_loss_count = pdata->get_context_loss_count; + timer->capability = pdata->timer_capability; /* Skip pm_runtime_enable for OMAP1 */ if (!pdata->needs_manual_reset) { diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 1e5ce5d5624..48e54caf900 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -101,6 +101,7 @@ struct dmtimer_platform_data { bool loses_context; int (*get_context_loss_count)(struct device *dev); + u32 timer_capability; }; int omap_dm_timer_reserve_systimer(int id); @@ -273,6 +274,7 @@ struct omap_dm_timer { bool loses_context; int ctx_loss_count; int revision; + u32 capability; struct platform_device *pdev; struct list_head node; -- cgit v1.2.3-70-g09d2 From 67d2e760ae1909f3a3c444a063961e35a54b7bb0 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:54 -0500 Subject: ARM: OMAP2+: Fix external clock support for dmtimers Currently, the dmtimer determines whether an timer can support an external clock source (sys_altclk) for driving the timer by the IP version. Only OMAP24xx devices can support an external clock source, but the IP version between OMAP24xx and OMAP3xxx is common and so this incorrectly indicates that OMAP3 devices can use an external clock source. Rather than use the IP version, just let the clock framework handle this. If the "alt_ck" does not exist for a timer then the clock framework will fail to find the clock and hence will return an error. By doing this we can eliminate the "timer_ip_version" variable passed as part of the platform data and simplify the code. We can also remove the timer IP version from the HWMOD data because the dmtimer driver uses the TIDR register to determine the IP version. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 -- arch/arm/mach-omap2/timer.c | 12 ++---------- arch/arm/plat-omap/include/plat/dmtimer.h | 7 ------- 4 files changed, 2 insertions(+), 20 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 7814e83fd03..afad69c6ba6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -68,7 +68,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { struct omap_hwmod_class omap2xxx_timer_hwmod_class = { .name = "timer", .sysc = &omap2xxx_timer_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 7b330944b3f..0ea53bcc7d1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -129,7 +129,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { .name = "timer", .sysc = &omap3xxx_timer_1ms_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, }; static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { @@ -145,7 +144,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { .name = "timer", .sysc = &omap3xxx_timer_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, }; /* secure timers dev attribute */ diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index d8a5dc3d695..8c046d9d8ae 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -397,7 +397,6 @@ OMAP_SYS_TIMER(4) static int omap2_dm_timer_set_src(struct platform_device *pdev, int source) { int ret; - struct dmtimer_platform_data *pdata = pdev->dev.platform_data; struct clk *fclk, *parent; char *parent_name = NULL; @@ -418,14 +417,8 @@ static int omap2_dm_timer_set_src(struct platform_device *pdev, int source) break; case OMAP_TIMER_SRC_EXT_CLK: - if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) { - parent_name = "alt_ck"; - break; - } - dev_err(&pdev->dev, "%s: %d: invalid clk src.\n", - __func__, __LINE__); - clk_put(fclk); - return -EINVAL; + parent_name = "alt_ck"; + break; } parent = clk_get(&pdev->dev, parent_name); @@ -498,7 +491,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) sscanf(oh->name, "timer%2d", &id); pdata->set_timer_src = omap2_dm_timer_set_src; - pdata->timer_ip_version = oh->class->rev; if (timer_dev_attr) pdata->timer_capability = timer_dev_attr->timer_capability; diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 48e54caf900..362cf97d721 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -55,12 +55,6 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 -/* - * IP revision identifier so that Highlander IP - * in OMAP4 can be distinguished. - */ -#define OMAP_TIMER_IP_VERSION_1 0x1 - /* timer capabilities used in hwmod database */ #define OMAP_TIMER_SECURE 0x80000000 #define OMAP_TIMER_ALWON 0x40000000 @@ -96,7 +90,6 @@ struct timer_regs { struct dmtimer_platform_data { int (*set_timer_src)(struct platform_device *pdev, int source); - int timer_ip_version; u32 needs_manual_reset:1; bool loses_context; -- cgit v1.2.3-70-g09d2 From 1c2d076b589225e51e022d85bb9f25dca26530f3 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:55 -0500 Subject: ARM: OMAP: Remove loses_context variable from timer platform data The platform data variable loses_context is used to determine if the timer may lose its logic state during power transitions and so needs to be restored. This information is also provided in the HWMOD device attributes for OMAP2+ devices via the OMAP_TIMER_ALWON flag. When this flag is set the timer will not lose context. So use the HWMOD device attributes to determine this. For OMAP1 devices, loses_context is never set and so set the OMAP_TIMER_ALWON flag for OMAP1 timers to ensure that code is equivalent. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/timer.c | 1 + arch/arm/mach-omap2/timer.c | 3 --- arch/arm/plat-omap/dmtimer.c | 8 ++++---- arch/arm/plat-omap/include/plat/dmtimer.h | 3 --- 4 files changed, 5 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 64c65bcb2d6..b4bf48c188f 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -141,6 +141,7 @@ static int __init omap1_dm_timer_init(void) pdata->set_timer_src = omap1_dm_timer_set_src; pdata->needs_manual_reset = 1; + pdata->timer_capability = OMAP_TIMER_ALWON; ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); if (ret) { diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 8c046d9d8ae..9b6880a3379 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -462,7 +462,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) struct dmtimer_platform_data *pdata; struct platform_device *pdev; struct omap_timer_capability_dev_attr *timer_dev_attr; - struct powerdomain *pwrdm; pr_debug("%s: %s\n", __func__, oh->name); @@ -495,8 +494,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) if (timer_dev_attr) pdata->timer_capability = timer_dev_attr->timer_capability; - pwrdm = omap_hwmod_get_pwrdm(oh); - pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); #ifdef CONFIG_PM pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; #endif diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 30742d8e681..7aa12785e23 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -341,7 +341,7 @@ int omap_dm_timer_start(struct omap_dm_timer *timer) omap_dm_timer_enable(timer); - if (timer->loses_context) { + if (!(timer->capability & OMAP_TIMER_ALWON)) { u32 ctx_loss_cnt_after = timer->get_context_loss_count(&timer->pdev->dev); if (ctx_loss_cnt_after != timer->ctx_loss_count) @@ -374,7 +374,8 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer) __omap_dm_timer_stop(timer, timer->posted, rate); - if (timer->loses_context && timer->get_context_loss_count) + if (!(timer->capability & OMAP_TIMER_ALWON) && + timer->get_context_loss_count) timer->ctx_loss_count = timer->get_context_loss_count(&timer->pdev->dev); @@ -447,7 +448,7 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, omap_dm_timer_enable(timer); - if (timer->loses_context) { + if (!(timer->capability & OMAP_TIMER_ALWON)) { u32 ctx_loss_cnt_after = timer->get_context_loss_count(&timer->pdev->dev); if (ctx_loss_cnt_after != timer->ctx_loss_count) @@ -692,7 +693,6 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->irq = irq->start; timer->reserved = omap_dm_timer_reserved_systimer(timer->id); timer->pdev = pdev; - timer->loses_context = pdata->loses_context; timer->get_context_loss_count = pdata->get_context_loss_count; timer->capability = pdata->timer_capability; diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 362cf97d721..0a7ed31954e 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -91,8 +91,6 @@ struct timer_regs { struct dmtimer_platform_data { int (*set_timer_src)(struct platform_device *pdev, int source); u32 needs_manual_reset:1; - bool loses_context; - int (*get_context_loss_count)(struct device *dev); u32 timer_capability; }; @@ -264,7 +262,6 @@ struct omap_dm_timer { unsigned reserved:1; unsigned posted:1; struct timer_regs context; - bool loses_context; int ctx_loss_count; int revision; u32 capability; -- cgit v1.2.3-70-g09d2 From 0b30ec1cb7f1b0134b16670f886baaf3521b083c Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:56 -0500 Subject: ARM: OMAP: Remove timer function pointer for context loss counter For OMAP2+ devices, a function pointer that returns the number of times a timer power domain has lost context is passed to the dmtimer driver. This function pointer is only populated for OMAP2+ devices and it is pointing to a platform function. Given that this is a platform function, we can simplify the code by removing the function pointer and referencing the function directly. We can use the OMAP_TIMER_ALWON flag to determine if we need to call this function for OMAP1 and OMAP2+ devices. The benefit of this change is the we can remove the function pointer from the platform data and simplifies the dmtimer migration to device-tree. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 3 --- arch/arm/plat-omap/dmtimer.c | 17 +++++++---------- arch/arm/plat-omap/include/plat/dmtimer.h | 3 --- 3 files changed, 7 insertions(+), 16 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 9b6880a3379..0e17a0d9690 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -494,9 +494,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) if (timer_dev_attr) pdata->timer_capability = timer_dev_attr->timer_capability; -#ifdef CONFIG_PM - pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; -#endif pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), NULL, 0, 0); diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 7aa12785e23..7875eefd047 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -42,6 +42,7 @@ #include #include +#include #include @@ -342,9 +343,8 @@ int omap_dm_timer_start(struct omap_dm_timer *timer) omap_dm_timer_enable(timer); if (!(timer->capability & OMAP_TIMER_ALWON)) { - u32 ctx_loss_cnt_after = - timer->get_context_loss_count(&timer->pdev->dev); - if (ctx_loss_cnt_after != timer->ctx_loss_count) + if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != + timer->ctx_loss_count) omap_timer_restore_context(timer); } @@ -374,10 +374,9 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer) __omap_dm_timer_stop(timer, timer->posted, rate); - if (!(timer->capability & OMAP_TIMER_ALWON) && - timer->get_context_loss_count) + if (!(timer->capability & OMAP_TIMER_ALWON)) timer->ctx_loss_count = - timer->get_context_loss_count(&timer->pdev->dev); + omap_pm_get_dev_context_loss_count(&timer->pdev->dev); /* * Since the register values are computed and written within @@ -449,9 +448,8 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, omap_dm_timer_enable(timer); if (!(timer->capability & OMAP_TIMER_ALWON)) { - u32 ctx_loss_cnt_after = - timer->get_context_loss_count(&timer->pdev->dev); - if (ctx_loss_cnt_after != timer->ctx_loss_count) + if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != + timer->ctx_loss_count) omap_timer_restore_context(timer); } @@ -693,7 +691,6 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->irq = irq->start; timer->reserved = omap_dm_timer_reserved_systimer(timer->id); timer->pdev = pdev; - timer->get_context_loss_count = pdata->get_context_loss_count; timer->capability = pdata->timer_capability; /* Skip pm_runtime_enable for OMAP1 */ diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 0a7ed31954e..e11c9ea7ec5 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -91,7 +91,6 @@ struct timer_regs { struct dmtimer_platform_data { int (*set_timer_src)(struct platform_device *pdev, int source); u32 needs_manual_reset:1; - int (*get_context_loss_count)(struct device *dev); u32 timer_capability; }; @@ -267,8 +266,6 @@ struct omap_dm_timer { u32 capability; struct platform_device *pdev; struct list_head node; - - int (*get_context_loss_count)(struct device *dev); }; int omap_dm_timer_prepare(struct omap_dm_timer *timer); -- cgit v1.2.3-70-g09d2 From 6615975bc58a1234bd401a7ff231dae85631fd58 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:57 -0500 Subject: ARM: OMAP: Add flag to indicate if a timer needs a manual reset For OMAP1 devices, it is necessary to perform a manual reset of the timer. Currently, this is indicating by setting the "needs_manual_reset" variable in the platform data. Instead of using an extra variable to indicate this add a new timer capabilities flag to indicate this and remove the "needs_manual_reset" member from the platform data. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/timer.c | 4 ++-- arch/arm/plat-omap/dmtimer.c | 9 +++------ arch/arm/plat-omap/include/plat/dmtimer.h | 2 +- 3 files changed, 6 insertions(+), 9 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index b4bf48c188f..aa81593db1a 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -140,8 +140,8 @@ static int __init omap1_dm_timer_init(void) } pdata->set_timer_src = omap1_dm_timer_set_src; - pdata->needs_manual_reset = 1; - pdata->timer_capability = OMAP_TIMER_ALWON; + pdata->timer_capability = OMAP_TIMER_ALWON | + OMAP_TIMER_NEEDS_RESET; ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); if (ret) { diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 7875eefd047..e3e22b3dc5c 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -135,7 +135,6 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) int omap_dm_timer_prepare(struct omap_dm_timer *timer) { - struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; int ret; timer->fclk = clk_get(&timer->pdev->dev, "fck"); @@ -145,7 +144,7 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer) return -EINVAL; } - if (pdata->needs_manual_reset) + if (timer->capability & OMAP_TIMER_NEEDS_RESET) omap_dm_timer_reset(timer); ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); @@ -363,13 +362,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start); int omap_dm_timer_stop(struct omap_dm_timer *timer) { unsigned long rate = 0; - struct dmtimer_platform_data *pdata; if (unlikely(!timer)) return -EINVAL; - pdata = timer->pdev->dev.platform_data; - if (!pdata->needs_manual_reset) + if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) rate = clk_get_rate(timer->fclk); __omap_dm_timer_stop(timer, timer->posted, rate); @@ -694,7 +691,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->capability = pdata->timer_capability; /* Skip pm_runtime_enable for OMAP1 */ - if (!pdata->needs_manual_reset) { + if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { pm_runtime_enable(&pdev->dev); pm_runtime_irq_safe(&pdev->dev); } diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index e11c9ea7ec5..c039e84bca7 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -59,6 +59,7 @@ #define OMAP_TIMER_SECURE 0x80000000 #define OMAP_TIMER_ALWON 0x40000000 #define OMAP_TIMER_HAS_PWM 0x20000000 +#define OMAP_TIMER_NEEDS_RESET 0x10000000 struct omap_timer_capability_dev_attr { u32 timer_capability; @@ -90,7 +91,6 @@ struct timer_regs { struct dmtimer_platform_data { int (*set_timer_src)(struct platform_device *pdev, int source); - u32 needs_manual_reset:1; u32 timer_capability; }; -- cgit v1.2.3-70-g09d2 From 2b2d35230099613365ad6000f4d71086130b9e71 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 5 Jun 2012 12:34:59 -0500 Subject: ARM: OMAP2+: Move dmtimer clock set function to dmtimer driver OMAP1 uses an architecture specific function for setting the dmtimer clock source, where as the OMAP2+ devices use the clock framework. Eventually OMAP1 device should also use the clock framework and hence we should not any architecture specific functions. For now move the OMAP2+ function for configuring the clock source into the dmtimer driver. Therefore, we do no longer need to specify an architecture specific function for setting the clock source for OMAP2+ devices. This will simplify device tree migration of the dmtimers for OMAP2+ devices. From now on, only OMAP1 devices should specify an architecture specific function for setting the clock source via the platform data set_dmtimer_src() function pointer. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 55 ------------------------------- arch/arm/plat-omap/dmtimer.c | 46 +++++++++++++++++++++++++- arch/arm/plat-omap/include/plat/dmtimer.h | 1 + 3 files changed, 46 insertions(+), 56 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 0e17a0d9690..8fe75a81e12 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -389,59 +389,6 @@ static void __init omap4_timer_init(void) OMAP_SYS_TIMER(4) #endif -/** - * omap2_dm_timer_set_src - change the timer input clock source - * @pdev: timer platform device pointer - * @source: array index of parent clock source - */ -static int omap2_dm_timer_set_src(struct platform_device *pdev, int source) -{ - int ret; - struct clk *fclk, *parent; - char *parent_name = NULL; - - fclk = clk_get(&pdev->dev, "fck"); - if (IS_ERR_OR_NULL(fclk)) { - dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n", - __func__, __LINE__); - return -EINVAL; - } - - switch (source) { - case OMAP_TIMER_SRC_SYS_CLK: - parent_name = "sys_ck"; - break; - - case OMAP_TIMER_SRC_32_KHZ: - parent_name = "32k_ck"; - break; - - case OMAP_TIMER_SRC_EXT_CLK: - parent_name = "alt_ck"; - break; - } - - parent = clk_get(&pdev->dev, parent_name); - if (IS_ERR_OR_NULL(parent)) { - dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n", - __func__, __LINE__, parent_name); - clk_put(fclk); - return -EINVAL; - } - - ret = clk_set_parent(fclk, parent); - if (IS_ERR_VALUE(ret)) { - dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n", - __func__, parent_name); - ret = -EINVAL; - } - - clk_put(parent); - clk_put(fclk); - - return ret; -} - /** * omap_timer_init - build and register timer device with an * associated timer hwmod @@ -489,8 +436,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) */ sscanf(oh->name, "timer%2d", &id); - pdata->set_timer_src = omap2_dm_timer_set_src; - if (timer_dev_attr) pdata->timer_capability = timer_dev_attr->timer_capability; diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 6510e5e7b7e..6a7088972c5 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -397,6 +397,8 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop); int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { int ret; + char *parent_name = NULL; + struct clk *fclk, *parent; struct dmtimer_platform_data *pdata; if (unlikely(!timer)) @@ -407,7 +409,49 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) if (source < 0 || source >= 3) return -EINVAL; - ret = pdata->set_timer_src(timer->pdev, source); + /* + * FIXME: Used for OMAP1 devices only because they do not currently + * use the clock framework to set the parent clock. To be removed + * once OMAP1 migrated to using clock framework for dmtimers + */ + if (pdata->set_timer_src) + return pdata->set_timer_src(timer->pdev, source); + + fclk = clk_get(&timer->pdev->dev, "fck"); + if (IS_ERR_OR_NULL(fclk)) { + pr_err("%s: fck not found\n", __func__); + return -EINVAL; + } + + switch (source) { + case OMAP_TIMER_SRC_SYS_CLK: + parent_name = "sys_ck"; + break; + + case OMAP_TIMER_SRC_32_KHZ: + parent_name = "32k_ck"; + break; + + case OMAP_TIMER_SRC_EXT_CLK: + parent_name = "alt_ck"; + break; + } + + parent = clk_get(&timer->pdev->dev, parent_name); + if (IS_ERR_OR_NULL(parent)) { + pr_err("%s: %s not found\n", __func__, parent_name); + ret = -EINVAL; + goto out; + } + + ret = clk_set_parent(fclk, parent); + if (IS_ERR_VALUE(ret)) + pr_err("%s: failed to set %s as parent\n", __func__, + parent_name); + + clk_put(parent); +out: + clk_put(fclk); return ret; } diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index c039e84bca7..19e7fa577bd 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -90,6 +90,7 @@ struct timer_regs { }; struct dmtimer_platform_data { + /* set_timer_src - Only used for OMAP1 devices */ int (*set_timer_src)(struct platform_device *pdev, int source); u32 timer_capability; }; -- cgit v1.2.3-70-g09d2 From 9ebfd285371835b1c0243d15aaacd72d5def76f8 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 18 Jun 2012 12:12:23 -0600 Subject: ARM: OMAP2+: hwmod: use init-time function ptrs for enable/disable module The enable/disable module functions are specific to SoCs with OMAP4-class PRCM. Rather than use cpu_is* checks at runtime inside the enable/disable module functions, use cpu_is at init time to initialize function pointers only for SoCs that need them. NOTE: the cpu_is* check for _enable_module was different than the one for _disable_module, and this patch uses cpu_is_omap44xx() for both. Signed-off-by: Kevin Hilman [paul@pwsan.com: moved soc_ops function pointers to be per-kernel rather than per-hwmod since they do not vary by hwmod; added kerneldoc] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 62 ++++++++++++++++++++++------ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 + arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 + arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 + arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 + 6 files changed, 57 insertions(+), 12 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 939032a427f..634a79836c6 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -166,6 +166,23 @@ */ #define LINKS_PER_OCP_IF 2 +/** + * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations + * @enable_module: function to enable a module (via MODULEMODE) + * @disable_module: function to disable a module (via MODULEMODE) + * + * XXX Eventually this functionality will be hidden inside the PRM/CM + * device drivers. Until then, this should avoid huge blocks of cpu_is_*() + * conditionals in this code. + */ +struct omap_hwmod_soc_ops { + void (*enable_module)(struct omap_hwmod *oh); + int (*disable_module)(struct omap_hwmod *oh); +}; + +/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ +static struct omap_hwmod_soc_ops soc_ops; + /* omap_hwmod_list contains all registered struct omap_hwmods */ static LIST_HEAD(omap_hwmod_list); @@ -186,6 +203,9 @@ static struct omap_hwmod_link *linkspace; */ static unsigned short free_ls, max_ls, ls_supp; +/* inited: set to true once the hwmod code is initialized */ +static bool inited; + /* Private functions */ /** @@ -779,10 +799,6 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) */ static void _omap4_enable_module(struct omap_hwmod *oh) { - /* The module mode does not exist prior OMAP4 */ - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return; - if (!oh->clkdm || !oh->prcm.omap4.modulemode) return; @@ -1571,10 +1587,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh) { int v; - /* The module mode does not exist prior OMAP4 */ - if (!cpu_is_omap44xx()) - return -EINVAL; - if (!oh->clkdm || !oh->prcm.omap4.modulemode) return -EINVAL; @@ -1814,7 +1826,8 @@ static int _enable(struct omap_hwmod *oh) } _enable_clocks(oh); - _omap4_enable_module(oh); + if (soc_ops.enable_module) + soc_ops.enable_module(oh); r = _wait_target_ready(oh); if (!r) { @@ -1870,7 +1883,8 @@ static int _idle(struct omap_hwmod *oh) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); - _omap4_disable_module(oh); + if (soc_ops.disable_module) + soc_ops.disable_module(oh); /* * The module must be in idle mode before disabling any parents @@ -1975,7 +1989,8 @@ static int _shutdown(struct omap_hwmod *oh) if (oh->_state == _HWMOD_STATE_ENABLED) { _del_initiator_dep(oh, mpu_oh); /* XXX what about the other system initiators here? dma, dsp */ - _omap4_disable_module(oh); + if (soc_ops.disable_module) + soc_ops.disable_module(oh); _disable_clocks(oh); if (oh->clkdm) clkdm_hwmod_disable(oh->clkdm, oh); @@ -2563,12 +2578,18 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), * * Intended to be called early in boot before the clock framework is * initialized. If @ois is not null, will register all omap_hwmods - * listed in @ois that are valid for this chip. Returns 0. + * listed in @ois that are valid for this chip. Returns -EINVAL if + * omap_hwmod_init() hasn't been called before calling this function, + * -ENOMEM if the link memory area can't be allocated, or 0 upon + * success. */ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) { int r, i; + if (!inited) + return -EINVAL; + if (!ois) return 0; @@ -3401,3 +3422,20 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) return 0; } + +/** + * omap_hwmod_init - initialize the hwmod code + * + * Sets up some function pointers needed by the hwmod code to operate on the + * currently-booted SoC. Intended to be called once during kernel init + * before any hwmods are registered. No return value. + */ +void __init omap_hwmod_init(void) +{ + if (cpu_is_omap44xx()) { + soc_ops.enable_module = _omap4_enable_module; + soc_ops.disable_module = _omap4_disable_module; + } + + inited = true; +} diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a7640d1b215..5b1938b52d0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -585,5 +585,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { int __init omap2420_hwmod_init(void) { + omap_hwmod_init(); return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4d726498123..71f199783c6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -938,5 +938,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { int __init omap2430_hwmod_init(void) { + omap_hwmod_init(); return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); } diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index b26d3c9bca1..abb1f6b56ee 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -3283,6 +3283,8 @@ int __init omap3xxx_hwmod_init(void) struct omap_hwmod_ocp_if **h = NULL; unsigned int rev; + omap_hwmod_init(); + /* Register hwmod links common to all OMAP3 */ r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); if (r < 0) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 950454a3fa3..d3c48dc26af 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -6144,6 +6144,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { int __init omap44xx_hwmod_init(void) { + omap_hwmod_init(); return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); } diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b7194ff..a8ecc53b367 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -629,6 +629,8 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); +extern void __init omap_hwmod_init(void); + /* * Chip variant-specific hwmod init routines - XXX should be converted * to use initcalls once the initial boot ordering is straightened out -- cgit v1.2.3-70-g09d2 From d44f42e6af483cbdc239d7f28666e711d2e8ab92 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 18 Jun 2012 16:17:44 -0600 Subject: ARM: OMAP2+: CLEANUP: Remove ARCH_OMAPx ifdef from struct dpll_data There are certain fields inside 'struct dpll_data' which are included under ARCH_OMAP3 and ARCH_OMAP4 option, which makes it difficult to use it for new devices like, am33xx, ti81xx, etc... So remove the ifdef completely, this will add few fields to the struct unused, but it improves readability and maintainability of the code. Signed-off-by: Kevin Hilman [hvaibhav@ti.com: wrote detailed changelog] Signed-off-by: Vaibhav Hiremath Cc: Tony Lindgren Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: R Sricharan Acked-by: Santosh Shilimkar Signed-off-by: Paul Walmsley --- arch/arm/plat-omap/include/plat/clock.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index d0ef57c1d71..656b9862279 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -156,7 +156,6 @@ struct dpll_data { u8 min_divider; u16 max_divider; u8 modes; -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) void __iomem *autoidle_reg; void __iomem *idlest_reg; u32 autoidle_mask; @@ -167,7 +166,6 @@ struct dpll_data { u8 auto_recal_bit; u8 recal_en_bit; u8 recal_st_bit; -# endif u8 flags; }; -- cgit v1.2.3-70-g09d2 From 3d3635c4d77a97c61a539dff86f9a4b67134b4cb Mon Sep 17 00:00:00 2001 From: Omar Ramirez Luna Date: Mon, 18 Jun 2012 16:18:10 -0600 Subject: ARM: OMAP: dsp: interface to control module functions Provide an interface for a driver to call SCM functions to set a boot address and boot mode. Signed-off-by: Omar Ramirez Luna Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/dsp.c | 4 ++++ arch/arm/plat-omap/include/plat/dsp.h | 3 +++ 2 files changed, 7 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index 845309f146f..8b251a995ab 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -20,6 +20,7 @@ #include #include +#include "control.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" #ifdef CONFIG_BRIDGE_DVFS @@ -43,6 +44,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { .dsp_cm_read = omap2_cm_read_mod_reg, .dsp_cm_write = omap2_cm_write_mod_reg, .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, + + .set_bootaddr = omap_ctrl_write_dsp_boot_addr, + .set_bootmode = omap_ctrl_write_dsp_boot_mode, }; static phys_addr_t omap_dsp_phys_mempool_base; diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h index 9c604b390f9..5927709b190 100644 --- a/arch/arm/plat-omap/include/plat/dsp.h +++ b/arch/arm/plat-omap/include/plat/dsp.h @@ -18,6 +18,9 @@ struct omap_dsp_platform_data { u32 (*dsp_cm_read)(s16 , u16); u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); + void (*set_bootaddr)(u32); + void (*set_bootmode)(u8); + phys_addr_t phys_mempool_base; phys_addr_t phys_mempool_size; }; -- cgit v1.2.3-70-g09d2 From 59757c750fb3a89f172537a9e0ea2c6977771eee Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Thu, 28 Jun 2012 00:08:10 -0700 Subject: ARM: OMAP7XX: Remove omap730.h and omap850.h No file includes omap730.h or omap850.h. That's not surprising, as commit e6684f7132c6e6333e96407b06910bebaa4c1935 ("OMAP7XX: Create omap7xx.h") created a header that was "intended to replace omap730.h and omap850.h", while all "values defined [in omap7xx.h] are identical to those in both the old files". So it seems it was just an oversight to keep both the old files after commit 7a8f48f8c611ac8c07023260258e2fec312b9242 ("OMAP7XX: omap_uwire.c: Convert to omap7xx.h") converted the last file still including one of those two old files. Convert the last reference to omap730.h to a reference to omap7xx.h too. Signed-off-by: Paul Bolle Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/mux.h | 2 +- arch/arm/plat-omap/include/plat/omap730.h | 102 ------------------------------ arch/arm/plat-omap/include/plat/omap850.h | 102 ------------------------------ 3 files changed, 1 insertion(+), 205 deletions(-) delete mode 100644 arch/arm/plat-omap/include/plat/omap730.h delete mode 100644 arch/arm/plat-omap/include/plat/omap850.h (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index aeba71796ad..32394895920 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h @@ -99,7 +99,7 @@ /* * OMAP730/850 has a slightly different config for the pin mux. - * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and + * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and * not the FUNC_MUX_CTRL_x regs from hardware.h * - for pull-up/down, only has one enable bit which is is in the same register * as mux config diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h deleted file mode 100644 index 14272bc1a6f..00000000000 --- a/arch/arm/plat-omap/include/plat/omap730.h +++ /dev/null @@ -1,102 +0,0 @@ -/* arch/arm/plat-omap/include/mach/omap730.h - * - * Hardware definitions for TI OMAP730 processor. - * - * Cleanup for Linux-2.6 by Dirk Behme - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP730_H -#define __ASM_ARCH_OMAP730_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP730_DSP_BASE 0xE0000000 -#define OMAP730_DSP_SIZE 0x50000 -#define OMAP730_DSP_START 0xE0000000 - -#define OMAP730_DSPREG_BASE 0xE1000000 -#define OMAP730_DSPREG_SIZE SZ_128K -#define OMAP730_DSPREG_START 0xE1000000 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 specific configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_CONFIG_BASE 0xfffe1000 -#define OMAP730_IO_CONF_0 0xfffe1070 -#define OMAP730_IO_CONF_1 0xfffe1074 -#define OMAP730_IO_CONF_2 0xfffe1078 -#define OMAP730_IO_CONF_3 0xfffe107c -#define OMAP730_IO_CONF_4 0xfffe1080 -#define OMAP730_IO_CONF_5 0xfffe1084 -#define OMAP730_IO_CONF_6 0xfffe1088 -#define OMAP730_IO_CONF_7 0xfffe108c -#define OMAP730_IO_CONF_8 0xfffe1090 -#define OMAP730_IO_CONF_9 0xfffe1094 -#define OMAP730_IO_CONF_10 0xfffe1098 -#define OMAP730_IO_CONF_11 0xfffe109c -#define OMAP730_IO_CONF_12 0xfffe10a0 -#define OMAP730_IO_CONF_13 0xfffe10a4 - -#define OMAP730_MODE_1 0xfffe1010 -#define OMAP730_MODE_2 0xfffe1014 - -/* CSMI specials: in terms of base + offset */ -#define OMAP730_MODE2_OFFSET 0x14 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 traffic controller configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_FLASH_CFG_0 0xfffecc10 -#define OMAP730_FLASH_ACFG_0 0xfffecc50 -#define OMAP730_FLASH_CFG_1 0xfffecc14 -#define OMAP730_FLASH_ACFG_1 0xfffecc54 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 DSP control registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_ICR_BASE 0xfffbb800 -#define OMAP730_DSP_M_CTL 0xfffbb804 -#define OMAP730_DSP_MMU_BASE 0xfffed200 - -/* - * ---------------------------------------------------------------------------- - * OMAP730 PCC_UPLD configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900) -#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00) - -#endif /* __ASM_ARCH_OMAP730_H */ - diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h deleted file mode 100644 index c33f6798171..00000000000 --- a/arch/arm/plat-omap/include/plat/omap850.h +++ /dev/null @@ -1,102 +0,0 @@ -/* arch/arm/plat-omap/include/mach/omap850.h - * - * Hardware definitions for TI OMAP850 processor. - * - * Derived from omap730.h by Zebediah C. McClure - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP850_H -#define __ASM_ARCH_OMAP850_H - -/* - * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP850_DSP_BASE 0xE0000000 -#define OMAP850_DSP_SIZE 0x50000 -#define OMAP850_DSP_START 0xE0000000 - -#define OMAP850_DSPREG_BASE 0xE1000000 -#define OMAP850_DSPREG_SIZE SZ_128K -#define OMAP850_DSPREG_START 0xE1000000 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 specific configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_CONFIG_BASE 0xfffe1000 -#define OMAP850_IO_CONF_0 0xfffe1070 -#define OMAP850_IO_CONF_1 0xfffe1074 -#define OMAP850_IO_CONF_2 0xfffe1078 -#define OMAP850_IO_CONF_3 0xfffe107c -#define OMAP850_IO_CONF_4 0xfffe1080 -#define OMAP850_IO_CONF_5 0xfffe1084 -#define OMAP850_IO_CONF_6 0xfffe1088 -#define OMAP850_IO_CONF_7 0xfffe108c -#define OMAP850_IO_CONF_8 0xfffe1090 -#define OMAP850_IO_CONF_9 0xfffe1094 -#define OMAP850_IO_CONF_10 0xfffe1098 -#define OMAP850_IO_CONF_11 0xfffe109c -#define OMAP850_IO_CONF_12 0xfffe10a0 -#define OMAP850_IO_CONF_13 0xfffe10a4 - -#define OMAP850_MODE_1 0xfffe1010 -#define OMAP850_MODE_2 0xfffe1014 - -/* CSMI specials: in terms of base + offset */ -#define OMAP850_MODE2_OFFSET 0x14 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 traffic controller configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_FLASH_CFG_0 0xfffecc10 -#define OMAP850_FLASH_ACFG_0 0xfffecc50 -#define OMAP850_FLASH_CFG_1 0xfffecc14 -#define OMAP850_FLASH_ACFG_1 0xfffecc54 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 DSP control registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_ICR_BASE 0xfffbb800 -#define OMAP850_DSP_M_CTL 0xfffbb804 -#define OMAP850_DSP_MMU_BASE 0xfffed200 - -/* - * ---------------------------------------------------------------------------- - * OMAP850 PCC_UPLD configuration registers - * ---------------------------------------------------------------------------- - */ -#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900) -#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00) - -#endif /* __ASM_ARCH_OMAP850_H */ - -- cgit v1.2.3-70-g09d2 From d2ba779afc84b2e05dcb64cb801a4af52f1c4be7 Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Tue, 26 Jun 2012 23:12:47 +0200 Subject: ARM: OMAP: fix typos related to OMAP330 Signed-off-by: Paul Bolle Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 297245dba66..f2bdf15bdce 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -238,7 +238,7 @@ IS_AM_SUBCLASS(335x, 0x335) /* * Macros to detect individual cpu types. * These are only rarely needed. - * cpu_is_omap330(): True for OMAP330 + * cpu_is_omap310(): True for OMAP310 * cpu_is_omap730(): True for OMAP730 * cpu_is_omap850(): True for OMAP850 * cpu_is_omap1510(): True for OMAP1510 @@ -304,7 +304,7 @@ IS_OMAP_TYPE(3517, 0x3517) /* * Whether we have MULTI_OMAP1 or not, we still need to distinguish - * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710. + * between 730 vs 850, 310 vs. 1510 and 1611B/5912 vs. 1710. */ #if defined(CONFIG_ARCH_OMAP730) -- cgit v1.2.3-70-g09d2 From 0fb37842e47dd7f96725b86cb89a03dcecc72a46 Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Tue, 26 Jun 2012 23:13:29 +0200 Subject: ARM: OMAP: remove unused cpu detection macros Now that OMAP730 and OMAP850 support is mostly unified, there's no need for separate cpu detection macros for these architectures. At least, currently there isn't, because both macros are unused. cpu_is_7xx() seems to cover all possible uses. Signed-off-by: Paul Bolle [tony@atomide.com: updated to also to remove related IS_OMAP_TYPE] Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/cpu.h | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index f2bdf15bdce..e79e913d95d 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -239,8 +239,6 @@ IS_AM_SUBCLASS(335x, 0x335) * Macros to detect individual cpu types. * These are only rarely needed. * cpu_is_omap310(): True for OMAP310 - * cpu_is_omap730(): True for OMAP730 - * cpu_is_omap850(): True for OMAP850 * cpu_is_omap1510(): True for OMAP1510 * cpu_is_omap1610(): True for OMAP1610 * cpu_is_omap1611(): True for OMAP1611 @@ -264,8 +262,6 @@ static inline int is_omap ##type (void) \ } IS_OMAP_TYPE(310, 0x0310) -IS_OMAP_TYPE(730, 0x0730) -IS_OMAP_TYPE(850, 0x0850) IS_OMAP_TYPE(1510, 0x1510) IS_OMAP_TYPE(1610, 0x1610) IS_OMAP_TYPE(1611, 0x1611) @@ -281,8 +277,6 @@ IS_OMAP_TYPE(3505, 0x3517) IS_OMAP_TYPE(3517, 0x3517) #define cpu_is_omap310() 0 -#define cpu_is_omap730() 0 -#define cpu_is_omap850() 0 #define cpu_is_omap1510() 0 #define cpu_is_omap1610() 0 #define cpu_is_omap5912() 0 @@ -304,19 +298,9 @@ IS_OMAP_TYPE(3517, 0x3517) /* * Whether we have MULTI_OMAP1 or not, we still need to distinguish - * between 730 vs 850, 310 vs. 1510 and 1611B/5912 vs. 1710. + * between 310 vs. 1510 and 1611B/5912 vs. 1710. */ -#if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap730 -# define cpu_is_omap730() is_omap730() -#endif - -#if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap850 -# define cpu_is_omap850() is_omap850() -#endif - #if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap310 # undef cpu_is_omap1510 -- cgit v1.2.3-70-g09d2 From e30384abd63dfa11508a38243e1d78f1d70486b1 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Tue, 29 May 2012 15:26:41 +0530 Subject: ARM: OMAP3+: clock33xx: Add AM33XX clock tree data AM33XX clock implementation is different than any existing OMAP family of devices. Although DPLL module is similar to OMAP4 device, but the usage is very much different than OMAP4. AM33XX has different peripheral set and each module gets integrated to the clock framework differently than OMAP family of devices. This patch adds full Clock tree data for AM33XX family of devices and also integrates it into existing OMAP framework. Signed-off-by: Vaibhav Hiremath Signed-off-by: Afzal Mohammed Signed-off-by: Vaibhav Bedia Cc: Kevin Hilman Cc: Rajendra Nayak CC: Tony Lindgren Cc: Paul Walmsley Cc: Benoit Cousson [paul@pwsan.com: updated to apply; changed 'soc_is_am33xx' to 'cpu_is_am33xx' to match usage in Tony's current am33xx branch] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/clock.h | 2 + arch/arm/mach-omap2/clock33xx_data.c | 1105 +++++++++++++++++++++++++ arch/arm/mach-omap2/io.c | 2 + arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 + 5 files changed, 1112 insertions(+) create mode 100644 arch/arm/mach-omap2/clock33xx_data.c (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index a4cf93242b0..b167152ca69 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -152,6 +152,8 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 980b0a436c2..35ec5f3d9a7 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -167,4 +167,6 @@ extern const struct clksel_rate div31_1to31_rates[]; extern struct clk virt_19200000_ck; extern struct clk virt_26000000_ck; +extern int am33xx_clk_init(void); + #endif diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c new file mode 100644 index 00000000000..9c8ac7dc9f3 --- /dev/null +++ b/arch/arm/mach-omap2/clock33xx_data.c @@ -0,0 +1,1105 @@ +/* + * AM33XX Clock data + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "iomap.h" +#include "control.h" +#include "clock.h" +#include "cm.h" +#include "cm33xx.h" +#include "cm-regbits-33xx.h" +#include "prm.h" + +/* Maximum DPLL multiplier, divider values for AM33XX */ +#define AM33XX_MAX_DPLL_MULT 2047 +#define AM33XX_MAX_DPLL_DIV 128 + +/* Modulemode control */ +#define AM33XX_MODULEMODE_HWCTRL 0 +#define AM33XX_MODULEMODE_SWCTRL 1 + +/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always + * physically present, in such a case HWMOD enabling of + * clock would be failure with default parent. And timer + * probe thinks clock is already enabled, this leads to + * crash upon accessing timer 3 & 6 registers in probe. + * Fix by setting parent of both these timers to master + * oscillator clock. + */ +static inline void am33xx_init_timer_parent(struct clk *clk) +{ + omap2_clksel_set_parent(clk, clk->parent); +} + +/* Root clocks */ + +/* RTC 32k */ +static struct clk clk_32768_ck = { + .name = "clk_32768_ck", + .clkdm_name = "l4_rtc_clkdm", + .rate = 32768, + .ops = &clkops_null, +}; + +/* On-Chip 32KHz RC OSC */ +static struct clk clk_rc32k_ck = { + .name = "clk_rc32k_ck", + .rate = 32000, + .ops = &clkops_null, +}; + +/* Crystal input clks */ +static struct clk virt_24000000_ck = { + .name = "virt_24000000_ck", + .rate = 24000000, + .ops = &clkops_null, +}; + +static struct clk virt_25000000_ck = { + .name = "virt_25000000_ck", + .rate = 25000000, + .ops = &clkops_null, +}; + +/* Oscillator clock */ +/* 19.2, 24, 25 or 26 MHz */ +static const struct clksel sys_clkin_sel[] = { + { .parent = &virt_19200000_ck, .rates = div_1_0_rates }, + { .parent = &virt_24000000_ck, .rates = div_1_1_rates }, + { .parent = &virt_25000000_ck, .rates = div_1_2_rates }, + { .parent = &virt_26000000_ck, .rates = div_1_3_rates }, + { .parent = NULL }, +}; + +/* External clock - 12 MHz */ +static struct clk tclkin_ck = { + .name = "tclkin_ck", + .rate = 12000000, + .ops = &clkops_null, +}; + +/* + * sys_clk in: input to the dpll and also used as funtional clock for, + * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse + * + */ +static struct clk sys_clkin_ck = { + .name = "sys_clkin_ck", + .parent = &virt_24000000_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), + .clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK, + .clksel = sys_clkin_sel, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKDCOLDO output */ +static struct clk dpll_core_ck = { + .name = "dpll_core_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_core_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_omap3_core_dpll_ops, + .recalc = &omap3_dpll_recalc, +}; + +static struct clk dpll_core_x2_ck = { + .name = "dpll_core_x2_ck", + .parent = &dpll_core_ck, + .flags = CLOCK_CLKOUTX2, + .ops = &clkops_null, + .recalc = &omap3_clkoutx2_recalc, +}; + + +static const struct clksel dpll_core_m4_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_core_m4_ck = { + .name = "dpll_core_m4_ck", + .parent = &dpll_core_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel = dpll_core_m4_div, + .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE, + .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel dpll_core_m5_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_core_m5_ck = { + .name = "dpll_core_m5_ck", + .parent = &dpll_core_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel = dpll_core_m5_div, + .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE, + .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel dpll_core_m6_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_core_m6_ck = { + .name = "dpll_core_m6_ck", + .parent = &dpll_core_x2_ck, + .init = &omap2_init_clksel_parent, + .clksel = dpll_core_m6_div, + .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE, + .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_mpu_ck = { + .name = "dpll_mpu_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_mpu_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_omap3_noncore_dpll_ops, + .recalc = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +static const struct clksel dpll_mpu_m2_div[] = { + { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_mpu_m2_ck = { + .name = "dpll_mpu_m2_ck", + .clkdm_name = "mpu_clkdm", + .parent = &dpll_mpu_ck, + .clksel = dpll_mpu_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* DPLL_DDR */ +static struct dpll_data dpll_ddr_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_ddr_ck = { + .name = "dpll_ddr_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_ddr_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_null, + .recalc = &omap3_dpll_recalc, +}; + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +static const struct clksel dpll_ddr_m2_div[] = { + { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_ddr_m2_ck = { + .name = "dpll_ddr_m2_ck", + .parent = &dpll_ddr_ck, + .clksel = dpll_ddr_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* emif_fck functional clock */ +static struct clk dpll_ddr_m2_div2_ck = { + .name = "dpll_ddr_m2_div2_ck", + .clkdm_name = "l3_clkdm", + .parent = &dpll_ddr_m2_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +/* DPLL_DISP */ +static struct dpll_data dpll_disp_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_disp_ck = { + .name = "dpll_disp_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_disp_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_null, + .recalc = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +static const struct clksel dpll_disp_m2_div[] = { + { .parent = &dpll_disp_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_disp_m2_ck = { + .name = "dpll_disp_m2_ck", + .parent = &dpll_disp_ck, + .clksel = dpll_disp_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, + .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, + .div1_mask = AM33XX_DPLL_PER_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = AM33XX_MAX_DPLL_MULT, + .max_divider = AM33XX_MAX_DPLL_DIV, + .min_divider = 1, + .flags = DPLL_J_TYPE, +}; + +/* CLKDCOLDO */ +static struct clk dpll_per_ck = { + .name = "dpll_per_ck", + .parent = &sys_clkin_ck, + .dpll_data = &dpll_per_dd, + .init = &omap2_init_dpll_parent, + .ops = &clkops_null, + .recalc = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +/* CLKOUT: fdpll/M2 */ +static const struct clksel dpll_per_m2_div[] = { + { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +static struct clk dpll_per_m2_ck = { + .name = "dpll_per_m2_ck", + .parent = &dpll_per_ck, + .clksel = dpll_per_m2_div, + .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER, + .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk dpll_per_m2_div4_wkupdm_ck = { + .name = "dpll_per_m2_div4_wkupdm_ck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &dpll_per_m2_ck, + .fixed_div = 4, + .ops = &clkops_null, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk dpll_per_m2_div4_ck = { + .name = "dpll_per_m2_div4_ck", + .clkdm_name = "l4ls_clkdm", + .parent = &dpll_per_m2_ck, + .fixed_div = 4, + .ops = &clkops_null, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk l3_gclk = { + .name = "l3_gclk", + .clkdm_name = "l3_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk dpll_core_m4_div2_ck = { + .name = "dpll_core_m4_div2_ck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk l4_rtc_gclk = { + .name = "l4_rtc_gclk", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk clk_24mhz = { + .name = "clk_24mhz", + .parent = &dpll_per_m2_ck, + .fixed_div = 8, + .ops = &clkops_null, + .recalc = &omap_fixed_divisor_recalc, +}; + +/* + * Below clock nodes describes clockdomains derived out + * of core clock. + */ +static struct clk l4hs_gclk = { + .name = "l4hs_gclk", + .clkdm_name = "l4hs_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk l3s_gclk = { + .name = "l3s_gclk", + .clkdm_name = "l3s_clkdm", + .parent = &dpll_core_m4_div2_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk l4fw_gclk = { + .name = "l4fw_gclk", + .clkdm_name = "l4fw_clkdm", + .parent = &dpll_core_m4_div2_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk l4ls_gclk = { + .name = "l4ls_gclk", + .clkdm_name = "l4ls_clkdm", + .parent = &dpll_core_m4_div2_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk sysclk_div_ck = { + .name = "sysclk_div_ck", + .parent = &dpll_core_m4_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +/* + * In order to match the clock domain with hwmod clockdomain entry, + * separate clock nodes is required for the modules which are + * directly getting their funtioncal clock from sys_clkin. + */ +static struct clk adc_tsc_fck = { + .name = "adc_tsc_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk dcan0_fck = { + .name = "dcan0_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk dcan1_fck = { + .name = "dcan1_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk mcasp0_fck = { + .name = "mcasp0_fck", + .clkdm_name = "l3s_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk mcasp1_fck = { + .name = "mcasp1_fck", + .clkdm_name = "l3s_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk smartreflex0_fck = { + .name = "smartreflex0_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk smartreflex1_fck = { + .name = "smartreflex1_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_clkin_ck, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +/* + * Modules clock nodes + * + * The following clock leaf nodes are added for the moment because: + * + * - hwmod data is not present for these modules, either hwmod + * control is not required or its not populated. + * - Driver code is not yet migrated to use hwmod/runtime pm + * - Modules outside kernel access (to disable them by default) + * + * - debugss + * - mmu (gfx domain) + * - cefuse + * - usbotg_fck (its additional clock and not really a modulemode) + * - ieee5000 + */ +static struct clk debugss_ick = { + .name = "debugss_ick", + .clkdm_name = "l3_aon_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_omap2_dflt, + .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .recalc = &followparent_recalc, +}; + +static struct clk mmu_fck = { + .name = "mmu_fck", + .clkdm_name = "gfx_l3_clkdm", + .parent = &dpll_core_m4_ck, + .ops = &clkops_omap2_dflt, + .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .recalc = &followparent_recalc, +}; + +static struct clk cefuse_fck = { + .name = "cefuse_fck", + .clkdm_name = "l4_cefuse_clkdm", + .parent = &sys_clkin_ck, + .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +/* + * clkdiv32 is generated from fixed division of 732.4219 + */ +static struct clk clkdiv32k_ick = { + .name = "clkdiv32k_ick", + .clkdm_name = "clk_24mhz_clkdm", + .rate = 32768, + .parent = &clk_24mhz, + .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .ops = &clkops_omap2_dflt, +}; + +static struct clk usbotg_fck = { + .name = "usbotg_fck", + .clkdm_name = "l3s_clkdm", + .parent = &dpll_per_ck, + .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER, + .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk ieee5000_fck = { + .name = "ieee5000_fck", + .clkdm_name = "l3s_clkdm", + .parent = &dpll_core_m4_div2_ck, + .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +/* Timers */ +static const struct clksel timer1_clkmux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = &tclkin_ck, .rates = div_1_2_rates }, + { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, + { .parent = &clk_32768_ck, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static struct clk timer1_fck = { + .name = "timer1_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer1_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, + .clksel_mask = AM33XX_CLKSEL_0_2_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel timer2_to_7_clk_sel[] = { + { .parent = &tclkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk timer2_fck = { + .name = "timer2_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer3_fck = { + .name = "timer3_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &am33xx_init_timer_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer4_fck = { + .name = "timer4_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer5_fck = { + .name = "timer5_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer6_fck = { + .name = "timer6_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &am33xx_init_timer_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk timer7_fck = { + .name = "timer7_fck", + .clkdm_name = "l4ls_clkdm", + .parent = &sys_clkin_ck, + .init = &omap2_init_clksel_parent, + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk cpsw_125mhz_gclk = { + .name = "cpsw_125mhz_gclk", + .clkdm_name = "cpsw_125mhz_clkdm", + .parent = &dpll_core_m5_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { + { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk cpsw_cpts_rft_clk = { + .name = "cpsw_cpts_rft_clk", + .clkdm_name = "cpsw_125mhz_clkdm", + .parent = &dpll_core_m5_ck, + .clksel = cpsw_cpts_rft_clkmux_sel, + .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +/* gpio */ +static const struct clksel gpio0_dbclk_mux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clk_32768_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk gpio0_dbclk_mux_ck = { + .name = "gpio0_dbclk_mux_ck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &clk_rc32k_ck, + .init = &omap2_init_clksel_parent, + .clksel = gpio0_dbclk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk gpio0_dbclk = { + .name = "gpio0_dbclk", + .clkdm_name = "l4_wkup_clkdm", + .parent = &gpio0_dbclk_mux_ck, + .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk gpio1_dbclk = { + .name = "gpio1_dbclk", + .clkdm_name = "l4ls_clkdm", + .parent = &clkdiv32k_ick, + .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk gpio2_dbclk = { + .name = "gpio2_dbclk", + .clkdm_name = "l4ls_clkdm", + .parent = &clkdiv32k_ick, + .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static struct clk gpio3_dbclk = { + .name = "gpio3_dbclk", + .clkdm_name = "l4ls_clkdm", + .parent = &clkdiv32k_ick, + .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL, + .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, + .ops = &clkops_omap2_dflt, + .recalc = &followparent_recalc, +}; + +static const struct clksel pruss_ocp_clk_mux_sel[] = { + { .parent = &l3_gclk, .rates = div_1_0_rates }, + { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk pruss_ocp_gclk = { + .name = "pruss_ocp_gclk", + .clkdm_name = "pruss_ocp_clkdm", + .parent = &l3_gclk, + .init = &omap2_init_clksel_parent, + .clksel = pruss_ocp_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static const struct clksel lcd_clk_mux_sel[] = { + { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk lcd_gclk = { + .name = "lcd_gclk", + .clkdm_name = "lcdc_clkdm", + .parent = &dpll_disp_m2_ck, + .init = &omap2_init_clksel_parent, + .clksel = lcd_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static struct clk mmc_clk = { + .name = "mmc_clk", + .clkdm_name = "l4ls_clkdm", + .parent = &dpll_per_m2_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + +static struct clk mmc2_fck = { + .name = "mmc2_fck", + .clkdm_name = "l3s_clkdm", + .parent = &mmc_clk, + .ops = &clkops_null, + .recalc = &followparent_recalc, +}; + +static const struct clksel gfx_clksel_sel[] = { + { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk gfx_fclk_clksel_ck = { + .name = "gfx_fclk_clksel_ck", + .parent = &dpll_core_m4_ck, + .clksel = gfx_clksel_sel, + .ops = &clkops_null, + .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, + .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, + .recalc = &omap2_clksel_recalc, +}; + +static const struct clksel_rate div_1_0_2_1_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, + { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, + { .div = 0 }, +}; + +static const struct clksel gfx_div_sel[] = { + { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates }, + { .parent = NULL }, +}; + +static struct clk gfx_fck_div_ck = { + .name = "gfx_fck_div_ck", + .clkdm_name = "gfx_l3_clkdm", + .parent = &gfx_fclk_clksel_ck, + .init = &omap2_init_clksel_parent, + .clksel = gfx_div_sel, + .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, + .ops = &clkops_null, +}; + +static const struct clksel sysclkout_pre_sel[] = { + { .parent = &clk_32768_ck, .rates = div_1_0_rates }, + { .parent = &l3_gclk, .rates = div_1_1_rates }, + { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, + { .parent = &lcd_gclk, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static struct clk sysclkout_pre_ck = { + .name = "sysclkout_pre_ck", + .parent = &clk_32768_ck, + .init = &omap2_init_clksel_parent, + .clksel = sysclkout_pre_sel, + .clksel_reg = AM33XX_CM_CLKOUT_CTRL, + .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +/* Divide by 8 clock rates with default clock is 1/1*/ +static const struct clksel_rate div8_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, + { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, + { .div = 3, .val = 2, .flags = RATE_IN_AM33XX }, + { .div = 4, .val = 3, .flags = RATE_IN_AM33XX }, + { .div = 5, .val = 4, .flags = RATE_IN_AM33XX }, + { .div = 6, .val = 5, .flags = RATE_IN_AM33XX }, + { .div = 7, .val = 6, .flags = RATE_IN_AM33XX }, + { .div = 8, .val = 7, .flags = RATE_IN_AM33XX }, + { .div = 0 }, +}; + +static const struct clksel clkout2_div[] = { + { .parent = &sysclkout_pre_ck, .rates = div8_rates }, + { .parent = NULL }, +}; + +static struct clk clkout2_ck = { + .name = "clkout2_ck", + .parent = &sysclkout_pre_ck, + .ops = &clkops_omap2_dflt, + .clksel = clkout2_div, + .clksel_reg = AM33XX_CM_CLKOUT_CTRL, + .clksel_mask = AM33XX_CLKOUT2DIV_MASK, + .enable_reg = AM33XX_CM_CLKOUT_CTRL, + .enable_bit = AM33XX_CLKOUT2EN_SHIFT, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static const struct clksel wdt_clkmux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk wdt1_fck = { + .name = "wdt1_fck", + .clkdm_name = "l4_wkup_clkdm", + .parent = &clk_rc32k_ck, + .init = &omap2_init_clksel_parent, + .clksel = wdt_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +/* + * clkdev + */ +static struct omap_clk am33xx_clks[] = { + CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), + CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), + CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), + CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), + CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), + CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), + CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), + CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), + CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), + CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), + CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), + CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX), + CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX), + CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX), + CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), + CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), + CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), + CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX), + CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX), + CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX), + CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX), + CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX), + CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX), + CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX), + CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), + CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), + CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), + CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), + CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), + CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), + CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), + CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), + CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), + CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), + CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), + CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), + CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), + CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), + CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), + CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), + CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), + CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), + CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), + CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), + CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX), +}; + +int __init am33xx_clk_init(void) +{ + struct omap_clk *c; + u32 cpu_clkflg; + + if (cpu_is_am33xx()) { + cpu_mask = RATE_IN_AM33XX; + cpu_clkflg = CK_AM33XX; + } + + clk_init(&omap2_clk_functions); + + for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) + clk_preinit(c->lk.clk); + + for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + clk_register(c->lk.clk); + omap2_init_clk_clkdm(c->lk.clk); + } + } + + recalculate_root_clocks(); + + /* + * Only enable those clocks we will need, let the drivers + * enable other clocks as necessary + */ + clk_enable_init_clocks(); + + return 0; +} diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cb6c11cd8df..eb007d03ec9 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -38,6 +38,7 @@ #include "powerdomain.h" #include "clockdomain.h" #include "common.h" +#include "clock.h" #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" @@ -487,6 +488,7 @@ void __init am33xx_init_early(void) am33xx_voltagedomains_init(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); + am33xx_clk_init(); } #endif diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index d0ed8c443a6..025d85a3ee8 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h @@ -39,6 +39,7 @@ struct omap_clk { #define CK_443X (1 << 11) #define CK_TI816X (1 << 12) #define CK_446X (1 << 13) +#define CK_AM33XX (1 << 14) /* AM33xx specific clocks */ #define CK_1710 (1 << 15) /* 1710 extra for rate selection */ -- cgit v1.2.3-70-g09d2 From 248b3b3d841b01d0a5a55b746fc7e5e9edbe65e6 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Wed, 4 Jul 2012 03:40:59 -0600 Subject: ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx In case of AM33xx family of devices (like cpsw) have different sysc bit field offsets defined, sysc_type3: | 3 2 | 1 0 | | STDBYMODE | IDLEMODE | So introduce new sysc_type3 in omap_hwmod common data. Signed-off-by: Vaibhav Hiremath Signed-off-by: Vaibhav Bedia Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_common_data.c | 9 +++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 10 ++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 51e5418899f..6dd922ef80c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c @@ -49,6 +49,15 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, }; +/** + * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme. + * Used by some IPs on AM33xx + */ +struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = { + .midle_shift = SYSC_TYPE3_MIDLEMODE_SHIFT, + .sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT, +}; + struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = { .manager_count = 2, .has_framedonetv_irq = 0 diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b7194ff..2c171038696 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -41,6 +41,7 @@ struct omap_device; extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; +extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; /* * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant @@ -70,6 +71,15 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) +/* + * OCP SYSCONFIG bit shifts/masks TYPE3. + * This is applicable for some IPs present in AM33XX + */ +#define SYSC_TYPE3_SIDLEMODE_SHIFT 0 +#define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT) +#define SYSC_TYPE3_MIDLEMODE_SHIFT 2 +#define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT) + /* OCP SYSSTATUS bit shifts/masks */ #define SYSS_RESETDONE_SHIFT 0 #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) -- cgit v1.2.3-70-g09d2 From 768c69f5e9227a855a7bbb490b18628133fa891a Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Wed, 4 Jul 2012 03:41:03 -0600 Subject: ARM: OMAP3/4: omap_hwmod: Add rstst_offs field to struct omap_hwmod_omap4_prcm In case of AM33XX device, XXX_RSTST register offset is not consistent across PRM modules/instances, PRM_XXX RSTST ========================= PRM_PER_MOD: 0x04 PRM_WKUP_MOD: 0x0C PRM_MPU_MOD: NA PRM_DEVICE_MOD: 0x08 This means, we need to pass on XXX_RSTST register offset information through omap_hwmod data, similar to XXX_RSTCTRL. Currently, this field is only applicable and used for AM33XX devices. Signed-off-by: Vaibhav Hiremath Cc: Benoit Cousson Cc: Tony Lindgren Cc: Kevin Hilman Cc: Paul Walmsley Cc: Rajendra Nayak Signed-off-by: Paul Walmsley --- arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 2c171038696..7cb8d7dddcc 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -384,11 +384,13 @@ struct omap_hwmod_omap2_prcm { * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data * @clkctrl_reg: PRCM address of the clock control register * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM + * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM * @submodule_wkdep_bit: bit shift of the WKDEP range */ struct omap_hwmod_omap4_prcm { u16 clkctrl_offs; u16 rstctrl_offs; + u16 rstst_offs; u16 context_offs; u8 submodule_wkdep_bit; u8 modulemode; -- cgit v1.2.3-70-g09d2 From bed9d1bb4ed8c9bdaca77d31a2562c3a9dae43a7 Mon Sep 17 00:00:00 2001 From: Tarun Kanti DebBarma Date: Wed, 4 Jul 2012 05:00:48 -0600 Subject: ARM: OMAP2+: hwmod: add omap_hwmod_get_main_clk() API Add an API to get main clock name associated with a given @oh. This will avoid the need to construct fclk names during early initialization in order to get fclk handle using clk_get(). Signed-off-by: Tarun Kanti DebBarma Cc: Benoit Cousson Cc: Paul Walmsley Cc: Tony Lindgren Cc: Kevin Hilman Cc: Rajendra Nayak Cc: Santosh Shilimkar Acked-by: Benoit Cousson Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 15 +++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 ++ 2 files changed, 17 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 773193670ea..a89214ee469 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3401,3 +3401,18 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) return 0; } + +/** + * omap_hwmod_get_main_clk - get pointer to main clock name + * @oh: struct omap_hwmod * + * + * Returns the main clock name assocated with @oh upon success, + * or NULL if @oh is NULL. + */ +const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) +{ + if (!oh) + return NULL; + + return oh->main_clk; +} diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b7194ff..da22acd0ce7 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -629,6 +629,8 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); +const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); + /* * Chip variant-specific hwmod init routines - XXX should be converted * to use initcalls once the initial boot ordering is straightened out -- cgit v1.2.3-70-g09d2 From 6668546f3bb4cc0dde75ac1ef1d436b67e4ef638 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 4 Jul 2012 05:09:21 -0600 Subject: ARM: OMAP2+: hwmod code: add support to set dmadisable in hwmod framework The DMADISABLE bit is a semi-automatic bit present in sysconfig register of some modules. When the DMA must perform read/write accesses, the DMADISABLE bit is cleared by the hardware. But when the DMA must stop for power management, software must set the DMADISABLE bit back to 1. In cases where the ROMCODE/BOOTLOADER uses dma, the hardware clears the DMADISABLE bit (but the romcode/bootloader might not set it back to 1). In order for the kernel to start in a clean state, it is necessary for the kernel to set DMADISABLE bit back to 1 (irrespective of whether it's been set to 1 in romcode or bootloader). During _reset of the (hwmod)device, the DMADISABLE bit is set so that it does not prevent idling of the system. (NOTE: having DMADISABLE to 0, prevents the system to idle) DMADISABLE bit is present in usbotgss module of omap5. Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Signed-off-by: Kishon Vijay Abraham I [paul@pwsan.com: updated to apply; fixed checkpatch warnings] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 61 +++++++++++++++++++++++++--- arch/arm/mach-omap2/omap_hwmod_common_data.c | 1 + arch/arm/plat-omap/include/plat/omap_hwmod.h | 5 +++ 3 files changed, 62 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index a89214ee469..98cde62c0ca 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -387,6 +387,49 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v) return 0; } +/** + * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v + * @oh: struct omap_hwmod * + * + * The DMADISABLE bit is a semi-automatic bit present in sysconfig register + * of some modules. When the DMA must perform read/write accesses, the + * DMADISABLE bit is cleared by the hardware. But when the DMA must stop + * for power management, software must set the DMADISABLE bit back to 1. + * + * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon + * error or 0 upon success. + */ +static int _set_dmadisable(struct omap_hwmod *oh) +{ + u32 v; + u32 dmadisable_mask; + + if (!oh->class->sysc || + !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) + return -EINVAL; + + if (!oh->class->sysc->sysc_fields) { + WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); + return -EINVAL; + } + + /* clocks must be on for this operation */ + if (oh->_state != _HWMOD_STATE_ENABLED) { + pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); + return -EINVAL; + } + + pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); + + v = oh->_sysc_cache; + dmadisable_mask = + (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); + v |= dmadisable_mask; + _write_sysconfig(v, oh); + + return 0; +} + /** * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v * @oh: struct omap_hwmod * @@ -1698,11 +1741,17 @@ dis_opt_clks: * therefore have no OCP header registers to access. Others (like the * IVA) have idiosyncratic reset sequences. So for these relatively * rare cases, custom reset code can be supplied in the struct - * omap_hwmod_class .reset function pointer. Passes along the return - * value from either _ocp_softreset() or the custom reset function - - * these must return -EINVAL if the hwmod cannot be reset this way or - * if the hwmod is in the wrong state, -ETIMEDOUT if the module did - * not reset in time, or 0 upon success. + * omap_hwmod_class .reset function pointer. + * + * _set_dmadisable() is called to set the DMADISABLE bit so that it + * does not prevent idling of the system. This is necessary for cases + * where ROMCODE/BOOTLOADER uses dma and transfers control to the + * kernel without disabling dma. + * + * Passes along the return value from either _ocp_softreset() or the + * custom reset function - these must return -EINVAL if the hwmod + * cannot be reset this way or if the hwmod is in the wrong state, + * -ETIMEDOUT if the module did not reset in time, or 0 upon success. */ static int _reset(struct omap_hwmod *oh) { @@ -1724,6 +1773,8 @@ static int _reset(struct omap_hwmod *oh) } } + _set_dmadisable(oh); + /* * OCP_SYSCONFIG bits need to be reprogrammed after a * softreset. The _enable() function should be split to avoid diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 51e5418899f..aff61385291 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c @@ -47,6 +47,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { .midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT, .sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT, .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, + .dmadisable_shift = SYSC_TYPE2_DMADISABLE_SHIFT, }; struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = { diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index da22acd0ce7..27455ed0a2a 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -69,6 +69,8 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) +#define SYSC_TYPE2_DMADISABLE_SHIFT 16 +#define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT) /* OCP SYSSTATUS bit shifts/masks */ #define SYSS_RESETDONE_SHIFT 0 @@ -283,6 +285,7 @@ struct omap_hwmod_ocp_if { #define SYSS_HAS_RESET_STATUS (1 << 7) #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ #define SYSC_HAS_RESET_STATUS (1 << 9) +#define SYSC_HAS_DMADISABLE (1 << 10) /* omap_hwmod_sysconfig.clockact flags */ #define CLOCKACT_TEST_BOTH 0x0 @@ -298,6 +301,7 @@ struct omap_hwmod_ocp_if { * @enwkup_shift: Offset of the enawakeup bit * @srst_shift: Offset of the softreset bit * @autoidle_shift: Offset of the autoidle bit + * @dmadisable_shift: Offset of the dmadisable bit */ struct omap_hwmod_sysc_fields { u8 midle_shift; @@ -306,6 +310,7 @@ struct omap_hwmod_sysc_fields { u8 enwkup_shift; u8 srst_shift; u8 autoidle_shift; + u8 dmadisable_shift; }; /** -- cgit v1.2.3-70-g09d2 From 1c213ba16ed8f48fc12dfec8a588d608ffef0904 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Thu, 5 Jul 2012 08:05:15 -0700 Subject: ARM: OMAP2+: am33xx: Make am33xx as a separate class Initially, we decided to make am33xx family of device to fall under omap3 class (cpu_is_omap34xx() = true), since it carries Cortex-A8 core. But while adding complete baseport support (like, clock, power and hwmod) support, it is observed that, we are creating more and more problems by treating am33xx device as omap3 family, as nothing matches between them (except cortex-A8 mpu). So, after long discussion we have came to the conclusion that, we should not consider am33xx device as omap3 family, instead create separate class (SOC_AM33XX) under OMAP2PLUS. This means, for am33xx device, cpu_is_omap34xx() will return false, and only cpu_is_am33xx() will be true. Please refer to the link below, for mailing-list discussion on this - http://www.spinics.net/lists/linux-omap/msg69439.html Signed-off-by: Vaibhav Hiremath Cc: Kevin Hilman Cc: Paul Walmsley [tony@atomide.com: fixed typo, updated for soc_is changes] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 4 +++- arch/arm/mach-omap2/Makefile | 5 +++++ arch/arm/mach-omap2/common.c | 2 ++ arch/arm/plat-omap/include/plat/cpu.h | 9 ++++++--- arch/arm/plat-omap/sram.c | 2 +- 5 files changed, 17 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 042f157a8f9..3649a34db00 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -82,8 +82,10 @@ config SOC_TI81XX config SOC_AM33XX bool "AM33XX support" - depends on ARCH_OMAP3 default y + select CPU_V7 + select ARM_CPU_SUSPEND if PM + select MULTI_IRQ_HANDLER config OMAP_PACKAGE_ZAF bool diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 54ad3a4b612..846d44547fd 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -16,6 +16,7 @@ secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -100,6 +101,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o # OMAP powerdomain framework @@ -115,6 +117,7 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o @@ -132,6 +135,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o @@ -151,6 +155,7 @@ obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 8a6953a34fe..a7aa538e681 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -134,7 +134,9 @@ void __init ti81xx_map_io(void) { omapti81xx_map_common_io(); } +#endif +#if defined(CONFIG_SOC_AM33XX) #define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \ TI81XX_CONTROL_DEVICE_ID - 0x204) diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index de6c0a08f46..4f9d60192ef 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -344,8 +344,6 @@ IS_OMAP_TYPE(3430, 0x3430) # undef cpu_is_ti816x # undef cpu_is_ti814x # undef soc_is_am35xx -# undef cpu_is_am33xx -# undef cpu_is_am335x # define cpu_is_omap3430() is_omap3430() # undef cpu_is_omap3630 # define cpu_is_omap3630() is_omap363x() @@ -353,6 +351,11 @@ IS_OMAP_TYPE(3430, 0x3430) # define cpu_is_ti816x() is_ti816x() # define cpu_is_ti814x() is_ti814x() # define soc_is_am35xx() is_am35xx() +#endif + +# if defined(CONFIG_SOC_AM33XX) +# undef cpu_is_am33xx +# undef cpu_is_am335x # define cpu_is_am33xx() is_am33xx() # define cpu_is_am335x() is_am335x() #endif @@ -408,7 +411,7 @@ IS_OMAP_TYPE(3430, 0x3430) #define AM35XX_REV_ES1_0 AM35XX_CLASS #define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8)) -#define AM335X_CLASS 0x33500034 +#define AM335X_CLASS 0x33500033 #define AM335X_REV_ES1_0 AM335X_CLASS #define OMAP443X_CLASS 0x44300044 diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 477363c163e..564cb4c84b1 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -85,7 +85,7 @@ static int is_sram_locked(void) __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ } - if (cpu_is_omap34xx() && !cpu_is_am33xx()) { + if (cpu_is_omap34xx()) { __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ -- cgit v1.2.3-70-g09d2 From 971b8a9c3eeb798f6201299728fdbb04ebb681c6 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Thu, 5 Jul 2012 08:05:15 -0700 Subject: ARM: OMAP2+: am33xx: Change cpu_is_am33xx to soc_is_am33xx As per recent discussion on the linux-omap list, we are moving in the direction where, we will have only architecture, ARCH_OMAP2PLUS and all devices/platforms will be treated as a SoC underneath. So the first step in this direction is to adopt this change for all new devices getting in, converting cpu_is_am33xx/335x() ==> soc_is_am33xx/335x() Signed-off-by: Vaibhav Hiremath Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock3xxx_data.c | 2 +- arch/arm/mach-omap2/id.c | 4 ++-- arch/arm/plat-omap/include/plat/cpu.h | 12 ++++++------ arch/arm/plat-omap/sram.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 71a1d338380..7300982a8e0 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3491,7 +3491,7 @@ int __init omap3xxx_clk_init(void) } else if (cpu_is_ti816x()) { cpu_mask = RATE_IN_TI816X; cpu_clkflg = CK_TI816X; - } else if (cpu_is_am33xx()) { + } else if (soc_is_am33xx()) { cpu_mask = RATE_IN_AM33XX; } else if (cpu_is_ti814x()) { cpu_mask = RATE_IN_TI814X; diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 00486a8564f..37eb95aaf2f 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -44,7 +44,7 @@ int omap_type(void) if (cpu_is_omap24xx()) { val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); - } else if (cpu_is_am33xx()) { + } else if (soc_is_am33xx()) { val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); @@ -189,7 +189,7 @@ static void __init omap3_cpuinfo(void) cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; } else if (cpu_is_ti816x()) { cpu_name = "TI816X"; - } else if (cpu_is_am335x()) { + } else if (soc_is_am335x()) { cpu_name = "AM335X"; } else if (cpu_is_ti814x()) { cpu_name = "TI814X"; diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 4f9d60192ef..14f050f7a89 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -150,8 +150,8 @@ IS_AM_SUBCLASS(335x, 0x335) #define cpu_is_ti816x() 0 #define cpu_is_ti814x() 0 #define soc_is_am35xx() 0 -#define cpu_is_am33xx() 0 -#define cpu_is_am335x() 0 +#define soc_is_am33xx() 0 +#define soc_is_am335x() 0 #define cpu_is_omap44xx() 0 #define cpu_is_omap443x() 0 #define cpu_is_omap446x() 0 @@ -354,10 +354,10 @@ IS_OMAP_TYPE(3430, 0x3430) #endif # if defined(CONFIG_SOC_AM33XX) -# undef cpu_is_am33xx -# undef cpu_is_am335x -# define cpu_is_am33xx() is_am33xx() -# define cpu_is_am335x() is_am335x() +# undef soc_is_am33xx +# undef soc_is_am335x +# define soc_is_am33xx() is_am33xx() +# define soc_is_am335x() is_am335x() #endif # if defined(CONFIG_ARCH_OMAP4) diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 564cb4c84b1..70cf825bdd8 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -123,7 +123,7 @@ static void __init omap_detect_sram(void) omap_sram_size = 0x800; /* 2K */ } } else { - if (cpu_is_am33xx()) { + if (soc_is_am33xx()) { omap_sram_start = AM33XX_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap34xx()) { @@ -386,7 +386,7 @@ int __init omap_sram_init(void) omap242x_sram_init(); else if (cpu_is_omap2430()) omap243x_sram_init(); - else if (cpu_is_am33xx()) + else if (soc_is_am33xx()) am33xx_sram_init(); else if (cpu_is_omap34xx()) omap34xx_sram_init(); -- cgit v1.2.3-70-g09d2 From 68c9a95e9253ce1776bd21bf8d37ddf213cced66 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 6 Jul 2012 00:58:43 -0700 Subject: ARM: OMAP2+: Fix mismerge for omap_hwmod_get_main_clk() API Commit ac5b0ea3d (Merge tag 'omap-devel-f-for-3.6'...) had a merge conflict that somehow got incorrecly resolved in a lossy way for commit bed9d1bb (ARM: OMAP2+: hwmod: add omap_hwmod_get_main_clk() API). Fix the issue by applying the missing pieces. Reported-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 15 +++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 ++ 2 files changed, 17 insertions(+) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index ebdf0016e53..ff76ef1d723 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3633,3 +3633,18 @@ void __init omap_hwmod_init(void) inited = true; } + +/** + * omap_hwmod_get_main_clk - get pointer to main clock name + * @oh: struct omap_hwmod * + * + * Returns the main clock name assocated with @oh upon success, + * or NULL if @oh is NULL. + */ +const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) +{ + if (!oh) + return NULL; + + return oh->main_clk; +} diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 30f55eb8b0b..6132972aff3 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -648,6 +648,8 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); extern void __init omap_hwmod_init(void); +const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); + /* * Chip variant-specific hwmod init routines - XXX should be converted * to use initcalls once the initial boot ordering is straightened out -- cgit v1.2.3-70-g09d2 From fb584511c4664573097ece7df0de06ad00b713a2 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Fri, 6 Jul 2012 14:55:42 +0530 Subject: ARM: OMAP: sdrc: Fix the build break for OMAP4 only builds OMAP4 only build breaks with below error arch/arm/mach-omap2/sdrc.c:135: error: redefinition of 'omap2_sdrc_init' arch/arm/plat-omap/include/plat/sdrc.h:130: note: previous definition of 'omap2_sdrc_init' was here make[1]: *** [arch/arm/mach-omap2/sdrc.o] Error 1 Fix the same by using newly introduced CONFIG_SOC_HAS_OMAP2_SDRC marco. Cc: Tony Lindgren Signed-off-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/sdrc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h index 9bb978ecd88..36d6a766621 100644 --- a/arch/arm/plat-omap/include/plat/sdrc.h +++ b/arch/arm/plat-omap/include/plat/sdrc.h @@ -123,7 +123,7 @@ struct omap_sdrc_params { u32 mr; }; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#ifdef CONFIG_SOC_HAS_OMAP2_SDRC void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); #else -- cgit v1.2.3-70-g09d2 From e799840a09c7e4b7e94d08a7b8c3ec4ba81611f9 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 10 May 2012 21:27:20 +0530 Subject: ARM: OMAP2+: Move stubbed secure_sram_reserve function to a common.c and call it __weak omap_secure_ram_reserve_memblock is stubbed for OMAP1,2 only builds using a ifdef check. But this results in adding CONFIG_ARCH_OMAPxx checks for future socs that use the real function. So move this to common.c file and call it __weak. Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar --- arch/arm/plat-omap/common.c | 9 +++++++++ arch/arm/plat-omap/include/plat/omap-secure.h | 5 ----- 2 files changed, 9 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 0a9b9a97011..89a3723b353 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -77,3 +77,12 @@ void __init omap_init_consistent_dma_size(void) init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20); #endif } + +/* + * Stub function for OMAP2 so that common files + * continue to build when custom builds are used + */ +int __weak omap_secure_ram_reserve_memblock(void) +{ + return 0; +} diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h index 8c7994ce986..0e4acd2d2de 100644 --- a/arch/arm/plat-omap/include/plat/omap-secure.h +++ b/arch/arm/plat-omap/include/plat/omap-secure.h @@ -3,12 +3,7 @@ #include -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) extern int omap_secure_ram_reserve_memblock(void); -#else -static inline void omap_secure_ram_reserve_memblock(void) -{ } -#endif #ifdef CONFIG_OMAP4_ERRATA_I688 extern int omap_barrier_reserve_memblock(void); -- cgit v1.2.3-70-g09d2 From b13e80a8bfe442406495a2fc9e7cbb79d33df48a Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Thu, 19 Apr 2012 17:42:19 +0530 Subject: ARM: OMAP5: id: Add cpu id for ES versions Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision detection support. Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/control.h | 4 ++++ arch/arm/mach-omap2/id.c | 42 ++++++++++++++++++++++++++++++++++- arch/arm/plat-omap/include/plat/cpu.h | 22 ++++++++++++++++-- 3 files changed, 65 insertions(+), 3 deletions(-) (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index 295b39047a7..b8cdc8531b6 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -253,6 +253,10 @@ /* TI81XX CONTROL_DEVCONF register offsets */ #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) +/* OMAP54XX CONTROL STATUS register */ +#define OMAP5XXX_CONTROL_STATUS 0x134 +#define OMAP5_DEVICETYPE_MASK (0x7 << 6) + /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37eb95aaf2f..40373db649a 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -50,6 +50,11 @@ int omap_type(void) val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); + } else if (soc_is_omap54xx()) { + val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); + val &= OMAP5_DEVICETYPE_MASK; + val >>= 6; + goto out; } else { pr_err("Cannot detect omap type!\n"); goto out; @@ -100,7 +105,7 @@ static u16 tap_prod_id; void omap_get_die_id(struct omap_die_id *odi) { - if (cpu_is_omap44xx()) { + if (cpu_is_omap44xx() || soc_is_omap54xx()) { odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); @@ -513,6 +518,41 @@ void __init omap4xxx_check_revision(void) ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); } +void __init omap5xxx_check_revision(void) +{ + u32 idcode; + u16 hawkeye; + u8 rev; + + idcode = read_tap_reg(OMAP_TAP_IDCODE); + hawkeye = (idcode >> 12) & 0xffff; + rev = (idcode >> 28) & 0xff; + switch (hawkeye) { + case 0xb942: + switch (rev) { + case 0: + default: + omap_revision = OMAP5430_REV_ES1_0; + } + break; + + case 0xb998: + switch (rev) { + case 0: + default: + omap_revision = OMAP5432_REV_ES1_0; + } + break; + + default: + /* Unknown default to latest silicon rev as default*/ + omap_revision = OMAP5430_REV_ES1_0; + } + + pr_info("OMAP%04x ES%d.0\n", + omap_rev() >> 16, ((omap_rev() >> 12) & 0xf)); +} + /* * Set up things for map_io and processor detection later on. Gets called * pretty much first thing from board init. For multi-omap, this gets diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 14f050f7a89..e2d911d16fb 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -9,7 +9,7 @@ * * Written by Tony Lindgren * - * Added OMAP4 specific defines - Santosh Shilimkar + * Added OMAP4/5 specific defines - Santosh Shilimkar * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -70,6 +70,7 @@ unsigned int omap_rev(void); * cpu_is_omap443x(): True for OMAP4430 * cpu_is_omap446x(): True for OMAP4460 * cpu_is_omap447x(): True for OMAP4470 + * soc_is_omap543x(): True for OMAP5430, OMAP5432 */ #define GET_OMAP_CLASS (omap_rev() & 0xff) @@ -122,6 +123,7 @@ IS_OMAP_CLASS(24xx, 0x24) IS_OMAP_CLASS(34xx, 0x34) IS_OMAP_CLASS(44xx, 0x44) IS_AM_CLASS(35xx, 0x35) +IS_OMAP_CLASS(54xx, 0x54) IS_AM_CLASS(33xx, 0x33) IS_TI_CLASS(81xx, 0x81) @@ -133,6 +135,7 @@ IS_OMAP_SUBCLASS(363x, 0x363) IS_OMAP_SUBCLASS(443x, 0x443) IS_OMAP_SUBCLASS(446x, 0x446) IS_OMAP_SUBCLASS(447x, 0x447) +IS_OMAP_SUBCLASS(543x, 0x543) IS_TI_SUBCLASS(816x, 0x816) IS_TI_SUBCLASS(814x, 0x814) @@ -156,6 +159,8 @@ IS_AM_SUBCLASS(335x, 0x335) #define cpu_is_omap443x() 0 #define cpu_is_omap446x() 0 #define cpu_is_omap447x() 0 +#define soc_is_omap54xx() 0 +#define soc_is_omap543x() 0 #if defined(MULTI_OMAP1) # if defined(CONFIG_ARCH_OMAP730) @@ -291,6 +296,7 @@ IS_OMAP_TYPE(3430, 0x3430) #define cpu_is_omap2430() 0 #define cpu_is_omap3430() 0 #define cpu_is_omap3630() 0 +#define soc_is_omap5430() 0 /* * Whether we have MULTI_OMAP1 or not, we still need to distinguish @@ -371,11 +377,18 @@ IS_OMAP_TYPE(3430, 0x3430) # define cpu_is_omap447x() is_omap447x() # endif +# if defined(CONFIG_SOC_OMAP5) +# undef soc_is_omap54xx +# undef soc_is_omap543x +# define soc_is_omap54xx() is_omap54xx() +# define soc_is_omap543x() is_omap543x() +#endif + /* Macros to detect if we have OMAP1 or OMAP2 */ #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ cpu_is_omap16xx()) #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ - cpu_is_omap44xx()) + cpu_is_omap44xx() || soc_is_omap54xx()) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 @@ -428,9 +441,14 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP447X_CLASS 0x44700044 #define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) +#define OMAP54XX_CLASS 0x54000054 +#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) +#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) + void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); void omap4xxx_check_revision(void); +void omap5xxx_check_revision(void); void omap3xxx_check_features(void); void ti81xx_check_features(void); void omap4xxx_check_features(void); -- cgit v1.2.3-70-g09d2 From 05e152c76a1efaa3165afecf5acf535c8283f386 Mon Sep 17 00:00:00 2001 From: R Sricharan Date: Tue, 5 Jun 2012 16:21:32 +0530 Subject: ARM: OMAP5: Add minimal support for OMAP5430 SOC OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller. OMAP5432 is another variant of OMAP5430, with a memory controller supporting DDR3 and SATA. Patch includes: - The machine specific headers and sources updates. - Platform header updates. - Minimum initialisation support for serial. - IO table init Signed-off-by: R Sricharan Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/Makefile | 23 +++++++++++--- arch/arm/mach-omap2/common.c | 24 ++++++++++++++ arch/arm/mach-omap2/common.h | 11 +++++++ arch/arm/mach-omap2/include/mach/debug-macro.S | 8 ++--- arch/arm/mach-omap2/io.c | 44 ++++++++++++++++++++++++++ arch/arm/mach-omap2/iomap.h | 27 ++++++++++++++++ arch/arm/mach-omap2/omap_hwmod.c | 2 +- arch/arm/mach-omap2/prcm-common.h | 2 +- arch/arm/mach-omap2/prcm.c | 2 +- arch/arm/plat-omap/include/plat/hardware.h | 1 + arch/arm/plat-omap/include/plat/multi.h | 9 ++++++ arch/arm/plat-omap/include/plat/omap54xx.h | 32 +++++++++++++++++++ arch/arm/plat-omap/include/plat/serial.h | 10 ++++++ arch/arm/plat-omap/include/plat/uncompress.h | 6 ++++ arch/arm/plat-omap/sram.c | 11 +++++-- 15 files changed, 198 insertions(+), 14 deletions(-) create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h (limited to 'arch/arm/plat-omap/include') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 240f1969f2a..085e17175ef 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) +obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -29,8 +30,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o +omap-4-5-common = omap4-common.o omap-wakeupgen.o \ + sleep44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -70,6 +73,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o @@ -85,14 +89,16 @@ endif endif # PRCM +omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \ + prcm_mpu44xx.o prminst44xx.o \ + vc44xx_data.o vp44xx_data.o obj-y += prm_common.o obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o -obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o -obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -104,6 +110,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -121,6 +128,8 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) +obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -139,6 +148,8 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) +obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o @@ -157,6 +168,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_OMAP5) += $(clock-common) +obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 73d2a0b9ca0..069f9725b1c 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -178,3 +178,27 @@ void __init omap4_map_io(void) } #endif +#if defined(CONFIG_SOC_OMAP5) +static struct omap_globals omap5_globals = { + .class = OMAP54XX_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + .ctrl = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE), + .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE), + .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), + .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE), + .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE), +}; + +void __init omap2_set_globals_5xxx(void) +{ + omap2_set_globals_tap(&omap5_globals); + omap2_set_globals_control(&omap5_globals); + omap2_set_globals_prcm(&omap5_globals); +} + +void __init omap5_map_io(void) +{ + omap5_map_common_io(); +} +#endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 404f172d95a..399e5bb1383 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -115,6 +115,14 @@ static inline int omap_mux_late_init(void) } #endif +#ifdef CONFIG_SOC_OMAP5 +extern void omap5_map_common_io(void); +#else +static inline void omap5_map_common_io(void) +{ +} +#endif + extern void omap2_init_common_infrastructure(void); extern struct sys_timer omap2_timer; @@ -134,6 +142,7 @@ void am35xx_init_early(void); void ti81xx_init_early(void); void am33xx_init_early(void); void omap4430_init_early(void); +void omap5_init_early(void); void omap3_init_late(void); /* Do not use this one */ void omap4430_init_late(void); void omap2420_init_late(void); @@ -169,6 +178,7 @@ void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_3xxx(void); void omap2_set_globals_443x(void); +void omap2_set_globals_5xxx(void); void omap2_set_globals_ti81xx(void); void omap2_set_globals_am33xx(void); @@ -188,6 +198,7 @@ void omap243x_map_io(void); void omap3_map_io(void); void am33xx_map_io(void); void omap4_map_io(void); +void omap5_map_io(void); void ti81xx_map_io(void); void omap_barriers_init(void); diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index d7f844a99a7..93d10de7129 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -60,12 +60,12 @@ omap_uart_lsr: .word 0 beq 23f @ configure OMAP2UART3 cmp \rp, #OMAP3UART3 @ only on 34xx beq 33f @ configure OMAP3UART3 - cmp \rp, #OMAP4UART3 @ only on 44xx - beq 43f @ configure OMAP4UART3 + cmp \rp, #OMAP4UART3 @ only on 44xx/54xx + beq 43f @ configure OMAP4/5UART3 cmp \rp, #OMAP3UART4 @ only on 36xx beq 34f @ configure OMAP3UART4 - cmp \rp, #OMAP4UART4 @ only on 44xx - beq 44f @ configure OMAP4UART4 + cmp \rp, #OMAP4UART4 @ only on 44xx/54xx + beq 44f @ configure OMAP4/5UART4 cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different beq 81f @ configure UART1 cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cb6c11cd8df..8976be90c8e 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -233,6 +233,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = { }; #endif +#ifdef CONFIG_SOC_OMAP5 +static struct map_desc omap54xx_io_desc[] __initdata = { + { + .virtual = L3_54XX_VIRT, + .pfn = __phys_to_pfn(L3_54XX_PHYS), + .length = L3_54XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_54XX_VIRT, + .pfn = __phys_to_pfn(L4_54XX_PHYS), + .length = L4_54XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_WK_54XX_VIRT, + .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), + .length = L4_WK_54XX_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = L4_PER_54XX_VIRT, + .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), + .length = L4_PER_54XX_SIZE, + .type = MT_DEVICE, + }, +}; +#endif + #ifdef CONFIG_SOC_OMAP2420 void __init omap242x_map_common_io(void) { @@ -278,6 +307,12 @@ void __init omap44xx_map_common_io(void) } #endif +#ifdef CONFIG_SOC_OMAP5 +void __init omap5_map_common_io(void) +{ + iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); +} +#endif /* * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters * @@ -513,6 +548,15 @@ void __init omap4430_init_late(void) } #endif +#ifdef CONFIG_SOC_OMAP5 +void __init omap5_init_early(void) +{ + omap2_set_globals_5xxx(); + omap5xxx_check_revision(); + omap_common_init_early(); +} +#endif + void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h index 80b88921fab..cce2b65039f 100644 --- a/arch/arm/mach-omap2/iomap.h +++ b/arch/arm/mach-omap2/iomap.h @@ -1,6 +1,14 @@ /* * IO mappings for OMAP2+ * + * IO definitions for TI OMAP processors and boards + * + * Copied from arch/arm/mach-sa1100/include/mach/io.h + * Copyright (C) 1997-1999 Russell King + * + * Copyright (C) 2009-2012 Texas Instruments + * Added OMAP4/5 support - Santosh Shilimkar + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -166,4 +174,23 @@ /* 0x49000000 --> 0xfb000000 */ #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) #define L4_ABE_44XX_SIZE SZ_1M +/* + * ---------------------------------------------------------------------------- + * Omap5 specific IO mapping + * ---------------------------------------------------------------------------- + */ +#define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */ +#define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET) +#define L3_54XX_SIZE SZ_1M + +#define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */ +#define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_54XX_SIZE SZ_4M + +#define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */ +#define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_WK_54XX_SIZE SZ_2M +#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */ +#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET) +#define L4_PER_54XX_SIZE SZ_4M diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index ff76ef1d723..2ada3642c67 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3619,7 +3619,7 @@ void __init omap_hwmod_init(void) soc_ops.assert_hardreset = _omap2_assert_hardreset; soc_ops.deassert_hardreset = _omap2_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; - } else if (cpu_is_omap44xx()) { + } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; soc_ops.wait_target_ready = _omap4_wait_target_ready; diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 6da3ba483ad..44485a8f255 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -416,7 +416,7 @@ extern void __iomem *cm_base; extern void __iomem *cm2_base; extern void __iomem *prcm_mpu_base; -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5) +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) extern void omap_prm_base_init(void); extern void omap_cm_base_init(void); #else diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 28cbfb2b573..053e24ed3c4 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -160,7 +160,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) if (omap2_globals->prcm_mpu) prcm_mpu_base = omap2_globals->prcm_mpu; - if (cpu_is_omap44xx()) { + if (cpu_is_omap44xx() || soc_is_omap54xx()) { omap_prm_base_init(); omap_cm_base_init(); } diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h index e897978371c..ddbde38e1e3 100644 --- a/arch/arm/plat-omap/include/plat/hardware.h +++ b/arch/arm/plat-omap/include/plat/hardware.h @@ -288,5 +288,6 @@ #include #include #include +#include #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h index 999ffba2690..045e320f106 100644 --- a/arch/arm/plat-omap/include/plat/multi.h +++ b/arch/arm/plat-omap/include/plat/multi.h @@ -99,4 +99,13 @@ # endif #endif +#ifdef CONFIG_SOC_OMAP5 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap5 +# endif +#endif + #endif /* __PLAT_OMAP_MULTI_H */ diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h new file mode 100644 index 00000000000..a2582bb3cab --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap54xx.h @@ -0,0 +1,32 @@ +/*: + * Address mappings and base address for OMAP5 interconnects + * and peripherals. + * + * Copyright (C) 2012 Texas Instruments + * Santosh Shilimkar + * Sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_SOC_OMAP54XX_H +#define __ASM_SOC_OMAP54XX_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ +#define L4_54XX_BASE 0x4a000000 +#define L4_WK_54XX_BASE 0x4ae00000 +#define L4_PER_54XX_BASE 0x48000000 +#define L3_54XX_BASE 0x44000000 +#define OMAP54XX_32KSYNCT_BASE 0x4ae04000 +#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 +#define OMAP54XX_CM_CORE_BASE 0x4a008000 +#define OMAP54XX_PRM_BASE 0x4ae06000 +#define OMAP54XX_PRCM_MPU_BASE 0x48243000 +#define OMAP54XX_SCM_BASE 0x4a002000 +#define OMAP54XX_CTRL_BASE 0x4a002800 + +#endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 28e2d250c2f..65fce44dce3 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -63,6 +63,14 @@ /* AM33XX serial port */ #define AM33XX_UART1_BASE 0x44E09000 +/* OMAP5 serial ports */ +#define OMAP5_UART1_BASE OMAP2_UART1_BASE +#define OMAP5_UART2_BASE OMAP2_UART2_BASE +#define OMAP5_UART3_BASE OMAP4_UART3_BASE +#define OMAP5_UART4_BASE OMAP4_UART4_BASE +#define OMAP5_UART5_BASE 0x48066000 +#define OMAP5_UART6_BASE 0x48068000 + /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 @@ -97,6 +105,8 @@ #define TI81XXUART2 82 #define TI81XXUART3 83 #define AM33XXUART1 84 +#define OMAP5UART3 OMAP4UART3 +#define OMAP5UART4 OMAP4UART4 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ac432339021..b8d19a13678 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -95,6 +95,9 @@ static inline void flush(void) _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \ OMAP4UART##p) +#define DEBUG_LL_OMAP5(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP5UART##p) /* Zoom2/3 shift is different for UART1 and external port */ #define DEBUG_LL_ZOOM(mach) \ _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) @@ -177,6 +180,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_OMAP4(3, omap_4430sdp); DEBUG_LL_OMAP4(3, omap4_panda); + /* omap5 based boards using UART3 */ + DEBUG_LL_OMAP5(3, omap5_sevm); + /* zoom2/3 external uart */ DEBUG_LL_ZOOM(omap_zoom2); DEBUG_LL_ZOOM(omap_zoom3); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 70cf825bdd8..766181cb5c9 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -6,8 +6,8 @@ * Copyright (C) 2005 Nokia Corporation * Written by Tony Lindgren * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar + * Copyright (C) 2009-2012 Texas Instruments + * Added OMAP4/5 support - Santosh Shilimkar * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -44,6 +44,7 @@ #else #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #endif +#define OMAP5_SRAM_PA 0x40300000 #if defined(CONFIG_ARCH_OMAP2PLUS) #define SRAM_BOOTLOADER_SZ 0x00 @@ -118,6 +119,9 @@ static void __init omap_detect_sram(void) } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PUB_PA; omap_sram_size = 0xa000; /* 40K */ + } else if (soc_is_omap54xx()) { + omap_sram_start = OMAP5_SRAM_PA; + omap_sram_size = SZ_128K; /* 128KB */ } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ @@ -132,6 +136,9 @@ static void __init omap_detect_sram(void) } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PA; omap_sram_size = 0xe000; /* 56K */ + } else if (soc_is_omap54xx()) { + omap_sram_start = OMAP5_SRAM_PA; + omap_sram_size = SZ_128K; /* 128KB */ } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) -- cgit v1.2.3-70-g09d2