From 6419711a164ba1304fa8fbb75ae9485455e04dcd Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 12 Dec 2008 00:24:06 +0000 Subject: [ARM] S3C: Move PM support functions to common location Start moving the PM code by moving all the common support functions to a common location in arch/arm/plat-s3c. With the move we rename the functions from s3cxxx_ to s3c_ to fit the new location. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c24xx/sleep.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/plat-s3c24xx/sleep.S') diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 76594b21280..7c1955ff317 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -84,7 +84,7 @@ resume_with_mmu: .ltorg @@ the next bits sit in the .data segment, even though they - @@ happen to be code... the s3c2410_sleep_save_phys needs to be + @@ happen to be code... the s3c_sleep_save_phys needs to be @@ accessed by the resume code before it can restore the MMU. @@ This means that the variable has to be close enough for the @@ code to read it... since the .text segment needs to be RO, @@ -92,8 +92,8 @@ resume_with_mmu: .data - .global s3c2410_sleep_save_phys -s3c2410_sleep_save_phys: + .global s3c_sleep_save_phys +s3c_sleep_save_phys: .word 0 @@ -145,7 +145,7 @@ ENTRY(s3c2410_cpu_resume) mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches - ldr r0, s3c2410_sleep_save_phys @ address of restore block + ldr r0, s3c_sleep_save_phys @ address of restore block ldmia r0, { r4 - r13 } mcr p15, 0, r4, c13, c0, 0 @ PID -- cgit v1.2.3-70-g09d2 From ef30e14420df546bc6576b00f9caf3379b6699d1 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 12 Dec 2008 00:24:19 +0000 Subject: [ARM] S3C: Rename sleep.S functions to be non-cpu specific Rename s3c2410_cpu_resume to s3c_cpu_resume and s3c2410_cpu_save to s3c_cpu_save to remove the CPU specific naming of these functions which are now in the generic PM code. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/pm.c | 2 +- arch/arm/mach-s3c2412/mach-jive.c | 2 +- arch/arm/plat-s3c/include/plat/pm.h | 5 +++-- arch/arm/plat-s3c/pm.c | 3 ++- arch/arm/plat-s3c24xx/sleep.S | 10 +++++----- 5 files changed, 12 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-s3c24xx/sleep.S') diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 72f96869aa9..87fc481d92d 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -41,7 +41,7 @@ static void s3c2410_pm_prepare(void) { /* ensure at least GSTATUS3 has the resume address */ - __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); + __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 50d8054292c..72c266aee14 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -494,7 +494,7 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) * correct address to resume from. */ __raw_writel(0x2BED, S3C2412_INFORM0); - __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1); + __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); return 0; } diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index a6104c8055f..f121a5ac742 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h @@ -46,9 +46,10 @@ extern unsigned long s3c_pm_flags; /* from sleep.S */ -extern int s3c2410_cpu_save(unsigned long *saveblk); +extern int s3c_cpu_save(unsigned long *saveblk); +extern void s3c_cpu_resume(void); + extern void s3c2410_cpu_suspend(void); -extern void s3c2410_cpu_resume(void); extern unsigned long s3c_sleep_save_phys; diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index e82ec628ced..e320b0ff385 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c @@ -280,8 +280,9 @@ static int s3c_pm_enter(suspend_state_t state) * we resume as it saves its own register state, so use the return * code to differentiate return from save and return from sleep */ - if (s3c2410_cpu_save(regs_save) == 0) { + if (s3c_cpu_save(regs_save) == 0) { flush_cache_all(); + S3C_PMDBG("preparing to sleep\n"); pm_cpu_sleep(); } diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 7c1955ff317..ecb830be67d 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -41,7 +41,7 @@ .text - /* s3c2410_cpu_save + /* s3c_cpu_save * * save enough of the CPU state to allow us to re-start * pm.c code. as we store items like the sp/lr, we will @@ -59,7 +59,7 @@ * 1 => resumed from sleep */ -ENTRY(s3c2410_cpu_save) +ENTRY(s3c_cpu_save) stmfd sp!, { r4 - r12, lr } @@ store co-processor registers @@ -99,12 +99,12 @@ s3c_sleep_save_phys: /* sleep magic, to allow the bootloader to check for an valid * image to resume to. Must be the first word before the - * s3c2410_cpu_resume entry. + * s3c_cpu_resume entry. */ .word 0x2bedf00d - /* s3c2410_cpu_resume + /* s3c_cpu_resume * * resume code entry for bootloader to call * @@ -113,7 +113,7 @@ s3c_sleep_save_phys: * must not write to the code segment (code is read-only) */ -ENTRY(s3c2410_cpu_resume) +ENTRY(s3c_cpu_resume) mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE msr cpsr_c, r0 -- cgit v1.2.3-70-g09d2 From fff94cd9f5527bbba13aa5ea5719d16531ca8e65 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 10 Mar 2009 11:48:07 +0000 Subject: [ARM] S3C: Tidy sleep code path to fix call flow As noted by Russell King, the sleep code path is not elegant and makes use of leaving items on the stack between calls. Change the code that does the following: if (s3c_cpu_save(regs_save) == 0) { flush_cache_all(); S3C_PMDBG("preparing to sleep\n"); pm_cpu_sleep(); } to simply call s3c_cpu_save, and let that do the necessary calls to quiesce and sleep the system. Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/pm.h | 8 ++++++++ arch/arm/plat-s3c/pm.c | 20 +++++++++++--------- arch/arm/plat-s3c24xx/sleep.S | 25 +++++++++---------------- 3 files changed, 28 insertions(+), 25 deletions(-) (limited to 'arch/arm/plat-s3c24xx/sleep.S') diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index 5ee26da2702..3779775133a 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h @@ -162,5 +162,13 @@ extern void s3c_pm_restore_gpios(void); */ extern void s3c_pm_save_gpios(void); +/** + * s3c_pm_cb_flushcache - callback for assembly code + * + * Callback to issue flush_cache_all() as this call is + * not a directly callable object. + */ +extern void s3c_pm_cb_flushcache(void); + extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index a0ca18a75b0..061182ca66e 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c @@ -229,7 +229,7 @@ void (*pm_cpu_sleep)(void); static int s3c_pm_enter(suspend_state_t state) { - unsigned long regs_save[16]; + static unsigned long regs_save[16]; /* ensure the debug is initialised (if enabled) */ @@ -289,15 +289,11 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_arch_stop_clocks(); - /* s3c2410_cpu_save will also act as our return point from when - * we resume as it saves its own register state, so use the return - * code to differentiate return from save and return from sleep */ + /* s3c_cpu_save will also act as our return point from when + * we resume as it saves its own register state and restores it + * during the resume. */ - if (s3c_cpu_save(regs_save) == 0) { - flush_cache_all(); - S3C_PMDBG("preparing to sleep\n"); - pm_cpu_sleep(); - } + s3c_cpu_save(regs_save); /* restore the cpu state using the kernel's cpu init code. */ @@ -325,6 +321,12 @@ static int s3c_pm_enter(suspend_state_t state) return 0; } +/* callback from assembly code */ +void s3c_pm_cb_flushcache(void) +{ + flush_cache_all(); +} + static int s3c_pm_prepare(void) { /* prepare check area if configured */ diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index ecb830be67d..e73e3b6e88d 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -42,21 +42,9 @@ .text /* s3c_cpu_save - * - * save enough of the CPU state to allow us to re-start - * pm.c code. as we store items like the sp/lr, we will - * end up returning from this function when the cpu resumes - * so the return value is set to mark this. - * - * This arangement means we avoid having to flush the cache - * from this code. * * entry: - * r0 = pointer to save block - * - * exit: - * r0 = 0 => we stored everything - * 1 => resumed from sleep + * r0 = save address (virtual addr of s3c_sleep_save_phys) */ ENTRY(s3c_cpu_save) @@ -71,14 +59,19 @@ ENTRY(s3c_cpu_save) stmia r0, { r4 - r13 } - mov r0, #0 - ldmfd sp, { r4 - r12, pc } + @@ write our state back to RAM + bl s3c_pm_cb_flushcache + @@ jump to final code to send system to sleep + ldr r0, =pm_cpu_sleep + @@ldr pc, [ r0 ] + ldr r0, [ r0 ] + mov pc, r0 + @@ return to the caller, after having the MMU @@ turned on, this restores the last bits from the @@ stack resume_with_mmu: - mov r0, #1 ldmfd sp!, { r4 - r12, pc } .ltorg -- cgit v1.2.3-70-g09d2