From 6ade7fa7bb4484b4dc78e55700d0f62bacd491e9 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Jun 2009 23:54:43 +0200 Subject: [ARM] S3C64XX: fix HCLK gate defines A few typos seems to have sneaked into the HCLK gate defines, causing the usb host clock to not get enabled. Fix them according to the reference manual and throw in the 3d accel bit for good measure. Signed-off-by: Peter Korsgaard Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/include/plat/regs-clock.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index 52836d41e33..a8777a755df 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -88,11 +88,11 @@ #define S3C6400_CLKDIV2_SPI0_SHIFT (0) /* HCLK GATE Registers */ -#define S3C_CLKCON_HCLK_BUS (1<<30) -#define S3C_CLKCON_HCLK_SECUR (1<<29) -#define S3C_CLKCON_HCLK_SDMA1 (1<<28) -#define S3C_CLKCON_HCLK_SDMA2 (1<<27) -#define S3C_CLKCON_HCLK_UHOST (1<<26) +#define S3C_CLKCON_HCLK_3DSE (1<<31) +#define S3C_CLKCON_HCLK_UHOST (1<<29) +#define S3C_CLKCON_HCLK_SECUR (1<<28) +#define S3C_CLKCON_HCLK_SDMA1 (1<<27) +#define S3C_CLKCON_HCLK_SDMA0 (1<<26) #define S3C_CLKCON_HCLK_IROM (1<<25) #define S3C_CLKCON_HCLK_DDR1 (1<<24) #define S3C_CLKCON_HCLK_DDR0 (1<<23) -- cgit v1.2.3-70-g09d2 From 386f43517f8bf026320fd4b9e077140681d7e595 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Jun 2009 23:54:44 +0200 Subject: [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit The usb-host clock was using the wrong define (the SCLK enable for the usb-host-bus) to change the HCLK register instead of the HCLK_UHOST bit. Signed-off-by: Peter Korsgaard Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index 0bc2fa1dfc4..7a36e899360 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -191,7 +191,7 @@ static struct clk init_clocks[] = { .id = -1, .parent = &clk_h, .enable = s3c64xx_hclk_ctrl, - .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .ctrlbit = S3C_CLKCON_HCLK_UHOST, }, { .name = "hsmmc", .id = 0, -- cgit v1.2.3-70-g09d2 From 0b495737f311cb8eb5e66404309ea16e4d7ded8a Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 18 Jun 2009 13:30:27 +0200 Subject: [ARM] S3C64XX: add to_irq() support for EINT() GPIO N group Add to_irq() function to onvert gpio to irq for external interrupt group (GPN). Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park Signed-off-by: Ben Dooks --- arch/arm/plat-s3c64xx/gpiolib.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index da7b60ee5e6..92859290ea3 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { .get_pull = s3c_gpio_getpull_updown, }; +int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin) +{ + return IRQ_EINT(0) + pin; +} + static struct s3c_gpio_chip gpio_2bit[] = { { .base = S3C64XX_GPF_BASE, @@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = { .base = S3C64XX_GPN(0), .ngpio = S3C64XX_GPIO_N_NR, .label = "GPN", + .to_irq = s3c64xx_gpio2int_gpn, }, }, { .base = S3C64XX_GPO_BASE, -- cgit v1.2.3-70-g09d2 From 49fb88af23f3344ba53d6dbe34ac0b1426d81006 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 18 Jun 2009 13:30:16 +0200 Subject: [ARM] S3C: Fix gpio-config off-by-one bug Fix gpio-config off-by-one bug. Without this patch, touching GPA0 pin on S3C64XX platform causes kernel oops. Reviewed-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/gpio-config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c index 08044dec973..456969b6fa0 100644 --- a/arch/arm/plat-s3c/gpio-config.c +++ b/arch/arm/plat-s3c/gpio-config.c @@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, unsigned int shift = (off & 7) * 4; u32 con; - if (off < 8 && chip->chip.ngpio >= 8) + if (off < 8 && chip->chip.ngpio > 8) reg -= 4; if (s3c_gpio_is_cfg_special(cfg)) { -- cgit v1.2.3-70-g09d2