From f80dff9da07d81da16e3b842118d47b9febf9c01 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Fri, 16 Feb 2007 22:16:32 +0100 Subject: [ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_user get_irqnr_preamble allows machines to take some action before entering the get_irqnr_and_base loop. On iop we enable cp6 access. arch_ret_to_user is added to the userspace return path to allow individual architectures to take actions, like disabling coprocessor access, before the final return to userspace. Per Nicolas Pitre's note, there is no need to cp_wait on the return to user as the latency to return is sufficient. Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/kernel/entry-armv.S | 1 + arch/arm/kernel/entry-common.S | 7 +++++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index cc10a093a54..d645897652c 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -27,6 +27,7 @@ * Interrupt handling. Preserves r7, r8, r9 */ .macro irq_handler + get_irqnr_preamble r5, lr 1: get_irqnr_and_base r0, r6, r5, lr movne r1, sp @ diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 6f5e7c50d42..c589dc3ecd1 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -9,6 +9,7 @@ */ #include +#include #include "entry-header.S" @@ -25,6 +26,9 @@ ret_fast_syscall: tst r1, #_TIF_WORK_MASK bne fast_work_pending + /* perform architecture specific actions before user return */ + arch_ret_to_user r1, lr + @ fast_restore_user_regs ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr ldr lr, [sp, #S_OFF + S_PC]! @ get pc @@ -61,6 +65,9 @@ ret_slow_syscall: tst r1, #_TIF_WORK_MASK bne work_pending no_work_pending: + /* perform architecture specific actions before user return */ + arch_ret_to_user r1, lr + @ slow_restore_user_regs ldr r1, [sp, #S_PSR] @ get calling cpsr ldr lr, [sp, #S_PC]! @ get pc -- cgit v1.2.3-70-g09d2 From 4434c5c7fd61c6713de882a2272b66f32fe7cac3 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 13 Feb 2007 17:13:04 +0100 Subject: [ARM] 4186/1: iop: remove cp6_enable/disable routines This functionality is replaced by cp6_trap Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/irq.c | 19 ------------------- arch/arm/mach-iop13xx/time.c | 10 ---------- arch/arm/mach-iop32x/irq.c | 4 ---- arch/arm/mach-iop33x/irq.c | 12 ------------ arch/arm/plat-iop/time.c | 4 ---- include/asm-arm/arch-iop13xx/iop13xx.h | 26 -------------------------- include/asm-arm/arch-iop13xx/irqs.h | 17 ----------------- include/asm-arm/arch-iop13xx/system.h | 2 -- include/asm-arm/hardware/iop3xx.h | 27 --------------------------- 9 files changed, 121 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index 162b9321496..b2eb0b96103 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c @@ -161,65 +161,49 @@ static void write_intsize(u32 val) static void iop13xx_irq_mask0 (unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); - iop13xx_cp6_restore(cp_flags); } static void iop13xx_irq_mask1 (unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); - iop13xx_cp6_restore(cp_flags); } static void iop13xx_irq_mask2 (unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); - iop13xx_cp6_restore(cp_flags); } static void iop13xx_irq_mask3 (unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); - iop13xx_cp6_restore(cp_flags); } static void iop13xx_irq_unmask0(unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_0(read_intctl_0() | (1 << (irq - 0))); - iop13xx_cp6_restore(cp_flags); } static void iop13xx_irq_unmask1(unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_1(read_intctl_1() | (1 << (irq - 32))); - iop13xx_cp6_restore(cp_flags); } static void iop13xx_irq_unmask2(unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_2(read_intctl_2() | (1 << (irq - 64))); - iop13xx_cp6_restore(cp_flags); } static void iop13xx_irq_unmask3(unsigned int irq) { - u32 cp_flags = iop13xx_cp6_save(); write_intctl_3(read_intctl_3() | (1 << (irq - 96))); - iop13xx_cp6_restore(cp_flags); } static struct irq_chip iop13xx_irqchip1 = { @@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void) { unsigned int i; - u32 cp_flags = iop13xx_cp6_save(); iop_init_cp6_handler(); /* disable all interrupts */ @@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void) set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } - - iop13xx_cp6_restore(cp_flags); } diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c index 8b21365f653..fc9d9d9a842 100644 --- a/arch/arm/mach-iop13xx/time.c +++ b/arch/arm/mach-iop13xx/time.c @@ -38,11 +38,8 @@ static inline u32 read_tcr1(void) unsigned long iop13xx_gettimeoffset(void) { unsigned long offset; - u32 cp_flags; - cp_flags = iop13xx_cp6_save(); offset = next_jiffy_time - read_tcr1(); - iop13xx_cp6_restore(cp_flags); return offset / ticks_per_usec; } @@ -50,8 +47,6 @@ unsigned long iop13xx_gettimeoffset(void) static irqreturn_t iop13xx_timer_interrupt(int irq, void *dev_id) { - u32 cp_flags = iop13xx_cp6_save(); - write_seqlock(&xtime_lock); asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1)); @@ -64,8 +59,6 @@ iop13xx_timer_interrupt(int irq, void *dev_id) write_sequnlock(&xtime_lock); - iop13xx_cp6_restore(cp_flags); - return IRQ_HANDLED; } @@ -78,7 +71,6 @@ static struct irqaction iop13xx_timer_irq = { void __init iop13xx_init_time(unsigned long tick_rate) { u32 timer_ctl; - u32 cp_flags; ticks_per_jiffy = (tick_rate + HZ/2) / HZ; ticks_per_usec = tick_rate / 1000000; @@ -91,12 +83,10 @@ void __init iop13xx_init_time(unsigned long tick_rate) * We use timer 0 for our timer interrupt, and timer 1 as * monotonic counter for tracking missed jiffies. */ - cp_flags = iop13xx_cp6_save(); asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1)); asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl)); asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff)); asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl)); - iop13xx_cp6_restore(cp_flags); setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq); } diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 8b0ac5590ae..82598dc18d8 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -23,16 +23,12 @@ static u32 iop32x_mask; static inline void intctl_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intstr_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static void diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index effbe6b782d..c65ea78a242 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -24,44 +24,32 @@ static u32 iop33x_mask1; static inline void intctl0_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intctl1_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intstr0_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intstr1_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intbase_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intsize_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static void diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index f530abdaa7a..0d53b813cbb 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -51,9 +51,7 @@ iop3xx_timer_interrupt(int irq, void *dev_id) { write_seqlock(&xtime_lock); - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); - iop3xx_cp6_disable(); while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) >= ticks_per_jiffy) { @@ -87,12 +85,10 @@ void __init iop3xx_init_time(unsigned long tick_rate) * We use timer 0 for our timer interrupt, and timer 1 as * monotonic counter for tracking missed jiffies. */ - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); - iop3xx_cp6_disable(); setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); } diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index a88522a0ff8..e7430593d6f 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -12,32 +12,6 @@ void iop13xx_init_irq(void); void iop13xx_init_time(unsigned long tickrate); unsigned long iop13xx_gettimeoffset(void); -/* handle cp6 access - * to do: handle access in entry-armv5.S and unify with - * the iop3xx implementation - * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h) - * when interrupts are enabled - */ -static inline unsigned long iop13xx_cp6_save(void) -{ - u32 temp, cp_flags; - - asm volatile ( - "mrc p15, 0, %1, c15, c1, 0\n\t" - "orr %0, %1, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - : "=r" (temp), "=r"(cp_flags)); - - return cp_flags; -} - -static inline void iop13xx_cp6_restore(unsigned long cp_flags) -{ - asm volatile ( - "mcr p15, 0, %0, c15, c1, 0\n\t" - : : "r" (cp_flags) ); -} - /* CPUID CP6 R0 Page 0 */ static inline int iop13xx_cpu_id(void) { diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h index 442e35a4035..5c6fac2a400 100644 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ b/include/asm-arm/arch-iop13xx/irqs.h @@ -3,8 +3,6 @@ #ifndef __ASSEMBLER__ #include -#include /* local_irq_save */ -#include /* iop13xx_cp6_* */ /* INTPND0 CP6 R0 Page 3 */ @@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void) asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); return val; } - -static inline void -iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags) -{ - local_irq_save(*irq_flags); - *cp_flags = iop13xx_cp6_save(); -} - -static inline void -iop13xx_cp6_irq_restore(unsigned long *cp_flags, - unsigned long *irq_flags) -{ - iop13xx_cp6_restore(*cp_flags); - local_irq_restore(*irq_flags); -} #endif #define INTBASE 0 diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h index ee3a62530af..127827058e1 100644 --- a/include/asm-arm/arch-iop13xx/system.h +++ b/include/asm-arm/arch-iop13xx/system.h @@ -48,12 +48,10 @@ static inline void arch_reset(char mode) /* * Reset the internal bus (warning both cores are reset) */ - u32 cp_flags = iop13xx_cp6_save(); write_wdtcr(IOP13XX_WDTCR_EN_ARM); write_wdtcr(IOP13XX_WDTCR_EN); write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); write_wdtcr(0x1000); - iop13xx_cp6_restore(cp_flags); for(;;); } diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index c91b546e20e..47fcbf6f52d 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -283,33 +283,6 @@ void iop_init_cp6_handler(void); extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c1_device; -extern inline void iop3xx_cp6_enable(void) -{ - u32 temp; - - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4\n\t" - : "=r" (temp) ); -} - -extern inline void iop3xx_cp6_disable(void) -{ - u32 temp; - - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "bic %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4\n\t" - : "=r" (temp) ); -} #endif -- cgit v1.2.3-70-g09d2 From 3668b45d46f777b0773ef5ff49531c1144efb6dd Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 13 Feb 2007 17:13:34 +0100 Subject: [ARM] 4187/1: iop: unify time implementation across iop32x, iop33x, and iop13xx * architecture specific details are handled in asm/arch/time.h * ARCH_IOP13XX now selects PLAT_IOP * as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on XSC3 Signed-off-by: Dan Williams Signed-off-by: Russell King --- arch/arm/mach-iop13xx/Makefile | 1 - arch/arm/mach-iop13xx/iq81340mc.c | 5 +- arch/arm/mach-iop13xx/iq81340sc.c | 5 +- arch/arm/mach-iop13xx/time.c | 92 ---------------------------------- arch/arm/mach-iop32x/glantank.c | 5 +- arch/arm/mach-iop32x/iq31244.c | 8 +-- arch/arm/mach-iop32x/iq80321.c | 5 +- arch/arm/mach-iop32x/n2100.c | 5 +- arch/arm/mach-iop33x/iq80331.c | 7 +-- arch/arm/mach-iop33x/iq80332.c | 7 +-- arch/arm/plat-iop/Makefile | 1 + arch/arm/plat-iop/time.c | 60 ++++++++++++---------- include/asm-arm/arch-iop13xx/iop13xx.h | 12 ----- include/asm-arm/arch-iop13xx/time.h | 51 +++++++++++++++++++ include/asm-arm/arch-iop32x/time.h | 4 ++ include/asm-arm/arch-iop33x/time.h | 4 ++ include/asm-arm/hardware/iop3xx.h | 55 ++++++++++++++++---- 17 files changed, 166 insertions(+), 161 deletions(-) delete mode 100644 arch/arm/mach-iop13xx/time.c create mode 100644 include/asm-arm/arch-iop13xx/time.h create mode 100644 include/asm-arm/arch-iop32x/time.h create mode 100644 include/asm-arm/arch-iop33x/time.h (limited to 'arch/arm') diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile index c3d6c08f2d4..4185e0586c3 100644 --- a/arch/arm/mach-iop13xx/Makefile +++ b/arch/arm/mach-iop13xx/Makefile @@ -5,7 +5,6 @@ obj- := obj-$(CONFIG_ARCH_IOP13XX) += setup.o obj-$(CONFIG_ARCH_IOP13XX) += irq.o -obj-$(CONFIG_ARCH_IOP13XX) += time.o obj-$(CONFIG_ARCH_IOP13XX) += pci.o obj-$(CONFIG_ARCH_IOP13XX) += io.o obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 2a1bbfe9896..a519d707571 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -25,6 +25,7 @@ #include #include #include +#include extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */ @@ -78,12 +79,12 @@ static void __init iq81340mc_init(void) static void __init iq81340mc_timer_init(void) { - iop13xx_init_time(400000000); + iop_init_time(400000000); } static struct sys_timer iq81340mc_timer = { .init = iq81340mc_timer_init, - .offset = iop13xx_gettimeoffset, + .offset = iop_gettimeoffset, }; MACHINE_START(IQ81340MC, "Intel IQ81340MC") diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index 5ad2b62c9bf..0e71fbcabe0 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -25,6 +25,7 @@ #include #include #include +#include extern int init_atu; @@ -80,12 +81,12 @@ static void __init iq81340sc_init(void) static void __init iq81340sc_timer_init(void) { - iop13xx_init_time(400000000); + iop_init_time(400000000); } static struct sys_timer iq81340sc_timer = { .init = iq81340sc_timer_init, - .offset = iop13xx_gettimeoffset, + .offset = iop_gettimeoffset, }; MACHINE_START(IQ81340SC, "Intel IQ81340SC") diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c deleted file mode 100644 index fc9d9d9a842..00000000000 --- a/arch/arm/mach-iop13xx/time.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * arch/arm/mach-iop13xx/time.c - * - * Timer code for IOP13xx (copied from IOP32x/IOP33x implementation) - * - * Author: Deepak Saxena - * - * Copyright 2002-2003 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned long ticks_per_jiffy; -static unsigned long ticks_per_usec; -static unsigned long next_jiffy_time; - -static inline u32 read_tcr1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); - return val; -} - -unsigned long iop13xx_gettimeoffset(void) -{ - unsigned long offset; - - offset = next_jiffy_time - read_tcr1(); - - return offset / ticks_per_usec; -} - -static irqreturn_t -iop13xx_timer_interrupt(int irq, void *dev_id) -{ - write_seqlock(&xtime_lock); - - asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1)); - - while ((signed long)(next_jiffy_time - read_tcr1()) - >= ticks_per_jiffy) { - timer_tick(); - next_jiffy_time -= ticks_per_jiffy; - } - - write_sequnlock(&xtime_lock); - - return IRQ_HANDLED; -} - -static struct irqaction iop13xx_timer_irq = { - .name = "IOP13XX Timer Tick", - .handler = iop13xx_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_TIMER, -}; - -void __init iop13xx_init_time(unsigned long tick_rate) -{ - u32 timer_ctl; - - ticks_per_jiffy = (tick_rate + HZ/2) / HZ; - ticks_per_usec = tick_rate / 1000000; - next_jiffy_time = 0xffffffff; - - timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED | - IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1; - - /* - * We use timer 0 for our timer interrupt, and timer 1 as - * monotonic counter for tracking missed jiffies. - */ - asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1)); - asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl)); - asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff)); - asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl)); - - setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq); -} diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index b9b765057db..45f4f13ae11 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -31,6 +31,7 @@ #include #include #include +#include /* * GLAN Tank timer tick configuration. @@ -38,12 +39,12 @@ static void __init glantank_timer_init(void) { /* 33.333 MHz crystal. */ - iop3xx_init_time(200000000); + iop_init_time(200000000); } static struct sys_timer glantank_timer = { .init = glantank_timer_init, - .offset = iop3xx_gettimeoffset, + .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index be4aedfa0de..571ac35bc2c 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -36,7 +36,7 @@ #include #include #include - +#include /* * The EP80219 and IQ31244 use the same machine ID. To find out @@ -56,16 +56,16 @@ static void __init iq31244_timer_init(void) { if (is_80219()) { /* 33.333 MHz crystal. */ - iop3xx_init_time(200000000); + iop_init_time(200000000); } else { /* 33.000 MHz crystal. */ - iop3xx_init_time(198000000); + iop_init_time(198000000); } } static struct sys_timer iq31244_timer = { .init = iq31244_timer_init, - .offset = iop3xx_gettimeoffset, + .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 1f37b550188..361c70c0f64 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -33,6 +33,7 @@ #include #include #include +#include /* * IQ80321 timer tick configuration. @@ -40,12 +41,12 @@ static void __init iq80321_timer_init(void) { /* 33.333 MHz crystal. */ - iop3xx_init_time(200000000); + iop_init_time(200000000); } static struct sys_timer iq80321_timer = { .init = iq80321_timer_init, - .offset = iop3xx_gettimeoffset, + .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index 2499a7707e3..92fa0c55443 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -37,6 +37,7 @@ #include #include #include +#include /* * N2100 timer tick configuration. @@ -44,12 +45,12 @@ static void __init n2100_timer_init(void) { /* 33.000 MHz crystal. */ - iop3xx_init_time(198000000); + iop_init_time(198000000); } static struct sys_timer n2100_timer = { .init = n2100_timer_init, - .offset = iop3xx_gettimeoffset, + .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 97a7b748826..1a9e36138d8 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * IQ80331 timer tick configuration. @@ -40,14 +41,14 @@ static void __init iq80331_timer_init(void) { /* D-Step parts run at a higher internal bus frequency */ if (*IOP3XX_ATURID >= 0xa) - iop3xx_init_time(333000000); + iop_init_time(333000000); else - iop3xx_init_time(266000000); + iop_init_time(266000000); } static struct sys_timer iq80331_timer = { .init = iq80331_timer_init, - .offset = iop3xx_gettimeoffset, + .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 9887bfc1c07..96d6f0f3cd2 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * IQ80332 timer tick configuration. @@ -40,14 +41,14 @@ static void __init iq80332_timer_init(void) { /* D-Step parts and the iop333 run at a higher internal bus frequency */ if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374) - iop3xx_init_time(333000000); + iop_init_time(333000000); else - iop3xx_init_time(266000000); + iop_init_time(266000000); } static struct sys_timer iq80332_timer = { .init = iq80332_timer_init, - .offset = iop3xx_gettimeoffset, + .offset = iop_gettimeoffset, }; diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile index 3250d732a17..4d2b1da3cd8 100644 --- a/arch/arm/plat-iop/Makefile +++ b/arch/arm/plat-iop/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_ARCH_IOP33X) += cp6.o # IOP13XX obj-$(CONFIG_ARCH_IOP13XX) += cp6.o +obj-$(CONFIG_ARCH_IOP13XX) += time.o obj-m := obj-n := diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 0d53b813cbb..16300adfb4d 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -24,37 +24,45 @@ #include #include #include - -#ifdef CONFIG_ARCH_IOP32X -#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0 -#else -#ifdef CONFIG_ARCH_IOP33X -#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0 -#endif -#endif +#include static unsigned long ticks_per_jiffy; static unsigned long ticks_per_usec; static unsigned long next_jiffy_time; -unsigned long iop3xx_gettimeoffset(void) +unsigned long iop_gettimeoffset(void) { - unsigned long offset; + unsigned long offset, temp1, temp2; + + /* enable cp6, if necessary, to avoid taking the overhead of an + * undefined instruction trap + */ + asm volatile ( + "mrc p15, 0, %0, c15, c1, 0\n\t" + "ands %1, %0, #(1 << 6)\n\t" + "orreq %0, %0, #(1 << 6)\n\t" + "mcreq p15, 0, %0, c15, c1, 0\n\t" +#ifdef CONFIG_XSCALE + "mrceq p15, 0, %0, c15, c1, 0\n\t" + "moveq %0, %0\n\t" + "subeq pc, pc, #4\n\t" +#endif + : "=r"(temp1), "=r"(temp2) : : "cc"); - offset = next_jiffy_time - *IOP3XX_TU_TCR1; + offset = next_jiffy_time - read_tcr1(); return offset / ticks_per_usec; } static irqreturn_t -iop3xx_timer_interrupt(int irq, void *dev_id) +iop_timer_interrupt(int irq, void *dev_id) { write_seqlock(&xtime_lock); - asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); + write_tisr(1); - while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) - >= ticks_per_jiffy) { + while ((signed long)(next_jiffy_time - read_tcr1()) + >= ticks_per_jiffy) { timer_tick(); next_jiffy_time -= ticks_per_jiffy; } @@ -64,13 +72,13 @@ iop3xx_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irqaction iop3xx_timer_irq = { - .name = "IOP3XX Timer Tick", - .handler = iop3xx_timer_interrupt, +static struct irqaction iop_timer_irq = { + .name = "IOP Timer Tick", + .handler = iop_timer_interrupt, .flags = IRQF_DISABLED | IRQF_TIMER, }; -void __init iop3xx_init_time(unsigned long tick_rate) +void __init iop_init_time(unsigned long tick_rate) { u32 timer_ctl; @@ -78,17 +86,17 @@ void __init iop3xx_init_time(unsigned long tick_rate) ticks_per_usec = tick_rate / 1000000; next_jiffy_time = 0xffffffff; - timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED | - IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1; + timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | + IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; /* * We use timer 0 for our timer interrupt, and timer 1 as * monotonic counter for tracking missed jiffies. */ - asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); - asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); - asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); - asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); + write_trr0(ticks_per_jiffy - 1); + write_tmr0(timer_ctl); + write_trr1(0xffffffff); + write_tmr1(timer_ctl); - setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); + setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); } diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index e7430593d6f..d26b755a987 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -9,8 +9,6 @@ void iop13xx_init_irq(void); void iop13xx_map_io(void); void iop13xx_platform_init(void); void iop13xx_init_irq(void); -void iop13xx_init_time(unsigned long tickrate); -unsigned long iop13xx_gettimeoffset(void); /* CPUID CP6 R0 Page 0 */ static inline int iop13xx_cpu_id(void) @@ -453,14 +451,4 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) -#define IOP13XX_TMR_TC 0x01 -#define IOP13XX_TMR_EN 0x02 -#define IOP13XX_TMR_RELOAD 0x04 -#define IOP13XX_TMR_PRIVILEGED 0x08 - -#define IOP13XX_TMR_RATIO_1_1 0x00 -#define IOP13XX_TMR_RATIO_4_1 0x10 -#define IOP13XX_TMR_RATIO_8_1 0x20 -#define IOP13XX_TMR_RATIO_16_1 0x30 - #endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h new file mode 100644 index 00000000000..77a837a02de --- /dev/null +++ b/include/asm-arm/arch-iop13xx/time.h @@ -0,0 +1,51 @@ +#ifndef _IOP13XX_TIME_H_ +#define _IOP13XX_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0 + +#define IOP_TMR_EN 0x02 +#define IOP_TMR_RELOAD 0x04 +#define IOP_TMR_PRIVILEGED 0x08 +#define IOP_TMR_RATIO_1_1 0x00 + +void iop_init_time(unsigned long tickrate); +unsigned long iop_gettimeoffset(void); + +static inline void write_tmr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); +} + +static inline void write_tmr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); +} + +static inline u32 read_tcr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); + return val; +} + +static inline u32 read_tcr1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); + return val; +} + +static inline void write_trr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); +} + +static inline void write_trr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); +} + +static inline void write_tisr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); +} +#endif diff --git a/include/asm-arm/arch-iop32x/time.h b/include/asm-arm/arch-iop32x/time.h new file mode 100644 index 00000000000..0f28c994962 --- /dev/null +++ b/include/asm-arm/arch-iop32x/time.h @@ -0,0 +1,4 @@ +#ifndef _IOP32X_TIME_H_ +#define _IOP32X_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0 +#endif diff --git a/include/asm-arm/arch-iop33x/time.h b/include/asm-arm/arch-iop33x/time.h new file mode 100644 index 00000000000..4ac4d7664f8 --- /dev/null +++ b/include/asm-arm/arch-iop33x/time.h @@ -0,0 +1,4 @@ +#ifndef _IOP33X_TIME_H_ +#define _IOP33X_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0 +#endif diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index 47fcbf6f52d..15141a9caca 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -188,14 +188,10 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) -#define IOP3XX_TMR_TC 0x01 -#define IOP3XX_TMR_EN 0x02 -#define IOP3XX_TMR_RELOAD 0x04 -#define IOP3XX_TMR_PRIVILEGED 0x09 -#define IOP3XX_TMR_RATIO_1_1 0x00 -#define IOP3XX_TMR_RATIO_4_1 0x10 -#define IOP3XX_TMR_RATIO_8_1 0x20 -#define IOP3XX_TMR_RATIO_16_1 0x30 +#define IOP_TMR_EN 0x02 +#define IOP_TMR_RELOAD 0x04 +#define IOP_TMR_PRIVILEGED 0x08 +#define IOP_TMR_RATIO_1_1 0x00 /* Application accelerator unit */ #define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) @@ -276,9 +272,48 @@ extern void gpio_line_set(int line, int value); #ifndef __ASSEMBLY__ void iop3xx_map_io(void); -void iop3xx_init_time(unsigned long); -unsigned long iop3xx_gettimeoffset(void); void iop_init_cp6_handler(void); +void iop_init_time(unsigned long tickrate); +unsigned long iop_gettimeoffset(void); + +static inline void write_tmr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); +} + +static inline void write_tmr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); +} + +static inline u32 read_tcr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); + return val; +} + +static inline u32 read_tcr1(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); + return val; +} + +static inline void write_trr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); +} + +static inline void write_trr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); +} + +static inline void write_tisr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); +} extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c1_device; -- cgit v1.2.3-70-g09d2