From a12cf0a8c6e2763ac865aa31f296557e07432b8a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 10:12:29 +1000 Subject: m68knommu: create bit definitions for the version 2 ColdFire cache controller The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m52xxacr.h | 56 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 arch/m68k/include/asm/m52xxacr.h (limited to 'arch/m68k/include/asm/m52xxacr.h') diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h new file mode 100644 index 00000000000..4c92d999ee0 --- /dev/null +++ b/arch/m68k/include/asm/m52xxacr.h @@ -0,0 +1,56 @@ +/****************************************************************************/ + +/* + * m52xxacr.h -- ColdFire version 2 core cache support + * + * (C) Copyright 2010, Greg Ungerer + */ + +/****************************************************************************/ +#ifndef m52xxacr_h +#define m52xxacr_h +/****************************************************************************/ + +/* + * All varients of the ColdFire using version 2 cores have a similar + * cache setup. Although not absolutely identical the cache register + * definitions are compatible for all of them. Mostly they support a + * configurable cache memory that can be instruction only, data only, + * or split instruction and data. The exception is the very old version 2 + * core based parts, like the 5206(e), 5249 and 5272, which are instruction + * cache only. Cache size varies from 2k up to 16k. + */ + +/* + * Define the Cache Control register flags. + */ +#define CACR_CENB 0x80000000 /* Enable cache */ +#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */ +#define CACR_CFRZ 0x08000000 /* Cache freeze mode */ +#define CACR_CINV 0x01000000 /* Invalidate cache */ +#define CACR_DISI 0x00800000 /* Disable instruction cache */ +#define CACR_DISD 0x00400000 /* Disable data cache */ +#define CACR_INVI 0x00200000 /* Invalidate instruction cache */ +#define CACR_INVD 0x00100000 /* Invalidate data cache */ +#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */ +#define CACR_DCM 0x00000200 /* Default cache mode */ +#define CACR_DBWE 0x00000100 /* Buffered write enable */ +#define CACR_DWP 0x00000020 /* Write protection */ +#define CACR_EUSP 0x00000010 /* Enable separate user a7 */ + +/* + * Define the Access Control register flags. + */ +#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ +#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ +#define ACR_ENABLE 0x00008000 /* Enable this ACR */ +#define ACR_USER 0x00000000 /* Allow only user accesses */ +#define ACR_SUPER 0x00002000 /* Allow supervisor access only */ +#define ACR_ANY 0x00004000 /* Allow any access type */ +#define ACR_CENB 0x00000000 /* Caching of region enabled */ +#define ACR_CDIS 0x00000040 /* Caching of region disabled */ +#define ACR_BWE 0x00000020 /* Write buffer enabled */ +#define ACR_WPROTECT 0x00000004 /* Write protect region */ + +/****************************************************************************/ +#endif /* m52xxsim_h */ -- cgit v1.2.3-70-g09d2 From 8ce877a8eb8293b5b2c07f259d694026b0f519e4 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 13:35:55 +1000 Subject: m68knommu: clean up ColdFire cache control code The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 40 ++------- arch/m68k/include/asm/m52xxacr.h | 27 ++++++ arch/m68k/include/asm/m53xxacr.h | 18 ++++ arch/m68k/include/asm/m54xxacr.h | 11 ++- arch/m68k/include/asm/mcfcache.h | 150 -------------------------------- arch/m68knommu/platform/coldfire/head.S | 26 ++++-- 6 files changed, 80 insertions(+), 192 deletions(-) delete mode 100644 arch/m68k/include/asm/mcfcache.h (limited to 'arch/m68k/include/asm/m52xxacr.h') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 52b11ac9a30..8ada4ffc98e 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -2,7 +2,7 @@ #define _M68KNOMMU_CACHEFLUSH_H /* - * (C) Copyright 2000-2004, Greg Ungerer + * (C) Copyright 2000-2010, Greg Ungerer */ #include #include @@ -10,7 +10,7 @@ #define flush_cache_all() __flush_cache_all() #define flush_cache_mm(mm) do { } while (0) #define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) __flush_cache_all() +#define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) #ifndef flush_dcache_range #define flush_dcache_range(start,len) __flush_cache_all() @@ -33,41 +33,13 @@ #ifndef __flush_cache_all static inline void __flush_cache_all(void) { -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) +#ifdef CACHE_INVALIDATE __asm__ __volatile__ ( - "movel #0x81400110, %%d0\n\t" + "movel %0, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M523x || CONFIG_M527x */ -#if defined(CONFIG_M528x) - __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M528x */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) - __asm__ __volatile__ ( - "movel #0x81000100, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ -#ifdef CONFIG_M5249 - __asm__ __volatile__ ( - "movel #0xa1000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5249 */ -#ifdef CONFIG_M532x - __asm__ __volatile__ ( - "movel #0x81000210, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M532x */ + : : "i" (CACHE_INVALIDATE) : "d0" ); +#endif } #endif /* __flush_cache_all */ diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 4c92d999ee0..52230b5e1e4 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h @@ -52,5 +52,32 @@ #define ACR_BWE 0x00000020 /* Write buffer enabled */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Set the cache controller settings we will use. This code is set to + * only use the instruction cache, even on the controllers that support + * split cache. (This setup is trying to preserve the existing behavior + * for now, in the furture I hope to actually use the split cache mode). + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5249) || defined(CONFIG_M5272) +#define CACHE_INIT (CACR_CINV) +#define CACHE_MODE (CACR_CENB + CACR_DCM) +#else +#ifdef CONFIG_COLDFIRE_SW_A7 +#define CACHE_INIT (CACR_CINV + CACR_DISD) +#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM) +#else +#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP) +#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP) +#endif +#endif + +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE)) +#define ACR1_MODE 0 + /****************************************************************************/ #endif /* m52xxsim_h */ diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index 532fbb91185..74c81c9b177 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -48,5 +48,23 @@ #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Set the cache controller settings we will use. This default in the + * CACR is cache inhibited, we use the ACR register to set cacheing + * enabled on the regions we want (eg RAM). + */ +#ifdef CONFIG_COLDFIRE_SW_A7 +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) +#else +#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) +#endif + +#define CACHE_INIT CACR_CINVA + +#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ + (0x000f0000) + \ + (ACR_ENABLE + ACR_ANY + ACR_CM_CB)) +#define ACR1_MODE 0 + /****************************************************************************/ #endif /* m53xxsim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 12209c68b90..3c81a7a34a8 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -73,11 +73,16 @@ #else #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) #endif - #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) - #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) +#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) +#define ACR1_MODE 0 +#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) +#define ACR3_MODE 0 + #ifndef __ASSEMBLY__ #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) @@ -112,7 +117,7 @@ static inline void __m54xx_flush_cache_all(void) : "i" (CACHE_LINE_SIZE), "i" (DCACHE_SIZE / CACHE_WAYS), "i" (CACHE_WAYS), - "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA) + "i" (CACHE_INVALIDATE) : "d0", "a0" ); } diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h deleted file mode 100644 index 2b3a6cfaaac..00000000000 --- a/arch/m68k/include/asm/mcfcache.h +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************/ - -/* - * mcfcache.h -- ColdFire CPU cache support code - * - * (C) Copyright 2004, Greg Ungerer - */ - -/****************************************************************************/ -#ifndef __M68KNOMMU_MCFCACHE_H -#define __M68KNOMMU_MCFCACHE_H -/****************************************************************************/ - - -/* - * The different ColdFire families have different cache arrangments. - * Everything from a small instruction only cache, to configurable - * data and/or instruction cache, to unified instruction/data, to - * harvard style separate instruction and data caches. - */ - -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) -/* - * Simple version 2 core cache. These have instruction cache only, - * we just need to invalidate it and enable it. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - movel #0x80000100,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ -.endm -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ - -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) -/* - * New version 2 cores have a configurable split cache arrangement. - * For now I am just enabling instruction cache - but ultimately I - * think a split instruction/data cache would be better. - */ -.macro CACHE_ENABLE - movel #0x01400000,%d0 - movec %d0,%CACR /* invalidate cache */ - nop - movel #0x0000c000,%d0 /* set SDRAM cached only */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80400110,%d0 /* configure cache */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M523x || CONFIG_M527x */ - -#if defined(CONFIG_M528x) -.macro CACHE_ENABLE - nop - movel #0x01000000, %d0 - movec %d0, %CACR /* Invalidate cache */ - nop - movel #0x0000c020, %d0 /* Set SDRAM cached only */ - movec %d0, %ACR0 - movel #0x00000000, %d0 /* No other regions cached */ - movec %d0, %ACR1 - movel #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop -.endm -#endif /* CONFIG_M528x */ - -#if defined(CONFIG_M5249) || defined(CONFIG_M5307) -/* - * The version 3 core cache. Oddly enough the version 2 core 5249 - * has the same SDRAM and cache setup as the version 3 cores. - * This is a single unified instruction/data cache. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop -#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3) - movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ -#else - movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */ -#endif - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0xa0000200,%d0 /* enable cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5249 || CONFIG_M5307 */ - -#if defined(CONFIG_M532x) -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - nop - movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80000210,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M532x */ - -#if defined(CONFIG_M5407) || defined(CONFIG_M54xx) - -.macro CACHE_ENABLE - /* invalidate whole cache */ - movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0 - movec %d0,%CACR - nop - /* addresses range for data cache : 0x00000000-0x0fffffff */ - movel #(0x000f0000+DATA_CACHE_MODE),%d0 /* set SDRAM cached */ - movec %d0, %ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR1 - /* addresses range for instruction cache : 0x00000000-0x0fffffff */ - movel #(0x000f0000+INSN_CACHE_MODE),%d0 /* set SDRAM cached */ - movec %d0, %ACR2 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR3 - /* enable caches */ - movel #(CACHE_MODE),%d0 - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5407 || CONFIG_M54xx */ - -#if defined(CONFIG_M520x) -.macro CACHE_ENABLE - move.l #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop - move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - move.l #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - move.l #0x80400010,%d0 /* enable 8K instruction cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M520x */ - -/****************************************************************************/ -#endif /* __M68KNOMMU_MCFCACHE_H */ diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 0b2d7c7adf7..d5977909ae5 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -3,7 +3,7 @@ /* * head.S -- common startup code for ColdFire CPUs. * - * (C) Copyright 1999-2006, Greg Ungerer . + * (C) Copyright 1999-2010, Greg Ungerer . */ /*****************************************************************************/ @@ -13,7 +13,6 @@ #include #include #include -#include #include #include @@ -173,10 +172,27 @@ _start: /* * Now that we know what the memory is, lets enable cache - * and get things moving. This is Coldfire CPU specific. + * and get things moving. This is Coldfire CPU specific. Not + * all version cores have identical cache register setup. But + * it is very similar. Define the exact settings in the headers + * then the code here is the same for all. */ - CACHE_ENABLE /* enable CPU cache */ - + movel #CACHE_INIT,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + movel #ACR0_MODE,%d0 /* set RAM region for caching */ + movec %d0,%ACR0 + movel #ACR1_MODE,%d0 /* anything else to cache? */ + movec %d0,%ACR1 +#ifdef ACR2_MODE + movel #ACR2_MODE,%d0 + movec %d0,%ACR2 + movel #ACR3_MODE,%d0 + movec %d0,%ACR3 +#endif + movel #CACHE_MODE,%d0 /* enable cache */ + movec %d0,%CACR + nop #ifdef CONFIG_ROMFS_FS /* -- cgit v1.2.3-70-g09d2 From 0ef6c9b8f7bf62ea05be5b26ee14b18a116b0c2a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 9 Nov 2010 15:31:08 +1000 Subject: m68knommu: support version 2 ColdFire split cache The newer version 2 ColdFire CPU cores support a configurable cache arrangement. The cache memory can be used as all instruction cache, all data cache, or split in half for both instruction and data caching. Support this setup via a Kconfig time menu that allows a kernel builder to choose the arrangement they want to use. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m52xxacr.h | 30 ++++++++++++++++-------------- arch/m68knommu/Kconfig | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 14 deletions(-) (limited to 'arch/m68k/include/asm/m52xxacr.h') diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 52230b5e1e4..701f680bced 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h @@ -53,23 +53,25 @@ #define ACR_WPROTECT 0x00000004 /* Write protect region */ /* - * Set the cache controller settings we will use. This code is set to - * only use the instruction cache, even on the controllers that support - * split cache. (This setup is trying to preserve the existing behavior - * for now, in the furture I hope to actually use the split cache mode). + * Set the cache controller settings we will use. On the cores that support + * a split cache configuration we allow all the combinations at Kconfig + * time. For those cores that only have an instruction cache we just set + * that as on. */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5249) || defined(CONFIG_M5272) -#define CACHE_INIT (CACR_CINV) -#define CACHE_MODE (CACR_CENB + CACR_DCM) +#if defined(CONFIG_CACHE_I) +#define CACHE_TYPE CACR_DISD +#elif defined(CONFIG_CACHE_D) +#define CACHE_TYPE CACR_DISI #else -#ifdef CONFIG_COLDFIRE_SW_A7 -#define CACHE_INIT (CACR_CINV + CACR_DISD) -#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM) -#else -#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP) -#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP) +#define CACHE_TYPE #endif + +#if defined(CONFIG_HAVE_CACHE_SPLIT) +#define CACHE_INIT (CACR_CINV + CACHE_TYPE + CACR_EUSP) +#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP) +#else +#define CACHE_INIT (CACR_CINV) +#define CACHE_MODE (CACR_CENB + CACR_DCM) #endif #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index e6f482d18d0..61c29081b99 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -79,6 +79,9 @@ config COLDFIRE_SW_A7 bool default n +config HAVE_CACHE_SPLIT + bool + source "init/Kconfig" source "kernel/Kconfig.freezer" @@ -124,12 +127,14 @@ config M5206e config M520x bool "MCF520x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5207/5208 processor support. config M523x bool "MCF523x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Freescale Coldfire 5230/1/2/4/5 processor support @@ -141,6 +146,7 @@ config M5249 config M5271 bool "MCF5271" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5270/5271 processor support. @@ -152,12 +158,14 @@ config M5272 config M5275 bool "MCF5275" + select HAVE_CACHE_SPLIT help Freescale (Motorola) ColdFire 5274/5275 processor support. config M528x bool "MCF528x" select GENERIC_CLOCKEVENTS + select HAVE_CACHE_SPLIT help Motorola ColdFire 5280/5282 processor support. @@ -250,6 +258,30 @@ config OLDMASK Build support for the older revision ColdFire 5307 silicon. Specifically this is the 1H55J mask revision. +if HAVE_CACHE_SPLIT +choice + prompt "Split Cache Configuration" + default CACHE_I + +config CACHE_I + bool "Instruction" + help + Use all of the ColdFire CPU cache memory as an instruction cache. + +config CACHE_D + bool "Data" + help + Use all of the ColdFire CPU cache memory as a data cache. + +config CACHE_BOTH + bool "Both" + help + Split the ColdFire CPU cache, and use half as an instruction cache + and half as a data cache. +endchoice + +endif + comment "Platform" config PILOT3 -- cgit v1.2.3-70-g09d2 From 07ffee59a756e3d16295fa1e0a4849c7a2273a13 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 10 Nov 2010 15:22:19 +1000 Subject: m68knommu: create optimal separate instruction and data cache for ColdFire Create separate functions to deal with instruction and data cache flushing. This way we can optimize them for the vairous cache types and arrangements used across the ColdFire family. For example the unified caches in the version 3 cores means we don't need to flush the instruction cache. For the version 2 cores that do not do data cacheing (or where we choose instruction cache only) we don't need to do any data flushing. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/cacheflush_no.h | 38 +++++++++++++++++++++++++++++++---- arch/m68k/include/asm/m52xxacr.h | 31 ++++++++++++++++++---------- arch/m68k/include/asm/m53xxacr.h | 27 ++++++++++++++++++++++++- arch/m68k/include/asm/m54xxacr.h | 7 +++---- 4 files changed, 83 insertions(+), 20 deletions(-) (limited to 'arch/m68k/include/asm/m52xxacr.h') diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index f931e182983..cb88aa96c4f 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -12,14 +12,12 @@ #define flush_cache_dup_mm(mm) do { } while (0) #define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) -#ifndef flush_dcache_range -#define flush_dcache_range(start,len) __flush_cache_all() -#endif +#define flush_dcache_range(start, len) __flush_dcache_all() #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 #define flush_dcache_page(page) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start,len) __flush_cache_all() +#define flush_icache_range(start, len) __flush_icache_all() #define flush_icache_page(vma,pg) do { } while (0) #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) #define flush_cache_vmap(start, end) do { } while (0) @@ -46,4 +44,36 @@ static inline void __flush_cache_all(void) #endif } +/* + * Some ColdFire parts implement separate instruction and data caches, + * on those we should just flush the appropriate cache. If we don't need + * to do any specific flushing then this will be optimized away. + */ +static inline void __flush_icache_all(void) +{ +#ifdef CACHE_INVALIDATEI + __asm__ __volatile__ ( + "movel %0, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : "i" (CACHE_INVALIDATEI) : "d0" ); +#endif +} + +static inline void __flush_dcache_all(void) +{ +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif +#ifdef CACHE_INVALIDATED + __asm__ __volatile__ ( + "movel %0, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : "i" (CACHE_INVALIDATED) : "d0" ); +#else + /* Flush the wrtite buffer */ + __asm__ __volatile__ ( "nop" ); +#endif +} #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h index 701f680bced..abc391a9ae8 100644 --- a/arch/m68k/include/asm/m52xxacr.h +++ b/arch/m68k/include/asm/m52xxacr.h @@ -59,22 +59,31 @@ * that as on. */ #if defined(CONFIG_CACHE_I) -#define CACHE_TYPE CACR_DISD +#define CACHE_TYPE (CACR_DISD + CACR_EUSP) +#define CACHE_INVTYPEI 0 #elif defined(CONFIG_CACHE_D) -#define CACHE_TYPE CACR_DISI +#define CACHE_TYPE (CACR_DISI + CACR_EUSP) +#define CACHE_INVTYPED 0 +#elif defined(CONFIG_CACHE_BOTH) +#define CACHE_TYPE CACR_EUSP +#define CACHE_INVTYPEI CACR_INVI +#define CACHE_INVTYPED CACR_INVD #else -#define CACHE_TYPE +/* This is the instruction cache only devices (no split cache, no eusp) */ +#define CACHE_TYPE 0 +#define CACHE_INVTYPEI 0 #endif -#if defined(CONFIG_HAVE_CACHE_SPLIT) -#define CACHE_INIT (CACR_CINV + CACHE_TYPE + CACR_EUSP) -#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP) -#else -#define CACHE_INIT (CACR_CINV) -#define CACHE_MODE (CACR_CENB + CACR_DCM) -#endif +#define CACHE_INIT (CACR_CINV + CACHE_TYPE) +#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM) -#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) +#if defined(CACHE_INVTYPEI) +#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI) +#endif +#if defined(CACHE_INVTYPED) +#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED) +#endif #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index d8b8dd68368..cd952b0a8bd 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -48,6 +48,22 @@ #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ #define ACR_WPROTECT 0x00000004 /* Write protect region */ +/* + * Define the cache type and arrangement (needed for pushes). + */ +#if defined(CONFIG_M5307) +#define CACHE_SIZE 0x2000 /* 8k of unified cache */ +#define ICACHE_SIZE CACHE_SIZE +#define DCACHE_SIZE CACHE_SIZE +#elif defined(CONFIG_M532x) +#define CACHE_SIZE 0x4000 /* 32k of unified cache */ +#define ICACHE_SIZE CACHE_SIZE +#define DCACHE_SIZE CACHE_SIZE +#endif + +#define CACHE_LINE_SIZE 16 /* 16 byte line size */ +#define CACHE_WAYS 4 /* 4 ways - set associative */ + /* * Set the cache controller settings we will use. This default in the * CACR is cache inhibited, we use the ACR register to set cacheing @@ -55,6 +71,7 @@ */ #if defined(CONFIG_CACHE_COPYBACK) #define CACHE_TYPE ACR_CM_CB +#define CACHE_PUSH #else #define CACHE_TYPE ACR_CM_WT #endif @@ -65,7 +82,15 @@ #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) #endif -#define CACHE_INIT CACR_CINVA +/* + * Unified cache means we will never need to flush for coherency of + * instruction fetch. We will need to flush to maintain memory/DMA + * coherency though in all cases. And for copyback caches we will need + * to push cached data as well. + */ +#define CACHE_INIT CACR_CINVA +#define CACHE_INVALIDATE CACR_CINVA +#define CACHE_INVALIDATED CACR_CINVA #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 29d4713f796..16a1835f9b2 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -81,15 +81,14 @@ #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) -#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) #define ACR1_MODE 0 #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 -#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) -#define flush_dcache_range(a, l) do { asm("nop"); } while (0) -#endif #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) /* Copyback cache mode must push dirty cache lines first */ #define CACHE_PUSH -- cgit v1.2.3-70-g09d2