From 07ffee59a756e3d16295fa1e0a4849c7a2273a13 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 10 Nov 2010 15:22:19 +1000 Subject: m68knommu: create optimal separate instruction and data cache for ColdFire Create separate functions to deal with instruction and data cache flushing. This way we can optimize them for the vairous cache types and arrangements used across the ColdFire family. For example the unified caches in the version 3 cores means we don't need to flush the instruction cache. For the version 2 cores that do not do data cacheing (or where we choose instruction cache only) we don't need to do any data flushing. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m54xxacr.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/m68k/include/asm/m54xxacr.h') diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 29d4713f796..16a1835f9b2 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -81,15 +81,14 @@ #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) -#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) #define ACR1_MODE 0 #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 -#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) -#define flush_dcache_range(a, l) do { asm("nop"); } while (0) -#endif #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) /* Copyback cache mode must push dirty cache lines first */ #define CACHE_PUSH -- cgit v1.2.3-70-g09d2