From c573b29baf3e1b71a60ee6de76dd28c9c49fb87f Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Thu, 2 Jul 2009 14:08:03 +1000 Subject: arch/m68knommu/kernel/time.c: Remove unnecessary semicolons Signed-off-by: Joe Perches Signed-off-by: Greg Ungerer --- arch/m68knommu/kernel/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/m68knommu/kernel') diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c index d182b2f7221..c2aa717de08 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68knommu/kernel/time.c @@ -69,7 +69,7 @@ static unsigned long read_rtc_mmss(void) if ((year += 1900) < 1970) year += 100; - return mktime(year, mon, day, hour, min, sec);; + return mktime(year, mon, day, hour, min, sec); } unsigned long read_persistent_clock(void) -- cgit v1.2.3-70-g09d2 From d668bf0a0d73daea4eaaf748435752f52cc077aa Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 4 Aug 2009 16:52:44 +0200 Subject: m68knommu: convert to asm-generic/hardirq.h Signed-off-by: Christoph Hellwig Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/hardirq_no.h | 10 +--------- arch/m68knommu/kernel/irq.c | 5 ----- 2 files changed, 1 insertion(+), 14 deletions(-) (limited to 'arch/m68knommu/kernel') diff --git a/arch/m68k/include/asm/hardirq_no.h b/arch/m68k/include/asm/hardirq_no.h index bfad28149a4..b44b14be87d 100644 --- a/arch/m68k/include/asm/hardirq_no.h +++ b/arch/m68k/include/asm/hardirq_no.h @@ -1,16 +1,8 @@ #ifndef __M68K_HARDIRQ_H #define __M68K_HARDIRQ_H -#include -#include #include -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include /* Standard mappings for irq_cpustat_t above */ - #define HARDIRQ_BITS 8 /* @@ -22,6 +14,6 @@ typedef struct { # error HARDIRQ_BITS is too low! #endif -void ack_bad_irq(unsigned int irq); +#include #endif /* __M68K_HARDIRQ_H */ diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c index 56e0f4c55a6..9e0c100447c 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68knommu/kernel/irq.c @@ -29,11 +29,6 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) set_irq_regs(oldregs); } -void ack_bad_irq(unsigned int irq) -{ - printk(KERN_ERR "IRQ: unexpected irq=%d\n", irq); -} - static struct irq_chip m_irq_chip = { .name = "M68K-INTC", .enable = enable_vector, -- cgit v1.2.3-70-g09d2 From cd3dd4068db5e1258a14b63e0feaf0332640d896 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 27 Apr 2009 15:09:29 +1000 Subject: m68knommu: use general interrupt controller for ColdFire 520x family Create general interrupt controller code for the ColdFire 520x family, that does proper masking and unmasking of interrupts. With this in place some of the driver hacks in place to support ColdFire interrupts can finally go away. Within the ColdFire family there is a variety of different interrupt controllers in use. Some are used on multiple parts, some on only one. There is quite some differences in some varients, so much so that common code for all ColdFire parts would be impossible. This commit introduces code to support one of the newer interrupt controllers in the ColdFire 5208 and 5207 parts. It has very simple mask and unmask operations, so is one of the easiest to support. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m520xsim.h | 2 + arch/m68knommu/kernel/irq.c | 4 ++ arch/m68knommu/platform/coldfire/Makefile | 2 +- arch/m68knommu/platform/coldfire/intc-simr.c | 61 ++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 arch/m68knommu/platform/coldfire/intc-simr.c (limited to 'arch/m68knommu/kernel') diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index e80b6a54ea9..e79b9bc76a1 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -22,6 +22,8 @@ #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ +#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ #define MCFINTC_ICR0 0x40 /* Base ICR register */ #define MCFINT_VECBASE 64 diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c index 9e0c100447c..47f6af57e18 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68knommu/kernel/irq.c @@ -29,6 +29,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) set_irq_regs(oldregs); } +#if !defined(CONFIG_M520x) + static struct irq_chip m_irq_chip = { .name = "M68K-INTC", .enable = enable_vector, @@ -50,6 +52,8 @@ void __init init_IRQ(void) } } +#endif + int show_interrupts(struct seq_file *p, void *v) { struct irqaction *ap; diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index 2667323c7fe..dd242db7daa 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -17,7 +17,7 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o obj-$(CONFIG_M5206) += timers.o obj-$(CONFIG_M5206e) += timers.o -obj-$(CONFIG_M520x) += pit.o +obj-$(CONFIG_M520x) += pit.o intc-simr.o obj-$(CONFIG_M523x) += pit.o dma_timer.o obj-$(CONFIG_M5249) += timers.o obj-$(CONFIG_M527x) += pit.o diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c new file mode 100644 index 00000000000..3b614a3508f --- /dev/null +++ b/arch/m68knommu/platform/coldfire/intc-simr.c @@ -0,0 +1,61 @@ +/* + * intc-simr.c + * + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void intc_irq_mask(unsigned int irq) +{ + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63)) + __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR); +} + +static void intc_irq_unmask(unsigned int irq) +{ + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63)) + __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR); +} + +static int intc_irq_set_type(unsigned int irq, unsigned int type) +{ + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63)) + __raw_writeb(5, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + irq - MCFINT_VECBASE); + return 0; +} + +static struct irq_chip intc_irq_chip = { + .name = "CF-INTC", + .mask = intc_irq_mask, + .unmask = intc_irq_unmask, + .set_type = intc_irq_set_type, +}; + +void __init init_IRQ(void) +{ + int irq; + + init_vectors(); + + for (irq = 0; (irq < NR_IRQS); irq++) { + irq_desc[irq].status = IRQ_DISABLED; + irq_desc[irq].action = NULL; + irq_desc[irq].depth = 1; + irq_desc[irq].chip = &intc_irq_chip; + intc_irq_set_type(irq, 0); + } +} + -- cgit v1.2.3-70-g09d2 From 2fba4f0b035f7723073068cf8b3a01ec38f72ed5 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 27 Apr 2009 15:38:03 +1000 Subject: m68knommu: general interrupt controller for ColdFire many 52xx parts Create general interrupt controller code for the many ColdFire version 2 cores that use the two region INTC interrupt controller. This includes the 523x family, 5270, 5271, 5274, 5275, and the 528x families. This code does proper masking and unmasking of interrupts. With this in place some of the driver hacks in place to support ColdFire interrupts can finally go away. Signed-off-by: Greg Ungerer --- arch/m68knommu/kernel/irq.c | 3 +- arch/m68knommu/platform/coldfire/Makefile | 6 +- arch/m68knommu/platform/coldfire/intc-2.c | 93 +++++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+), 4 deletions(-) create mode 100644 arch/m68knommu/platform/coldfire/intc-2.c (limited to 'arch/m68knommu/kernel') diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c index 47f6af57e18..f9965d7ee7c 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68knommu/kernel/irq.c @@ -29,7 +29,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) set_irq_regs(oldregs); } -#if !defined(CONFIG_M520x) +#if !defined(CONFIG_M520x) && !defined(CONFIG_M523x) && \ + !defined(CONFIG_M527x) && !defined(CONFIG_M528x) static struct irq_chip m_irq_chip = { .name = "M68K-INTC", diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index dd242db7daa..bce9a62d3a1 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -18,11 +18,11 @@ obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o obj-$(CONFIG_M5206) += timers.o obj-$(CONFIG_M5206e) += timers.o obj-$(CONFIG_M520x) += pit.o intc-simr.o -obj-$(CONFIG_M523x) += pit.o dma_timer.o +obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o obj-$(CONFIG_M5249) += timers.o -obj-$(CONFIG_M527x) += pit.o +obj-$(CONFIG_M527x) += pit.o intc-2.o obj-$(CONFIG_M5272) += timers.o -obj-$(CONFIG_M528x) += pit.o +obj-$(CONFIG_M528x) += pit.o intc-2.o obj-$(CONFIG_M5307) += timers.o obj-$(CONFIG_M532x) += timers.o obj-$(CONFIG_M5407) += timers.o diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c new file mode 100644 index 00000000000..5598c8b8661 --- /dev/null +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -0,0 +1,93 @@ +/* + * intc-1.c + * + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Each vector needs a unique priority and level asscoiated with it. + * We don't really care so much what they are, we don't rely on the + * tranditional priority interrupt scheme of the m68k/ColdFire. + */ +static u8 intc_intpri = 0x36; + +static void intc_irq_mask(unsigned int irq) +{ + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { + unsigned long imraddr; + u32 val, imrbit; + + irq -= MCFINT_VECBASE; + imraddr = MCF_IPSBAR; + imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; + imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; + imrbit = 0x1 << (irq & 0x1f); + + val = __raw_readl(imraddr); + __raw_writel(val | imrbit, imraddr); + } +} + +static void intc_irq_unmask(unsigned int irq) +{ + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { + unsigned long intaddr, imraddr, icraddr; + u32 val, imrbit; + + irq -= MCFINT_VECBASE; + intaddr = MCF_IPSBAR; + intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; + imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); + icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); + imrbit = 0x1 << (irq & 0x1f); + + /* Don't set the "maskall" bit! */ + if ((irq & 0x20) == 0) + imrbit |= 0x1; + + if (__raw_readb(icraddr) == 0) + __raw_writeb(intc_intpri--, icraddr); + + val = __raw_readl(imraddr); + __raw_writel(val & ~imrbit, imraddr); + } +} + +static struct irq_chip intc_irq_chip = { + .name = "CF-INTC", + .mask = intc_irq_mask, + .unmask = intc_irq_unmask, +}; + +void __init init_IRQ(void) +{ + int irq; + + init_vectors(); + + /* Mask all interrupt sources */ + __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); + __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); + + for (irq = 0; (irq < NR_IRQS); irq++) { + irq_desc[irq].status = IRQ_DISABLED; + irq_desc[irq].action = NULL; + irq_desc[irq].depth = 1; + irq_desc[irq].chip = &intc_irq_chip; + } +} + -- cgit v1.2.3-70-g09d2 From 277c5e3e26cac45010f57a581c56476639b2cfa0 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Wed, 29 Apr 2009 12:07:13 +1000 Subject: m68knommu: general interrupt controller for ColdFire 532x parts The ColdFire 532x family of parts uses 2 of the same INTC interrupt controlers used in the ColdFire 520x family. So modify the code to support both parts. The extra code for the second INTC controler in the case of the 520x is easily optimized away to nothing. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m520xsim.h | 15 +++++++++++++-- arch/m68k/include/asm/m532xsim.h | 18 ++++++++++-------- arch/m68knommu/kernel/irq.c | 3 ++- arch/m68knommu/platform/coldfire/Makefile | 2 +- arch/m68knommu/platform/coldfire/intc-simr.c | 24 ++++++++++++++++++------ 5 files changed, 44 insertions(+), 18 deletions(-) (limited to 'arch/m68knommu/kernel') diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index e79b9bc76a1..91de39c8d86 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -11,9 +11,8 @@ #define m520xsim_h /****************************************************************************/ - /* - * Define the 5282 SIM register set addresses. + * Define the 520x SIM register set addresses. */ #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ @@ -26,6 +25,18 @@ #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ #define MCFINTC_ICR0 0x40 /* Base ICR register */ +/* + * The common interrupt controller code just wants to know the absolute + * address to the SIMR and CIMR registers (not offsets into IPSBAR). + * The 520x family only has a single INTC unit. + */ +#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR) +#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR) +#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0) +#define MCFINTC1_SIMR (0) +#define MCFINTC1_CIMR (0) +#define MCFINTC1_ICR0 (0) + #define MCFINT_VECBASE 64 #define MCFINT_UART0 26 /* Interrupt number for UART0 */ #define MCFINT_UART1 27 /* Interrupt number for UART1 */ diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 3e80810b378..41c57e0f445 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -58,10 +58,12 @@ #define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */ -#define MCFSIM_IMR_SIMR0 0xFC04801C -#define MCFSIM_IMR_SIMR1 0xFC04C01C -#define MCFSIM_IMR_CIMR0 0xFC04801D -#define MCFSIM_IMR_CIMR1 0xFC04C01D +#define MCFINTC0_SIMR 0xFC04801C +#define MCFINTC0_CIMR 0xFC04801D +#define MCFINTC0_ICR0 0xFC048040 +#define MCFINTC1_SIMR 0xFC04C01C +#define MCFINTC1_CIMR 0xFC04C01D +#define MCFINTC1_ICR0 0xFC04C040 #define MCFSIM_ICR_TIMER1 (0xFC048040+32) #define MCFSIM_ICR_TIMER2 (0xFC048040+33) @@ -87,16 +89,16 @@ #define mcf_enable_irq0(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq); + *((volatile unsigned char *) (MCFINTC0_CIMR)) = (irq); #define mcf_enable_irq1(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq); + *((volatile unsigned char *) (MCFINTC1_CIMR)) = (irq); #define mcf_disable_irq0(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq); + *((volatile unsigned char *) (MCFINTC0_SIMR)) = (irq); #define mcf_disable_irq1(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq); + *((volatile unsigned char *) (MCFINTC1_SIMR)) = (irq); /* * Define the Cache register flags. diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c index f9965d7ee7c..93d567bbf33 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68knommu/kernel/irq.c @@ -30,7 +30,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) } #if !defined(CONFIG_M520x) && !defined(CONFIG_M523x) && \ - !defined(CONFIG_M527x) && !defined(CONFIG_M528x) + !defined(CONFIG_M527x) && !defined(CONFIG_M528x) && \ + !defined(CONFIG_M532x) static struct irq_chip m_irq_chip = { .name = "M68K-INTC", diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index bce9a62d3a1..6c5f699cf14 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_M527x) += pit.o intc-2.o obj-$(CONFIG_M5272) += timers.o obj-$(CONFIG_M528x) += pit.o intc-2.o obj-$(CONFIG_M5307) += timers.o -obj-$(CONFIG_M532x) += timers.o +obj-$(CONFIG_M532x) += timers.o intc-simr.o obj-$(CONFIG_M5407) += timers.o obj-y += pinmux.o gpio.o diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c index 3b614a3508f..86fc2047d7a 100644 --- a/arch/m68knommu/platform/coldfire/intc-simr.c +++ b/arch/m68knommu/platform/coldfire/intc-simr.c @@ -20,20 +20,32 @@ static void intc_irq_mask(unsigned int irq) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63)) - __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR); + if (irq >= MCFINT_VECBASE) { + if (irq < MCFINT_VECBASE + 64) + __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR); + else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR) + __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR); + } } static void intc_irq_unmask(unsigned int irq) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63)) - __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR); + if (irq >= MCFINT_VECBASE) { + if (irq < MCFINT_VECBASE + 64) + __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR); + else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR) + __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR); + } } static int intc_irq_set_type(unsigned int irq, unsigned int type) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63)) - __raw_writeb(5, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + irq - MCFINT_VECBASE); + if (irq >= MCFINT_VECBASE) { + if (irq < MCFINT_VECBASE + 64) + __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE); + else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0) + __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64); + } return 0; } -- cgit v1.2.3-70-g09d2 From 33a21263bf74177209c11f08246fc308916d9ffa Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 30 Apr 2009 16:22:24 +1000 Subject: m68knommu: use common interrupt controller code for older ColdFire CPU's The old ColdFire CPU's (5206, 5307, 5407, 5249 etc) use a simple interrupt controller. Use common setup code for them. This addition means that all ColdFire CPU's now have some specific type of interrupt controller code. Signed-off-by: Greg Ungerer --- arch/m68knommu/kernel/irq.c | 4 +-- arch/m68knommu/platform/coldfire/Makefile | 12 +++---- arch/m68knommu/platform/coldfire/intc.c | 55 ++++++++++++++++++++++++++++++ arch/m68knommu/platform/coldfire/vectors.c | 20 +---------- 4 files changed, 63 insertions(+), 28 deletions(-) create mode 100644 arch/m68knommu/platform/coldfire/intc.c (limited to 'arch/m68knommu/kernel') diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c index 93d567bbf33..73daaf0a455 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68knommu/kernel/irq.c @@ -29,9 +29,7 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) set_irq_regs(oldregs); } -#if !defined(CONFIG_M520x) && !defined(CONFIG_M523x) && \ - !defined(CONFIG_M527x) && !defined(CONFIG_M528x) && \ - !defined(CONFIG_M532x) +#if !defined(CONFIG_COLDFIRE) static struct irq_chip m_irq_chip = { .name = "M68K-INTC", diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile index 6c5f699cf14..24ea95a2312 100644 --- a/arch/m68knommu/platform/coldfire/Makefile +++ b/arch/m68knommu/platform/coldfire/Makefile @@ -15,17 +15,17 @@ asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o -obj-$(CONFIG_M5206) += timers.o -obj-$(CONFIG_M5206e) += timers.o +obj-$(CONFIG_M5206) += timers.o intc.o +obj-$(CONFIG_M5206e) += timers.o intc.o obj-$(CONFIG_M520x) += pit.o intc-simr.o obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o -obj-$(CONFIG_M5249) += timers.o +obj-$(CONFIG_M5249) += timers.o intc.o obj-$(CONFIG_M527x) += pit.o intc-2.o -obj-$(CONFIG_M5272) += timers.o +obj-$(CONFIG_M5272) += timers.o intc.o obj-$(CONFIG_M528x) += pit.o intc-2.o -obj-$(CONFIG_M5307) += timers.o +obj-$(CONFIG_M5307) += timers.o intc.o obj-$(CONFIG_M532x) += timers.o intc-simr.o -obj-$(CONFIG_M5407) += timers.o +obj-$(CONFIG_M5407) += timers.o intc.o obj-y += pinmux.o gpio.o extra-y := head.o diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c new file mode 100644 index 00000000000..c81ab6e5cf2 --- /dev/null +++ b/arch/m68knommu/platform/coldfire/intc.c @@ -0,0 +1,55 @@ +/* + * intc.c + * + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void intc_irq_mask(unsigned int irq) +{ +} + +static void intc_irq_unmask(unsigned int irq) +{ +} + +static int intc_irq_set_type(unsigned int irq, unsigned int type) +{ + return 0; +} + +static struct irq_chip intc_irq_chip = { + .name = "CF-INTC", + .mask = intc_irq_mask, + .unmask = intc_irq_unmask, + .set_type = intc_irq_set_type, +}; + +void __init init_IRQ(void) +{ + int irq; + + init_vectors(); + + for (irq = 0; (irq < NR_IRQS); irq++) { + irq_desc[irq].status = IRQ_DISABLED; + irq_desc[irq].action = NULL; + irq_desc[irq].depth = 1; + irq_desc[irq].chip = &intc_irq_chip; + intc_irq_set_type(irq, 0); + } +} + diff --git a/arch/m68knommu/platform/coldfire/vectors.c b/arch/m68knommu/platform/coldfire/vectors.c index bdca0297fa9..a21d3f870b7 100644 --- a/arch/m68knommu/platform/coldfire/vectors.c +++ b/arch/m68knommu/platform/coldfire/vectors.c @@ -1,7 +1,7 @@ /***************************************************************************/ /* - * linux/arch/m68knommu/platform/5307/vectors.c + * linux/arch/m68knommu/platform/coldfire/vectors.c * * Copyright (C) 1999-2007, Greg Ungerer */ @@ -15,7 +15,6 @@ #include #include #include -#include #include /***************************************************************************/ @@ -79,20 +78,3 @@ void __init init_vectors(void) } /***************************************************************************/ - -void enable_vector(unsigned int irq) -{ - /* Currently no action on ColdFire */ -} - -void disable_vector(unsigned int irq) -{ - /* Currently no action on ColdFire */ -} - -void ack_vector(unsigned int irq) -{ - /* Currently no action on ColdFire */ -} - -/***************************************************************************/ -- cgit v1.2.3-70-g09d2 From de4cbfb5994465e7c0f4cc545722b1144e8ba717 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Fri, 1 May 2009 17:23:37 +1000 Subject: m68knommu: remove the common interrupt controller structure Each different m68knommu CPU interrupt controller type has its own interrupt controller data structures now. Remove the old, and now not used, common irq structs and init code from here. Signed-off-by: Greg Ungerer --- arch/m68knommu/kernel/irq.c | 25 ------------------------- 1 file changed, 25 deletions(-) (limited to 'arch/m68knommu/kernel') diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c index 73daaf0a455..c9cac36d442 100644 --- a/arch/m68knommu/kernel/irq.c +++ b/arch/m68knommu/kernel/irq.c @@ -29,31 +29,6 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) set_irq_regs(oldregs); } -#if !defined(CONFIG_COLDFIRE) - -static struct irq_chip m_irq_chip = { - .name = "M68K-INTC", - .enable = enable_vector, - .disable = disable_vector, - .ack = ack_vector, -}; - -void __init init_IRQ(void) -{ - int irq; - - init_vectors(); - - for (irq = 0; (irq < NR_IRQS); irq++) { - irq_desc[irq].status = IRQ_DISABLED; - irq_desc[irq].action = NULL; - irq_desc[irq].depth = 1; - irq_desc[irq].chip = &m_irq_chip; - } -} - -#endif - int show_interrupts(struct seq_file *p, void *v) { struct irqaction *ap; -- cgit v1.2.3-70-g09d2