From e87dddeb92618d9dbb8b9f946a193739a4447609 Mon Sep 17 00:00:00 2001 From: Peter Horton Date: Sun, 12 Feb 2006 17:10:25 +0000 Subject: [MIPS] Add early console for Cobalt. Signed-off-by: Peter Horton Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3a0f89d2c8d..9d1e78f9c06 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -790,6 +790,7 @@ source "arch/mips/tx4927/Kconfig" source "arch/mips/tx4938/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/philips/pnx8550/common/Kconfig" +source "arch/mips/cobalt/Kconfig" endmenu -- cgit v1.2.3-70-g09d2 From c1449c8fa40859eb269025a7db85b34115205f5b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 15 Feb 2006 15:17:19 +0000 Subject: [MIPS] Symmetric Uniprocessor support for Qemu. SMP bits needed to builds and run an SMP kernel. While only a single processor is supported ATM it's still useful for some SMP debugging using Qemu. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 2 +- arch/mips/qemu/Makefile | 2 ++ arch/mips/qemu/q-smp.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 arch/mips/qemu/q-smp.c (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9d1e78f9c06..6356f7d52ce 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1582,7 +1582,7 @@ source "mm/Kconfig" config SMP bool "Multi-Processing support" - depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP + depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP ---help--- This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile index 934944ab9e8..6a8e8bcef55 100644 --- a/arch/mips/qemu/Makefile +++ b/arch/mips/qemu/Makefile @@ -3,3 +3,5 @@ # obj-y = q-firmware.o q-int.o q-irq.o q-mem.o q-setup.o + +obj-$(CONFIG_SMP) += q-smp.o diff --git a/arch/mips/qemu/q-smp.c b/arch/mips/qemu/q-smp.c new file mode 100644 index 00000000000..5a12354cd57 --- /dev/null +++ b/arch/mips/qemu/q-smp.c @@ -0,0 +1,48 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org) + * + * Symmetric Uniprocessor (TM) Support + */ +#include +#include + +/* + * Send inter-processor interrupt + */ +void core_send_ipi(int cpu, unsigned int action) +{ + panic(KERN_ERR "%s called", __FUNCTION__); +} + +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +void prom_init_secondary(void) +{ +} + +void prom_smp_finish(void) +{ +} + +/* Hook for after all CPUs are online */ +void prom_cpus_done(void) +{ +} + +void __init prom_prepare_cpus(unsigned int max_cpus) +{ + cpus_clear(phys_cpu_present_map); +} + +/* + * Firmware CPU startup hook + */ +void prom_boot_secondary(int cpu, struct task_struct *idle) +{ +} -- cgit v1.2.3-70-g09d2 From a206f6a7aa78cfaad1d4519e87d9a54fa2b5cfa6 Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Wed, 1 Mar 2006 01:55:05 +0000 Subject: [MIPS] Mention Broadcom part number for BigSur board Mention the Broadcom part number for the BigSur board (BCM91480B) in Kconfig, just like it's done for other Broadcom boards. Signed-off-by: Martin Michlmayr Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6356f7d52ce..97a9769a904 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -602,7 +602,7 @@ config SGI_IP32 If you want this kernel to run on SGI O2 workstation, say Y here. config SIBYTE_BIGSUR - bool "Support for Sibyte BigSur" + bool "Support for Sibyte BCM91480B-BigSur" select BOOT_ELF32 select DMA_COHERENT select PCI_DOMAINS -- cgit v1.2.3-70-g09d2 From de862b488e81172d4c610945efd9f3fc7f4b84a7 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Fri, 17 Mar 2006 12:59:22 +0900 Subject: [MIPS] TX49XX has prefetch. The TX49XX has the prefetch instruction. It supports only Pref_Load (hint 0). Actually changes in this patch except for Kconfig are not have any effects, I added these changes to prevent misuse of unsupported hints. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/pg-r4k.c | 10 ++++++++-- 3 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 97a9769a904..ac2012f033d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1160,6 +1160,7 @@ config CPU_R4X00 config CPU_TX49XX bool "R49XX" depends on SYS_HAS_CPU_TX49XX + select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 9572ed44f0d..32b7f6aeb98 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -786,6 +786,7 @@ static void __init probe_pcache(void) c->dcache.waybit = 0; c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_PREFETCH; break; case CPU_R4000PC: diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index f51e180072e..e4390dc3eb4 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c @@ -124,7 +124,7 @@ static inline void build_nop(void) static inline void build_src_pref(int advance) { - if (!(load_offset & (cpu_dcache_line_size() - 1))) { + if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) { union mips_instruction mi; mi.i_format.opcode = pref_op; @@ -166,7 +166,7 @@ static inline void build_load_reg(int reg) static inline void build_dst_pref(int advance) { - if (!(store_offset & (cpu_dcache_line_size() - 1))) { + if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) { union mips_instruction mi; mi.i_format.opcode = pref_op; @@ -340,6 +340,12 @@ void __init build_clear_page(void) if (cpu_has_prefetch) { switch (current_cpu_data.cputype) { + case CPU_TX49XX: + /* TX49 supports only Pref_Load */ + pref_offset_clear = 0; + pref_offset_copy = 0; + break; + case CPU_RM9000: /* * As a workaround for erratum G105 which make the -- cgit v1.2.3-70-g09d2 From 3c9ee7ef87414cba80dbdf433d3547bb20055ef7 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sun, 26 Mar 2006 01:39:30 -0800 Subject: [PATCH] bitops: mips: use generic bitops - remove __{,test_and_}{set,clear,change}_bit() and test_bit() - unless defined(CONFIG_CPU_MIPS32) or defined(CONFIG_CPU_MIPS64) - remove __ffs() - remove ffs() - remove ffz() - remove fls() - remove fls64() - remove find_{next,first}{,_zero}_bit() - remove sched_find_first_bit() - remove generic_hweight64() - remove generic_hweight{32,16,8}() - remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit() - remove ext2_{set,clear}_bit_atomic() - remove minix_{test,set,test_and_clear,test,find_first_zero}_bit() Signed-off-by: Akinobu Mita Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/mips/Kconfig | 8 + include/asm-mips/bitops.h | 465 ++-------------------------------------------- 2 files changed, 24 insertions(+), 449 deletions(-) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ac2012f033d..5080ea1799a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -801,6 +801,14 @@ config RWSEM_GENERIC_SPINLOCK config RWSEM_XCHGADD_ALGORITHM bool +config GENERIC_FIND_NEXT_BIT + bool + default y + +config GENERIC_HWEIGHT + bool + default y + config GENERIC_CALIBRATE_DELAY bool default y diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 0e83abc829d..a1728f8c070 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -104,22 +104,6 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) } } -/* - * __set_bit - Set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * Unlike set_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __set_bit(unsigned long nr, volatile unsigned long * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - - *m |= 1UL << (nr & SZLONG_MASK); -} - /* * clear_bit - Clears a bit in memory * @nr: Bit to clear @@ -168,22 +152,6 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) } } -/* - * __clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * Unlike clear_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - - *m &= ~(1UL << (nr & SZLONG_MASK)); -} - /* * change_bit - Toggle a bit in memory * @nr: Bit to change @@ -234,22 +202,6 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) } } -/* - * __change_bit - Toggle a bit in memory - * @nr: the bit to change - * @addr: the address to start counting from - * - * Unlike change_bit(), this function is non-atomic and may be reordered. - * If it's called on the same region of memory simultaneously, the effect - * may be that only one operation succeeds. - */ -static inline void __change_bit(unsigned long nr, volatile unsigned long * addr) -{ - unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - - *m ^= 1UL << (nr & SZLONG_MASK); -} - /* * test_and_set_bit - Set a bit and return its old value * @nr: Bit to set @@ -320,30 +272,6 @@ static inline int test_and_set_bit(unsigned long nr, } } -/* - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(unsigned long nr, - volatile unsigned long *addr) -{ - volatile unsigned long *a = addr; - unsigned long mask; - int retval; - - a += nr >> SZLONG_LOG; - mask = 1UL << (nr & SZLONG_MASK); - retval = (mask & *a) != 0; - *a |= mask; - - return retval; -} - /* * test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to clear @@ -416,30 +344,6 @@ static inline int test_and_clear_bit(unsigned long nr, } } -/* - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(unsigned long nr, - volatile unsigned long * addr) -{ - volatile unsigned long *a = addr; - unsigned long mask; - int retval; - - a += (nr >> SZLONG_LOG); - mask = 1UL << (nr & SZLONG_MASK); - retval = ((mask & *a) != 0); - *a &= ~mask; - - return retval; -} - /* * test_and_change_bit - Change a bit and return its old value * @nr: Bit to change @@ -509,43 +413,11 @@ static inline int test_and_change_bit(unsigned long nr, } } -/* - * __test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_change_bit(unsigned long nr, - volatile unsigned long *addr) -{ - volatile unsigned long *a = addr; - unsigned long mask; - int retval; - - a += (nr >> SZLONG_LOG); - mask = 1UL << (nr & SZLONG_MASK); - retval = ((mask & *a) != 0); - *a ^= mask; - - return retval; -} - #undef __bi_flags #undef __bi_local_irq_save #undef __bi_local_irq_restore -/* - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(unsigned long nr, const volatile unsigned long *addr) -{ - return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK)); -} +#include /* * Return the bit position (0..63) of the most significant 1 bit in a word @@ -580,6 +452,8 @@ static inline int __ilog2(unsigned long x) return 63 - lz; } +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + /* * __ffs - find first bit in word. * @word: The word to search @@ -589,31 +463,7 @@ static inline int __ilog2(unsigned long x) */ static inline unsigned long __ffs(unsigned long word) { -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) return __ilog2(word & -word); -#else - int b = 0, s; - -#ifdef CONFIG_32BIT - s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; - s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; - s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; - s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; - s = 1; if (word << 31 != 0) s = 0; b += s; - - return b; -#endif -#ifdef CONFIG_64BIT - s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s; - s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s; - s = 8; if (word << 56 != 0) s = 0; b += s; word >>= s; - s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s; - s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s; - s = 1; if (word << 63 != 0) s = 0; b += s; - - return b; -#endif -#endif } /* @@ -652,321 +502,38 @@ static inline unsigned long ffz(unsigned long word) */ static inline unsigned long fls(unsigned long word) { -#ifdef CONFIG_32BIT #ifdef CONFIG_CPU_MIPS32 __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); return 32 - word; -#else - { - int r = 32, s; - - if (word == 0) - return 0; - - s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; - s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s; - s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; - s = 2; if ((word & 0xc0000000)) s = 0; r -= s; word <<= s; - s = 1; if ((word & 0x80000000)) s = 0; r -= s; - - return r; - } #endif -#endif /* CONFIG_32BIT */ -#ifdef CONFIG_64BIT #ifdef CONFIG_CPU_MIPS64 - __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); return 64 - word; -#else - { - int r = 64, s; - - if (word == 0) - return 0; - - s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; - s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s; - s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s; - s = 4; if ((word & 0xf000000000000000UL)) s = 0; r -= s; word <<= s; - s = 2; if ((word & 0xc000000000000000UL)) s = 0; r -= s; word <<= s; - s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; - - return r; - } #endif -#endif /* CONFIG_64BIT */ } -#define fls64(x) generic_fls64(x) - -/* - * find_next_zero_bit - find the first zero bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The maximum size to search - */ -static inline unsigned long find_next_zero_bit(const unsigned long *addr, - unsigned long size, unsigned long offset) -{ - const unsigned long *p = addr + (offset >> SZLONG_LOG); - unsigned long result = offset & ~SZLONG_MASK; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= SZLONG_MASK; - if (offset) { - tmp = *(p++); - tmp |= ~0UL >> (_MIPS_SZLONG-offset); - if (size < _MIPS_SZLONG) - goto found_first; - if (~tmp) - goto found_middle; - size -= _MIPS_SZLONG; - result += _MIPS_SZLONG; - } - while (size & ~SZLONG_MASK) { - if (~(tmp = *(p++))) - goto found_middle; - result += _MIPS_SZLONG; - size -= _MIPS_SZLONG; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp |= ~0UL << size; - if (tmp == ~0UL) /* Are any bits zero? */ - return result + size; /* Nope. */ -found_middle: - return result + ffz(tmp); -} +#else -#define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) +#include +#include +#include +#include -/* - * find_next_bit - find the next set bit in a memory region - * @addr: The address to base the search on - * @offset: The bitnumber to start searching at - * @size: The maximum size to search - */ -static inline unsigned long find_next_bit(const unsigned long *addr, - unsigned long size, unsigned long offset) -{ - const unsigned long *p = addr + (offset >> SZLONG_LOG); - unsigned long result = offset & ~SZLONG_MASK; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= SZLONG_MASK; - if (offset) { - tmp = *(p++); - tmp &= ~0UL << offset; - if (size < _MIPS_SZLONG) - goto found_first; - if (tmp) - goto found_middle; - size -= _MIPS_SZLONG; - result += _MIPS_SZLONG; - } - while (size & ~SZLONG_MASK) { - if ((tmp = *(p++))) - goto found_middle; - result += _MIPS_SZLONG; - size -= _MIPS_SZLONG; - } - if (!size) - return result; - tmp = *p; - -found_first: - tmp &= ~0UL >> (_MIPS_SZLONG - size); - if (tmp == 0UL) /* Are any bits set? */ - return result + size; /* Nope. */ -found_middle: - return result + __ffs(tmp); -} +#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ -/* - * find_first_bit - find the first set bit in a memory region - * @addr: The address to start the search at - * @size: The maximum size to search - * - * Returns the bit-number of the first set bit, not the number of the byte - * containing a bit. - */ -#define find_first_bit(addr, size) \ - find_next_bit((addr), (size), 0) +#include +#include #ifdef __KERNEL__ -/* - * Every architecture must define this function. It's the fastest - * way of searching a 140-bit bitmap where the first 100 bits are - * unlikely to be set. It's guaranteed that at least one of the 140 - * bits is cleared. - */ -static inline int sched_find_first_bit(const unsigned long *b) -{ -#ifdef CONFIG_32BIT - if (unlikely(b[0])) - return __ffs(b[0]); - if (unlikely(b[1])) - return __ffs(b[1]) + 32; - if (unlikely(b[2])) - return __ffs(b[2]) + 64; - if (b[3]) - return __ffs(b[3]) + 96; - return __ffs(b[4]) + 128; -#endif -#ifdef CONFIG_64BIT - if (unlikely(b[0])) - return __ffs(b[0]); - if (unlikely(b[1])) - return __ffs(b[1]) + 64; - return __ffs(b[2]) + 128; -#endif -} - -/* - * hweightN - returns the hamming weight of a N-bit word - * @x: the word to weigh - * - * The Hamming Weight of a number is the total number of bits set in it. - */ - -#define hweight64(x) generic_hweight64(x) -#define hweight32(x) generic_hweight32(x) -#define hweight16(x) generic_hweight16(x) -#define hweight8(x) generic_hweight8(x) - -static inline int __test_and_set_le_bit(unsigned long nr, unsigned long *addr) -{ - unsigned char *ADDR = (unsigned char *) addr; - int mask, retval; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - retval = (mask & *ADDR) != 0; - *ADDR |= mask; - - return retval; -} - -static inline int __test_and_clear_le_bit(unsigned long nr, unsigned long *addr) -{ - unsigned char *ADDR = (unsigned char *) addr; - int mask, retval; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - retval = (mask & *ADDR) != 0; - *ADDR &= ~mask; - - return retval; -} - -static inline int test_le_bit(unsigned long nr, const unsigned long * addr) -{ - const unsigned char *ADDR = (const unsigned char *) addr; - int mask; - - ADDR += nr >> 3; - mask = 1 << (nr & 0x07); - - return ((mask & *ADDR) != 0); -} - -static inline unsigned long find_next_zero_le_bit(unsigned long *addr, - unsigned long size, unsigned long offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> SZLONG_LOG); - unsigned long result = offset & ~SZLONG_MASK; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= SZLONG_MASK; - if (offset) { - tmp = cpu_to_lelongp(p++); - tmp |= ~0UL >> (_MIPS_SZLONG-offset); /* bug or feature ? */ - if (size < _MIPS_SZLONG) - goto found_first; - if (~tmp) - goto found_middle; - size -= _MIPS_SZLONG; - result += _MIPS_SZLONG; - } - while (size & ~SZLONG_MASK) { - if (~(tmp = cpu_to_lelongp(p++))) - goto found_middle; - result += _MIPS_SZLONG; - size -= _MIPS_SZLONG; - } - if (!size) - return result; - tmp = cpu_to_lelongp(p); - -found_first: - tmp |= ~0UL << size; - if (tmp == ~0UL) /* Are any bits zero? */ - return result + size; /* Nope. */ - -found_middle: - return result + ffz(tmp); -} - -#define find_first_zero_le_bit(addr, size) \ - find_next_zero_le_bit((addr), (size), 0) - -#define ext2_set_bit(nr,addr) \ - __test_and_set_le_bit((nr),(unsigned long*)addr) -#define ext2_clear_bit(nr, addr) \ - __test_and_clear_le_bit((nr),(unsigned long*)addr) - #define ext2_set_bit_atomic(lock, nr, addr) \ -({ \ - int ret; \ - spin_lock(lock); \ - ret = ext2_set_bit((nr), (addr)); \ - spin_unlock(lock); \ - ret; \ -}) - -#define ext2_clear_bit_atomic(lock, nr, addr) \ -({ \ - int ret; \ - spin_lock(lock); \ - ret = ext2_clear_bit((nr), (addr)); \ - spin_unlock(lock); \ - ret; \ -}) -#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr) -#define ext2_find_first_zero_bit(addr, size) \ - find_first_zero_le_bit((unsigned long*)addr, size) -#define ext2_find_next_zero_bit(addr, size, off) \ - find_next_zero_le_bit((unsigned long*)addr, size, off) - -/* - * Bitmap functions for the minix filesystem. - * - * FIXME: These assume that Minix uses the native byte/bitorder. - * This limits the Minix filesystem's value for data exchange very much. - */ -#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) __set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) +#include +#include +#include +#include +#include #endif /* __KERNEL__ */ -- cgit v1.2.3-70-g09d2