From f29ad10de6c345c8ae4cb33a99ba8ff29bdcd751 Mon Sep 17 00:00:00 2001 From: Kelvin Cheung Date: Fri, 10 Oct 2014 11:40:01 +0800 Subject: MIPS: Loongson1B: Some fixes/updates for LS1B - Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data. (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1) - Add GMAC1 support and setup MUX in terms of PHY mode. - Add CPUFreq support. - Add MUX Register Definitions. - Add PWM Register Definitions. - Update clock register bitfields according to the latest spec. - Update clock related stuff. Signed-off-by: Kelvin Cheung Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8024/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/Kconfig') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4a7e0c13c61..9ea76ed1c2e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1573,6 +1573,7 @@ config CPU_LOONGSON1 select CPU_HAS_PREFETCH select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_HIGHMEM + select CPU_SUPPORTS_CPUFREQ config CPU_BMIPS32_3300 select SMP_UP if SMP -- cgit v1.2.3-70-g09d2