From 1990e5429c2149a30a81ff634215c1aa76560a89 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 26 Jun 2013 17:06:34 +0200 Subject: MIPS: Get rid of MIPS I flag and test macros. MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle Patchwork: https://patchwork.linux-mips.org/patch/5551/ --- arch/mips/include/asm/cpu-features.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/mips/include/asm/cpu-features.h') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index e5ec8fcd8af..9609812bc8f 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -24,6 +24,16 @@ #ifndef cpu_has_tlb #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) #endif + +/* + * For the moment we don't consider R6000 and R8000 so we can assume that + * anything that doesn't support R4000-style exceptions and interrupts is + * R3000-like. Users should still treat these two macro definitions as + * opaque. + */ +#ifndef cpu_has_3kex +#define cpu_has_3kex (!cpu_has_4kex) +#endif #ifndef cpu_has_4kex #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) #endif @@ -136,7 +146,6 @@ #endif #endif -# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I) #ifndef cpu_has_mips_2 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) #endif -- cgit v1.2.3-70-g09d2 From 3ddc14add5e6341cf8ef4058c34c67ba7fd15317 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 24 May 2013 20:54:10 +0000 Subject: MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS As Jonas Gorske said in his patch: Disable cpu_has_mmips for everything but SEAD3 and MALTA. Most of these platforms are from before the micromips introduction, so they are very unlikely to implement it. Reduces an -Os compiled, uncompressed kernel image by 8KiB for BCM63XX. This patch taks a different approach than his, we gate the runtime test for microMIPS by the config symbol SYS_SUPPORTS_MICROMIPS. Signed-off-by: David Daney Cc: Jonas Gorski Cc: Steven J. Hill Acked-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5327/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu-features.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/mips/include/asm/cpu-features.h') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 9609812bc8f..8e0c125c59a 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -109,7 +109,11 @@ #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) #endif #ifndef cpu_has_mmips -#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS +# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) +# else +# define cpu_has_mmips 0 +# endif #endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) -- cgit v1.2.3-70-g09d2 From fc192e50f868d8f34b15a18c38407f4b9468a31d Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 21 Jun 2013 10:10:46 +0000 Subject: MIPS: Cleanup indentation and whitespace Signed-off-by: Tony Wu Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5536/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu-features.h | 32 +++++++++++----------- .../include/asm/mach-generic/kernel-entry-init.h | 4 +-- arch/mips/include/asm/processor.h | 4 +-- arch/mips/kernel/branch.c | 1 - arch/mips/kernel/unaligned.c | 1 + arch/mips/mm/page.c | 2 +- 6 files changed, 22 insertions(+), 22 deletions(-) (limited to 'arch/mips/include/asm/cpu-features.h') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 8e0c125c59a..1dc086087a7 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -97,13 +97,13 @@ #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) #endif #ifndef cpu_has_mdmx -#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) +#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) #endif #ifndef cpu_has_mips3d -#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) +#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) #endif #ifndef cpu_has_smartmips -#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) +#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif #ifndef cpu_has_rixi #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) @@ -125,7 +125,7 @@ #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) #endif #ifndef cpu_has_pindexed_dcache -#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) +#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #endif #ifndef cpu_has_local_ebase #define cpu_has_local_ebase 1 @@ -162,18 +162,18 @@ #ifndef cpu_has_mips_5 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) #endif -# ifndef cpu_has_mips32r1 +#ifndef cpu_has_mips32r1 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) -# endif -# ifndef cpu_has_mips32r2 +#endif +#ifndef cpu_has_mips32r2 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) -# endif -# ifndef cpu_has_mips64r1 +#endif +#ifndef cpu_has_mips64r1 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) -# endif -# ifndef cpu_has_mips64r2 +#endif +#ifndef cpu_has_mips64r2 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) -# endif +#endif /* * Shortcuts ... @@ -195,9 +195,9 @@ * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. */ -# ifndef cpu_has_clo_clz -# define cpu_has_clo_clz cpu_has_mips_r -# endif +#ifndef cpu_has_clo_clz +#define cpu_has_clo_clz cpu_has_mips_r +#endif #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) @@ -223,7 +223,7 @@ # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) # endif # ifndef cpu_has_64bit_zero_reg -# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) # endif # ifndef cpu_has_64bit_gp_regs # define cpu_has_64bit_gp_regs 0 diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h index 7e66505fa57..13b0751b010 100644 --- a/arch/mips/include/asm/mach-generic/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h @@ -12,8 +12,8 @@ /* Intentionally empty macro, used in head.S. Override in * arch/mips/mach-xxx/kernel-entry-init.h when necessary. */ -.macro kernel_entry_setup -.endm + .macro kernel_entry_setup + .endm /* * Do SMP slave processor setup necessary before we can savely execute C code. diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 016dc4bffc8..3605b844ad8 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -244,8 +244,8 @@ struct thread_struct { unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; #ifdef CONFIG_CPU_CAVIUM_OCTEON - struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); - struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); + struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); + struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); #endif #ifdef CONFIG_CPU_XLP struct nlm_cop2_state cp2; diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index 46c2ad0703a..4d78bf445a9 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -467,5 +467,4 @@ unaligned: printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); force_sig(SIGBUS, current); return -EFAULT; - } diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 3eaa02aa8ae..8eaf310ffc6 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -1549,6 +1549,7 @@ sigill: ("Unhandled kernel unaligned access or invalid instruction", regs); force_sig(SIGILL, current); } + asmlinkage void do_ade(struct pt_regs *regs) { enum ctx_state prev_state; diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 4eb8dcfaf1c..2c0bd580b9d 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -232,7 +232,7 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off) uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); } - } + } } extern u32 __clear_page_start; -- cgit v1.2.3-70-g09d2