From 2909060699226f70d731d9c242489418f7da4972 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 23 Feb 2012 20:18:57 -0700 Subject: mips/PCI: replace pci_probe_only with pci_flags Some architectures (alpha, mips, powerpc) have an arch-specific "pci_probe_only" flag. Others use PCI_PROBE_ONLY in pci_flags for the same purpose. This moves mips to the pci_flags approach so generic code can use the same test across all architectures. CC: Ralf Baechle CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas --- arch/mips/include/asm/pci.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips/include/asm') diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 576397c6992..1e4fa3da3f7 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -92,6 +92,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, #include #include #include +#include struct pci_dev; @@ -145,8 +146,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) #define arch_setup_msi_irqs arch_setup_msi_irqs #endif -extern int pci_probe_only; - extern char * (*pcibios_plat_setup)(char *str); #endif /* _ASM_PCI_H */ -- cgit v1.2.3-70-g09d2 From 96a6b9ad05a2d5654f168d3ad9d9696d3b03a7c2 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 23 Feb 2012 20:19:02 -0700 Subject: mips/PCI: get rid of device resource fixups Tell the PCI core about host bridge address translation so it can take care of bus-to-resource conversion for us. Here's the wrinkle on Cobalt: we can't generate normal I/O port addresses on PCI because the GT-64111 doesn't do any address translation, so we have this: CPU I/O port addresses [io 0x0000-0xffffff] PCI bus I/O port addresses [io 0x10000000-0x10ffffff] Legacy-mode IDE controllers start out with the legacy bus addresses, e.g., 0x1f0, assigned by pci_setup_device(). These are outside the range of addresses GT-64111 can generate on PCI, but pcibios_fixup_device_resources() converted them to CPU addresses anyway by adding io_offset. Therefore, we had to pre-adjust them in cobalt_legacy_ide_fixup(). With io_offset = 0xf0000000, we had this: res->start = 0x1f0 initialized in pci_setup_device() res->start = 0x100001f0 -= io_offset in cobalt_legacy_ide_fixup() res->start = 0x1f0 += io_offset in pcibios_fixup_device_resources() The difference after this patch is that the generic pci_bus_to_resource() only adds the offset if the bus address is inside a host bridge window. Since 0x1f0 is not a valid bus address and is not inside any windows, it is unaffected, so we now have this: region->start = 0x1f0 initialized in pci_setup_device() res->start = 0x1f0 no offset by pci_bus_to_resource() That means we can remove both pcibios_fixup_device_resources() and cobalt_legacy_ide_fixup(). I would *rather* set the host bridge offset to zero (which corresponds to what the GT-64111 actually does), and have both CPU and PCI addresses of [io 0x10000000-0x10ffffff]. However, that would require changes to generic code that assumes legacy I/O addresses, such as pic1_io_resource ([io 0x0020-0x00021]), and we'd have to keep a Cobalt IDE fixup. Of course, none of this changes the fact that references to I/O port 0x1f0 actually go to port 0x100001f0, not 0x1f0, on the Cobalt PCI bus. Fortunately the VT82C586 IDE controller only decodes the low 24 address bits, so it does work. CC: Ralf Baechle CC: Yoichi Yuasa Signed-off-by: Bjorn Helgaas --- arch/mips/include/asm/pci.h | 6 +--- arch/mips/pci/fixup-cobalt.c | 61 -------------------------------------- arch/mips/pci/pci.c | 70 ++------------------------------------------ 3 files changed, 4 insertions(+), 133 deletions(-) (limited to 'arch/mips/include/asm') diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 1e4fa3da3f7..6420e8df4e4 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -113,11 +113,7 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -extern void pcibios_resource_to_bus(struct pci_dev *dev, - struct pci_bus_region *region, struct resource *res); - -extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region); +#define ARCH_HAS_GENERIC_PCI_OFFSETS #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index acacd1407c6..9553b14002d 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -51,67 +51,6 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, qube_raq_galileo_early_fixup); -static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev, - struct resource *res) -{ - struct pci_controller *hose = (struct pci_controller *)dev->sysdata; - unsigned long offset = hose->io_offset; - struct resource orig = *res; - - if (!(res->flags & IORESOURCE_IO) || - !(res->flags & IORESOURCE_PCI_FIXED)) - return; - - res->start -= offset; - res->end -= offset; - dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n", - &orig, res); -} - -static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev) -{ - u32 class; - u8 progif; - - /* - * If the IDE controller is in legacy mode, pci_setup_device() fills in - * the resources with the legacy addresses that normally appear on the - * PCI bus, just as if we had read them from a BAR. - * - * However, with the GT-64111, those legacy addresses, e.g., 0x1f0, - * will never appear on the PCI bus because it converts memory accesses - * in the PCI I/O region (which is never at address zero) into I/O port - * accesses with no address translation. - * - * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store - * to physical address 0x100001f0 will become a PCI access to I/O port - * 0x100001f0. There's no way to generate an access to I/O port 0x1f0, - * but the VT82C586 IDE controller does respond at 0x100001f0 because - * it only decodes the low 24 bits of the address. - * - * When this quirk runs, the pci_dev resources should contain bus - * addresses, not Linux I/O port numbers, so convert legacy addresses - * like 0x1f0 to bus addresses like 0x100001f0. Later, we'll convert - * them back with pcibios_fixup_bus() or pcibios_bus_to_resource(). - */ - class = dev->class >> 8; - if (class != PCI_CLASS_STORAGE_IDE) - return; - - pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); - if ((progif & 1) == 0) { - cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]); - cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]); - } - if ((progif & 4) == 0) { - cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]); - cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]); - } -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, - cobalt_legacy_ide_fixup); - static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) { unsigned short cfgword; diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 19f6d194a56..0514866fa92 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -88,8 +88,9 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose) if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) next_busno = (*hose->get_busno)(); - pci_add_resource(&resources, hose->mem_resource); - pci_add_resource(&resources, hose->io_resource); + pci_add_resource_offset(&resources, + hose->mem_resource, hose->mem_offset); + pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset); bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, &resources); if (!bus) @@ -247,45 +248,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pcibios_plat_dev_init(dev); } -static void pcibios_fixup_device_resources(struct pci_dev *dev, - struct pci_bus *bus) -{ - /* Update device resources. */ - struct pci_controller *hose = (struct pci_controller *)bus->sysdata; - unsigned long offset = 0; - int i; - - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - if (!dev->resource[i].start) - continue; - if (dev->resource[i].flags & IORESOURCE_IO) - offset = hose->io_offset; - else if (dev->resource[i].flags & IORESOURCE_MEM) - offset = hose->mem_offset; - - dev->resource[i].start += offset; - dev->resource[i].end += offset; - } -} - void __devinit pcibios_fixup_bus(struct pci_bus *bus) { - /* Propagate hose info into the subordinate devices. */ - - struct list_head *ln; struct pci_dev *dev = bus->self; if (pci_has_flag(PCI_PROBE_ONLY) && dev && (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); - pcibios_fixup_device_resources(dev, bus); - } - - for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { - dev = pci_dev_b(ln); - - if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) - pcibios_fixup_device_resources(dev, bus); } } @@ -295,40 +264,7 @@ pcibios_update_irq(struct pci_dev *dev, int irq) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } -void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, - struct resource *res) -{ - struct pci_controller *hose = (struct pci_controller *)dev->sysdata; - unsigned long offset = 0; - - if (res->flags & IORESOURCE_IO) - offset = hose->io_offset; - else if (res->flags & IORESOURCE_MEM) - offset = hose->mem_offset; - - region->start = res->start - offset; - region->end = res->end - offset; -} - -void __devinit -pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region) -{ - struct pci_controller *hose = (struct pci_controller *)dev->sysdata; - unsigned long offset = 0; - - if (res->flags & IORESOURCE_IO) - offset = hose->io_offset; - else if (res->flags & IORESOURCE_MEM) - offset = hose->mem_offset; - - res->start = region->start + offset; - res->end = region->end + offset; -} - #ifdef CONFIG_HOTPLUG -EXPORT_SYMBOL(pcibios_resource_to_bus); -EXPORT_SYMBOL(pcibios_bus_to_resource); EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); #endif -- cgit v1.2.3-70-g09d2 From fb127cb9de791d62fb393d6e65fa9869bddd2460 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 23 Feb 2012 20:19:04 -0700 Subject: PCI: collapse pcibios_resource_to_bus Everybody uses the generic pcibios_resource_to_bus() supplied by the core now, so remove the ARCH_HAS_GENERIC_PCI_OFFSETS used during conversion. Signed-off-by: Bjorn Helgaas --- arch/alpha/include/asm/pci.h | 2 -- arch/arm/include/asm/pci.h | 2 -- arch/ia64/include/asm/pci.h | 2 -- arch/microblaze/include/asm/pci.h | 2 -- arch/mips/include/asm/pci.h | 2 -- arch/mn10300/include/asm/pci.h | 2 -- arch/parisc/include/asm/pci.h | 2 -- arch/powerpc/include/asm/pci.h | 2 -- arch/sh/include/asm/pci.h | 2 -- arch/sparc/include/asm/pci_32.h | 2 -- arch/sparc/include/asm/pci_64.h | 2 -- drivers/pci/probe.c | 44 +++++++++++++-------------------------- include/asm-generic/pci.h | 2 -- 13 files changed, 15 insertions(+), 53 deletions(-) (limited to 'arch/mips/include/asm') diff --git a/arch/alpha/include/asm/pci.h b/arch/alpha/include/asm/pci.h index 121c797eb14..d01afb78919 100644 --- a/arch/alpha/include/asm/pci.h +++ b/arch/alpha/include/asm/pci.h @@ -100,8 +100,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) return channel ? 15 : 14; } -#define ARCH_HAS_GENERIC_PCI_OFFSETS - #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h index 4748a75ed11..a98a2e112fa 100644 --- a/arch/arm/include/asm/pci.h +++ b/arch/arm/include/asm/pci.h @@ -57,8 +57,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -#define ARCH_HAS_GENERIC_PCI_OFFSETS - /* * Dummy implementation; always return 0. */ diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h index 519bb5ce307..b22e5f5fa59 100644 --- a/arch/ia64/include/asm/pci.h +++ b/arch/ia64/include/asm/pci.h @@ -108,8 +108,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return (pci_domain_nr(bus) != 0); } -#define ARCH_HAS_GENERIC_PCI_OFFSETS - static inline struct resource * pcibios_select_root(struct pci_dev *pdev, struct resource *res) { diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index 8db01f705b3..a0da88bf70c 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h @@ -94,8 +94,6 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus, */ #define PCI_DMA_BUS_IS_PHYS (1) -#define ARCH_HAS_GENERIC_PCI_OFFSETS - static inline struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *res) { diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 6420e8df4e4..fcd4060f642 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -113,8 +113,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -#define ARCH_HAS_GENERIC_PCI_OFFSETS - #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h index dfe1581c0c9..8137c25c4e1 100644 --- a/arch/mn10300/include/asm/pci.h +++ b/arch/mn10300/include/asm/pci.h @@ -85,8 +85,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, /* implement the pci_ DMA API in terms of the generic device dma_ one */ #include -#define ARCH_HAS_GENERIC_PCI_OFFSETS - static inline struct resource * pcibios_select_root(struct pci_dev *pdev, struct resource *res) { diff --git a/arch/parisc/include/asm/pci.h b/arch/parisc/include/asm/pci.h index a8b591fdd56..3234f492d57 100644 --- a/arch/parisc/include/asm/pci.h +++ b/arch/parisc/include/asm/pci.h @@ -215,8 +215,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -#define ARCH_HAS_GENERIC_PCI_OFFSETS - static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't need to penalize isa irq's */ diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index 839178bf277..201e352d488 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -154,8 +154,6 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus, #endif /* CONFIG_PPC64 */ -#define ARCH_HAS_GENERIC_PCI_OFFSETS - extern void pcibios_claim_one_bus(struct pci_bus *b); extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index 3b5b6abb3ae..bff96c2e7d2 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -114,8 +114,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, /* Board-specific fixup routines. */ int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin); -#define ARCH_HAS_GENERIC_PCI_OFFSETS - #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index static inline int pci_proc_domain(struct pci_bus *bus) diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h index 6384f30429b..dc503297481 100644 --- a/arch/sparc/include/asm/pci_32.h +++ b/arch/sparc/include/asm/pci_32.h @@ -52,8 +52,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, * 64Kbytes by the Host controller. */ -#define ARCH_HAS_GENERIC_PCI_OFFSETS - static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return PCI_IRQ_NONE; diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h index 2918bd12c19..1633b718d3b 100644 --- a/arch/sparc/include/asm/pci_64.h +++ b/arch/sparc/include/asm/pci_64.h @@ -73,8 +73,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -#define ARCH_HAS_GENERIC_PCI_OFFSETS - static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return PCI_IRQ_NONE; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index a677b1e995d..36c22032ea1 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -66,8 +66,8 @@ static bool resource_contains(struct resource *res1, struct resource *res2) return res1->start <= res2->start && res1->end >= res2->end; } -void pci_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, - struct resource *res) +void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, + struct resource *res) { struct pci_host_bridge *bridge = pci_host_bridge(dev); struct pci_host_bridge_window *window; @@ -86,6 +86,7 @@ void pci_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, region->start = res->start - offset; region->end = res->end - offset; } +EXPORT_SYMBOL(pcibios_resource_to_bus); static bool region_contains(struct pci_bus_region *region1, struct pci_bus_region *region2) @@ -93,8 +94,8 @@ static bool region_contains(struct pci_bus_region *region1, return region1->start <= region2->start && region1->end >= region2->end; } -void pci_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region) +void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region) { struct pci_host_bridge *bridge = pci_host_bridge(dev); struct pci_host_bridge_window *window; @@ -117,22 +118,7 @@ void pci_bus_to_resource(struct pci_dev *dev, struct resource *res, res->start = region->start + offset; res->end = region->end + offset; } - -#ifdef ARCH_HAS_GENERIC_PCI_OFFSETS -void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, - struct resource *res) -{ - pci_resource_to_bus(dev, region, res); -} -EXPORT_SYMBOL(pcibios_resource_to_bus); - -void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, - struct pci_bus_region *region) -{ - pci_bus_to_resource(dev, res, region); -} EXPORT_SYMBOL(pcibios_bus_to_resource); -#endif /* * PCI Bus Class @@ -309,11 +295,11 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, pci_write_config_dword(dev, pos + 4, 0); region.start = 0; region.end = sz64; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); } else { region.start = l64; region.end = l64 + sz64; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); } @@ -325,7 +311,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, region.start = l; region.end = l + sz; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); } @@ -383,7 +369,7 @@ static void __devinit pci_read_bridge_io(struct pci_bus *child) res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; region.start = base; region.end = limit + 0xfff; - pci_bus_to_resource(dev, &res2, ®ion); + pcibios_bus_to_resource(dev, &res2, ®ion); if (!res->start) res->start = res2.start; if (!res->end) @@ -409,7 +395,7 @@ static void __devinit pci_read_bridge_mmio(struct pci_bus *child) res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; region.start = base; region.end = limit + 0xfffff; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); } } @@ -458,7 +444,7 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) res->flags |= IORESOURCE_MEM_64; region.start = base; region.end = limit + 0xfffff; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); } } @@ -1071,24 +1057,24 @@ int pci_setup_device(struct pci_dev *dev) region.end = 0x1F7; res = &dev->resource[0]; res->flags = LEGACY_IO_RESOURCE; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); region.start = 0x3F6; region.end = 0x3F6; res = &dev->resource[1]; res->flags = LEGACY_IO_RESOURCE; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); } if ((progif & 4) == 0) { region.start = 0x170; region.end = 0x177; res = &dev->resource[2]; res->flags = LEGACY_IO_RESOURCE; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); region.start = 0x376; region.end = 0x376; res = &dev->resource[3]; res->flags = LEGACY_IO_RESOURCE; - pci_bus_to_resource(dev, res, ®ion); + pcibios_bus_to_resource(dev, res, ®ion); } } break; diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h index 0410346e2cf..e80a0495e5b 100644 --- a/include/asm-generic/pci.h +++ b/include/asm-generic/pci.h @@ -6,8 +6,6 @@ #ifndef _ASM_GENERIC_PCI_H #define _ASM_GENERIC_PCI_H -#define ARCH_HAS_GENERIC_PCI_OFFSETS - static inline struct resource * pcibios_select_root(struct pci_dev *pdev, struct resource *res) { -- cgit v1.2.3-70-g09d2